Image sensor and readout circuit thereof

Abstract

The present application provides an image sensor and a readout circuit (1) thereof. The readout circuit (1) of the image sensor comprises a ramp voltage circuit (10), a comparator circuit (20), a counter circuit (30), and a negation control circuit (40). When switching counting, the negation control circuit (40) is arranged to control the counter circuit (30) to negate a first digital code value into a second digital code value; and in a second quantization time period, the counter circuit (30) performs counting on the basis of the second digital code value to generate a third digital code value. Therefore, correlated double sampling is achieved, fixed-pattern noise is eliminated, and the imaging quality is improved. Additionally, a buffer and an additional holding circuit do not need to be arranged in the readout circuit (1), thereby simplifying the circuit structure, reducing power consumption, and ensuring that the counter circuit works in a high-frequency counting mode.

Description

Image sensor and its readout circuit

[0001] This application claims the priority of Chinese patent application No. 202310729218.X, filed with the Patent Office of China on June 19, 2023, with invention name “Image sensor and readout circuit thereof”; and the priority of Chinese patent application No. 202310732730.X, with invention name “Image sensor and readout circuit thereof”; and the priority of Chinese patent application No. 202321569685.2, with utility model name “Image sensor and readout circuit thereof”; and the priority of Chinese patent application No. 202321569770.9, with utility model name “Image sensor and readout circuit thereof”, all of which are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the technical field of image sensors, and in particular relates to an image sensor and a readout circuit thereof. Background Art

[0003] CMOS image sensors offer advantages such as low voltage, low power consumption, low cost, and high integration, making them valuable applications in fields such as machine vision, consumer electronics, high-definition surveillance, and medical imaging. The analog-to-digital converter (ADC) is a crucial component of the readout circuitry of a CMOS image sensor, responsible for converting the analog pixel output signal into a digital signal. CMOS image sensors typically employ column-level ADCs, including the single-slope ADC (SS SDC), the successive approximation register ADC (SAR ADC), and the cyclic ADC.

[0004] The counter in a traditional SS ADC is generally a reversible counter, which can switch between up and down counting. As shown in Figure 1, the N-bit counter circuit is composed of cascaded counter units. When count_up is 1, the output signal QB of the inverting output terminal of this stage is used as the clock signal of the next stage, which is in up counting mode; when count_up is 0, the output signal Q of the non-inverting output terminal of this stage is used as the clock signal of the next stage, which is in down counting mode. After the two counting stops, the final counting result D is used as the clock signal of the next stage. <n-1:0>Stored in memory.

[0005] Because count_clk operates at a very high frequency (typically several hundred MHz or even exceeding 1 GHz), traditional reversible counters require a binary data selector and a driver buffer between each stage of the counter unit, increasing power consumption. Furthermore, this structure faces the challenge of maintaining the stability of the first quantization result during the up / down counting transition. This requires an additional hold circuit, complicating the circuit layout, increasing parasitic capacitance and resistance in the routing, further increasing power consumption, and limiting the maximum operating frequency of the counter. Technical issues

[0006] The purpose of the present application is to provide a readout circuit for an image sensor, aiming to solve the problems of high power consumption and complex structure of a traditional reversible counter. Technical Solutions

[0007] In order to solve the above technical problems, the technical solutions adopted in the embodiments of the present application are:

[0008] A first aspect of an embodiment of the present application provides a readout circuit of an image sensor, comprising:

[0009] A ramp voltage circuit is configured to output a ramp voltage signal in a first quantization time period and a second quantization time period of the pixel unit respectively;

[0010] a comparator circuit, a first input terminal of which is connected to the pixel unit, a second input terminal of which is connected to the ramp voltage circuit, and configured to compare the reset signal or pixel signal output by the pixel unit with the ramp voltage signal, and output a reset pulse signal or a pixel pulse signal;

[0011] a counter circuit connected to the comparison circuit, configured to count the first pulse signal in the first quantization time period and store a first digital code value; in the second quantization time period, the counter circuit counts the second pulse signal based on the second digital code value and stores it as a third digital code value, the first pulse signal and the second pulse signal serving as the reset pulse signal and the pixel pulse signal, respectively;

[0012] An inversion control circuit is connected to the counter circuit. Between the first quantization time period and the second quantization time period, the inversion control circuit is triggered by a mode selection signal to output an inversion control signal, so that the counter circuit is triggered by the inversion control signal to invert the first digital code value to the second digital code value and store it.

[0013] A second aspect of the embodiments of the present application provides an image sensor, comprising a pixel array, a control circuit, and a plurality of readout circuits of the image sensor described above, wherein the pixel array comprises a plurality of pixel units arranged in an array;

[0014] The readout circuit of each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit of each image sensor is also respectively connected to the control circuit. Beneficial effects

[0015] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the readout circuit of the above-mentioned image sensor is connected by a ramp voltage circuit, a comparison circuit, a counter circuit and an inversion control circuit. When switching counting, the inversion control circuit is set to control the counter circuit to invert the first digital code value to a second digital code value, so that in the second quantization time period, the counter circuit counts the second digital code value as a third digital code value based on the second digital code value, realizing correlated double sampling, eliminating fixed pattern noise, and improving imaging quality. In addition, there is no need to set a buffer and an additional holding circuit in the readout circuit, which simplifies the circuit structure, reduces power consumption, and ensures that the counter circuit operates in a high-frequency counting mode.

[0016] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] FIG1 is a circuit diagram of a conventional counter circuit;

[0019] FIG2 is a schematic structural diagram of an image sensor provided in Example 13 of the present application;

[0020] FIG3 is a schematic diagram of a first circuit of a pixel unit in the image sensor shown in FIG2 ;

[0021] FIG4 is a schematic structural diagram of a readout circuit provided in Example 1 of the present application;

[0022] FIG5 is a schematic diagram of the structure of a readout circuit provided in Example 2 of the present application;

[0023] FIG6 is a circuit diagram of a readout circuit provided in Example 3 of the present application;

[0024] FIG7 is a schematic diagram of signal timing of the readout circuit provided in Embodiments 3 and 4 of the present application;

[0025] FIG8 is a circuit diagram of a readout circuit provided in Example 4 of the present application;

[0026] FIG9 is a schematic structural diagram of a readout circuit provided in Example 5 of the present application;

[0027] FIG10 is a circuit diagram of a storage circuit in the readout circuit shown in FIG9 ;

[0028] FIG11 is a second circuit diagram of a pixel unit provided in Example 6 of the present application;

[0029] FIG12 is a schematic diagram of the structure of a readout circuit provided in Example 6 of the present application;

[0030] FIG13 is a schematic diagram of signal timing of a readout circuit provided in Embodiment 7 of the present application;

[0031] FIG14 is a schematic diagram of signal timing of a readout circuit provided in Example 8 of the present application;

[0032] FIG15 is a circuit diagram of a readout circuit provided in Embodiment 7 and Embodiment 8 of the present application;

[0033] FIG16 is a schematic diagram of signal timing of a readout circuit provided in Example 9 of the present application;

[0034] FIG17 is a schematic diagram of signal timing of a readout circuit provided in the tenth embodiment of the present application;

[0035] FIG18 is a circuit diagram of a readout circuit provided in Embodiment 9 and Embodiment 10 of the present application;

[0036] FIG19 is a circuit diagram of a readout circuit provided in Example 11 of the present application;

[0037] Figure 20 is a circuit diagram of a D flip-flop in a readout circuit provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0040] Example 1

[0041] A first aspect of an embodiment of the present application provides a readout circuit for an image sensor. As shown in FIG2 , the image sensor generally includes a control circuit 3, a pixel array 100, a readout circuit 1, and may further include a clock generator and a digital I / O port. The pixel array 100 includes a plurality of pixel units arranged in an array, and the plurality of pixel units arranged in columns are connected in common. The control circuit 3 selects the pixel units in each row through a row selection signal and sequentially outputs the pixel signals of each row to the readout circuit 1. The plurality of pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3, so that the control circuit 3 determines the image information based on the digital code value.

[0042] The pixel unit generally includes a photoelectric conversion element, a transmission transistor TX, a reset transistor RST, a source follower transistor SF and a row selection transistor SEL, wherein the photoelectric conversion element includes but is not limited to a photodiode PD, such as a Pin-type photodiode PD. At the same time, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL can be one or more, that is, the structure of the pixel unit can be selected accordingly, and the specific structure is not limited. As shown in FIG3 , taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL, wherein the cathode of the photodiode PD is connected to the first end of the transfer transistor TX, the second end of the transfer transistor TX, the first end of the reset transistor RST, and the controlled end of the source follower transistor SF are all coupled to the floating diffusion node, the anode of the photodiode PD is grounded, the second end of the reset transistor RST and the first end of the source follower transistor SF are both connected to the positive power supply terminal VDD, the second end of the source follower transistor SF is connected to the first end of the row selection transistor SEL, and the second end of the row selection transistor SEL constitutes the output end of the pixel unit 2 and is used to output the corresponding pixel signal.

[0043] CMOS image sensors using a column-arranged readout circuit 1 face the problem of fixed pattern noise (FPN). This is because, due to factors such as process and temperature, there is a certain degree of mismatch in the threshold voltages of the transistors of each column of pixels. Under the same lighting conditions, the mismatch will cause the column consistency of the pixel output signal to deteriorate. Using the 4T active pixel structure shown in Figure 3, a correlated double sampling (CDS) operation can be performed to read out the reset signal and exposure signal of the pixel separately, and then subtract the two. Since the two signals contain the same fixed pattern noise (FPN), FPN can be eliminated by subtracting, thereby improving image quality.

[0044] The common CDS operation is to use two ramp signals in the SS ADC to quantize the reset signal and exposure signal of the pixel twice, and control the counter circuit to count down and up during the two quantization periods, so as to make a difference in the analog voltage value output by the pixel in the digital domain. Therefore, the counter circuit in this structure is a reversible counter, that is, it can realize the switching between up-counting and down-counting. As shown in Figure 1, the N-bit counter circuit is composed of cascaded counter units. When count_up is 1, the output signal QB of the inverting output terminal of this stage is used as the clock signal count_clk of the next stage, which is an up-counting mode; when count_up is 0, the output signal Q of the positive-phase output terminal of this stage is used as the clock signal count_clk of the next stage, which is a down-counting mode. After the two counts are stopped, the final counting result D is used. <n-1:0>Stored in memory.

[0045] Because count_clk operates at a very high frequency (typically several hundred MHz or even exceeding 1 GHz), traditional reversible counters require a binary data selector (MUX1) and a driver buffer between each stage of the counter unit, increasing power consumption. Furthermore, this structure faces the challenge of maintaining the stability of the first quantization result during the up / down counting transition. This requires an additional hold circuit, complicating the circuit layout, increasing parasitic capacitance and resistance in the routing, further increasing power consumption, and limiting the counter's maximum operating frequency.

[0046] In order to solve the above technical problems, as shown in FIG4 , in this embodiment, the readout circuit 1 of the image sensor includes:

[0047] The ramp voltage circuit 10 is configured to output a ramp voltage signal in a first quantization time period and a second quantization time period of the pixel unit respectively;

[0048] a comparator circuit 20, a first input terminal of which is connected to the pixel unit, and a second input terminal of which is connected to the ramp voltage circuit 10, configured to compare the reset signal or pixel signal output by the pixel unit with the ramp voltage signal, and output a reset pulse signal or a pixel pulse signal;

[0049] The counter circuit 30 is connected to the comparison circuit 20 and is configured to count the first pulse signal in a first quantization time period and store a first digital code value; in a second quantization time period, the counter circuit 30 counts the second pulse signal based on the second digital code value and stores it as a third digital code value, wherein one of the first pulse signal and the second pulse signal is a reset pulse signal and the other is a pixel pulse signal;

[0050] The inversion control circuit 40 is connected to the counter circuit 30. Between the first quantization time period and the second quantization time period, it is triggered by the mode selection signal mode_sel to output the inversion control signal trig_pulse, so that the counter circuit 30 is triggered by the inversion control signal trig_pulse to invert the first digital code value to the second digital code value and store it.

[0051] In this embodiment, the ramp voltage circuit 10 generates two ramp voltage signals in the first quantization time period and the second quantization time period. The slopes and gains of the two ramp voltage signals may be the same or different.

[0052] The ramp voltage signal of the corresponding time period is output to the comparison circuit 20. The comparison circuit 20 receives the reset signal or pixel signal of the pixel unit in the corresponding time period. The reset signal and the pixel signal are respectively compared with the ramp voltage signal. The reset signal and the ramp voltage signal are compared in the first quantization time period or the second quantization time period to generate a reset pulse signal. The pixel signal and the ramp voltage signal are compared in another quantization time period to generate a pixel pulse signal.

[0053] The counter circuit 30 counts up or down the reset pulse signal or the pixel pulse signal within the first quantization time period. When the first quantization is completed, the counter circuit 30 generates and stores the first digital code value after the current quantization. The counter circuit 30 has a rewritable function, that is, it inverts the digital code value stored in itself according to the inversion control signal trig_pulse, for example, inverts the first digital code value 0100 to generate 1011.

[0054] Between two quantization time periods, the inversion control circuit 40 receives the mode selection signal mode_sel, and the inversion control circuit 40 triggers the output of the inversion control signal trig_pulse accordingly. The counter circuit 30 inverts the first digital code value stored in itself according to the received inversion control signal trig_pulse, and generates a second digital code value as the initial state of the second quantization, that is, as the basic value of the counter circuit 30 in the second counting.

[0055] At the initial moment of the second quantization time period, the mode selection signal mode_sel switches state, the counter circuit 30 returns to the counting mode, and quantizes the second pulse signal within the second quantization time period. The counter circuit 30 counts up or down based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting and the second quantization ends.

[0056] Since the second quantization is counted based on the inverse digital code value of the first quantization result, it is equivalent to performing a difference operation on the two digital code values. For example, the first quantization result is the reset signal, which is inverted to -Vrst. The second quantization result of the pixel signal is -Vrst+Vsig. Since the two signals contain the same FPN, the FPN can be eliminated by taking the difference, thereby improving the imaging quality.

[0057] At the same time, by adopting the inverted counting, the counter circuit 30 does not need to switch between up-counting and down-counting, nor does it need to set up an additional holding circuit. It only needs to add the corresponding inverted control circuit 40. Compared with the traditional counter circuit 30, the number of transistors can be reduced, thereby reducing the layout area and optimizing the routing, thereby achieving the purpose of reducing power consumption.

[0058] Among them, the ramp voltage circuit 10 can adopt a corresponding signal source, voltage generating circuit, etc., such as the ramp generator shown in Figure 2, and the comparison circuit 20 can adopt a comparator and other structures. Optionally, as shown in Figure 2, the comparison circuit 20 includes a first capacitor, a second capacitor and a comparator, the first end of the first capacitor is connected to the signal end of the ramp generating circuit, the first end of the second capacitor is used to input the reset signal or pixel signal output by the pixel unit, the second end of the first capacitor is connected to the non-inverting input end of the comparator, and the second end of the second capacitor is connected to the inverting input end of the comparator. When the ramp voltage signal is less than the corresponding reset signal or pixel signal, the comparator outputs a low level and the counter circuit 30 starts counting. When the ramp voltage signal is greater than the corresponding reset signal or pixel signal, the comparator outputs a high level and the counter circuit 30 stops counting. At this time, the counting result is the digital code value after signal quantization.

[0059] The quantization order of the reset pulse signal and the pixel pulse signal can be set according to requirements. The reset pulse signal can be quantized first and then the pixel pulse signal, or the pixel pulse signal can be quantized first and then the reset pulse signal. Optionally, the counter circuit 30 is configured to count the reset pulse signal in a first quantization time period and store a first digital code value, and to count the pixel pulse signal based on the second digital code value in a second quantization time period and store it as a third digital code value.

[0060] Alternatively, the counter circuit 30 is configured to count the pixel pulse signal in a first quantization time period and store a first digital code value, and to count the reset pulse signal based on the second digital code value in a second quantization time period and store it as a third digital code value.

[0061] When the reset pulse signal is quantized first and the pixel pulse signal is quantized later, in the first quantization time period, the counter circuit 30 first quantizes the reset pulse signal, and the counter circuit 30 quantizes to generate a first digital code value, such as Vrst. Between the two quantization time periods, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the first digital code value corresponding to the reset pulse signal to a second digital code value, that is, generates -Vrst. In the second quantization time period, the pixel pulse signal is quantized, and the counter circuit 30 counts based on the second digital code value and generates a third digital code value, that is, -Vrst+Vsig. Since the two signals contain the same FPN, the FPN can be eliminated by taking the difference, thereby improving the imaging quality.

[0062] Alternatively, when the pixel pulse signal is quantized first and the reset pulse signal is quantized later, in the first quantization time period, the counter circuit 30 first quantizes the pixel pulse signal, and the counter circuit 30 quantizes to generate a first digital code value, such as Vsig. Between the two quantization time periods, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the first digital code value corresponding to the pixel pulse signal to a second digital code value, that is, generates -Vsig. In the second quantization time period, the pixel pulse signal is quantized, and the counter circuit 30 counts based on the second digital code value and generates a third digital code value, that is, -Vsig+Vrst. Since the two signals contain the same FPN, the FPN can be eliminated by taking the difference, thereby improving the imaging quality.

[0063] The counter circuit 30 may adopt a structure corresponding to a D flip-flop DFF, a latch, etc., and the inversion control circuit 40 may adopt a signal source, a selection circuit, etc.

[0064] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the readout circuit 1 of the above-mentioned image sensor is connected by a ramp voltage circuit 10, a comparison circuit 20, a counter circuit 30 and an inversion control circuit 40. When switching counting, the inversion control circuit 40 is set to control the counter circuit 30 to invert the first digital code value to a second digital code value, so that in the second quantization time period, the counter circuit 30 counts the second digital code value as a third digital code value based on the second digital code value, realizing correlated double sampling, eliminating fixed pattern noise, and improving imaging quality. In addition, there is no need to set a buffer and an additional holding circuit in the readout circuit 1, which simplifies the circuit structure, reduces power consumption, and ensures that the counter circuit 30 operates in a high-frequency counting mode.

[0065] Example 2

[0066] Based on the optimization and specific implementation of the first embodiment, as shown in FIG5 , optionally, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0067] The negation control circuit 40 includes n selection circuits, the first input terminal of the i-th selection circuit is used to input the negation control signal trig_pulse, the second input terminal of the first selection circuit 41 is used to input the clock signal count_clk, the third input terminal of the first selection circuit 41 is used to input the output signal cmp_out of the comparator, the second input terminals of the second selection circuit 42 to the n-th selection circuit are connected to the output terminal of the i-1-th stage counter unit, and the output terminal of the i-th selection circuit is connected to the input terminal of the i-th stage counter unit, where i is 1, 2, ..n;

[0068] The i-th selection circuit outputs a negated control signal trig_pulse or a clock signal count_clk in response to a mode selection signal mode_sel;

[0069] The first counter unit 31 to the nth counter unit are configured to count the first pulse signal in a first quantization time period and respectively store the first count value of the corresponding stage, and the count values ​​of the counter units at each stage are combined to generate a first digital code value; between the first quantization time period and the second quantization time period, the first counter unit 31 to the nth counter unit are inverted by the inverted control signal trig_pulse and stored as a second count value, and the count values ​​of the counter units at each stage are combined to generate a second digital code value;

[0070] In the second quantization period, the first counter unit 31 to the nth counter unit count the second pulse signal based on the second count value and store it as a third count value. The count values ​​of the counter units at each level are combined to generate a third digital code value.

[0071] In this embodiment, taking the first quantization reset pulse signal and the second quantization pixel pulse signal as examples, each selection circuit is connected to the front end of a counter unit, and outputs the signal corresponding to the signal input end to its own output end according to the received mode selection signal mode_sel. Before quantization, each counter unit is reset, and in the first quantization time period, the pixel unit outputs a reset signal to the comparison circuit 20. The comparison circuit 20 compares the reset signal with the ramp voltage signal and generates a reset pulse signal. The reset pulse signal is output to the first selection circuit 41. Each selection circuit receives the first level mode selection signal mode_sel and triggers the connection of its own second input end and output end. The first selection circuit 41 outputs the clock signal count_clk to the first counter unit 31. The subsequent selection circuit selects and outputs the count value of the previous level counter unit to the next level counter unit. The counter units at each level respectively store the first count value of the current level, and the first count values ​​of the counter units at each level are combined to generate the first digital code value.

[0072] Between the first quantization time period and the second quantization time period, the mode selection signal mode_sel is switched to the second level, and each selection circuit outputs the inversion control signal trig_pulse of the first input end to the counter unit at the back end. Each counter unit switches to the inversion mode and inverts the first count value stored in itself to the second count value. The second count values ​​stored in each counter unit are combined to generate a second digital code value. Then, the mode selection signal mode_sel is switched to the first level again, and the inversion control signal trig_pulse also switches the level state, and each counter unit switches to the counting mode.

[0073] In the second quantization time period, each selection circuit triggers the output clock signal count_clk to the back-end counter unit according to the received first-level mode selection signal mode_sel. Each counter unit counts the second pulse signal based on the second count value and stores it as a third count value. The count values ​​of the counter units at each level are combined to generate a third digital code value and read out accordingly. At this point, a complete quantization cycle is completed, and the third digital code value after the difference between the pixel reset signal and the pixel signal is finally obtained, thereby eliminating fixed pattern noise and improving imaging quality.

[0074] The selection circuit may select a corresponding switch structure, a selector, etc., and the counter unit may select a corresponding trigger, latch, etc. structure.

[0075] Example 3

[0076] Based on the optimization and specific implementation of the second embodiment, in an optional embodiment, as shown in FIG6 , the first selection circuit 41 includes an AND gate AND1 , a two-to-one data selector MUX1 , and a first inverter U1 ;

[0077] A first input terminal of the AND gate AND1 is used to input the clock signal count_clk, a second input terminal of the AND gate AND1 is used to input the output signal cmp_out of the comparator, a first input terminal of the two-to-one data selector MUX1 is used to input the inversion control signal trig_pulse, an output terminal of the AND gate AND1 is connected to the second input terminal of the two-to-one data selector MUX1, an output terminal of the two-to-one data selector MUX1 is connected to the input terminal of the first inverter U1, and an output terminal of the first inverter U1 constitutes an output terminal of the first selection circuit 41;

[0078] The second selection circuit 42 to the nth selection circuit respectively include a two-to-one data selector MUX1 and a first inverter U1. In the second selection circuit 42 to the nth selection circuit, the first input end of the two-to-one data selector MUX1 is used to input the inversion control signal trig_pulse, and the second input end of the two-to-one data selector MUX1 is used to input the numerical value output by the previous stage counter unit. The output end of the two-to-one data selector MUX1 is connected to the input end of the first inverter U1, and the output end of the first inverter U1 is used to constitute the output end of its selection circuit.

[0079] The counter unit includes a D flip-flop DFF and a second inverter U2;

[0080] The clock signal count_clk terminal of the D flip-flop DFF of the i-th counter unit is connected to the signal output terminal of the i-th selection circuit, the inverting output terminal of the D flip-flop DFF of the i-th counter unit is connected to the input terminal of the second inverter U2 and the data input terminal of the D flip-flop DFF, and the output terminal of the second inverter U2 is connected to the second input terminal of the (i+1)th selection circuit.

[0081] In this embodiment, the inverting output terminal of the D flip-flop DFF is connected to the first inverter U1 , and the output terminal of the first inverter U1 serves as the counting output terminal of the counter unit to implement upward counting.

[0082] 6 and 7 , before quantization, at time t1 - t2 , count_rst switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0083] At time t3, the first quantization is performed. At this time, the output signal cmp_out of the comparator switches to a high level. After the clock signal count_clk is ANDed with the high level by the AND1 operation of the AND gate, the clock signal count_clk is output to the second input terminal of the two-to-one data selector MUX1. At this time, the mode selection signal mode_sel is a high level, and the clock signal count_clk is selected and output to the first inverter U1 and then to the D flip-flop DFF. The D flip-flop DFF counts up under the action of the clock signal count_clk.

[0084] At time t4, the output of the comparison circuit 20 is flipped, the counting stops, the first quantization ends, and the count value of the first quantization result is stored in each D flip-flop DFF. The first count values ​​output by each second inverter U2 are combined to generate the first digital code value.

[0085] At time t5, the mode selection signal mode_sel switches to a low level, and each counter unit switches to the inversion mode.

[0086] At time t6, the inversion control signal trig_pulse switches to a low level and is selected and output to the first inverter U1 through the two-to-one data selector MUX1, and a rising edge is generated at the clock input end of the D flip-flop DFF, and the count value of the first quantization result stored in the D flip-flop DFF is inverted as the initial state before the second quantization. The second count values ​​output by each second inverter U2 are combined to generate a second digital code value.

[0087] At time t7, the mode selection signal mode_sel switches to a high level, and the counter unit returns to the counting mode. At time t8, the inversion control signal trig_pulse switches to a high level.

[0088] At time t9, the second quantization of the pixel pulse signal begins from the initial state. At time t10, the output of comparator circuit 20 flips, counting stops, and the second quantization ends. Between t11 and t12, the final quantization result is stored in the corresponding storage module and subsequently read out. This completes a full quantization cycle, ultimately yielding the digital code value that is the difference between the pixel's reset signal and the exposure signal.

[0089] Example 4

[0090] Based on the optimization and specific implementation of the second embodiment, in another optional embodiment, as shown in FIG8 , the first selection circuit 41 includes an AND gate AND1 , a two-to-one data selector MUX1 , and a first inverter U1 ;

[0091] A first input terminal of the AND gate AND1 is used to input the clock signal count_clk, a second input terminal of the AND gate AND1 is used to input the output signal cmp_out of the comparator, a first input terminal of the two-to-one data selector MUX1 is used to input the inversion control signal trig_pulse, an output terminal of the AND gate AND1 is connected to the second input terminal of the two-to-one data selector MUX1, an output terminal of the two-to-one data selector MUX1 is connected to the input terminal of the first inverter U1, and an output terminal of the first inverter U1 constitutes an output terminal of the first selection circuit 41;

[0092] The second selection circuit 42 to the nth selection circuit respectively include a two-to-one data selector MUX1 and a first inverter U1. In the second selection circuit 42 to the nth selection circuit, the first input end of the two-to-one data selector MUX1 is used to input the inversion control signal trig_pulse, and the second input end of the two-to-one data selector MUX1 is used to input the numerical value output by the previous stage counter unit. The output end of the two-to-one data selector MUX1 is connected to the input end of the first inverter U1, and the output end of the first inverter U1 is used to constitute the output end of its selection circuit.

[0093] Optionally, the counter unit includes a D flip-flop DFF;

[0094] The clock signal count_clk terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit, the inverting output terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the data input terminal of the D flip-flop DFF, and the non-inverting output terminal of the D flip-flop DFF is connected to the second input terminal of the (i+1)th selection circuit.

[0095] In this embodiment, the positive phase output terminal of the D flip-flop DFF serves as the counting output terminal of the counter unit to implement down counting.

[0096] 7 and 8 , before quantization, at time t1-t2, count_rst switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0097] At time t3, the first quantization is performed. At this time, the output signal cmp_out of the comparator switches to a high level. After the clock signal count_clk is ANDed with the high level by the AND1 operation of the AND gate, the clock signal count_clk is output to the second input terminal of the two-to-one data selector MUX1. At this time, the mode selection signal mode_sel is a high level, and the clock signal count_clk is selected and output to the first inverter U1 and then to the D flip-flop DFF. The D flip-flop DFF counts down under the action of the clock signal count_clk.

[0098] At time t4, the output of the comparison circuit 20 is flipped, the counting stops, the first quantization ends, and the count value of the first quantization result is stored in each D flip-flop DFF. The first count values ​​output by each D flip-flop DFF are combined to generate the first digital code value.

[0099] At time t5, the mode selection signal mode_sel switches to a low level, and each counter unit switches to the inversion mode.

[0100] At time t6, the inversion control signal trig_pulse switches to a low level and is selected and output to the first inverter U1 through the two-to-one data selector MUX1, and a rising edge is generated at the clock input end of the D-type flip-flop DFF. The count value of the first quantization result stored in the D-type flip-flop DFF is inverted as the initial state before the second quantization. The second count values ​​output by each D-type flip-flop DFF are combined to generate the second digital code value.

[0101] At time t7, the mode selection signal mode_sel switches to a high level, and the counter unit returns to the counting mode. At time t8, the inversion control signal trig_pulse switches to a high level.

[0102] At time t9, the second quantization of the pixel pulse signal begins from the initial state. At time t10, the output of comparator circuit 20 flips, counting stops, and the second quantization ends. Between t11 and t12, the final quantization result is stored in the corresponding storage module and subsequently read out. This completes a full quantization cycle, ultimately yielding the digital code value that is the difference between the pixel's reset signal and the exposure signal.

[0103] Example 5

[0104] Based on the optimization and specific implementation of the first embodiment, as shown in FIG9 , optionally, the readout circuit 1 of the image sensor further includes:

[0105] The storage circuit 50 is connected to the counter circuit 30 and is used to store the third digital code value and to be read out by the read control signal.

[0106] In this embodiment, after the second quantization, the counter circuit 30 obtains the difference between the digital code values ​​corresponding to the reset pulse signal and the pixel pulse signal, i.e., the third digital code value. Referring to FIG. 7 , at time t11-t12, the write enable signal output to the storage circuit 50 is set to a high level, writing the final quantization result into the storage circuit 50 for subsequent reading. At this point, a full quantization cycle is completed, and the digital code value resulting from the difference between the reset signal and the exposure signal for the pixel is ultimately obtained.

[0107] Among them, the storage circuit 50 can select a single memory Mem or multiple memories Mem. When a single memory Mem is used, the memory Mem is provided with multiple storage partitions, each storage partition stores a third count value respectively, and multiple third count values ​​are combined to generate a third digital code value. When multiple memories Mem are used, each memory Mem stores a third count value respectively.

[0108] In an optional embodiment, as shown in FIG10 , the storage circuit 50 includes:

[0109] The n memories Mem are respectively connected to a counter unit and store count values ​​of corresponding bits of the third digital code value.

[0110] In this embodiment, the storage circuit 50 is composed of a plurality of memories Mem, and each of the memories stores one bit of the third count value. To simplify the structure, the memory capacity of the memory Mem is optionally 1 bit.

[0111] Example 6

[0112] Omnidirectional autofocus (ADAF) plays a crucial role in image sensors. As shown in Figure 11, the pixel array consists of four pixels arranged in a 2×2 configuration, sharing a floating diffusion node and source-follower transistor. During readout, TXA and TXC are first turned on to read the signals from the two right pixels, obtaining the right phase information. Then, TXB and TXD are turned on to read the signals from the two left pixels, obtaining the left phase information. Using these two phase information, the phase difference can be calculated, enabling autofocus.

[0113] Secondly, dynamic range is a key factor in the imaging quality of image sensors. Dual Conversion Gain (DCG) is applied to the pixel circuit of image sensors. Under low illumination conditions, a smaller integral capacitor is used to increase the conversion gain to improve sensitivity. Under high illumination conditions, a larger integral capacitor is used to increase the stored charge and reduce the conversion gain to improve the dynamic range.

[0114] Correlated double sampling (CDS) can eliminate thermal noise and some fixed pattern noise caused by pixel reset, significantly improving the noise performance of image sensors. CDS requires separately reading the pixel's reset signal and exposure signal, then taking the difference between the two. Therefore, using CDS in a four-phase pixel structure or dual-conversion gain technology requires two sets of readout circuits for each column of pixels: one for quantizing the reset signal and the right pixel signal or a high-gain pulse signal, and the other for quantizing the reset signal and the left pixel signal or a low-gain pulse signal. This approach increases the structural complexity and power consumption of the image sensor.

[0115] Among them, a pixel unit usually has at least one sub-pixel. For example, the pixel unit shown in Figure 11 includes at least four sub-pixels arranged in a 2×2 manner, wherein at least two sub-pixels constitute a pixel group and are controlled to output a reset signal or a pixel signal at the same time. The sub-pixels in the pixel unit can be grouped into a pixel group in pairs, or in other combinations, and the specific grouping method is not limited.

[0116] When a pixel unit includes at least four sub-pixels arranged in a 2×2 configuration, the four sub-pixels share a floating diffusion node FD and a source-follower transistor. During readout, txa and txc are first turned on to read out the signals of the two right pixels, obtaining the right phase information. Then, txb and txd are turned on to read out the signals of the two left pixels, obtaining the left phase information. (Alternatively, txa and txb are first turned on to read out the signals of the two upper pixels, obtaining the upper phase information. Then, txc and txd are turned on to read out the signals of the two lower pixels, obtaining the lower phase information.) Using these two phase information, the phase difference can be calculated, enabling autofocus.

[0117] In order to simplify the structure of the image sensor and its readout circuit 1 and reduce power consumption, in this embodiment, the first quantization time period is a reset sampling time period, the second quantization time period is a first exposure sampling time period, the reset sampling time period includes at least one, and the pixel signal includes two;

[0118] The ramp voltage circuit 10 is further configured to output a ramp voltage signal in each sampling time period;

[0119] The comparison circuit 20 is further configured to compare at least one reset signal or two pixel signals output by the pixel unit with the ramp voltage signal, and output at least one reset pulse signal and two pixel pulse signals at intervals;

[0120] The counter circuit 30 is further configured to count at least one reset pulse signal in at least one reset sampling period and store the counted number of reset pulse signals as at least one first digital code value, count first pixel pulse signals based on the second digital code value in the first exposure sampling period and store the counted number of first pixel pulse signals as a third digital code value, and count second pixel pulse signals based on the fourth digital code value in the second exposure sampling period and store the counted number of second pixel pulse signals as a fifth digital code value.

[0121] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the inversion control circuit 40 is triggered by the mode selection signal mode_sel to output the inversion control signal trig_pulse to the counter circuit 30 to trigger the counter circuit 30 to invert the first digital code value in the memory to generate the second digital code value or the fourth digital code value;

[0122] As shown in FIG12 , the readout circuit of the image sensor further includes:

[0123] The storage circuit 50 is connected to the counter circuit 30 and configured to store at least one first digital code value and write back one of the at least one first digital code value to the counter circuit 30 before the second exposure sampling period when triggered by the write-back control signal rewrite_en.

[0124] In this embodiment, the ramp voltage signals output by the ramp voltage circuit 10 during the reset sampling period and the exposure sampling period may be the same or different, and the specific magnitudes are set according to the voltage amplitudes of the reset signal and the pixel signal.

[0125] Among them, the reset signal may include one or more, and correspondingly, the reset sampling period may be one or more. When it is a reset signal, in the reset sampling period, the comparison circuit 20 compares the reset signal with the reset ramp voltage signal and generates a reset pulse signal. The reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts the reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the reset signal quantization ends, and the counter circuit 30 counts to generate a first digital code value and stores it in itself and writes it into the storage circuit 50.

[0126] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel, and the inversion control circuit 40 outputs the inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode and inverts the stored first digital code value to a second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal and generates a first pixel pulse signal. The first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the first pixel pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops working, the quantization of the first pixel pulse signal is completed, and the counter circuit 30 counts to generate a third digital code value. The third digital code value is the difference between the first pixel signal and the digital code value corresponding to the reset signal, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0127] Afterwards, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first digital code value to generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value. The fourth digital code value serves as the initial state of the second exposure sampling. Then, the counter circuit 30 returns to the counting mode and quantizes the second pixel signal in the second exposure sampling period. The comparison circuit 50 generates a fourth digital code value. Circuit 20 compares the second pixel signal with the pixel ramp voltage signal and generates a second pixel pulse signal. The second pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the second pixel pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the second pixel pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the reset signal, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0128] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the storage circuit 50, and are read out to the corresponding control circuit 3 under the control of the read control signal. The control circuit 3 determines the image information according to the third digital code value and the fifth digital code value.

[0129] When the reset signal includes two reset signals corresponding to two pixel signals, in the first reset sampling period, the comparison circuit 20 compares the first reset signal with the reset ramp voltage signal and generates a first reset pulse signal. The first reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts the first reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the first reset signal is completed, and the counter circuit 30 counts to generate the first digital code value and writes it into the storage circuit 50.

[0130] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the second reset signal with the reset ramp voltage signal and generates a second reset pulse signal. The second reset pulse signal is output to the counter circuit 30, and the counter circuit 30 counts the second reset pulse signal in the same direction. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the second reset signal is completed, and the counter circuit 30 counts to generate the second first digital code value and stores it inside itself.

[0131] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel, and the inversion control circuit 40 outputs the inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode and inverts the stored second first digital code value to the second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal and generates a first pixel pulse signal. The first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the first pixel pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops working, the quantization of the first pixel pulse signal is completed, and the counter circuit 30 counts to generate a third digital code value. The third digital code value is the difference between the digital code value corresponding to the first pixel signal and the second reset signal, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0132] Afterwards, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state for the second exposure sampling. Then, the counter circuit 30 returns to the counting mode and quantizes the second pixel signal in the second exposure sampling period. The comparison circuit 20 compares the second pixel signal with the pixel ramp voltage signal and generates a second pixel pulse signal. The second pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the second pixel pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, and the quantization of the second pixel pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value, where the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the second reset signal, thereby realizing correlated double sampling, reducing noise effects, and improving imaging quality.

[0133] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the storage circuit 50 and read out to the corresponding control circuit 3 in the readout control signal. The control circuit 3 determines the image information according to the third digital code value and the fifth digital code value.

[0134] During the entire quantization process, the reset signal only needs to be quantized once, and the two read-out pixel signals are time-shared multiplexed using a set of counter circuits 30. Therefore, only one set of read-out circuits 1 is required to complete the quantization of two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption. The image information is determined based on the quantization results of the two pixel pulse signals, achieving autofocus or high dynamic range, and improving imaging quality.

[0135] The counter circuit 30 , the negation control circuit 40 and the storage circuit 50 may be specifically determined according to the corresponding reset signal, the type of the pixel signal and the input and output logic.

[0136] Furthermore, the write-back path of the storage circuit 50 can be directly output to the counter circuit 30 , or indirectly output to the counter circuit 30 via the inversion control circuit 40 . The specific write-back method is not limited.

[0137] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the above-mentioned image sensor circuit quantizes the reset signal into a first digital code value and stores it during the reset sampling period, quantizes the first pixel pulse signal based on the second digital code value during the first exposure sampling period to achieve correlated double sampling, and quantizes the second pixel pulse signal based on the fourth digital code value during the second exposure sampling period to achieve correlated double sampling, and the second digital code value and the fourth digital code value are the inverse values ​​of the corresponding first digital code value. During the entire quantization process, the reset signal only needs to be quantized once, and the pixel signals read out twice use a set of counter circuits 30 for time-sharing multiplexing. Therefore, only one set of readout circuits 1 is required to complete the quantization of the two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption. The image information is determined based on the quantization results of the two pixel pulse signals to achieve autofocus or high dynamic range, thereby improving imaging quality.

[0138] Example 7

[0139] Based on the optimization and specific implementation of the sixth embodiment, in an optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit includes at least four sub-pixels arranged in a 2×2 manner, wherein at least two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal;

[0140] The at least one reset signal is a reset signal generated when the pixel units are reset simultaneously;

[0141] The first pixel pulse signal and the second pixel pulse signal are respectively one of a pixel group pulse signal corresponding to simultaneous exposure of a pixel group and an image pulse signal corresponding to simultaneous exposure of sub-pixels in a pixel unit.

[0142] In this embodiment, the readout circuit 1 is applicable to ADAF technology. Four sub-pixels share a floating diffusion node and a source follower transistor. During readout, the pixel group is first turned on, and the pixel group signal Vsigl of at least two sub-pixels in the pixel group is read out. For example, the two pixel signals on the right are read out to obtain the right phase information.

[0143] Then, all the sub-pixels of the pixel unit are turned on, and the image signal Vsig corresponding to the pixel unit is read out. Correspondingly, the comparison circuit 20 obtains full phase information.

[0144] Specifically, as shown in reference figure 13, during the reset sampling period, the comparison circuit 20 compares the reset signal with the reset ramp voltage signal and generates a reset pulse signal. The reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts the reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the reset signal quantization ends, and the counter circuit 30 counts to generate a first digital code value and stores it in itself and writes it into the storage circuit 50.

[0145] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel. The inversion control circuit 40 outputs the inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode and inverts the stored first digital code value to a second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the pixel group signal Vsig1 with the pixel ramp voltage signal and generates a pixel group pulse signal. The pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the pixel group pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops operating, the pixel group pulse signal is quantized, and the counter circuit 30 counts to generate a third digital code value. The third digital code value is the difference between the pixel group signal Vsig1 and the digital code value corresponding to the reset signal, i.e., Vsigr-Vrst. This implements correlated double sampling, reduces noise effects, and improves imaging quality.

[0146] Afterwards, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first digital code value to generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value. The fourth digital code value serves as the initial state of the second exposure sampling. Then, the counter circuit 30 returns to the counting mode and quantizes the image signal Vsig during the second exposure sampling period. The comparison circuit 20 The image signal Vsig is compared with the pixel ramp voltage signal, and an image pulse signal is generated. The image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the image pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the reset signal, that is, Vsigr+Vsigl-Vrst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0147] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the storage circuit 50 and read out to the corresponding control circuit 3 in the read-out control signal. The control circuit 3 can determine the left and right pixel information or the upper and lower pixel information based on the fifth digital code value and the third digital code value, and obtain the phase difference through the pixel information to perform automatic focus and improve the user experience.

[0148] Moreover, during the quantization process, only one reset signal needs to be quantized, and the two pixel signals read out are time-shared and multiplexed with a set of counter circuits 30, which simplifies the structure of the image sensor and reduces power consumption. The image information is determined based on the quantization results of the two pixel pulse signals, thereby achieving automatic focus and improving imaging quality.

[0149] Example 8

[0150] Based on the optimization and specific implementation of the sixth embodiment, in another optional embodiment, the reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0151] The first pixel pulse signal and the second pixel pulse signal are respectively one of a high-gain image pulse signal and a low-gain image pulse signal;

[0152] The counter circuit 30 is configured to: count one of the reset pulse signals during a first reset sampling period to generate a first digital code value;

[0153] During a second reset sampling period, another reset pulse signal is counted to generate another first digital code value;

[0154] During the first exposure sampling period, counting the first pixel pulse signal based on the second digital code value and storing the counted ...

[0155] During the second exposure sampling period, the second pixel pulse signal is counted based on the fourth digital code value and stored as a fifth digital code value.

[0156] In this embodiment, the readout circuit 1 is suitable for HDR technology. The pixel unit or sub-pixel includes different integral capacitors, and different integral capacitors are switched under different illumination conditions. Under low illumination conditions, a smaller integral capacitor is used to increase the conversion gain to improve the sensitivity; under high illumination conditions, a larger integral capacitor is used to increase the stored charge and reduce the conversion gain to improve the dynamic range.

[0157] Correspondingly, the reset signal includes a low-gain reset signal lcg_rst and a high-gain reset signal hcg_rst. Referring to Figure 14, in the first reset sampling period, the comparison circuit 20 compares the first reset signal with the reset ramp voltage signal and generates a first reset pulse signal. The first reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts the first reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the first reset signal is completed, and the counter circuit 30 counts to generate the first first digital code value and writes it into the storage circuit 50.

[0158] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the second reset signal with the reset ramp voltage signal, and generates a second reset pulse signal to output to the counter circuit 30. The counter circuit 30 counts the second reset pulse signal in the same direction, and stops counting when the output of the comparison circuit 20 flips. The quantization of the second reset signal is completed, and the counter circuit 30 counts to generate the second first digital code value and stores it inside itself.

[0159] Among them, the second reset signal and the first reset signal are one of the high gain reset signal hcg_rst and the other is the low gain reset signal lcg_rst. Correspondingly, the second reset pulse signal and the first reset pulse signal are one of the high gain reset pulse signal and the other is the low gain reset pulse signal.

[0160] Before the first exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the negation mode and inverts the stored second first digital code value to the second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal, wherein the first pixel signal and the second reset signal are the image signal and the reset signal at the same gain. For example, the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst are compared to generate a first pixel pulse signal, and the first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the first pixel pulse signal in the same direction based on the second digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops working, the quantization of the first pixel pulse signal is completed, and the counter circuit 30 counts to generate a third digital code value, wherein the third digital code value is the difference between the digital code values ​​corresponding to the first pixel signal and the second reset signal, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0161] Afterwards, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes back the first stored digital code value to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state of the second exposure sampling. Then, the counter circuit 30 returns to the counting mode and quantizes the second pixel signal during the second exposure sampling period. The second pixel signal and the first reset signal are an image signal and a reset signal at the same gain, for example, a low-gain image signal l and a low-gain image signal l, respectively. cg_sig and the low-gain reset signal lcg_rst, the comparison circuit 20 compares the second pixel signal with the pixel ramp voltage signal and generates a second pixel pulse signal, which is output to the counter circuit 30. The counter circuit 30 counts the second pixel pulse signal in the same direction based on the fourth digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, the quantization of the second pixel pulse signal is completed, and the counter circuit 30 counts to generate a fifth digital code value, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the first reset signal, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0162] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the storage circuit 50 and read out to the corresponding control circuit 3 in the readout control signal. The control circuit 3 determines the image information according to the third digital code value and the fifth digital code value.

[0163] During the entire quantization process, the reset signal only needs to be quantized once, and the two read-out pixel signals are time-shared multiplexed using a set of counter circuits 30. Therefore, only one set of read-out circuits 1 is required to complete the quantization of two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption. Image information is determined based on the quantization results of the two pixel pulse signals, achieving a high dynamic range and improving imaging quality.

[0164] Corresponding to the signal input and output logic of the seventh and eighth embodiments above, optionally, as shown in FIG15 , the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0165] The storage circuit 50 includes n storage units, such as a first storage unit 51, a second storage unit 52, etc., and each storage unit is connected to a counter unit and an inversion control circuit 40;

[0166] Each storage unit includes a first memory Mem1, a second memory Mem2 and a NAND gate NOR1;

[0167] The input ends of the first memory Mem1 and the second memory Mem2 are respectively connected to a counter unit, the output end of the first memory Mem1 is connected to the first input end of the NAND gate NOR1, the second input end of the NAND gate NOR1 is used to input the write-back control signal rewrite_en, and the NAND gate NOR1 constitutes the output end of the storage unit;

[0168] A first memory Mem1 is configured to store a corresponding one-bit count value of at least one first digital code value;

[0169] The first memory Mem1 and the second memory Mem2 respectively store a corresponding one-bit count value of one of the third digital code value and the fifth digital code value.

[0170] When applicable to the readout circuit 1 of Example 7, referring to Figures 12, 13 and 15, during the reset sampling period, the comparison circuit 20 compares the reset signal with the reset ramp voltage signal and generates a reset pulse signal. The reset pulse signal is input to the counter circuit 30, and the reset pulse signal is output to the first counter unit 31 to the nth counter unit through the inversion control circuit 40. The n counter units count the reset pulse signal up or down, and when the output of the comparison circuit 20 is flipped, the n counter units stop counting, the reset signal quantization ends, the n counter units count and generate each bit count value of the first digital code value and store them, and the each bit count value of the first digital code value is respectively stored in the first memory Mem1.

[0171] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel, and the inversion control circuit 40 outputs the inversion control signal trig_pulse to the counter circuit 30. The n counter units are switched to the inversion mode and the stored first digital code value is inverted to the second digital code value as the initial state of the first exposure sampling period. Then, the n counter units are restored to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the pixel group signal Vsigl with the pixel ramp voltage signal and generates a pixel group pulse signal. The pixel group pulse signal is converted into a pixel group pulse signal by the inversion control circuit 30. The control circuit 40 outputs to n counter units, and the n counter units count the pixel group pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 is flipped, the n counter units stop counting, and the quantization of the pixel group pulse signal is completed. The n counter units count to generate a third digital code value, wherein the third digital code value is the difference between the pixel group signal Vsigl and the digital code value corresponding to the reset signal, that is, Vsigr-Vrst, to realize correlated double sampling, reduce noise influence, and improve imaging quality. The n-bit count value in the third digital code value is respectively stored in n second memories Mem2.

[0172] Afterwards, the n counter units are reset. Before the second exposure sampling period, the first memory Mem1 receives the write-back control signal rewrite_en and writes the stored first digital code value back to the counter circuit 30 through the NAND gate NOR1 and the inversion control circuit 40. At the same time, the n counter units receive the inversion control signal trig_pulse and invert the written-back first digital code value to generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value. The fourth digital code value serves as the initial state of the second exposure sampling. Then, the n counter units return to the counting mode and quantize the image signal Vsig in the second exposure sampling period. The comparison circuit 20 converts the image signal Vsig into a digital code. The image signal Vsig is compared with the pixel ramp voltage signal to generate an image pulse signal, which is output to n counter units. The n counter units count the image pulse signal in the same direction based on the fourth digital code value, and when the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, the quantization of the image pulse signal is completed, and the counter circuit 30 counts to generate a fifth digital code value. The n-bit count value of the fifth digital code value is stored in the first memory Mem1, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the reset signal, that is, Vsigr+Vsigl-Vrst, to achieve correlated double sampling, reduce noise impact, and improve imaging quality.

[0173] When applicable to the readout circuit 1 of Example 8, referring to Figures 11, 13 and 14, in the first reset sampling period, the comparison circuit 20 compares the first reset signal with the reset ramp voltage signal and generates a first reset pulse signal. The first reset pulse signal corresponds to the pulse signal of the high-gain reset signal hcg_rst or the low-gain reset signal lcg_rst. The first reset pulse signal is input to n counter units through the inversion control circuit 40. The n counter units count up or down the first reset pulse signal, and when the output of the comparison circuit 20 is flipped, the n counter units stop counting, the first reset signal quantization ends, the n counter units count to generate a count value, the n count values ​​are combined to generate a first digital code value and written into the n first memories Mem1.

[0174] Before the second reset sampling period, the n counter units are reset, and during the second reset sampling period, the comparison circuit 20 compares the second reset signal with the reset ramp voltage signal. The second reset signal and the first reset signal are a high-gain reset signal hcg_rst and a low-gain reset signal lcg_rst, and a second reset pulse signal is generated. The second reset pulse signal and the first reset pulse signal are a high-gain reset pulse signal and a low-gain reset pulse signal, respectively. The second reset pulse signal is output to the n counter units through the inversion control circuit 40. The n counter units count the second reset pulse signal in the same direction, and when the output of the comparison circuit 20 is flipped, the n counter units stop counting, and the quantization of the second reset signal ends. The n counter units count to generate n count values, and the n count values ​​are combined to generate the second first digital code value and stored in the n counter units themselves.

[0175] Before the first exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the n counter units. The n counter units switch to the negation mode and invert the count values ​​stored in each of them. The inverted count values ​​are combined to generate a second digital code value as the initial state of the first exposure sampling period. Then, the n counter units return to the counting mode, and in the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal to generate a first pixel pulse signal. The first The pixel pulse signal is output to n counter units through the inversion control circuit 40. The n counter units count the first pixel pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 is flipped, the n counter units stop working, the quantization of the first pixel pulse signal is completed, and the n counter units count to generate a third digital code value. The count values ​​of each bit of the third digital code value are respectively stored in each second memory Mem2, wherein the third digital code value is the difference between the digital code value corresponding to the first pixel signal and the second reset signal, thereby realizing correlated double sampling, reducing the influence of noise, and improving imaging quality.

[0176] Afterwards, the n counter units are reset. Before the second exposure sampling period, each first memory Mem1 receives a write-back control signal rewrite_en and writes back the first stored first digital code value to the n counter units. At the same time, the n counter units receive a negation control signal trig_pulse and invert the written-back first first digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state of the second exposure sampling. Then, the n counter units return to the counting mode and quantize the second pixel signal during the second exposure sampling period. The comparison circuit 20 compares the second pixel signal with the pixel ramp voltage signal. The comparison circuit 20 performs row comparison and generates a second pixel pulse signal, which is output to n counter units. The n counter units count the second pixel pulse signal in the same direction based on the fourth digital code value, and when the output of the comparison circuit 20 is flipped, the n counter units stop counting, the quantization of the second pixel pulse signal is completed, and the n counter units count to generate a fifth digital code value, wherein the fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the first reset signal. The n-bit count value of the fifth digital code value is respectively stored in the n first memories Mem1 to realize correlated double sampling, reduce noise influence, and improve imaging quality.

[0177] Example 9

[0178] Based on the optimization and specific implementation of the sixth embodiment, in another optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit includes at least four sub-pixels arranged in a 2×2 manner, wherein at least two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal;

[0179] The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0180] The first pixel pulse signal includes a high-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to simultaneous exposure of a pixel group in a low-gain mode and a low-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in a pixel unit;

[0181] The second exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive;

[0182] The first digital code value includes a first sub-digital code value and a second sub-digital code value;

[0183] The counter circuit 30 is configured to: count the low-gain reset pulse signal during a first reset sampling period to generate a first sub-digital code value;

[0184] During a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value;

[0185] During the first exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as a third digital code value;

[0186] The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value;

[0187] In a third exposure sampling period, the low-gain pixel group pulse signal is counted based on the fourth digital code value and stored as a fifth sub-digital code value;

[0188] In a fourth exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as a sixth sub-digital code value;

[0189] The storage circuit 50 is connected to the counter circuit 30 and configured to store the first sub-digital code value and write the first sub-digital code value back to the counter circuit 30 when triggered by the write-back control signal rewrite_en before the third exposure sampling period and the fourth exposure sampling period;

[0190] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the inversion control signal trig_pulse triggers the control circuit 30 to invert the first sub-digital code value of the memory to generate a fourth digital code value, and to invert the second sub-digital code value to generate a second digital code value.

[0191] In this embodiment, the readout circuit 1 is suitable for realizing autofocus under low conversion gain, the reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal, the first pixel pulse signal includes a high-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the low-gain mode and a low-gain image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit.

[0192] Referring to Figure 16, in the first reset sampling period, the comparison circuit 20 compares the low gain reset signal lcg_rst with the reset ramp voltage signal, generates a low gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts the low gain reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low gain reset signal lcg_rst is completed, and the counter circuit 30 counts to generate the first sub-digital code value and writes it into the storage circuit 50.

[0193] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the high-gain reset signal hcg_rst with the reset ramp voltage signal and generates a high-gain reset pulse signal. The high-gain reset pulse signal is output to the counter circuit 30, and the counter circuit 30 counts the high-gain reset pulse signal in the same direction. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, and the quantization of the high-gain reset signal hcg_rst is completed. The counter circuit 30 counts to generate a second sub-digital code value and stores it inside itself.

[0194] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel and outputs the inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode and inverts the stored second sub-digital code value to the second digital code value as the initial state for the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the high-gain image signal hcg_sig with the pixel ramp voltage signal to generate a high-gain image pulse signal. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain image pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops operating, completing the quantization of the high-gain image pulse signal. The counter circuit 30 then counts to generate a third digital code value. The third digital code value is the difference between the corresponding digital code values ​​of the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst. This implements correlated double sampling, reduces noise effects, and improves imaging quality.

[0195] Afterwards, the counter circuit 30 is reset. Before the third exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first sub-digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first sub-digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state of the third exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the low-gain pixel group signal lcg_sigl in the third exposure sampling period. The comparison circuit 20 compares the low-gain pixel group signal lcg_sigl with The pixel ramp voltage signal is compared and a low-gain pixel group pulse signal is generated. The low-gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain pixel group pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low-gain pixel group pulse signal is completed. The counter circuit 30 counts to generate a fifth sub-digital code value, wherein the fifth sub-digital code value is the difference between the digital code values ​​corresponding to the low-gain pixel group signal lcg_sigl and the low-gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0196] Then, the counter circuit 30 is reset again. Before the fourth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first sub-digital code value back to the counter circuit 30 again. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first sub-digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state of the fourth exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the low-gain image signal lcg_sig in the fourth exposure sampling period. The comparison circuit 20 quantizes the low-gain image signal lcg_sig. ig is compared with the pixel ramp voltage signal to generate a low-gain image pulse signal. The low-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low-gain image pulse signal is completed. The counter circuit 30 counts to generate a sixth sub-digital code value, where the sixth sub-digital code value is the difference between the digital code values ​​corresponding to the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0197] At the same time, the third digital code value, the fifth sub-digital code value and the sixth sub-digital code value obtained by the three quantizations are finally stored in the storage circuit 50, and are read out to the corresponding control circuit 3 in the read-out control signal. The control circuit 3 determines the image information according to the third digital code value, the fifth sub-digital code value and the sixth sub-digital code value, and realizes automatic focus in the low conversion gain mode, thereby improving the imaging quality and user experience.

[0198] Example 10

[0199] Based on the optimization and specific implementation of the sixth embodiment, in another optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit includes four sub-pixels arranged in a 2×2 manner, wherein two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal;

[0200] The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0201] The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to simultaneous exposure of a pixel group in a high-gain mode and a high-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in a pixel unit;

[0202] The second pixel pulse signal includes a low-gain image pulse signal;

[0203] The first exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive;

[0204] The first digital code value includes a first sub-digital code value and a second sub-digital code value;

[0205] The counter circuit 30 is configured to: count the low-gain reset pulse signal during a first reset sampling period to generate a first sub-digital code value;

[0206] During a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value;

[0207] The third digital code value includes a third sub-digital code value and a fourth sub-digital code value;

[0208] In a third exposure sampling period, the high-gain pixel group pulse signal is counted based on the second digital code value and stored as a third sub-digital code value;

[0209] In a fourth exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as a fourth sub-digital code value;

[0210] During the second exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as a fifth digital code value;

[0211] The storage circuit 50 is connected to the counter circuit 30 and is configured to store the first sub-digital code value and the second sub-digital code value, and before the fourth exposure sampling period and the second exposure sampling period, is triggered by the write-back control signal rewrite_en to write the second sub-digital code value and the first sub-digital code value back to the counter circuit 30;

[0212] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the inversion control signal trig_pulse triggers the counter circuit 30 to invert the second sub-digital code value of the memory to generate a second digital code value, and to invert the first sub-digital code value to generate a fourth digital code value.

[0213] In this embodiment, the readout circuit 1 is suitable for realizing autofocus under high conversion gain, the reset pulse signal includes a high-gain reset pulse signal and a low-gain reset signal lcg_rst, the first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the high-gain mode and a high-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit, and the second pixel pulse signal includes a low-gain image pulse signal.

[0214] Referring to Figure 17, in the first reset sampling period, the comparison circuit 20 compares the low gain reset signal lcg_rst with the reset ramp voltage signal, generates a low gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts the low gain reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low gain reset signal lcg_rst is completed, and the counter circuit 30 counts to generate the first sub-digital code value and writes it into the storage circuit 50.

[0215] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the high-gain reset signal hcg_rst with the reset ramp voltage signal and generates a high-gain reset pulse signal. The high-gain reset pulse signal is output to the counter circuit 30, and the counter circuit 30 counts the high-gain reset pulse signal in the same direction. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, and the quantization of the high-gain reset signal hcg_rst is completed. The counter circuit 30 counts to generate a second sub-digital code value and stores it inside itself.

[0216] Before the third exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the negation mode and inverts the stored second sub-digital code value to the second digital code value as the initial state of the third exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the high-gain pixel group signal hcg_sigl in the third exposure sampling period. The comparison circuit 20 compares the high-gain pixel group signal hcg_sigl with the pixel ramp voltage signal. The comparison circuit 20 compares the high-gain pixel group pulse signal and generates a high-gain pixel group pulse signal. The high-gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain pixel group pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the high-gain pixel group pulse signal is completed. The counter circuit 30 counts to generate a third sub-digital code value, wherein the third sub-digital code value is the difference between the digital code values ​​corresponding to the high-gain pixel group signal hcg_sigl and the high-gain reset signal hcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0217] Then, the counter circuit 30 is reset again. Before the fourth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored second sub-digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back second sub-digital code value to generate a second digital code value. The second digital code value serves as the initial state of the fourth exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the high-gain image signal hcg_sig in the fourth exposure sampling period. The comparison circuit 20 quantizes the high-gain image signal hcg_sig. ig is compared with the pixel ramp voltage signal to generate a high-gain image pulse signal. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain image pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the high-gain image pulse signal is completed. The counter circuit 30 counts to generate a fourth sub-digital code value, wherein the fourth sub-digital code value is the difference between the digital code values ​​corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0218] Then, the counter circuit 30 is reset again, and before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first sub-digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first sub-digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state of the second exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the low-gain image signal lcg_sig in the second exposure sampling period. The comparison circuit 20 quantizes the low-gain image signal lcg_sig. sig is compared with the pixel ramp voltage signal to generate a low-gain image pulse signal. The low-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low-gain image pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value, where the fifth digital code value is the difference between the digital code values ​​corresponding to the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0219] At the same time, the third sub-digital code value, the fourth sub-digital code value and the fifth sub-digital code value obtained by the three quantizations are finally stored in the storage circuit 50, and are read out to the corresponding control circuit 3 in the read-out control signal. The control circuit 3 determines the image information according to the third sub-digital code value, the fourth sub-digital code value and the fifth digital code value, and realizes automatic focus in the high conversion gain mode, thereby improving the imaging quality and user experience.

[0220] Corresponding to the signal input and output logic of the ninth and tenth embodiments above, as shown in FIG18 , optionally, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0221] The storage circuit 50 includes n storage units, each of which is connected to a counter unit and an inversion control circuit 40;

[0222] Each storage unit includes a first memory Mem1, a second memory Mem2, a third memory Mem3, a NAND gate NOR1 and a first two-to-one data selector MUX1;

[0223] The input end of the first memory Mem1, the input end of the second memory Mem2, and the input end of the third memory Mem3 are simultaneously connected to a counter unit, the output end of the first memory Mem1 is connected to the first input end of the first two-to-one data selector MUX1, the output end of the second memory Mem2 is connected to the second input end of the first two-to-one data selector MUX1, the control end of the first two-to-one data selector MUX1 is used to input the write-back selection signal mem_sel, the output end of the first two-to-one data selector MUX1 is connected to the first input end of the NAND gate NOR1, the second input end of the NAND gate NOR1 is used to input the write-back control signal rewrite_en, and the NAND gate NOR1 constitutes the output end of the storage circuit 50;

[0224] The first memory Mem1 is used to store a corresponding count value of the first sub-digit code value;

[0225] The second memory Mem2 is used to store a corresponding one-bit count value in the second sub-digit code value;

[0226] The first memory Mem1 , the second memory Mem2 and the third memory Mem3 further store corresponding one-bit count values ​​of the three digital code values ​​after three exposure samplings respectively.

[0227] In this embodiment, the difference from the circuit structure adopted in Embodiment 7 and Embodiment 8 is that the storage circuit 50 includes three memories and also includes a first two-to-one data selector MUX1, the n first memories Mem1 are used to store the n-bit count value of the first sub-digital code value corresponding to the low-gain reset signal lcg_rst during the reset sampling period, and the n second memories Mem2 are used to store the n-bit count value of the second sub-digital code value corresponding to the high-gain reset signal hcg_rst during the reset sampling period.

[0228] At the same time, when autofocus is implemented in low gain mode or high gain mode, before the corresponding exposure sampling period, the corresponding write-back selection signal mem_sel is output to the first two-to-one data selector MUX1 according to the first sub-digital code value or the second sub-digital code value to be written back, thereby selecting the first sub-digital code value or the second sub-digital code value to be written back to n counter units through the inversion control circuit 40.

[0229] The n-bit counter unit counts pulse signals input during the reset sampling period and the exposure sampling period and generates corresponding digital code values.

[0230] After each exposure sampling period, the three quantized digital code values ​​are finally stored in the first memory Mem1, the second memory Mem2 and the third memory Mem3 respectively. For example, when the readout circuit 1 is suitable for realizing autofocus under low conversion gain, the third digital code value, the fifth sub-digital code value and the sixth sub-digital code value are obtained by three exposure samplings, wherein the n-bit count value of the third digital code value is stored in n first memories Mem1 respectively, the n-bit count value of the fifth sub-digital code value is stored in n second memories Mem2 respectively, and the n-bit count value of the sixth sub-digital code value is stored in n third memories Mem3 respectively.

[0231] Alternatively, the readout circuit 1 is suitable for achieving autofocus at a high conversion gain by sampling the third sub-digital code value, the fourth sub-digital code value, and the fifth digital code value obtained by three exposures, wherein the n-bit count value of the third sub-digital code value is respectively stored in n first memories Mem1, the n-bit count value of the fourth sub-digital code value is respectively stored in n second memories Mem2, and the n-bit count value of the fifth digital code value is respectively stored in n third memories Mem3, and the three memories are read out to the corresponding control circuit 3 according to the readout control signal, so that the control circuit 3 determines the image information according to the count code value of each storage circuit 50.

[0232] Example 11

[0233] Based on the optimization and specific implementation of the sixth embodiment, in another optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit includes four sub-pixels arranged in a 2×2 manner, wherein two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal;

[0234] The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0235] The first pixel pulse signal includes a first pixel group pulse signal corresponding to simultaneous exposure of a pixel group in a high gain mode and a first image pulse signal corresponding to simultaneous exposure of sub-pixels in a pixel unit;

[0236] The second pixel pulse signal includes a second pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the low gain mode and a second image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit;

[0237] The first exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive;

[0238] The second exposure sampling period includes a fifth exposure sampling period and a sixth exposure sampling period that are consecutive;

[0239] The first digital code value includes a first sub-digital code value and a second sub-digital code value;

[0240] The counter circuit 30 is configured to: count the low-gain reset pulse signal during a first reset sampling period to generate a first sub-digital code value;

[0241] During a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value;

[0242] The third digital code value includes a third sub-digital code value and a fourth sub-digital code value;

[0243] In a third exposure sampling period, counting the pulse signal of the first pixel group based on the second digital code value and storing it as a third sub-digital code value;

[0244] In a fourth exposure sampling period, the first image pulse signal is counted based on the second digital code value and stored as a fourth sub-digital code value;

[0245] The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value;

[0246] In a fifth exposure sampling period, counting the second pixel group pulse signal based on the fourth digital code value and storing it as a fifth sub-digital code value;

[0247] In a sixth exposure sampling period, the second image pulse signal is counted based on the fourth digital code value and stored as a sixth sub-digital code value;

[0248] The storage circuit 50 is connected to the counter circuit 30 and is configured to store the first sub-digital code value and the second sub-digital code value, and to write the second sub-digital code value back to the counter circuit 30 when triggered by the write-back control signal rewrite_en before the fourth exposure sampling period, and to write the first sub-digital code value back to the counter circuit 30 when triggered by the write-back control signal rewrite_en before the fifth exposure sampling period and the sixth exposure sampling period;

[0249] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the inversion control signal trig_pulse triggers the counter circuit 30 to invert the second sub-digital code value of the memory to generate a second digital code value, and to invert the first sub-digital code value to generate a fourth digital code value.

[0250] In this embodiment, the readout circuit 1 is suitable for simultaneously realizing autofocus under high conversion gain and low conversion gain, the reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal, the first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the high-gain mode and a high-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit, the second pixel pulse signal includes a low-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the low-gain mode and a low-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit.

[0251] As shown in Figures 16 and 17, in the first reset sampling period, the comparison circuit 20 compares the low-gain reset signal lcg_rst with the reset ramp voltage signal, generates a low-gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts the low-gain reset pulse signal up or down, and when the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low-gain reset signal lcg_rst is completed, and the counter circuit 30 counts to generate the first sub-digital code value and writes it into the storage circuit 50.

[0252] Before the second reset sampling period, the counter circuit 30 is reset, and during the second reset sampling period, the comparison circuit 20 compares the high-gain reset signal hcg_rst with the reset ramp voltage signal and generates a high-gain reset pulse signal. The high-gain reset pulse signal is output to the counter circuit 30, and the counter circuit 30 counts the high-gain reset pulse signal in the same direction. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, and the quantization of the high-gain reset signal hcg_rst is completed. The counter circuit 30 counts to generate a second sub-digital code value and stores it inside itself.

[0253] Before the third exposure sampling period, the negation control circuit 40 receives the mode selection signal mode_sel, and the negation control circuit 40 outputs the negation control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the negation mode and inverts the stored second sub-digital code value to the second digital code value as the initial state of the third exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the high-gain pixel group signal hcg_sigl in the third exposure sampling period. The comparison circuit 20 compares the high-gain pixel group signal hcg_sigl with the pixel ramp voltage signal. The comparison circuit 20 compares the high-gain pixel group pulse signal and generates a high-gain pixel group pulse signal. The high-gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain pixel group pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the high-gain pixel group pulse signal is completed. The counter circuit 30 counts to generate a third sub-digital code value, wherein the third sub-digital code value is the difference between the digital code values ​​corresponding to the high-gain pixel group signal hcg_sigl and the high-gain reset signal hcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0254] Then, the counter circuit 30 is reset again. Before the fourth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored second sub-digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back second sub-digital code value to generate a second digital code value. The second digital code value serves as the initial state of the fourth exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the high-gain image signal hcg_sig in the fourth exposure sampling period. The comparison circuit 20 quantizes the high-gain image signal hcg_sig. ig is compared with the pixel ramp voltage signal to generate a high-gain image pulse signal. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain image pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the high-gain image pulse signal is completed. The counter circuit 30 counts to generate a fourth sub-digital code value, wherein the fourth sub-digital code value is the difference between the digital code values ​​corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0255] Before the fifth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes back the stored first sub-digital code value to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first sub-digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state of the fifth exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the low-gain pixel group signal lcg_sigl in the fifth exposure sampling period. The comparison circuit 20 compares the low-gain pixel group signal lcg_sigl with the pixel ramp voltage The signals are compared and a low-gain pixel group pulse signal is generated. The low-gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain pixel group pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low-gain pixel group pulse signal is completed. The counter circuit 30 counts to generate a fifth sub-digital code value, wherein the fifth sub-digital code value is the difference between the digital code values ​​corresponding to the low-gain pixel group signal lcg_sigl and the low-gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0256] Then, the counter circuit 30 is reset again. Before the sixth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes the stored first sub-digital code value back to the counter circuit 30. At the same time, the counter circuit 30 receives the inversion control signal trig_pulse and inverts the written-back first sub-digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state of the sixth exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the low-gain image signal lcg_sig in the sixth exposure sampling period. The comparison circuit 20 quantizes the low-gain image signal lcg_sig. ig is compared with the pixel ramp voltage signal to generate a low-gain image pulse signal. The low-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 is flipped, the counter circuit 30 stops counting, and the quantization of the low-gain image pulse signal is completed. The counter circuit 30 counts to generate a sixth sub-digital code value, where the sixth sub-digital code value is the difference between the digital code values ​​corresponding to the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, thereby realizing correlated double sampling, reducing noise influence, and improving imaging quality.

[0257] At the same time, the third sub-digital code value, the fourth sub-digital code value, the fifth sub-digital code value and the sixth sub-digital code value obtained by the four quantizations are finally stored in the storage circuit 50 and read out to the corresponding control circuit 3 in the read-out control signal. The control circuit 3 determines the image information according to the third sub-digital code value, the fourth sub-digital code value and the fifth sub-digital code value, and realizes automatic focus in the high conversion gain mode, thereby improving the imaging quality and user experience.

[0258] Corresponding to the signal input and output logic of the eleventh embodiment, as shown in FIG19 , optionally, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0259] The storage circuit 50 includes n storage units, each of which is connected to a counter unit and an inversion control circuit 40;

[0260] Each storage unit includes a first memory Mem1, a second memory Mem2, a third memory Mem3, a fourth memory Mem4, a NAND gate NOR1 and a first two-to-one data selector MUX1;

[0261] The input end of the first memory Mem1, the input end of the second memory Mem2, and the input end of the third memory Mem3 are simultaneously connected to a counter unit, the output end of the first memory Mem1 is connected to the first input end of the first two-to-one data selector MUX1, the output end of the second memory Mem2 is connected to the second input end of the first two-to-one data selector MUX1, the control end of the first two-to-one data selector MUX1 is used to input the write-back selection signal mem_sel, the output end of the first two-to-one data selector MUX1 is connected to the first input end of the NAND gate NOR1, the second input end of the NAND gate NOR1 is used to input the write-back control signal rewrite_en, and the NAND gate NOR1 constitutes the output end of the storage circuit 50;

[0262] The first memory Mem1 is used to store a corresponding count value of the first sub-digit code value;

[0263] The second memory Mem2 is used to store a corresponding one-bit count value in the second sub-digit code value;

[0264] The first memory Mem1, the second memory Mem2, the third memory Mem3 and the fourth memory Mem4 further store corresponding one-bit count values ​​of the third sub-digital code value, the fourth sub-digital code value, the fifth sub-digital code value and the sixth sub-digital code value respectively.

[0265] In this embodiment, the difference from the circuit structure adopted in Embodiment 9 and Embodiment 10 is that the storage circuit 50 includes four memories, n first memories Mem1 are used to store the n-bit count value of the first sub-digital code value corresponding to the low-gain reset signal lcg_rst during the reset sampling period, and n second memories Mem2 are used to store the n-bit count value of the second sub-digital code value corresponding to the high-gain reset signal hcg_rst during the reset sampling period.

[0266] At the same time, when autofocus is implemented in low gain mode or high gain mode, before the corresponding exposure sampling period, the corresponding write-back selection signal mem_sel is output to the first two-to-one data selector MUX1 according to the first sub-digital code value or the second sub-digital code value to be written back, thereby selecting the first sub-digital code value or the second sub-digital code value to be written back to n counter units through the inversion control circuit 40.

[0267] The n-bit counter unit counts pulse signals input during the reset sampling period and the exposure sampling period and generates corresponding digital code values.

[0268] After each exposure sampling period, the four quantized digital code values ​​are finally stored in the first memory Mem1, the second memory Mem2, the third memory Mem3 and the fourth memory Mem4 respectively. The four memories are read out to the corresponding control circuit 3 according to the read control signal, so that the control circuit 3 determines the image information according to the counting code value of each storage circuit 50.

[0269] Optionally, in some embodiments, the corresponding digital code value can be read out in advance through the memory and then reset, so that the memory read out in advance can be reused as a memory for subsequent digital code values, which can further reduce the number of memories and reduce the occupied area.

[0270] Example 12

[0271] Based on the optimization and specific implementation of the sixth to eleventh embodiments, optionally, as shown in FIG15 , FIG18 and FIG19 , the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0272] The inversion control circuit 40 includes n selection circuits;

[0273] The first input terminal of the i-th selection circuit is used to input the inversion control signal trig_pulse, the second input terminal of the first selection circuit 41 is used to input the clock signal count_clk, the second input terminals of the second selection circuit 42 to the n-th selection circuit are connected to the output terminal of the i-1-th stage counter unit, the third input terminal of the i-th selection circuit is used to input a low-level signal, the fourth input terminal of the first selection circuit 41 is used to input the output signal count_out of the comparison circuit 20, and the output terminal of the i-th selection circuit is connected to the input terminal of the i-th stage counter unit, where i is 1, 2, ..n;

[0274] The i-th selection circuit is triggered by the mode selection signal mode_sel and the write-back control signal rewrite_en to output the signal inputted from the first input terminal, the second input terminal or the third input terminal.

[0275] In this embodiment, the inversion control circuit 40 is used to transmit the inversion control signal trig_pulse, the written-back digital code value, and the clock signal count_clk.

[0276] Each selection circuit is connected to the front end of a counter unit, and outputs the corresponding signal of the input end to its own output end according to the received mode selection signal mode_sel. Before quantization, each counter unit is reset, and during the reset sampling period, the pixel unit outputs a reset signal to the comparison circuit 20. The comparison circuit 20 compares the reset signal with the ramp voltage signal and generates a reset pulse signal. The reset pulse signal is output to the first selection circuit 41. Each selection circuit receives the first level mode selection signal mode_sel and triggers the connection of its own second input end and output end. The first selection circuit 41 outputs the clock signal count_clk to the first counter unit 31. The subsequent selection circuit selects and outputs the count value of the previous level counter unit to the next level counter unit. The counter units at each level respectively store the first count value of the current level, and the first count values ​​of the counter units at each level are combined to generate the first digital code value.

[0277] In the inversion mode of the exposure sampling period, the mode selection signal mode_sel is switched to the second level, and each selection circuit outputs the inversion control signal trig_pulse of the first input end to the counter unit at the back end. Each counter unit switches to the inversion mode and inverts the first count value stored inside itself to the second count value or the fourth digital code value. Then, the mode selection signal mode_sel is switched to the first level again, and the inversion control signal trig_pulse also switches the level state, and each counter unit switches to the counting mode.

[0278] And in the write-back mode during the exposure sampling period, after receiving the write-back control signal rewrite_en, the storage circuit 50 writes back the stored corresponding first digital code value to the n selection circuits, and the n selection circuits write back the written-back first digital code value to the n counter units.

[0279] Continuing to refer to FIG. 15 , FIG. 18 and FIG. 19 , optionally, the first selection circuit 41 includes an AND gate AND1 , a second two-to-one data selector MUX2 , a third two-to-one data selector MUX3 and a first inverter U1 ;

[0280] The first input terminal of the AND gate AND1 is used to input the clock signal count_clk, the second input terminal of the AND gate AND1 is used to input the output signal count_out of the comparison circuit 20, the first input terminal of the second two-to-one data selector MUX2 is used to input the inversion control signal trig_pulse, the output terminal of the AND gate AND1 is connected to the second input terminal of the two-to-one data selector, the second input terminal of the second two-to-one data selector MUX2 is used to input the low-level signal tie_lo, the control terminal of the second two-to-one data selector MUX2 is connected to the output terminal of the storage circuit 50, and the second two-to-one data selector MUX2 is connected to the output terminal of the storage circuit 50. The output end of X2 is connected to the first input end of its third two-choose-one data selector MUX3, the second input end of the third two-choose-one data selector MUX3 is used to input the clock signal count_clk or the value output by the previous stage counter unit, the control end of the third two-choose-one data selector MUX3 is used to input the mode selection signal mode_sel, the output end of the third two-choose-one data selector MUX3 is connected to the input end of the first inverter U1, and the output end of the first inverter U1 is used to output a corresponding one of the inverted control signal trig_pulse, the clock signal count_clk, and the low-level signal tie_lo;

[0281] The second selection circuit 42 to the nth selection circuit respectively include a second two-to-one data selector MUX2, a third two-to-one data selector MUX3 and a first inverter U1;

[0282] The first input end of its second two-to-one data selector MUX2 is used to input the inversion control signal trig_pulse, the second input end of its second two-to-one data selector MUX2 is used to input the low-level signal tie_lo, the control end of its second two-to-one data selector MUX2 is connected to the output end of its storage circuit 50, the output end of its second two-to-one data selector MUX2 is connected to the first input end of its third two-to-one data selector MUX3, the second input end of its third two-to-one data selector MUX3 is used to input the clock signal count_clk or the value output by the previous stage counter unit, the control end of its third two-to-one data selector MUX3 is used to input its mode selection signal mode_sel, the output end of its third two-to-one data selector MUX3 is connected to the input end of its first inverter U1, and the output end of its first inverter U1 is used to output the corresponding one of the inversion control signal trig_pulse, its clock signal count_clk, the low-level signal tie_lo and the value output by the previous stage counter unit.

[0283] Continuing to refer to FIG6 , FIG8 , FIG15 , FIG18 and FIG19 , the counter unit includes a D flip-flop DFF and a second inverter U2 , or the counter unit includes a D flip-flop DFF.

[0284] In this embodiment, when the inverting output end of the D flip-flop DFF is connected to the second inverter U2 and the second inverter U2 serves as the output end of the counter unit, the counter unit constitutes an up-counter; and when the positive output end of the D flip-flop DFF constitutes the output end of the counter unit, the counter unit constitutes a down-counter. By performing operations such as inverting and writing back the reset signal, the counter unit does not need to switch between up-counting and down-counting when continuously quantizing the reset signal and the pixel signal, nor does it need to set up an additional holding circuit. Compared with the traditional counter circuit 30, the number of transistors can be reduced, thereby reducing the layout area and optimizing the routing, thereby achieving the purpose of reducing power consumption.

[0285] Referring to Figures 13 and 14, taking up counting as an example, when the selection circuit and the counter unit are applied to the ADAF mode, the timing of a complete quantization cycle in the ADAF mode is as follows:

[0286] At time t0-t1, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0287] At time t2, the reset signal is quantized. At this time, the output signal count_out of the comparison circuit 20 switches to a high level. After the clock signal count_clk is ANDed with the high level by the AND1 operation of the AND gate, the clock signal count_clk is output to the second input terminal of the third 2-to-1 data selector MUX3. At this time, the mode selection signal mode_sel is a high level, and the clock signal count_clk is selected and output to the first inverter U1 and the first D flip-flop DFF. Each D flip-flop DFF counts upward under the action of the clock signal count_clk.

[0288] At time t3, the output of the comparison circuit 20 flips, the counting stops, the reset signal quantization ends, and each D flip-flop DFF stores the count value of each bit of the first digital code value of the reset signal quantization result. The first count value output by each second inverter U2 is combined to generate the first digital code value.

[0289] At time t4-t5, the readout control signal is switched to a high level, and the first quantization result is stored in the first memory Mem1.

[0290] At time t5, the mode selection signal mode_sel switches to a low level, and each counter unit switches to the inversion mode.

[0291] At time t6, the inversion control signal trig_pulse switches to a low level, and generates a rising edge at the clock input end of each D-type flip-flop DFF through the second two-to-one data selector MUX2 and the third two-to-one data selector MUX3, and inverts the first quantization result digital code stored in each D-type flip-flop DFF as the initial state before the second quantization.

[0292] At time t7 , the mode selection signal mode_sel switches to a high level, and the counter unit returns to the counting mode; at time t8 , the inversion control circuit 40 switches to a high level.

[0293] At time t9, the pixel group signal Vsigl is quantized starting from the initial state. At time t10, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the pixel group signal Vsigl is completed, and the D flip-flop DFF stores the third digital code value of the difference between the pixel group signal Vsigl and the reset signal.

[0294] At time t11-t12, sram_wrt is enabled, and the final quantization result is stored in the second memory Mem2 and then read out.

[0295] At time t12-t13, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0296] At time t13, the mode selection signal mode_sel switches to a low level, the write-back control signal rewrite_en switches to a high level, and the counter unit switches to the write-back mode.

[0297] At time t14, the inversion control signal trig_pulse switches to a low level, and a rising edge is generated at the clock input end of the D flip-flop DFF through the second two-to-one data selector MUX2 and the third two-to-one data selector MUX3. The first digital code value stored in the first memory Mem1 is written into the n-bit counter unit and inverted as the initial state before quantization of the image signal Vsig.

[0298] At time t15 , the mode selection signal mode_sel switches to a high level, and the counter unit returns to the counting mode. At time t16 , the inversion control signal trig_pulse switches to a high level.

[0299] At time t17, the quantization of the image signal Vsig starts from the initial state. At time t18, the output of the comparison circuit 20 is flipped, the counting stops, and the quantization of the image signal Vsig is completed. The D flip-flop DFF stores the difference between the image signal Vsig and the reset signal, that is, the image quantization value of the correlated double sampling.

[0300] At time t19-t20, the readout control signal is enabled, and the final quantization result is stored in the first memory Mem1 and then read out.

[0301] Referring to Figures 13 and 15, when the selection circuit is applied to the PGHDR mode, the timing of a complete quantization cycle in the PGHDR mode is as follows:

[0302] At time t0-t1, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0303] At time t2, the low-gain reset signal lcg_rst is quantized. At this time, the output signal count_out of the comparison circuit 20 switches to a high level. After the clock signal count_clk is ANDed with the high level by the AND1 operation of the AND gate, the clock signal count_clk is output to the second input terminal of the third 2-to-1 data selector MUX3. At this time, the mode selection signal mode_sel is high, and the clock signal count_clk is selected and output to the first inverter U1 and the first D-type flip-flop DFF. Each D-type flip-flop DFF counts upward under the action of the clock signal count_clk.

[0304] At time t3, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the low gain reset signal lcg_rst is completed, and the D flip-flop DFF stores the first sub-digit code of the quantization result of the low gain reset signal lcg_rst.

[0305] At time t4-t5, the read control signal is switched to a high level, and the first sub-digital code is stored in each first memory Mem1.

[0306] At time t5-t6, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0307] At time t7, the high gain reset signal hcg_rst is quantized starting from the initial state. At time t8, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the high gain reset signal hcg_rst is completed, and the D flip-flop DFF stores the second sub-digit code of the high gain reset signal hcg_rst.

[0308] At time t9, the mode selection signal mode_sel switches to a low level, and the counter switches to the inversion mode. At time t10, the inversion control signal trig_pulse switches to a low level, and a rising edge is generated at the clock input terminal of the D-type flip-flop DFF output through the second two-to-one data selector MUX2 and the third two-to-one data selector MUX3, and the second quantization result digital code stored in each D-type flip-flop DFF is inverted to the second digital code value, which serves as the initial state before the second quantization.

[0309] At time t11, the mode selection signal mode_sel switches to a high level, and the counter unit returns to the counting mode; at time t12, the mode selection signal mode_sel switches to a high level.

[0310] At time t13, quantization of the high-gain image signal hcg_sig begins from its initial state. At time t14, the output of comparator circuit 20 flips, stopping counting and completing the quantization of the high-gain image signal hcg_sig. D-type flip-flop DFF stores the difference between the high-gain image signal hcg_sig and the reset signal, representing the image quantization value of correlated double sampling at high conversion gain. Between t15 and t16, sram_wrt is enabled, storing the final quantization result in the second memory Mem2 and subsequently reading it out.

[0311] At t16-t17, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0); at t17, the mode selection signal mode_sel switches to a low level, the write-back control signal rewrite_en switches to a high level, and the counter unit switches to write-back mode.

[0312] At time t18, the inversion control signal trig_pulse switches to a low level, generating a rising edge at the clock input terminal of the D flip-flop DFF. The first sub-digital code value corresponding to the low-gain reset signal lcg_rst stored in the first memory Mem1 is written back into the counter unit and inverted as the initial state of the low-gain image signal lcg_sig before quantization.

[0313] At time t19, the mode selection signal mode_sel switches to a high level, and the counter unit returns to the counting mode; at time t20, the negation control signal trig_pulse switches to a high level.

[0314] At time t21, quantization of the low-gain image signal lcg_sig begins from its initial state. At time t22, the output of comparator circuit 20 flips, stopping counting and completing the quantization of the low-gain image signal lcg_sig. D-type flip-flop DFF stores the difference between the low-gain image signal lcg_sig and the reset signal, representing the image quantization value of correlated double sampling at low conversion gain. Between t23 and t24, the readout control signal is enabled, storing the final quantization result in the first memory Mem1 and subsequently reading it out.

[0315] At this point, a complete quantization cycle is completed, and finally the image quantization value of the correlated double sampling under high conversion gain and the image quantization value of the correlated double sampling under low conversion gain are obtained.

[0316] When the selection circuit is used to implement the ADAF mode at low conversion gain, the timing within a complete quantization cycle is shown in Figure 16:

[0317] At time t0-t1, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0318] At time t2, the low-gain reset signal lcg_rst is quantized, and the counter counts up under the action of the high-speed clock count_clk. At time t3, the output of the comparison circuit 20 is flipped, the counting stops, and the quantization of the low-gain reset signal lcg_rst is completed. The D-type flip-flop DFF stores the first sub-digital code value of the quantization result of the low-gain reset signal lcg_rst.

[0319] At time t4-t5, the readout control signal is switched to a high level, and the first quantization result is stored in the first memory Mem1.

[0320] At time t5-t6, count_rstb switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0321] At time t7, the high gain reset signal hcg_rst is quantized starting from the initial state. At time t8, the output of the comparison circuit 20 is flipped, the counting stops, the quantization of the high gain reset signal hcg_rst is completed, and the second sub-digital code value of the high gain reset signal hcg_rst is stored in the D flip-flop DFF.

[0322] At time t9, the mode selection signal mode_sel switches to a low level, and the connections between the various stages of the counter are disconnected. At time t10, the inversion control signal trig_pulse switches to a low level, generating a rising edge at the clock input of the D-type flip-flop DFF. The digital code of the second quantization result stored in the D-type flip-flop DFF is inverted and used as the initial state before the third quantization.

[0323] At time t11, the mode selection signal mode_sel switches to a high level, and the counter returns to the counting mode; at time t12, the inversion control signal trig_pulse switches to a high level.

[0324] At time t13, quantization of the high-gain image signal hcg_sig begins from the initial state; at time t14, the output of the comparison circuit 20 is flipped, the counting stops, and the quantization of the high-gain image signal hcg_sig is completed. The D flip-flop DFF stores the difference between the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, that is, the image quantization value of the correlated double sampling under high conversion gain.

[0325] At time t15, the write-back control signal rewrite_en and the mode selection signal mode_sel are switched to high level, the counter switches to write-back mode, and the first sub-digital code value stored in the first memory Mem1 is selected to be written back into the counter; at time t15-t16, sram_wrt is enabled, and the final quantization result is stored in the second memory Mem2, and then read out.

[0326] At t16-t17, count_rstb switches to a low level, resetting the values ​​in all D-type flip-flops DFF (all outputs become 0); at t17, the mode selection signal mode_sel switches to a low level, and the connections between the various levels of the counter are disconnected; at t18, the inversion control signal trig_pulse switches to a low level, generating a rising edge at the clock input of the D-type flip-flop DFF, and writing the first sub-digital code value corresponding to the low-gain reset signal lcg_rst stored in the first memory Mem1 back to the counter unit and inverting it; as the initial state before the fourth quantization; at t19, the mode selection signal mode_sel switches to a high level, and the counter returns to the counting mode; at t20, the inversion control signal trig_pulse switches to a high level.

[0327] At time t21, quantization of the low-gain pixel group signal lcg_sigl begins from its initial state. At time t22, the output of the comparison circuit 20 flips, the counting stops, and the quantization of the low-gain pixel group signal lcg_sigl ends. The D-type flip-flop DFF stores the difference between the low-gain pixel group signal lcg_sigl and the low-gain reset signal lcg_rst, i.e., the quantized value of the correlated double sampling pixel group signal Vsigl at low conversion gain. At time t23-t24, hcg_wrt is enabled, and the final quantization result is stored in the third memory Mem3 and subsequently read out.

[0328] At time t24-t25, count_rstb switches to a low level, resetting the values ​​in all D-type flip-flops DFF (all outputs become 0); at time t25, the mode selection signal mode_sel switches to a low level, and the connections between the various levels of the counter units are disconnected; at time t26, the inversion control signal trig_pulse switches to a low level, generating a rising edge at the clock input of the D-type flip-flop DFF, writing the first digital code value stored in the first memory Mem1 back to the counter and inverting it; serving as the initial state before the fifth sub-quantization; at time t27, the mode selection signal mode_sel switches to a high level, and the counter returns to the counting mode; at time t28, the inversion control signal trig_pulse switches to a high level.

[0329] At time t29, quantization of the low-gain image signal lcg_sig begins from its initial state. At time t30, the output of comparator circuit 20 flips, stopping counting and completing the quantization of the low-gain image signal lcg_sig. D-type flip-flop DFF stores the difference between the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, representing the image quantization value of correlated double sampling at low conversion gain. Between t31 and t32, lcg_wrt is enabled, storing the final quantization result in the first memory Mem1 and subsequently reading it out.

[0330] At this point, a complete quantization cycle is completed, and the image quantization value of the correlated double sampling under high conversion gain, the pixel group quantization value of the correlated double sampling under low conversion gain, and the image quantization value of the correlated double sampling under low conversion gain are obtained in turn.

[0331] By analogy, when the selection circuit is applied to implement the ADAF mode under high conversion gain, or is applied to implement the ADAF mode under high conversion gain and low conversion gain at the same time, the selection circuit selects and outputs the corresponding inversion control signal trig_pulse or digital code value to the counter unit according to the corresponding mode selection signal mode_sel received or the written-back digital code value, so that the counter unit performs counting, inversion and other operations.

[0332] After each quantization is completed, the corresponding digital code value is stored in the corresponding memory, and each memory reads it to the control circuit 3 according to the received read control signal, so that the control circuit 3 determines the image information according to each digital code value.

[0333] In order to implement the inversion function of the D flip-flop DFF in the above embodiment, as shown in FIG20 , optionally, the D flip-flop DFF includes a third inverter U3, a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a seventh inverter U7, an eighth inverter U8, a first transmission gate tran1, a second transmission gate tran2, a third transmission gate tran3, and a fourth transmission gate tran4;

[0334] In this embodiment, the first transmission gate tran1, the fourth inverter U4, the fifth inverter U5 and the second transmission gate tran2 constitute a master latch, and the third transmission gate tran3, the sixth inverter U6, the seventh inverter U7 and the fourth transmission gate tran4 constitute a slave latch. The master latch is used to stably latch and output the input value of the D flip-flop DFF, and the slave latch is used to stably latch and output the output value of the master latch. The third inverter U3 is used to invert the input data signal and output it to the master latch. The eighth inverter U8 is used to invert and output the output value of the slave latch. When the clock signal count_clk end of the D flip-flop DFF receives a rising edge, the third inverter U3, the master latch, the slave latch and the eighth inverter U8 invert and output the latched value.

[0335] Example 13

[0336] This application also proposes an image sensor, as shown in FIG2 , which includes a pixel array 100, a control circuit 3, and a plurality of image sensor readout circuits 1. The specific structure of the image sensor readout circuit 1 refers to the above-mentioned embodiment. Since this image sensor adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above-mentioned embodiments, which will not be described in detail here. The pixel array 100 includes a plurality of pixel units arranged in an array;

[0337] The readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit 1 of each image sensor is also respectively connected to the control circuit 3 .

[0338] In this embodiment, the image sensor generally includes a control circuit 3, a pixel array 100, a readout circuit 1, and may also include a clock generator and a digital I / O port. The pixel array 100 includes a plurality of pixel units arranged in an array, and the plurality of pixel units arranged in columns are connected in common. The control circuit 3 selects the pixel units in each row via a row selection signal and sequentially outputs the pixel signals of each row to the readout circuit 1. The plurality of pixel units arranged in columns are connected to corresponding readout circuits 1. The readout circuit 1 performs analog-to-digital conversion and outputs corresponding digital code values ​​to the control circuit 3, so that the control circuit 3 determines image information based on the digital code values.

[0339] Among them, the pixel unit generally includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF and a row selection transistor SEL, wherein the photoelectric conversion element includes but is not limited to a photodiode PD, such as a Pin-type photodiode PD. At the same time, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF and the row selection transistor SEL can be one or more, that is, the structure of the pixel unit can be selected accordingly, and the specific structure is not limited. As shown in Figure 3, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, source follower transistor SF, row selection transistor SEL, wherein the cathode of the photodiode PD is connected to the first end of the transfer transistor TX, the second end of the transfer transistor TX, the first end of the reset transistor RST and the controlled end of the source follower transistor SF are all coupled to the floating diffusion node, the anode of the photodiode PD is grounded, the second end of the reset transistor RST and the first end of the source follower transistor SF are both connected to the positive power supply terminal VDD, the second end of the source follower transistor SF is connected to the first end of the row selection transistor SEL, and the second end of the row selection transistor SEL constitutes the output end of the pixel unit 2 and is used to output the corresponding pixel signal.

[0340] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A readout circuit for an image sensor, wherein: include: A ramp voltage circuit configured to output a ramp voltage signal in a first quantization time period and a second quantization time period of the pixel unit respectively; a comparison circuit, wherein a first input terminal of the comparison circuit is connected to the pixel unit, and a second input terminal of the comparison circuit is connected to the ramp voltage circuit, and is configured to compare a reset signal or a pixel signal output by the pixel unit with the ramp voltage signal, and output a reset pulse signal or a pixel pulse signal; a counter circuit connected to the comparison circuit, configured to count the first pulse signal in the first quantization time period and store the first digital code value; in the second quantization time period, the counter circuit counts the second pulse signal based on the second digital code value and stores it as a third digital code value, the first pulse signal and the second pulse signal are the reset pulse signal and the pixel pulse signal to each other; An inversion control circuit is connected to the counter circuit. Between the first quantization time period and the second quantization time period, the inversion control circuit is triggered by a mode selection signal to output an inversion control signal, so that the counter circuit is triggered by the inversion control signal to invert the first digital code value into the second digital code value and store it.

2. The readout circuit of the image sensor according to claim 1, wherein: The counter circuit is configured to count the reset pulse signal in the first quantization time period and store the first digital code value, and to count the pixel pulse signal based on the second digital code value in the second quantization time period and store it as the third digital code value; Alternatively, the counter circuit is configured to count the pixel pulse signal in the first quantization time period and store the first digital code value, and to count the reset pulse signal based on the second digital code value in the second quantization time period and store it as the third digital code value.

3. The readout circuit of the image sensor according to claim 1, wherein: The counter circuit includes a first counter unit to an nth counter unit; The negation control circuit comprises n selection circuits, the first input end of the i-th selection circuit is used to input the negation control signal, the second input end of the first selection circuit is used to input the clock signal, the third input end of the first selection circuit is used to input the output signal of the comparator, the second input end of the second selection circuit to the n-th selection circuit is connected to the output end of the i-1-th stage counter unit, the output end of the i-th selection circuit is connected to the input end of the i-th stage counter unit, i is 1, 2, ..n; The i-th selection circuit is configured to output the inverted control signal or the clock signal in response to the mode selection signal; The first counter unit to the nth counter unit are configured to count the first pulse signal in the first quantization time period, and respectively store the first count value of the current stage, and the count values ​​of the counter units at each stage are combined to generate the first digital code value; between the first quantization time period and the second quantization time period, the first counter unit to the nth counter unit are inverted by the inversion control signal to the first count value and stored as the second count value, and the count values ​​of the counter units at each stage are combined to generate the second digital code value; In the second quantization time period, the first counter unit to the nth counter unit count the second pulse signal based on the second count value and store it as a third count value, and the count values ​​of the counter units at each level are combined to generate the third digital code value.

4. The readout circuit of the image sensor according to claim 3, wherein: The first selection circuit includes an AND gate, a two-to-one data selector and a first inverter; The first input end of the AND gate is used to input the clock signal, the second input end of the AND gate is used to input the output signal of the comparator, the first input end of the two-to-one data selector is used to input the inversion control signal, the output end of the AND gate is connected to the second input end of the two-to-one data selector, the output end of the two-to-one data selector is connected to the input end of the first inverter, and the output end of the first inverter constitutes the output end of the first selection circuit; The second selection circuit to the nth selection circuit respectively include a two-to-one data selector and a first inverter. In the nth selection circuit, the first input end of its two-to-one data selector is used to input the inversion control signal, the second input end of its two-to-one data selector is used to input the numerical value output by the previous stage counter unit, the output end of its two-to-one data selector is connected to the input end of the first inverter, and the output end of the first inverter is used to constitute the output end of its selection circuit.

5. The readout circuit of the image sensor according to claim 3, wherein: The readout circuit of the image sensor further includes: A storage circuit, connected to the counter circuit, used to store the third digital code value and to be read out by a read control signal; The storage circuit comprises: n memories are respectively connected to one of the counter units and store count values ​​of corresponding bits of the third digital code value respectively.

6. The readout circuit of the image sensor according to claim 2, wherein: The first quantization time period is a reset sampling time period, the second quantization time period is a first exposure sampling time period, the reset sampling time period includes at least one, and the pixel signal includes two; The ramp voltage circuit is further configured to output a ramp voltage signal in each sampling time period; The comparison circuit is further configured to compare at least one reset signal or two pixel signals output by the pixel unit with the ramp voltage signal, and output at least one reset pulse signal and two pixel pulse signals at intervals; The counter circuit is further configured to count the at least one reset pulse signal in at least one reset sampling period and store it as at least one first digital code value, count the first pixel pulse signal based on the second digital code value in the first exposure sampling period and store it as a third digital code value, and count the second pixel pulse signal based on the fourth digital code value in the second exposure sampling period and store it as a fifth digital code value; an inversion control circuit connected to the counter circuit and the storage circuit, and before each exposure sampling period, triggered by a mode selection signal to output an inversion control signal to the counter circuit, so as to trigger the counter circuit to invert the first digital code value in the memory to generate the second digital code value or the fourth digital code value; The readout circuit of the image sensor further includes: The storage circuit is connected to the counter circuit and configured to store the at least one first digital code value and, before the second exposure sampling period, is triggered by a write-back control signal to write back one of the at least one first digital code value to the counter circuit.

7. The readout circuit of the image sensor according to claim 6, wherein: The image sensor comprises a pixel array, each pixel array comprises pixel units arranged in an array, and each readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit comprises at least four sub-pixels arranged in a 2×2 manner, wherein at least two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal; The at least one reset signal is a reset signal generated when the pixel units are reset simultaneously; The first pixel pulse signal and the second pixel pulse signal are respectively one of a pixel group pulse signal corresponding to simultaneous exposure of the pixel group and an image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit.

8. The readout circuit of the image sensor according to claim 6, wherein: The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal and the second pixel pulse signal are respectively one of a high-gain image pulse signal and a low-gain image pulse signal; The counter circuit is configured to: count one of the reset pulse signals in a first reset sampling period to generate a first digital code value; In a second reset sampling period, another reset pulse signal is counted to generate another first digital code value; In a first exposure sampling period, the first pixel pulse signal is counted based on the second digital code value and stored as a third digital code value; In a second exposure sampling period, the second pixel pulse signal is counted based on the fourth digital code value and stored as a fifth digital code value.

9. The readout circuit of the image sensor according to claim 7 or 8, wherein: The counter circuit includes a first counter unit to an nth counter unit; The storage circuit comprises n storage units, each of which is connected to one of the counter units and the inversion control circuit respectively; Each of the storage units includes a first memory, a second memory and a NAND gate; The input ends of the first memory and the second memory are respectively connected to a counter unit, the output end of the first memory is connected to the first input end of the NAND gate, the second input end of the NAND gate is used to input the write-back control signal, and the NAND gate constitutes the output end of the storage unit; The first memory is configured to store a corresponding one-bit count value of at least one first digital code value; The first memory and the second memory respectively store a corresponding one-bit count value of one of the third digital code value and the fifth digital code value.

10. The readout circuit of the image sensor according to claim 6, wherein: The image sensor comprises a pixel array, each pixel array comprises pixel units arranged in an array, and each readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit comprises at least four sub-pixels arranged in a 2×2 manner, wherein at least two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal; The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal includes a high-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the low-gain mode and a low-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit; The second exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive; The first digital code value includes a first sub-digital code value and a second sub-digital code value; The counter circuit is configured to: count the low-gain reset pulse signal in a first reset sampling period to generate a first sub-digital code value; In a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value; In the first exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as a third digital code value; The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value; In a third exposure sampling period, counting the low-gain pixel group pulse signal based on the fourth digital code value and storing it as a fifth sub-digital code value; In a fourth exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as a sixth sub-digital code value; a storage circuit connected to the counter circuit and configured to store the first sub-digital code value and write the first sub-digital code value back to the counter circuit when triggered by a write-back control signal before the third exposure sampling period and the fourth exposure sampling period; an inversion control circuit connected to the counter circuit and the storage circuit, and before each exposure sampling period, the inversion control circuit is triggered by the inversion control signal to control the counter circuit to invert the first sub-digital code value in the memory to generate the fourth digital code value, and to The second sub-digital code value is inverted to generate the second digital code value.

11. The readout circuit of the image sensor according to claim 6, wherein: The image sensor comprises a pixel array, each pixel array comprises pixel units arranged in an array, and each readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit comprises four sub-pixels arranged in a 2×2 manner, wherein two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal; The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the high-gain mode and a high-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit; The second pixel pulse signal comprises a low-gain image pulse signal; The first exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive; The first digital code value includes a first sub-digital code value and a second sub-digital code value; The counter circuit is configured to: count the low-gain reset pulse signal in a first reset sampling period to generate a first sub-digital code value; In a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value; The third digital code value includes a third sub-digital code value and a fourth sub-digital code value; In a third exposure sampling period, the high-gain pixel group pulse signal is counted based on the second digital code value and stored as a third sub-digital code value; In a fourth exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as a fourth sub-digital code value; In a second exposure sampling period, counting the low-gain image pulse signal based on the fourth digital code value and storing it as a fifth digital code value; a storage circuit connected to the counter circuit, configured to store the first sub-digital code value and the second sub-digital code value, and before the fourth exposure sampling period and the second exposure sampling period, triggered by a write-back control signal to write the second sub-digital code value and the first sub-digital code value back to the counter circuit; The inversion control circuit is connected to the counter circuit and the storage circuit. Before each exposure sampling period, the inversion control circuit is triggered by the inversion control signal to control the counter circuit to invert the second sub-digital code value of the memory to generate the second digital code value, and to invert the first sub-digital code value to generate the fourth digital code value.

12. The readout circuit of the image sensor according to claim 10 or 11, wherein: The counter circuit includes a first counter unit to an nth counter unit; The storage circuit comprises n storage units, each of which is connected to one of the counter units and the inversion control circuit respectively; Each of the storage units includes a first memory, a second memory, a third memory, a NAND gate and a first two-to-one data selector; The input end of the first memory, the input end of the second memory and the input end of the third memory are connected to the counter unit at the same time, the output end of the first memory is connected to the first input end of the first two-to-one data selector, the output end of the second memory is connected to the second input end of the first two-to-one data selector, the control end of the first two-to-one data selector is used to input a write-back selection signal, the output end of the first two-to-one data selector is connected to the first input end of the NAND gate, the second input end of the NAND gate is used to input the write-back control signal, and the NAND gate constitutes the output end of the storage circuit; The first memory is used to store a corresponding one-bit count value in the first sub-digit code value; The second memory is used to store a corresponding one-bit count value in the second sub-digit code value; The first memory, the second memory and the third memory also respectively store a corresponding one-bit count value in the three digital code values ​​after three exposure samplings.

13. The readout circuit of the image sensor according to claim 6, wherein: The image sensor comprises a pixel array, each pixel array comprises pixel units arranged in an array, and each readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, wherein the pixel unit comprises four sub-pixels arranged in a 2×2 manner, wherein two sub-pixels constitute a pixel group and are controlled to simultaneously output a reset signal or a pixel signal; The reset sampling period includes a first reset sampling period and a second reset sampling period that are consecutive, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal includes a first pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the high gain mode and a first image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit; The second pixel pulse signal includes a second pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the low gain mode and a second image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit; The first exposure sampling period includes a third exposure sampling period and a fourth exposure sampling period that are consecutive; The second exposure sampling period includes a fifth exposure sampling period and a sixth exposure sampling period that are consecutive; The first digital code value includes a first sub-digital code value and a second sub-digital code value; The counter circuit is configured to: count the low-gain reset pulse signal in a first reset sampling period to generate a first sub-digital code value; In a second reset sampling period, the high-gain reset pulse signal is counted to generate a second sub-digital code value; The third digital code value includes a third sub-digital code value and a fourth sub-digital code value; In a third exposure sampling period, counting the first pixel group pulse signal based on the second digital code value and storing it as a third sub-digital code value; In a fourth exposure sampling period, the first image pulse signal is counted based on the second digital code value and stored as a fourth sub-digital code value; The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value; In a fifth exposure sampling period, the second pixel group pulse signal is counted based on the fourth digital code value and stored as a fifth sub-digital code value; In a sixth exposure sampling period, counting the second image pulse signal based on the fourth digital code value and storing it as a sixth sub-digital code value; a storage circuit connected to the counter circuit, configured to store the first sub-digital code value and the second sub-digital code value, and to write the second sub-digital code value back to the counter circuit before a fourth exposure sampling period under the triggering of a write-back control signal, and to write the first sub-digital code value back to the counter circuit before a fifth exposure sampling period and a sixth exposure sampling period under the triggering of a write-back control signal; The inversion control circuit is connected to the counter circuit and the storage circuit. Before each exposure sampling period, the inversion control circuit is triggered by the inversion control signal to control the counter circuit to invert the second sub-digital code value of the memory to generate the second digital code value, and to invert the first sub-digital code value to generate the fourth digital code value.

14. The readout circuit of the image sensor according to claim 13, wherein: The counter circuit includes a first counter unit to an nth counter unit; The storage circuit includes n storage units, each of which is respectively connected to a counter unit and the inversion control circuit. connect; Each of the storage units includes a first memory, a second memory, a third memory, a fourth memory, a NAND gate and a first two-to-one data selector; The input end of the first memory, the input end of the second memory and the input end of the third memory are connected to the counter unit at the same time, the output end of the first memory is connected to the first input end of the first two-to-one data selector, the output end of the second memory is connected to the second input end of the first two-to-one data selector, the control end of the first two-to-one data selector is used to input a write-back selection signal, the output end of the first two-to-one data selector is connected to the first input end of the NAND gate, the second input end of the NAND gate is used to input the write-back control signal, and the NAND gate constitutes the output end of the storage circuit; The first memory is used to store a corresponding one-bit count value in the first sub-digit code value; The second memory is used to store a corresponding one-bit count value in the second sub-digit code value; The first memory, the second memory, the third memory and the fourth memory also store corresponding one-bit count values ​​of the third sub-digital code value, the fourth sub-digital code value, the fifth sub-digital code value and the sixth sub-digital code value respectively.

15. The readout circuit of the image sensor according to claim 6, wherein: The counter circuit includes a first counter unit to an nth counter unit; The negation control circuit includes n selection circuits; The first input end of the i-th selection circuit is used to input the negation control signal, the second input end of the first selection circuit is used to input the clock signal, the second input end of the second selection circuit to the n-th selection circuit is connected to the output end of the i-1-th level counter unit, the third input end of the i-th selection circuit is used to input a low level signal, the fourth input end of the first selection circuit is used to input the output signal of the comparison circuit, the output end of the i-th selection circuit is connected to the input end of the i-th level counter unit, i is 1, 2, ..n; The i-th selection circuit is triggered by the mode selection signal and the write-back control signal to output the signal inputted from the first input terminal, the second input terminal or the third input terminal.

16. The readout circuit of the image sensor according to claim 15, wherein: The first selection circuit includes an AND gate, a second two-to-one data selector, a third two-to-one data selector, and a first inverter; The first input end of the AND gate is used to input the clock signal, the second input end of the AND gate is used to input the output signal of the comparison circuit, the first input end of the second two-to-one data selector is used to input the inversion control signal, the output end of the AND gate is connected to the second input end of the two-to-one data selector, the second input end of the second two-to-one data selector is used to input the low-level signal, the control end of the second two-to-one data selector is connected to the output end of the storage circuit, the output end of the second two-to-one data selector is connected to the first input end of the third two-to-one data selector, the second input end of the third two-to-one data selector is used to input the clock signal or the value output by the previous stage counter unit, the control end of the third two-to-one data selector is used to input the mode selection signal, the output end of the third two-to-one data selector is connected to the input end of the first inverter, and the output end of the first inverter is used to output a corresponding one of the inversion control signal, the clock signal and the low-level signal; The second selection circuit to the nth selection circuit respectively include a second two-to-one data selector, a third two-to-one data selector and a first inverter; The first input end of its second two-to-one data selector is used to input an inversion control signal, the second input end of its second two-to-one data selector is used to input a low-level signal, the control end of its second two-to-one data selector is connected to the output end of its storage circuit, the output end of its second two-to-one data selector is connected to the first input end of its third two-to-one data selector, the second input end of its third two-to-one data selector is used to input a clock signal or a numerical value output by a previous-stage counter unit, the control end of its third two-to-one data selector is used to input its mode selection signal, the output end of its third two-to-one data selector is connected to the input end of its first inverter, and the output end of its first inverter is used to output a corresponding one of the inversion control signal, its clock signal, a low-level signal, and the numerical value output by the previous-stage counter unit.

17. The readout circuit of the image sensor according to claim 3 or 15, wherein: The counter unit includes a D flip-flop and a second inverter; The clock signal end of the D flip-flop of the i-th counter unit is connected to the signal output end of the i-th selection circuit, the inverting output end of the D flip-flop of the i-th counter unit is connected to the input end of the second inverter and the data input end of the D flip-flop, and the output end of the second inverter is connected to the second input end of the (i+1)-th selection circuit.

18. The readout circuit of the image sensor according to claim 3 or 15, wherein: The counter unit comprises a D flip-flop; The clock signal terminal of the D flip-flop of the i-th counter unit is connected to the signal output terminal of the i-th selection circuit, the inverting output terminal of the D flip-flop of the i-th counter unit is connected to the data input terminal of the D flip-flop, and the positive output terminal of the D flip-flop is connected to the second input terminal of the i+1-th selection circuit.

19. An image sensor, wherein: A method of manufacturing an image sensor comprising a pixel array, a control circuit, and a plurality of readout circuits of the image sensor according to claim 1, wherein the pixel array comprises a plurality of pixel units arranged in an array; The readout circuit of each of the image sensors is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit of each of the image sensors is also respectively connected to the control circuit.

Images