Memory page processing method, device and apparatus, and storage medium

Abstract

The present application belongs to the technical field of communications. Disclosed are a memory page processing method, device and apparatus, and a storage medium. In the method, a memory page is allocated to a virtual address which causes a page fault, the allocated memory page is then filled with first data in advance, and the memory page filled with the first data is then accessed. If data is subsequently migrated from the memory page to a cache, the first data filled in the memory page is also migrated to the cache. If the data of the memory page is eliminated from the cache and transferred to a memory, the eliminated cache data may also comprise the first data. Since the first data is data in a data sequence corresponding to a cache compression mode, when the cache data comprising the first data is eliminated and transferred back to the memory, the probability of the cache data matching the cache compression mode can be increased, such that the compression rate of the cache data can be increased.

Description

Memory page processing method, device, apparatus and storage medium

[0001] This application claims priority to Chinese patent application No. 202310740304.0, filed on June 20, 2023, entitled “A Memory Setting Method,” the entire contents of which are incorporated herein by reference.

[0002] This application claims priority to Chinese patent application No. 202311086477.1 filed on August 25, 2023, entitled “Method, device, apparatus and storage medium for processing memory pages,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of communication technology, and in particular to a method, device, apparatus, and storage medium for processing a memory page. Background Art

[0004] To alleviate the performance bottleneck caused by the memory wall, related technologies attempt to bridge the performance gap between the central processing unit (CPU) and memory through optimization at the microarchitecture level. For example, chip microarchitecture design attempts to reduce the amount of data in off-chip communication through cache compression technologies such as frequent pattern compression (FPC). Specifically, when data in the CPU's cache is evicted from a cache line to the memory, the memory management unit (MMU) compresses the data in the cache line according to the cache compression pattern that matches the data in the cache line to obtain compressed data, and then stores the compressed data in the memory to achieve the purpose of evicting the cache line data to the memory.

[0005] However, in addition to the data written by the application, there may also be some random values ​​in the cache line, which causes the data in the cache line to not match the data compression pattern well. When the data that does not match the data compression pattern is eliminated from the cache line, it cannot be stored in the memory in a compressed manner, which reduces the compression rate of the cached data when the cache eliminates the data from the memory.

[0006] Summary of the Invention

[0007] The present invention provides a method, device, apparatus, and storage medium for processing memory pages, which can improve the compression rate of cached data. The technical solution is as follows:

[0008] In a first aspect, a method for processing a memory page is provided, the method comprising the following steps: when a virtual address accessed by an application (referred to as a first address virtual) causes a page fault interrupt, a memory page (referred to as a first memory page) is allocated to the first virtual address; thereafter, the first memory page is filled with: data in a data sequence corresponding to a cache compression mode (referred to as first data), wherein the cache compression mode is a data compression mode used when migrating data written by an application in a cache to a memory page; and then, based on the first virtual address, the filled first memory page is accessed.

[0009] This method pre-fills the allocated memory page with the first data after allocating the memory page for the virtual address that caused the page fault interrupt, and then accesses the memory page filled with the first data. If the data in the memory page is subsequently migrated to the cache, the first data filled in the memory page will also be migrated to the cache. If the data of the memory page in the cache is eliminated to the main memory, the eliminated cache data may also include the first data. Since the first data is data in the data sequence corresponding to the cache compression mode, when the cache data including the first data is eliminated back to the main memory, the probability of the cache data matching the cache compression mode can be increased, thereby improving the compression rate of the cache data.

[0010] In one possible implementation, the above-mentioned process of filling the first data in the first memory page may be: when the application turns on the memory pre-filling function, filling the first data in the first memory page, wherein the memory pre-filling function indicates filling the first data in the empty memory page before the application accesses the empty memory page.

[0011] Based on the above possible implementation methods, the first data will be pre-filled for the memory pages allocated to the application only when the memory pre-filling function is turned on by the application. There is no need to pre-fill the first data for the memory pages allocated to each running application, which reduces the workload of filling the first data.

[0012] In a possible implementation, when the application enables the memory pre-filling function, before filling the first memory page with the first data, the method further includes the following steps: based on the running status of the application, periodically enabling the memory pre-filling function for the application.

[0013] In one possible implementation, when the application turns on the memory pre-filling function, before filling the first memory page with the first data, the method also includes the following steps: when the type of the application is a target type, turning on the memory pre-filling function for the application, and the target type application applies the cache compression mode.

[0014] Based on the above possible implementation methods, the memory pre-filling function will only be enabled for the application when the cache compression mode is applicable to the application, so that during the operation of the application, the first data can be pre-filled for the memory pages of the application to improve the compression efficiency of the application data when migrating from the cache to the memory, and it can also avoid filling the memory pages of the application that is not applicable to the cache compression mode with the first data, thereby reducing the workload of filling the first data.

[0015] In one possible implementation, the above-mentioned access to the filled first memory page based on the first virtual address includes the following steps: first receiving a first write request from the application, the first write request instructing to write the second data to the first virtual address, and then updating the first data at the position corresponding to the first virtual address in the first memory page to the second data.

[0016] Based on the above possible implementation methods, the first data is the data filled by the application before the memory page. When the application subsequently writes data to the memory page, it only needs to update the first data to the data to be written. In this way, the cache compression rate can be improved by pre-filling the first data without affecting the normal writing of data by the application.

[0017] In one possible implementation, multiple second memory pages are used to store task data of the same computing task of an application, and multiple second memory pages are filled with first data. The method also includes the following steps: receiving a second write request from the application, the second write request instructing to write task data to a second virtual address; updating the first data at the corresponding position of the second virtual address in the multiple second memory pages to task data.

[0018] Based on the above possible implementation methods, multiple memory pages corresponding to the same computing task have been filled with the first data. When writing task data to any memory page, the first data in any memory page can be updated to the task data. Even if any memory page among the multiple memory pages has not written task data, due to the existence of the first data, no random value will be written to the memory page, thereby avoiding the random value affecting the compression of the cache data of the memory page, thereby improving the cache compression rate.

[0019] In one possible implementation, the first data is each data in the data sequence; or, the first data is the S data with the highest frequency of occurrence in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0020] Based on the above possible implementation method, the first data in the data sequence is filled in the first memory page. If the data of the first memory page is subsequently migrated to the cache, when the cache data of the first memory page is migrated from the cache, part of the first data in the cache data may still remain in the cache, so that the cache data is easier to match the data compression pattern, so as to further improve the compression rate of the cache data.

[0021] In one possible implementation, the first data is the S data with the highest occurrence frequency in multiple data sequences, the multiple data sequences correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0022] Based on the above possible implementation method, the first data in multiple data sequences is filled in the first memory page. If the data of the first memory page is subsequently migrated to the cache, when the cache data of the first memory page is migrated from the cache, some of the first data in the cache data may still remain in the cache, so that the cache data is easier to match these multiple data compression patterns, thereby increasing the probability of the cache data matching the data compression pattern, thereby further improving the compression rate of the cache data.

[0023] In the second aspect, a method for processing a memory page is provided, which includes the following steps: after obtaining an allocation notification message, filling a first memory page with first data, wherein the allocation notification message is used to notify a page fault interrupt caused by an application accessing a first virtual address, and a first memory page has been allocated for the first virtual address. The first data is data in a data sequence corresponding to a cache compression mode, and the cache compression mode is a data compression mode used when migrating data written by an application in the cache to a memory page.

[0024] In one possible implementation, filling the first data in the first memory page includes the following steps: filling the first data in the first memory page when the application turns on the memory pre-filling function, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

[0025] In a possible implementation, when the application enables the memory pre-filling function, before filling the first memory page with the first data, the method further includes the following steps: based on the running status of the application, periodically enabling the memory pre-filling function for the application.

[0026] In one possible implementation, when the application turns on the memory pre-filling function, before filling the first memory page with the first data, the method also includes the following steps: when the type of the application is a target type, turning on the memory pre-filling function for the application, and the target type application applies the cache compression mode.

[0027] In one possible implementation, the first data is each data in the data sequence; or, the first data is the S data with the highest frequency of occurrence in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0028] In one possible implementation, the first data is the S data with the highest occurrence frequency in multiple data sequences, the multiple data sequences correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0029] In a third aspect, a memory page processing device is provided, which includes a functional module for executing the memory page processing method provided by the first aspect or any optional method of the first aspect.

[0030] In a fourth aspect, a memory filling device is provided, which includes a functional module for executing the memory page processing method provided by the second aspect or any optional method of the second aspect.

[0031] In a fifth aspect, an electronic device is provided, which includes a processor, wherein the processor is used to execute program code so that the electronic device performs operations performed to implement the memory page processing method provided in the first aspect or any optional method of the first aspect.

[0032] In the sixth aspect, a memory filling device is provided, which includes a processor, and the processor is used to execute program code so that the memory filling device performs the operations performed by the memory page processing method provided in the second aspect or any optional method of the second aspect.

[0033] In the seventh aspect, a computer-readable storage medium is provided, which stores at least one program code, and the program code is read by a processor to enable an electronic device to perform the operations performed by the memory page processing method provided in the first aspect or any optional method of the first aspect.

[0034] In an eighth aspect, a computer-readable storage medium is provided, in which at least one program code is stored. The program code is read by a processor to enable a memory filling device to perform the operations performed by the memory page processing method provided in the second aspect or any optional method of the second aspect.

[0035] In the ninth aspect, a computer program product or computer program is provided, which includes a program code, and the program code is stored in a computer-readable storage medium. The processor of an electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code, so that the electronic device executes the method provided in the above-mentioned first aspect or various optional implementations of the first aspect.

[0036] In the tenth aspect, a computer program product or computer program is provided, which includes a program code, which is stored in a computer-readable storage medium. The processor of the memory filling device reads the program code from the computer-readable storage medium, and the processor executes the program code, so that the memory filling device executes the method provided in the above-mentioned second aspect or various optional implementations of the second aspect.

[0037] Based on the implementation methods provided in the above aspects, this application can also be further combined to provide more implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a diagram illustrating an electronic device architecture that uses a method for processing memory pages according to an embodiment of the present application;

[0039] FIG2 is a flow chart of a method for processing a memory page provided in an embodiment of the present application;

[0040] FIG3 is a diagram illustrating an electronic device architecture that uses another method for processing memory pages according to an embodiment of the present application;

[0041] FIG4 is a flow chart of another method for processing a memory page provided in an embodiment of the present application;

[0042] FIG5 is a schematic diagram of an application accessing memory provided by an embodiment of the present application;

[0043] FIG6 is a schematic structural diagram of a memory page processing device provided in an embodiment of the present application;

[0044] FIG7 is a schematic structural diagram of a memory filling device provided in an embodiment of the present application;

[0045] FIG8 is a schematic structural diagram of another memory filling device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to facilitate understanding of the specific implementation of the present application, some of the nouns involved in the specific implementation are introduced as follows.

[0047] Memory page: Divide the memory space into partitions of equal size. Each partition is a memory page. Each memory page is referred to by a physical page number. Different memory pages have different physical page numbers. Memory pages are also called physical blocks or page frames.

[0048] Virtual page: Divide the virtual address space of an application into regions of equal size. The size of each region is equal to the size of a memory page. Each region is a virtual page. Each virtual page is referred to by a virtual page number. Different virtual pages have different virtual page numbers. Virtual pages are also called pages or pages.

[0049] Page table: includes multiple page table entries (PTE), each PPE includes a virtual page number of a virtual page, a physical page number of a physical page and a valid flag to indicate that the virtual page is mapped to the memory page (i.e., whether the virtual page is called into the memory page). The value of the valid flag is used to indicate whether the mapping relationship between the virtual page and the physical page is valid (i.e., whether the PTE is valid). For example, the valid flag value is 1, indicating that the mapping relationship is valid and the virtual page has been called into the memory page. The valid flag value is 0, indicating that the mapping relationship is invalid and the virtual page has not been called into the memory page.

[0050] Page fault interrupt: When an application accesses a virtual page, the memory management unit (MMU) queries the page table to determine whether the virtual page to be accessed has been loaded into the memory page. Whenever the virtual page is not loaded into the memory page, a page fault interrupt is generated. The operating system allocates a memory page for the virtual page from the memory requested by the application and loads the virtual page into the allocated memory page to resolve the page fault interrupt.

[0051] Virtual address (VA): is an address in the virtual address space. The virtual address space includes multiple virtual addresses. A virtual address includes a virtual page number of a virtual page and an offset within the page. The offset within the page indicates the address offset of the virtual address in the virtual page.

[0052] Physical address (PA): It is an address in the physical address space. The physical address space is the space provided by the memory. The physical address space includes multiple physical addresses. The physical address includes the physical page number of a physical page and the offset within the page. The offset within the page indicates the address offset of the physical address in the memory page.

[0053] Cache compression algorithm: The data compression algorithm used when migrating data in the cache (referred to as cache data) to a memory page. The cache compression algorithm defines at least one cache compression mode, the data compression method for each cache compression mode, and the data sequence required by each cache compression mode. Different cache compression modes require different data sequences. The cache compression mode is the data compression mode used when migrating cache data to a memory page. When the cache data to be compressed is the same as (i.e., matches) the data sequence required by any cache compression mode, the cache compression scheme used for any cache compression mode can be used to compress the cache data to be compressed. If the cache data to be compressed is different from the data sequence required by at least one cache compression mode, the cache data to be compressed cannot be compressed. The data sequence required by any cache compression mode includes N (N>1) data. The N data are N values ​​in the same N-base. Therefore, the data sequence can also be called a value sequence. Taking hexadecimal as an example, each of the N data is a value from 0 to F in hexadecimal. Taking decimal as an example, each data is a value from 0 to 9 in decimal. The N data may be the same value or different values. Each of the N data is stored in binary data. When stored, each data is represented by a binary value (0 / 1) of M bits (M>0). Taking N=16 and M=4 as an example, a hexadecimal data is represented by a 4-bit binary value. When stored, the length of the data sequence is M*N bits.

[0054] FPC: A cache compression algorithm based on cache line compression / decompression. Each cache line is divided into 32-bit words. For example, a 64-byte cache line is 16 words. Each 32-bit word is encoded as a 3-bit prefix plus the data. Specifically, FPC defines seven cache compression modes: zero run mode, 4-bit sign-extended mode, 1-byte sign-extended mode, halfword sign-extended mode, halfword padded with a zero halfword mode, two halfwords (each a byte sign-extended) mode, and word consisting of repeated bytes mode. Each cache compression mode corresponds to a 3-bit prefix (prefix), which is the corresponding data compression method. Taking the zero-run mode as an example, the prefix corresponding to the zero-run mode is 000. The data sequence required by the zero-run mode is a 32-bit word represented by the value 0. If the cache data to be compressed is a 32-bit word and the cache data is 0x0000000000000000, then the cache data matches the zero-run mode. The zero-run mode is used to compress the cache data to obtain compressed data 0x0, that is, the compressed data is 0-bit data + 3-bit prefix.

[0055] First data: data pre-filled in an empty memory page by the memory filling device before the application reads or writes data to the empty memory page. An empty memory page refers to a memory page without any data written thereto.

[0056] Memory pre-fill function: indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

[0057] Next, the application environment of the memory page processing method provided by this application is introduced with reference to the accompanying drawings.

[0058] Figure 1 is an electronic device architecture diagram of a method for processing an application memory page provided in an embodiment of the present application. The electronic device 100 shown in Figure 1 can be a terminal, a server or a network device. Here, the embodiment of the present application does not limit the device type of the electronic device 100.

[0059] As shown in FIG1 , an electronic device 100 includes a processor core 101, a performance monitoring unit (PMU) 102, a translation lookaside buffer (TLB) 103, an MMU 104, a memory filling device 105, a memory 106, and a bus 107. The processor core 101, the PMU 102, the MMU 104, and the TLB 103 are all integrated into a central processing unit (CPU). The CPU includes one or more processor cores 101. The CPU may also include a cache, which is used to cache data stored in the memory 106. The cache in the CPU may also be a multi-level cache, such as a level 1 cache to a level 3 cache, or a level 1 cache and a level 2 cache. The embodiment of the present application does not limit the number of caches in the CPU or the level of the cache. The MMU 104 communicates with the memory 106 via the bus 107. The memory 106 is also called the main memory.

[0060] The processor core 101 is used to run applications. One processor core 101 can run one or more applications. During the running of the application in the processor core 101, the application performs read and write access (i.e., read access or write access) to the virtual page. The processor core 101 performs read and write access to the memory page corresponding to the virtual page in the memory 106 through the MMU 104 to complete the read and write access to the virtual page, where read access refers to reading data on the page, and write access refers to writing data on the page.

[0061] PMU102 is a performance monitoring component embedded in the CPU, which is used to count specific hardware events (called PMU events) occurring in the CPU, such as events related to the processor core, events related to the cache, and events related to the TLB. Among them, events related to the processor core include the number of instructions executed, captured exceptions, clock cycles, branch prediction errors, etc., events related to the cache include the number of cache accesses at each level, cache misses, etc., and events related to TLB103 include TLB misses.

[0062] The TLB 103 is used to cache page table entries in the page table, which is stored in the memory 106. The MMU 104 is a component used to manage the memory 106 and is also called a memory management unit. The MMU 104 can translate the virtual addresses accessed by the application into physical addresses in the memory 106 and access the physical addresses. For example, when the processor core 101 is running an application, it sends the virtual address to the MMU 104. The MMU 104 searches the page table entries cached in the TLB 103 for the virtual page number in the virtual address. If a PTE containing the virtual page number is found, a TLB hit occurs. If the PTE containing the virtual page number is not found in TLB103, a TLB miss occurs. MMU104 queries the PTE containing the virtual page number from the page table in memory 106, and composes the physical address from the physical page number in the queried PTE and the address offset in the virtual address to achieve virtual address to physical address conversion. Read and write access is performed on the location indicated by the physical address in memory 106 to achieve read and write access to the virtual address. During the application program execution, MMU104 migrates data frequently accessed by the application program in memory 106 to the last level cache (LLC) in the CPU. When the space in the LLC is insufficient, the MMU can evict cache data in at least one cache line in the LLC back to memory 106. In the process of evict cache data from memory 106, a cache compression algorithm can be used to migrate cache data to memory 106.

[0063] When the virtual page accessed by the application is not loaded into the memory page, a page fault interrupt is triggered. In response to the page fault interrupt, the operating system loads the virtual page into a memory page in the memory 106. The loaded memory page is an empty memory page without any data. For this empty memory page, the memory filling device 105 is used to pre-fill the memory page with the first data before the application accesses the loaded virtual page. In this way, when the application subsequently writes data to the virtual page, the first data at the to-be-written location in the memory page can be updated with the to-be-written data. Optionally, before filling the memory page with the first data, the memory filling device 105 can also first determine whether the application to which the memory page belongs has enabled the memory pre-fill function. If the memory pre-fill function is enabled, the first data is filled into the memory page; otherwise, the first data is not filled into the memory page. For example, the memory filling device 105 can enable the memory pre-fill function for the application based on the PMU events monitored by the PMU 102 during the application's operation. This process will be described in detail later in conjunction with the method embodiment.

[0064] The memory filling device 105 can be implemented by software, hardware, or a combination of software and hardware. As an example of a software functional unit, the memory filling device 105 includes program code, and the processor core 101 implements the functions of the memory filling device 105 by running the program code.

[0065] As an example of a hardware functional unit, the memory filling device 105 may be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be implemented using a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0066] When the memory filling device 105 serves as a hardware functional unit, the memory filling device 105 is integrated into the MMU 104 or is independent of the MMU 104. For example, the memory filling device 105 is located outside the MMU 104 in the CPU or is located outside the CPU in the electronic device where the electronic device 100 is located. Here, the embodiment of the present application does not limit the location of the memory filling device 105.

[0067] Optionally, as shown in FIG1 , the memory filling device 105 includes a judgment unit 51 and a filling unit 52. The judgment unit 51 is configured to determine whether the application to which the memory page belongs has enabled the memory pre-fill function, and is further configured to enable the memory pre-fill function for the application based on PMU events monitored by the PMU 102 during the application's operation. The filling unit 52 is configured to pre-fill the memory page with the first data, or not pre-fill the memory page with the first data, based on the judgment result of the judgment unit 51. Any sub-unit in the judgment unit 51 and the filling unit 52 can be implemented in software, hardware, or a combination of software and hardware. For example, in the case where both the judgment unit and the filling unit 52 are implemented in hardware, as shown in FIG1 , the filling unit 52 is integrated into the MMU 104, and the judgment unit 51 is independent of the MMU 104. In other embodiments, the filling unit 52 and the judgment unit 51 are both integrated into the MMU 104 or independent of the MMU 104.

[0068] Next, in conjunction with FIG2 , a process of pre-filling a memory page with the first data by the memory filling apparatus is described in detail.

[0069] Figure 2 is a flow chart of a memory page processing method provided in an embodiment of the present application. The method is applied to an electronic device, such as electronic device 100. The method is implemented by the operating system, memory filling device and MMU in the electronic device through interaction. The method includes the following steps.

[0070] 201. When a first virtual address accessed by an application causes a page fault interrupt, the operating system allocates a first memory page to the first virtual address.

[0071] Among them, the application is any application running on any processor core in any CPU of the electronic device, the application corresponds to a virtual address space, the first virtual address is any virtual address in the virtual address space, for the convenience of description, the virtual page number in the first virtual address is called the first virtual page number, the virtual page indicated by the first virtual page number is called the first virtual page, the first virtual page is the virtual page accessed by the application, and the memory page is allocated to the first virtual address, that is, the memory page is allocated to the first virtual page. This step 201 also means that when the first virtual page accessed by the application causes a page fault interrupt, the operating system allocates a memory page to the first virtual page, and the first memory page is the memory page allocated by the operating system to the first virtual page.

[0072] In one possible implementation, when a processing core in an electronic device is running an application, if a page fault interrupt is caused by accessing a first virtual address, the processing core notifies the operating system of the page fault interrupt, and the operating system allocates a memory page for the first virtual page and loads the first virtual page into the memory page to end the page fault interrupt. Next, in conjunction with the electronic device architecture diagram shown in FIG3 and the flowchart of another memory page processing method shown in FIG4, the triggering process and processing flow of the page fault interrupt are described as follows:

[0073] Step A1: When running an application, the processor core sends a first read / write request to the MMU. The first read / write request includes a first virtual address to instruct to read or write data to the first virtual address.

[0074] Among them, reading and writing data to the first virtual address means performing read and write access to the first virtual address, and the first read and write request is a write request or a read request. When the first read and write request is a write request, the first read and write request also includes data to be written (called second data), and the first read and write request indicates writing the second data to the first virtual address. When the first read and write request is a read request, the first read and write request indicates reading the data stored at the first virtual address.

[0075] Exemplarily, when the processor core executes any instruction (referred to as a first instruction) in an application program, if there is a need to access a first virtual address, the processor core sends a first read / write request to the MMU.

[0076] Step A2: The MMU receives the first read / write request and queries the PTE (referred to as the first PTE) corresponding to the first virtual address based on the first read / write request. The first PTE is the PTE in the page table that includes the first virtual page number.

[0077] As shown in Figure 3, the MMU first requests the TLB to query the first PTE. If the TLB finds the first PTE in the locally cached PTEs, the TLB returns the first PTE to the MMU. If the first PTE is not found in the TLB, the MMU requests the memory to query the page table for the first PTE. If the memory finds the first PTE in the page table, the memory returns the first PTE to the MMU. In this way, the MMU can query the first PTE from the TLB or memory.

[0078] As shown in Figure 3, if the TLB does not cache the first PTE and the page table includes the first PTE, as the application runs, the MMU can also cache the first PTE in the page table in the TLB so that the first PTE can be found in the TLB when the application subsequently accesses the first virtual page. After the first PTE is cached in the TLB, the TLB may also evict the first PTE from the page table as the application runs.

[0079] After obtaining the first PTE, if the valid flag in the first PTE is not 0, for example, the valid flag in the first PTE is 1, the MMU is triggered to execute the following steps A3 and A4. If the valid flag in the first PTE is 0, the MMU jumps to execute the following step A5.

[0080] Step A3: When the valid flag in the first PTE is not 0, the MMU constructs a first physical address to be accessed based on the first PTE and the first virtual address, and accesses the first physical address in the memory.

[0081] The first physical address is a physical address corresponding to the first virtual address, that is, a physical address converted from the first virtual address. The first virtual address is accessed by accessing the first physical address.

[0082] For example, the MMU combines the memory page number in the first PTE (referred to as the first memory page number) with the intra-page offset in the first virtual address to obtain a first physical address. When the first read / write request is a read request, the MMU reads the data stored at the first physical address in the first memory page (referred to as the fourth data) to access the first physical address. When the memory access request is a write request, the MMU writes the second data to the first physical address in the first memory page to access the first physical address.

[0083] Step A4: The MMU sends a read / write completion response to the processor core, where the read / write completion response indicates that the reading and writing of data to the first virtual address is completed. At this point, the process of accessing the first virtual address ends.

[0084] Among them, when the first read / write request is a read request, the read / write completion response is a read completion response, indicating that the data has been read at the first virtual address. At this time, the read / write completion response also includes the fourth data read from the first physical address. When the first read / write request is a write request, the read / write completion response is a write completion response, indicating that the second data has been written at the first virtual address.

[0085] Step A5: When the valid flag in the first PTE is 0, the MMU sends a read / write failure response to the processor core, where the read / write failure response indicates that the read / write of the first virtual address fails due to the lack of a corresponding memory page.

[0086] Step A6: Based on the read / write failure response, the processor core suspends the first instruction, triggers a page fault interrupt, and sends a page fault interrupt notification message to the operating system. The page fault interrupt notification message indicates that a page fault occurs on the first virtual page.

[0087] The page fault interrupt notification message includes the first virtual page number.

[0088] Step A7: The operating system receives the page fault interrupt notification message and allocates a first memory page to the first virtual page based on the page fault interrupt notification message to perform page fault exception processing.

[0089] As shown in Figure 4, after receiving the page fault interrupt notification message, the operating system queries whether there are any unoccupied memory pages from the memory pages allocated to the application. The memory pages allocated to the application are memory pages in the memory space allocated to the application by the operating system when the application applies for memory. The application is allocated multiple memory pages. The unoccupied memory pages refer to memory pages that have not been called into the virtual pages, that is, memory pages that have no valid mapping relationship with the virtual pages in the page table.

[0090] If there are unoccupied memory pages among the memory pages allocated to the application, the operating system allocates any unoccupied memory page to the first virtual page. Exemplarily, as shown in FIG3 , the operating system sends a first memory allocation request to the MMU, wherein the first memory allocation request includes a first virtual page number and the physical page number of the memory page to indicate that the memory page is allocated to the first virtual page. After receiving the first memory allocation request, the MMU queries the page table for a valid PTE including the physical page number. Since the memory page has not been occupied, the MMU cannot query the valid PTE including the physical page number. The MMU continues to query the first PTE in the page table. As shown in FIG4 , the MMU fills the physical page number of the memory page into the first PTE, sets the valid flag in the first PTE to 1, and makes the first PTE valid, to indicate that the memory page is allocated to the first virtual page, that is, to call the first virtual page into the any memory page. At this time, the memory page is the first memory page.

[0091] If there are no unoccupied memory pages in the memory pages allocated to the application, at this time, the memory pages allocated to the application are all occupied. The operating system determines the victim page from the memory pages occupied by the application according to the memory page swap-in and swap-out mechanism, and allocates the victim page to the first virtual page, wherein the victim page is the memory page to be allocated to the first virtual page. Exemplarily, as shown in FIG3 , the operating system sends a second memory allocation request to the MMU, the second memory allocation request including the first virtual page number and the physical page number of the victim page to indicate that the victim page is allocated to the first virtual page. After receiving the second memory allocation request, the MMU queries the page table for a valid PTE including the physical page number. The valid PTE found is called the second PTE. The second PTE found indicates that the victim page has been allocated to other virtual pages other than the first virtual page. To avoid data loss in the other virtual pages, as shown in FIG3 and FIG4 , the MMU queries whether data is stored in the victim page. If data is stored in the victim page, the data in the victim page is written to the disk of the electronic device, so that the victim page becomes an empty memory page. If the victim page does not store data, the victim page is an empty memory page. In this case, the MMU sets the valid flag in the second PTE to 0 to invalidate the second PTE, searches the page table for the first PTE, populates the first PTE with the physical page number of the victim page, and sets the valid flag in the first PTE to 1, making the first PTE valid. This indicates that the victim page is assigned to the first virtual page, that is, the first virtual page is loaded into the victim page. At this time, the victim page is the first memory page.

[0092] The above is explained using an example in which the page table includes an invalid first PTE when the application accesses the first virtual page. In other embodiments, when the application accesses the first virtual page, the MMU may not be able to query the first PTE in the page table. In this case, the MMU still sends a read / write failure response to the processor core, triggering a page fault interrupt, thereby triggering the operating system to allocate a first memory page to the first virtual page. In this case, after the MMU determines the first memory page to be allocated to the first virtual page (such as a sacrifice page or any unoccupied memory page), the MMU creates a valid first PTE in the page table based on the first virtual page number and the physical page number of the first memory page (referred to as the first physical page number).

[0093] As shown in Figure 3, after the first PTE is valid, the MMU sends an allocation notification message to the memory filling device. This allocation notification message is used to notify that the first memory page has been allocated to the first virtual page. In other words, it is used to notify that the first memory page has been allocated to the first virtual address in response to a page fault interrupt caused by an application accessing the first virtual address. After receiving the allocation notification message, the memory allocation unit performs the following step 202 based on the allocation notification message. The allocation notification message includes the first virtual page number and the first physical page number.

[0094] 202. A memory filling device fills a first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode. The cache compression mode is a data compression mode used when migrating data written by an application in a cache to a memory page.

[0095] The cache compression mode is defined in a cache compression algorithm used by the MMU, such as FPC or other cache compression techniques that rely on the cache compression mode. The cache compression algorithm defines at least one cache compression mode, a data sequence corresponding to each cache compression mode, and a data compression method. The data sequence corresponding to each cache compression mode is the data sequence required by each cache compression mode for compressed data.

[0096] The first data is data in a data sequence corresponding to any cache compression mode in the at least one cache compression mode. Exemplarily, the first data is all the data in the data sequence (i.e., each data in the data sequence), or the first data is part of the data in the data sequence. Taking the example of the first data being part of the data in the data sequence, assuming that the data sequence includes N data, the first data is the S data with the highest frequency of occurrence in the data sequence, where N is greater than 1, and S is greater than 0 and less than N. For example, if S=1, and the cache compression mode is the zero operation mode in FPC as an example, the hexadecimal value 0 is the data with the highest frequency of occurrence in the data sequence corresponding to the zero operation mode. Taking the cache compression mode as the 1-byte sign extension mode in FPC as an example, the data with the highest frequency of occurrence in the 1-byte sign extension mode is the hexadecimal value F. For another example, if S=2, the data sequence is 0000FFFF, and the first data is 0 and F. Alternatively, the first data is R consecutive data in the data sequence, for example, the first R data in the data sequence are the first data, or the middle R data are the first data, or the last R data are the first data, where R is greater than 0 and less than N, and R and S may be the same or different. Here, the embodiments of the present application do not limit the values ​​of R and S.

[0097] In other embodiments, the first data is data in multiple data sequences required by multiple data compression modes defined by the cache compression algorithm. For example, the first data is the S data with the highest frequency of occurrence in the multiple data sequences, or the first data is data common to multiple data sequences.

[0098] As shown in Figure 3, after receiving the allocation notification message from the MMU, the memory filling device learns, based on the first virtual page number and the first physical page number in the allocation notification message, that the MMU has allocated the first memory page to the first virtual page. At this time, the first memory page is an empty memory page, and the memory filling device fills the first memory page with the first data. For example, the first memory page is filled with the first data, or part of the memory space of the first memory page is filled with the first data, and the remaining space is not filled with the first data (that is, the first memory page is not filled with the first data).

[0099] Taking the example of filling the first memory page with the first data, assuming the size of the first memory page is 64 bytes (64 bytes = 16 * 8 * 4 bits), if the size of the first data during storage is 4 bits, as shown in Table 1, the memory filling device fills the first memory page with 8 first data every 4 bytes (i.e., 8 * 4 bits) to fill the first memory page with the first data. In this way, when the application subsequently writes data to the first virtual page, the MMU simply updates the first data at the to-be-written location in the first memory page with the to-be-written data.

[0100] Table 1

[0101] As shown in Figure 3, after the first memory page is filled with the first data, the memory filling device sends a filling completion response to the MMU, and the filling completion response is used to indicate that the first data has been filled in the first memory page. After receiving the filling completion response, the MMU sends an allocation completion response to the operating system, and the allocation completion response indicates that the first memory page has been allocated to the first virtual page. After receiving the allocation completion response, the operating system sends a page fault interrupt processing completion response to the processor core to indicate that the page fault interrupt caused by the first virtual page has been processed. After receiving the interrupt processing completion response, the processor core ends the page fault interrupt processing process, releases the suspended first instruction, and executes the first instruction again. Therefore, for the application, it can only perceive the occurrence of a page fault interrupt, and cannot perceive the action of pre-filling the first memory page with the first data.

[0102] When the processor core executes the first instruction again, it sends a first read / write request to the MMU. After receiving the first read / write request again, the MMU accesses the first memory page based on the first virtual address in the first read / write request (ie, step 203 below).

[0103] 203. The memory management unit accesses the filled first memory page based on the first virtual address.

[0104] Exemplarily, if the first read / write request received again is a write request, in order to distinguish it from other write requests described later, the first read / write request is referred to as a first write request. The MMU executes step A2 again, queries the first PTE corresponding to the first virtual address, and the valid flag in the first PTE at this time is 1, that is, the first PTE is a valid PTE. The MMU then constructs a first physical address based on the first PTE and the first virtual address, and writes the second data to the location indicated by the first physical address in the first memory page (referred to as the first location) to achieve writing data to the corresponding location of the first virtual address in the first memory page. At this time, the first location may or may not have been filled with the first data. If the first location is not filled with the first data, the MMU writes the second data to the first location to complete access to the first physical address and the first virtual address. If the first location has been pre-filled with the first data, when writing the second data to the first location, the first data at the first location is updated to the second data, wherein the storage space occupied by the second data is greater than or equal to the storage space occupied by the first data. Exemplarily, the MMU writes the second data to the first location indicated by the first physical address in the first memory page in the form of an overwrite, so that the first data at the first location is updated to the second data to complete access to the first physical address and the first virtual address.

[0105] Here, writing data to the first location means writing data starting from the first location. Still taking Table 1 above as an example, assuming that the page offset in the first physical address is 0, the first location indicated by the first physical address is the starting location of the first memory page. If the size of the second data is 4 bytes, as shown in Table 2, the MMU updates the first data stored in the first 4 bytes of the first memory page with the second data.

[0106] Table 2

[0107] Assume that the first read / write request is a read request. Since the first memory page is pre-filled with the first data at this time, which is not the data to be read by the application, the data to be read by the application has not yet been loaded into the first memory page. As shown in Figure 3, in order for the application to read the required fourth data, the MMU first writes the fourth data stored in the disk to the first physical address of the first memory page to update the first data at the first physical address to the fourth data. Afterwards, the application reads the fourth data from the first physical address to complete the access to the first physical address and the first virtual address.

[0108] After completing the access to the first physical address, thus completing the access to the first memory page, the MMU returns a read / write completion response to the processor core (ie, step A4 above).

[0109] After the processing core receives the read / write completion response, the processor core continues to execute the first instruction or executes other instructions of the application program other than the first instruction (referred to as the second instruction). In the process of continuing to execute the first instruction or the second instruction, the application program will access the first virtual page or other virtual pages other than the first virtual page. In the case of accessing the first virtual page, the application program may access other virtual addresses of the first virtual page other than the first virtual address, or access the first virtual address again. The process of accessing other virtual addresses of the first virtual page can refer to the process of accessing the first virtual address, which will not be repeated here. The process of accessing other virtual pages can refer to the process of accessing the first virtual page, which will not be repeated here.

[0110] During the process of the processor core running the application, the application may access the first virtual page multiple times. For the application's write access to any virtual address of the first virtual page, the MMU updates the first data at the corresponding position of the any virtual address in the first memory page to the data to be written. If the application frequently accesses at least one virtual address of the first virtual page during operation, the MMU migrates the data in the target memory space where the at least one virtual address of the first memory page is located to a cache line (referred to as the first cache line) in the cache (such as LLC), wherein the at least one virtual address may include the first virtual address or may not include the first virtual address, the size of the target memory space is the same as the size of the cache line, the size of the target memory space may be the same as the size of the memory page or may be different from the size of the memory page. When the size of the target memory space is the same as the size of the memory page, the target memory space is the first memory page, and all data stored in the first memory page must be migrated to the first cache line.

[0111] For ease of description, the data in the target memory space (i.e., the data migrated to the cache) is referred to as first migration data. As the application accesses the target memory space, the first migration data includes the first data and / or data written by the application. Taking Table 2 as an example, assuming the cache line size is the same as the memory page size, both 64 bytes, and the application frequently accesses the first memory page shown in Table 2, the first memory page is the target memory space, the second data stored in the first memory page and the various first data constitute the first migration data. The MMU migrates the first migration data to the first cache line in the cache and caches the first PTE in the page table in the TLB.

[0112] After migrating the first migration data to the first cache line, when the application reads the first virtual page, the MMU returns the data to be read in the first cache line to the application to achieve read access to the first memory page and the first virtual page. When the application writes to the first virtual page, the MMU writes data in the first cache line to achieve write access to the first memory page and the first virtual page. At this time, the first migration data is updated, and the updated first migration data is called second migration data.

[0113] Still taking the application accessing the first virtual address as an example, the processor core sends an instruction to the MMU for the first read / write request. Based on the first virtual address in the first read / write request, the MMU can query the first PTE from the TLB, construct the first physical address based on the first PTE and the first virtual address, and perform read access or write access to the position corresponding to the first physical address in the first cache line. Taking write access as an example, the data to be written is called the fifth data. The MMU writes the fifth data to the position corresponding to the first physical address in the first cache line (called the second position) in the form of an overwrite write, so that the data at the second position is updated to the fifth data, and then the first migration data in the first cache line is updated to the second migration data. The data at the second position may be the first data or may not be the first data. Still taking the first migration data as the data shown in Table 2 as an example, assuming that the second position is the first bit of the 9th byte of the first memory page, if the fifth data is 4 bytes, as shown in Table 3, after writing the fifth data to the first cache line, the fifth data can overwrite the 8 first data from the 9th byte to the 12th byte of the first memory page in the first cache line. Assume that the second position is the first bite of the 13th byte of the first memory page. If the fifth data is 2 bytes, as shown in Table 3, after the fifth data is written to the first cache line, the fifth data can overwrite the four first data of the 9th byte and the 10th byte of the first memory page in the first cache line.

[0114] Table 3

[0115] Subsequently, when the cache data (first migration data or second migration data) in the first cache line meets the elimination condition, the MMU migrates the cache data to the first memory page. The elimination condition is the condition for eliminating the cache data in the cache line to the memory. Assuming that the data sequence length required by the cache compression mode is M*Nbit, the storage space size of the first cache line is Kbit, where K is greater than M*N, then K / (M*N) data to be migrated are stored in the first cache line. Still taking Table 3 as an example, K=64 bytes, M*N=4 bytes, then 16 data to be migrated are stored in the first cache line, such as the second data is one data to be migrated, 8 first data are one data to be migrated, 4 bytes of the fifth data are one data to be migrated, and 2 bytes of the fifth data and 4 first data are one data to be migrated.

[0116] When migrating cache data in the first cache row to the first memory page, for each data to be migrated, the MMU matches the data to be migrated with the data sequence required by at least one cache compression mode. If the data to be migrated is the same as the data sequence required by any cache compression mode, then the data to be migrated matches the data sequence and matches any cache compression mode. Otherwise, the data to be migrated does not match any cache compression mode. If the data to be migrated matches any cache compression mode, the MMU uses the data compression method corresponding to any cache compression mode to compress the data to be migrated to obtain compressed data, and writes the compressed data to the first memory page to achieve migration of the data to be migrated to the first memory page. If the data to be migrated does not match any cache compression mode, the MMU writes the data to be migrated to the first memory page to achieve migration of the data to be migrated to the first memory page.

[0117] As shown in Table 3, the data to be migrated may be the first data, a combination of the fifth data and part of the first data (referred to as combined data), or the fifth data. If the first data is data in a cache compression mode in the cache compression algorithm, then when the data to be migrated is the first data or the combined data, the data to be migrated is more likely to match the cache compression mode than random data, thereby increasing the probability of the data to be migrated being compressed, and further increasing the compression rate of the cache data when the cache is evicted from the memory. For example, if the first data is the hexadecimal value 0, the data to be migrated is 8 zeros, and the cache compression mode is the zero run mode in FPC, the data to be migrated will definitely match the zero run mode compared to random data. If the first data is data from multiple data sequences of multiple cache compression patterns defined by a cache compression algorithm, such as the S most frequently appearing data in the multiple data sequences or data common to the multiple data sequences, and the data to be migrated is the first data or a combination of data, the data to be migrated is more likely to match a cache compression pattern in the multiple cache compression patterns than random data, thereby further increasing the probability of the data to be migrated matching the cache compression pattern, further increasing the probability of the data to be migrated being compressed, and further improving the compression rate of the cache data when the cache is evicted from the memory. Assuming the first data is a hexadecimal value of 0, and the data sequences corresponding to multiple data cache patterns in the FPC, such as a zero-running pattern, a 4-bit sign-extended pattern, a half-word sign-extended pattern, and a half-word padded with zero halfwords, all contain the value 0, if the data to be migrated consists of eight zeros, the data to be migrated may match the zero-running pattern. If the data to be migrated consists of a combination of multiple zeros and other values, the data to be migrated may match the 4-bit sign-extended pattern, the half-word sign-extended pattern, or the half-word padded with zero halfwords pattern.

[0118] The method provided in an embodiment of the present application pre-fills the allocated memory page with the first data after allocating the memory page for the virtual address that causes the page fault interrupt, and then accesses the memory page filled with the first data. If the data in the memory page is subsequently migrated to the cache, the first data filled in the memory page will also be migrated to the cache. If the data of the memory page in the cache is eliminated to the memory, the eliminated cache data may also include the first data. Since the first data is the data in the data sequence corresponding to the cache compression mode, when the cache data including the first data is eliminated back to the memory, the probability of the cache data matching the cache compression mode can be increased, and then the compression rate of the cache data can be increased, thereby reducing the overhead of transmitting the cache data from the cache to the memory.

[0119] The embodiment shown in FIG2 illustrates an example in which the memory filling device fills the first memory page with the first data after the operating system allocates the first memory page for the first virtual page. In another possible implementation, as shown in FIG4 , before filling the first memory page with the first data, the memory filling device first determines whether the application accessing the first virtual page has enabled the memory pre-fill function. If the application does not enable the memory pre-fill function, the memory filling device does not perform the step of filling the first memory page with the first data and returns a fill failure response to the MMU to indicate that the first memory page was not filled with the first data. As shown in step A8 of FIG4 , after the application enables the memory pre-fill function, the memory filling device fills the first memory page allocated to the virtual address with the first data and returns a fill completion response to the MMU. In this way, after sending the allocation notification message to the memory filling device, the MMU receives the fill failure response or fill completion response from the memory filling device and then returns the allocation completion response to the operating system, so that the operating system sends a page fault interrupt handling completion response to the processor core, causing the processor core to execute step A1 again. In other embodiments, when the first data is not filled into the first memory page, the memory filling device may not return a filling failure response to the MMU. When the first data is filled into the first memory page, the memory filling device may not return a filling completion response to the MMU. In this case, after the MMU sends the allocation notification message to the memory filling device, it will return an interrupt processing completion response to the operating system after a certain period of time to reserve time for the memory filling device to fill the first data.

[0120] With respect to the implementation method described in FIG4 , only when the memory pre-filling function is turned on by the application program will the memory filling device pre-fill the memory pages allocated to the application program with the first data. There is no need to pre-fill the memory pages allocated to each application program running in the electronic device with the first data, thereby reducing the workload of the memory filling device.

[0121] Next, a method for enabling the memory pre-filling function for an application program to determine whether the memory pre-filling function is enabled for the application program is described below.

[0122] In one possible manner, the memory filling device enables the memory pre-filling function for the application through the following enabling method 1 or enabling method 2.

[0123] Enabling method 1: When the type of the application is the target type, the memory filling device enables the memory pre-filling function for the application.

[0124] Cache compression mode is suitable for target applications, such as compilers, discrete event simulation applications, and big data processing applications. Cache compression mode is not suitable for non-target applications, such as compression applications for compressed data and scientific computing applications.

[0125] Before or during the running of an application, the memory filling device queries the application's program type from the application's configuration information in the operating system. If the application's program type is the target type, the memory filling device enables the memory pre-fill function for the application. If the application's program type is not the target type, the memory filling device does not enable the memory pre-fill function for the application. The enabling method may be, for example, to add a preset function enabling flag to the configuration information, which indicates that the application has enabled the memory pre-fill function.

[0126] In another possible implementation, the memory filling device is not responsible for enabling the memory pre-filling function for the application, and the operating system enables the memory pre-filling function for the target type of application in a similar manner. Alternatively, neither the memory filling device nor the operating system actively enables the memory pre-filling function for the application. Only when the user issues an instruction to enable the memory pre-filling function for the application, the operating system will add a preset function enable flag to the configuration information of the application according to the user's instruction to enable the memory pre-filling function for the application.

[0127] For the above-mentioned activation method 1, before filling the first data into any memory page, the memory filling device determines whether the application has enabled the memory pre-filling function by querying whether the configuration information of the application accessing the memory page includes a preset function activation flag. Taking the schematic diagram of application accessing memory shown in Figure 5 as an example, it is assumed that the processing core runs process 1 and process 2, and the process identifiers (PIDs) of process 1 and process 2 are 11111 and 22222 respectively. Process 1 and process 2 correspond to application 1 and application 2 respectively. Application 1 is a big data application, suitable for cache compression mode, and has enabled the memory pre-filling function. Application 2 is a compression application, not suitable for cache compression mode, and has not enabled the memory pre-filling function. The processor core runs process 1 and process 2 to run application 1 and application 2. Assuming that virtual page 1 accessed by process 1 and virtual page 2 accessed by process 2 both trigger page fault interrupts, after the MMU creates valid PTEs for virtual page 1 and virtual page 2, it notifies the filling unit in the memory filling device that memory pages have been allocated for virtual pages 1 and 2. Based on the notification of the MMU, the memory filling device sends a judgment request to the judgment unit to request whether the applications corresponding to process 1 and process 2 have enabled the memory pre-filling function. After receiving the judgment request, the judgment unit queries the configuration information of application 1 and the configuration information of application 1, queries the preset function enable flag from the configuration information of application 2, and queries the preset function enable flag from the configuration information of application 1 to correspond to PID1 of process 1. Then, a judgment response is returned to the filling unit to indicate that application 2 corresponding to process 2 has not enabled the memory pre-filling function, and application 1 corresponding to process 1 has enabled the memory pre-filling function. After receiving the determination response, the memory preset module fills the first data in the memory page allocated for virtual page 1 according to the instruction of the determination response, and does not fill the first data in the memory page allocated for virtual page 2.

[0128] Given that even if the memory pages allocated to an application that is not applicable to the cache compression mode are pre-filled with the first data, the data of the application cannot be well matched with the cache compression mode when it is migrated from the cache to the memory, through the above-mentioned activation method 1, the memory filling device will enable the memory pre-filling function for the application only when the application is applicable to the cache compression mode, so that during the operation of the application, the memory pages of the application are pre-filled with the first data, thereby improving the compression efficiency of the application data when it is migrated from the cache to the memory, and avoiding filling the memory pages of the application that is not applicable to the cache compression mode with the first data, thereby reducing the workload of the memory filling device.

[0129] Enabling method 2: During the running of the application, the memory filling device periodically enables the memory pre-filling function for the application based on the running status of the application.

[0130] Among them, the running status of the application is reflected by the first PMU event and / or the second PMU event triggered during the running of the application. The first PMU event is the running of a floating-point operation instruction when running the application. The floating-point operation instruction refers to an instruction used for floating-point operation.

[0131] The second PMU event refers to the PMU event related to the data exchange between the cache and the memory. The second PMU event can reflect the data exchange between the cache and the memory during the application program running. There is at least one second PMU event, such as a cache miss event, a TLB miss event, and a pipeline stall (core_pipeline_stall_due_to_cache_miss) event caused by the number of first / second cache misses.

[0132] In one possible implementation, during the application's operation, at each time period, the memory pre-filling device predicts, based on the application's operation status during that time period, whether the cache compression mode is applicable to the application during the next time period. If applicable, the memory pre-filling function is enabled for the application during the next time period; otherwise, the step of enabling the memory pre-filling function for the application during the next time period is not performed. The duration of the time period is the same as the duration of the next time period, and the duration of the time period is the unit duration for enabling the memory pre-filling function.

[0133] Taking Figure 5 as an example, when the processor core is running an application, the PMU records and counts the first PMU event and / or the second PMU event triggered by the application. The judgment unit in the memory filling device obtains statistical information of the first PMU event and / or the second PMU event in each time period from the PMU, and based on the statistical information, predicts whether the cache compression mode is applicable when the application runs in the next time period.

[0134] Exemplarily, taking the acquisition of statistical information of the first PMU event in the time period as an example, the statistical information of the first PMU event in the time period is the number of floating-point operation instructions running in the time period. The judgment unit also obtains the total number of instructions of the application running in the time period from the PMU. Based on the number of floating-point operation instructions and the total number of instructions, the proportion of floating-point operation instructions in the application instructions running in the time period is obtained. The proportion is the ratio between the number of floating-point operation instructions and the total number of instructions. The cache compression mode is applicable to non-floating-point data (such as integer data) and not to floating-point data. If the proportion is less than or equal to the proportion threshold, it indicates that the application is applicable to the cache compression mode, and the judgment unit then enables the memory pre-fill function for the application in the next time period. If the proportion is greater than the proportion threshold, it indicates that the application is not applicable to the cache compression mode, and the judgment unit then temporarily does not enable the memory pre-fill function for the application.

[0135] Taking the statistical information of the second PMU event as an example, assuming that at least one of the cache miss event, the TLB miss event, and the pipeline pause event caused by the first / second cache miss is a second PMU event, the statistical information of the cache miss event in the time period is the number of occurrences of the cache miss event in the time period (referred to as the first occurrence number). If the first occurrence number is greater than or equal to the first occurrence threshold, it indicates that data is frequently exchanged between the cache and the memory in the time period. If the first occurrence number is less than the first occurrence threshold, it indicates that data is not frequently exchanged between the cache and the memory in the time period. The statistical information of the TLB miss event in the time period is the number of occurrences of the TLB miss event in the time period (referred to as the second occurrence number). If the second occurrence number is greater than or equal to the second occurrence threshold, it indicates that data is frequently exchanged between the cache and the memory in the time period. If the second occurrence number is less than the first occurrence threshold, it indicates that data is not frequently exchanged between the cache and the memory in the time period. The statistics for pipeline stall events during this time period include: the total pipeline stall duration caused by pipeline stall events during this time period (pipeline stall). If the pipeline stall duration is greater than or equal to the duration threshold, data was frequently exchanged between the cache and memory during this time period. If the pipeline stall duration is less than the duration threshold, data was not frequently exchanged between the cache and memory during this time period. If data was frequently exchanged between the cache and memory during this time period, the cache compression mode was applicable to the application during this time period and may also be applicable to the application during the next time period. If data was not frequently exchanged between the cache and memory during this time period, the cache compression mode was not applicable to the application during this time period and may not be applicable to the application during the next time period. Based on this, if the first occurrence count is less than the first count threshold, the second occurrence count is less than the second count threshold, and the pipeline stall is less than the duration threshold, the cache compression mode is not applicable to the application when it runs in the next time period, and the judgment unit temporarily does not enable the memory pre-filling function for the application. If the first sending count, the second occurrence count, and the pipeline stall satisfy at least one of the following conditions: the first occurrence count is greater than or equal to the first count threshold, the second occurrence count is greater than or equal to the second count threshold, and the pipeline stall is greater than or equal to the duration threshold, the cache compression mode is applicable to the application when it runs in the next time period, and the judgment unit enables the memory pre-filling function for the application in the next time period.

[0136] In other embodiments, the preset submodule does not obtain the statistical information of the first PMU event in the time period, obtains the statistical information of the second PMU event, and only determines whether it is necessary to enable the memory pre-fill function for the next time period for the application based on the statistical information of the second PMU event.

[0137] In other embodiments, the judgment unit may also input the statistical information of the first PMU event and / or the statistical information of the first PMU event in the time period into an artificial intelligence (AI) model, and the AI ​​model outputs a judgment result based on the statistical information of the first PMU event and / or the statistical information of the first PMU event in the time period, wherein the judgment result indicates whether the memory pre-fill function needs to be enabled for the application in the next time period, and the threshold judgment submodule enables the memory pre-fill function for the application in the next time period based on the indication of the judgment result, or temporarily does not enable the memory pre-fill function for the application in the next time period. The AI ​​model is trained based on a plurality of first training data and a plurality of second training data statistical information, wherein the first training data is statistical information of the first PMU event and / or the second PMU event triggered during the operation of the target type application, and the second training data is statistical information of the first PMU event and / or the second PMU event triggered during the operation of the non-target type application, so that the AI ​​model can learn the mapping relationship between the statistical information of the first PMU event and / or the second PMU event and whether the memory pre-fill function needs to be enabled for the application in the next time period during the training process. The AI ​​model may be a decision tree model or other types of AI models.

[0138] Taking the statistical information of the first PMU event and the second PMU event in the time period as an example, if the statistical information of the first PMU event determines that the cache compression mode is not applicable to the application when it runs in the next time period, the judgment unit then determines whether to enable the memory pre-fill function for the application in the next time period based on the statistical information of the second PMU event. If the statistical information of the first PMU event determines that the cache compression mode is applicable to the application when it runs in the next time period, the judgment unit does not need to make further judgments based on the statistical information of the second PMU event. In other embodiments, the judgment logic is implemented using a decision tree. When in use, the judgment unit can input the statistical information of the first PMU event and the second PMU event in the time period into the decision tree, and the decision tree outputs a judgment result based on the above judgment logic, which indicates whether to enable the memory pre-fill function for the application in the next time period.

[0139] In other embodiments, the judgment unit may also input the statistical information of the first PMU event and / or the statistical information of the first PMU event in the time period into an artificial intelligence (AI) model, and the AI ​​model outputs the judgment result based on the statistical information of the first PMU event and / or the statistical information of the first PMU event in the time period. The AI ​​model is trained based on a plurality of first training data and a plurality of second training data statistical information, the first training data being the statistical information of the first PMU event and / or the second PMU event triggered during the operation of the target type application, and the second training data being the statistical information of the first PMU event and / or the second PMU event triggered during the operation of the non-target type application, and the training enables the AI ​​model to learn the mapping relationship between the statistical information of the first PMU event and / or the second PMU event and the judgment result. The AI ​​model is, for example, a neural network model.

[0140] If the determination unit determines that the memory pre-fill function is enabled for the application in the next time period, the determination unit queries the operating system to determine whether the configuration information of the application includes a preset function enable flag. If the preset function enable flag is not included, the preset function enable flag is added to the configuration information. If the preset function enable flag is included, the preset function enable flag does not need to be added. In this way, in the next time period, the determination unit can determine that the memory pre-fill function is enabled for the application in the next time period based on the preset function enable flag in the configuration information.

[0141] If the determination unit determines that the memory pre-fill function is not enabled for the application in the next time period, the determination unit queries the operating system to determine whether the configuration information of the application includes a preset function enable flag. If the preset function enable flag is included, the determination unit deletes the preset function enable flag from the configuration information. In this way, in the next time period, the determination unit will not find the preset function enable flag in the configuration information, and thus can determine that the memory pre-fill function is not enabled for the application in the next time period.

[0142] The embodiment shown in Figure 5 is illustrated by taking the memory filling device including a judgment unit and a filling unit as an example. In other embodiments, the memory filling device is not divided into sub-units. In this case, the steps performed by the judgment unit and the filling unit are all implemented by the memory filling device.

[0143] Based on the above-mentioned activation method 2, during the operation of the application, the memory pre-filling function can be periodically enabled for the application, so that more detailed control can be exercised over whether the application enables the memory filling function. During the time period when the memory pre-filling function is not enabled, there is no need to fill the empty memory page called into the virtual page with the first data, which further reduces the workload of the memory filling device.

[0144] In other embodiments, the memory pre-filling unit does not have the ability to enable the memory pre-filling function for the application. In this case, the operating system or other units can enable the memory pre-filling function for the application according to the above-mentioned enabling method 1 or enabling method 2.

[0145] The embodiments described in Figures 2 to 5 are all explained using an application accessing a virtual page as an example. In other embodiments, a computing task of the application may correspond to multiple virtual pages, and the multiple virtual pages are continuous. The multiple memory pages corresponding to the multiple virtual pages are used to store task data of the computing task, and the task data is the data generated by the application in the process of executing the computing task.

[0146] When the application writes the task data, it may write the task data to all virtual pages of the multiple virtual pages, or it may write the task data to some virtual pages of the multiple virtual pages. When writing data to some virtual pages, the virtual pages where the task data is written may be adjacent or non-adjacent. For example, the computing task corresponds to virtual pages 1-3, and virtual pages 1-3 are continuous. Assume that when the computing task meets condition 1, the application writes the task data of the computing task to virtual page 1, when the computing task meets condition 2, the application writes the task data of the computing task to virtual page 2, and when the computing task meets condition 3, the application writes the task data of the computing task to virtual page 3. When the application executes the computing task, the computing task may not meet one of the conditions 1-3, resulting in the application not filling task data into some virtual pages in virtual pages 1-3. For example, during the execution of the computing task, only conditions 1 and 3 are met, and condition 2 is not met, then the application will write task data to virtual pages 1 and 3, and will not write task data to virtual page 2. In related technologies, the MMU writes task data to memory pages 1 and 3 corresponding to virtual pages 1 and virtual page 3 to achieve writing task data to virtual pages 1 and 3. Since the application does not write task data to virtual page 2, the MMU will fill random values ​​in the inner page 2 corresponding to virtual page 2. Once the data in memory pages 1-3 are migrated to the cache, the random values ​​filled in memory page 2 will also be migrated to the cache. When the cached data in memory pages 1-3 in the cache are eliminated back to the memory page, the random values ​​in the cache data of memory page 2 make it difficult for the cache data to match the cache compression mode, resulting in a low cache compression rate.

[0147] The present application fills the first data in each empty memory page of the application through the memory filling unit. If the task data of the computing task executed by the application is not filled into the corresponding memory page, since the first data has been filled in the memory page, the MMU will not continue to fill the random value in the memory page, thereby avoiding the problem of low cache compression rate caused by filling random value.

[0148] For example, taking a computing task of an application corresponding to multiple virtual pages (referred to as second virtual pages) as an example, the memory page corresponding to the second virtual page is referred to as a second memory page, and the multiple second memory pages are all used to store the task data of the computing task of the application. According to the processing flow of filling the first data in the first memory page (Figure 2 or Figure 4), when each second memory page is transferred into the corresponding second virtual page, the memory filling unit will fill the second memory page with the first data, thereby enabling the application to pre-fill the first data for each second memory page before writing the task data to each second memory page.

[0149] During the process of the processor core executing the computing task of the application, when the application writes task data to the second virtual address of any virtual address (referred to as the second virtual address) in the plurality of second virtual pages, the processor core is triggered to send a second write request of the application to the memory management device, and the second write request indicates to write the task data to the second virtual address. After receiving the second write request, the memory management device converts the second virtual address in the second write request into a physical address (referred to as the second physical address), wherein the process of converting the address can refer to the process of converting the first virtual address into the first physical address. The memory management device updates the first data at the second physical address in the plurality of second memory pages with the task data to be written, so as to update the first data at the corresponding position of the second virtual address in the plurality of second memory pages to the task data. The second memory page where the second physical address is located is called the third memory page. When writing task data to the second physical address in the third memory page, if the data in the third memory page has not yet been migrated to the cache line in the cache (called the second cache line), the memory management device writes the task data to the second physical address in the third memory page. If the data in the third memory page has been migrated to the second cache line, the memory management device writes the task data to the position corresponding to the second physical address in the second cache line to overwrite the first data at the position. If the cache data of the third memory page in the second cache line is subsequently eliminated and returned to the third memory page, since the cache data includes the first data, the cache data is easier to match the cache compression mode, thereby improving the cache compression rate.

[0150] After the data in the multiple second memory pages are migrated to the cache, the first data filled in the multiple second memory pages and / or the task data written by the application will be migrated to the cache together. For any memory page other than the third memory page in the multiple second memory pages (referred to as the fourth memory page), before writing the task data to the fourth memory page, the data in the fourth memory page is all the first data, and the cached data of the fourth memory page in the cache is all the second data. If the application has not written the task data to the fourth memory page during the execution of the computing task, the cached data of the fourth memory page in the cache is always the first data, and will not be a random value. When the cached data of the fourth memory page is subsequently eliminated and returned to the fourth memory page, the cached data is more likely to match the cache compression mode, thereby improving the cache compression rate. If the application subsequently writes task data to the fourth memory page, the task data will be written to the cached data of the fourth memory page in the cache to overwrite part or all of the first data in the cached data. When the cached data of the fourth memory page is subsequently eliminated and returned to the fourth memory page, if the cached data of the fourth memory page still contains the first data, the cached data is more likely to match the cache compression mode, thereby improving the cache compression rate.

[0151] The above describes the method of the embodiment of the present application. The following describes the device and equipment of the embodiment of the present application. It should be understood that the device and equipment described below have the same inventive concept as the above method embodiment and can achieve the beneficial effects achieved by the above method embodiment. The device and equipment of the embodiment of the present application will be described below in conjunction with Figures 6 to 8. It should be understood that the technical features described in the method embodiment are also applicable to the following device and equipment embodiments.

[0152] FIG6 is a schematic diagram of the structure of a memory page processing device provided in an embodiment of the present application. The device 600 shown in FIG6 can be an electronic device, such as a terminal, a server, or a network device, etc. The device type of the device 600 is not limited here. As shown in FIG6, the device 600 includes:

[0153] The running device 601 is used to allocate a first memory page to the first virtual address accessed by the application by running the operating system when a page fault interrupt is caused by the first virtual address accessed by the application. The running device 601 is a module that runs the operating system in the device 600.

[0154] a memory filling device 602 configured to fill the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, where the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page;

[0155] The memory management device 603 is used to access the filled first memory page based on the first virtual address.

[0156] In a possible implementation, the memory filling device 602 is further configured to:

[0157] In a case where the application program starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application program accesses the empty memory page.

[0158] In a possible implementation, the memory filling device 602 is further configured to:

[0159] The memory filling device periodically enables the memory pre-filling function for the application based on the running status of the application; otherwise, the step of enabling the memory pre-filling function for the application is not performed.

[0160] In a possible implementation, the memory filling device 602 is further configured to:

[0161] In the case that the type of the application is a target type, the memory pre-filling function is enabled for the application, and the cache compression mode is applicable to the target type application.

[0162] In a possible implementation, the memory management device 603 is configured to:

[0163] receiving a first write request from the application, where the first write request indicates writing second data to the first virtual address;

[0164] The first data at a position corresponding to the first virtual address in the first memory page is updated to the second data.

[0165] In a possible implementation, the plurality of second memory pages are all used to store task data of the same computing task of the application, the plurality of second memory pages are all filled with the first data, and the memory management device 603 is further used to:

[0166] receiving a second write request from the application, wherein the second write request instructs writing the task data to a second virtual address;

[0167] The first data at a position corresponding to the second virtual address in the plurality of second memory pages is updated to the task data.

[0168] In one possible implementation, the first data is each data in the data sequence; or, the first data is the S data with the highest frequency of occurrence in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0169] In a possible implementation, the first data is S data with the highest occurrence frequency in multiple data sequences, the multiple data sequences correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0170] The division of the functional modules described above is used only as an example to illustrate the processing of memory pages by device 600. In actual applications, the functions described above can be assigned to different functional modules as needed, that is, the internal structure of device 600 can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the device 600 provided in the above embodiment and the above method embodiment share the same concept. The specific implementation process is detailed in the above method embodiment and will not be repeated here.

[0171] FIG7 is a schematic diagram of the structure of a memory filling device provided in an embodiment of the present application. As shown in FIG7 , the device 700 includes:

[0172] An acquiring unit 701 is configured to acquire an allocation notification message, where the allocation notification message is used to notify that a first memory page has been allocated to a first virtual address in response to a page fault interrupt caused by an application accessing a first virtual address.

[0173] The filling unit 702 is used to fill the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, and the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page.

[0174] In a possible implementation, the filling unit 702 is further configured to:

[0175] In a case where the application program starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application program accesses the empty memory page.

[0176] In a possible implementation, the apparatus 700 further includes:

[0177] An enabling unit is used to periodically enable the memory pre-filling function for the application based on the running status of the application.

[0178] In a possible implementation, the apparatus 700 further includes:

[0179] An enabling unit is used to enable the memory pre-filling function for the application when the type of the application is a target type, and the target type application is applicable to the cache compression mode.

[0180] The opening unit involved in the above two implementations may be the judgment unit in the memory filling device introduced in the above embodiments.

[0181] In one possible implementation, the first data is each data in the data sequence; or, the first data is the S data with the highest frequency of occurrence in the data sequence, where S is greater than 0; or, the first data is R consecutive data in the data sequence, where R is greater than 0.

[0182] In a possible implementation, the first data is S data with the highest occurrence frequency in multiple data sequences, the multiple data sequences correspond to different cache compression modes, and S is greater than 0; or, the first data is data common to the multiple data sequences.

[0183] It should be understood that the division of the functional modules described above is merely an example of how the device 700 processes memory pages. In actual applications, the functions described above can be assigned to different functional modules as needed, i.e., the internal structure of the device 700 can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the device 700 provided in the above embodiment and the method embodiment described above share the same concept. The specific implementation process is detailed in the above method embodiment and will not be further described here.

[0184] FIG8 is a schematic diagram of the structure of another memory filling device provided in an embodiment of the present application. As shown in FIG8 , memory filling device 800 includes: a bus 802, a processor 804, a memory 806, and a communication interface 808. Processor 804, memory 806, and communication interface 808 communicate with each other via bus 802. Memory filling device 800 can be a server or a client. It should be understood that the present application does not limit the number of processors and memories in memory filling device 800. Bus 802 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. Buses can be classified as address buses, data buses, control buses, etc. For ease of illustration, FIG8 shows only one line, but this does not mean that there is only one bus or only one type of bus. Bus 802 can include a path for transmitting information between the various components of memory filling device 800 (e.g., memory 806, processor 804, and communication interface 808). The processor 804 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP). The memory 806 may include a volatile memory, such as a random access memory (RAM). The memory 806 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD). The memory 806 stores an executable program code, and the processor 804 executes the executable program code, so that the memory filling device 800 implements the memory page processing method. In one possible implementation, the memory filling device 800 is a chip.

[0185] In an exemplary embodiment, an electronic device is also provided, which includes a processor for executing program code so that the electronic device executes operations performed by a method for processing memory pages applied to the electronic device. Exemplarily, the hardware structure of the electronic device can refer to the memory filling device 800. The difference from the memory filling device 800 is that the program code stored in the memory in the electronic device is used to implement the method for processing memory pages applied to the electronic device.

[0186] In an exemplary embodiment, a computer-readable storage medium is further provided, such as a memory including a program code, and the program code can be executed by a processor of the memory filling device 800 to complete the memory page processing method in the above embodiment. Alternatively, the program code is executed by a processor of an electronic device to complete the memory page processing method applied to the electronic device in the above embodiment. For example, the computer-readable storage medium is a non-temporary computer-readable storage medium, such as a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0187] The present application also provides a computer program product or computer program, which includes program code, wherein the computer instructions are stored in a computer-readable storage medium. The processor of the memory filling device reads the program code from the computer-readable storage medium and executes the program code, causing the memory filling device to perform the memory page processing method described in the above embodiment. Alternatively, the processor of an electronic device reads the program code from the computer-readable storage medium and executes the program code, causing the electronic device to perform the memory page processing method described in the above embodiment.

[0188] Among them, the devices, equipment, computer-readable storage media, computer program products or chips provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0189] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0190] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0191] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0192] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0193] In the description of this application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one" means one or more, and "a plurality" means two or more. Words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not limit them to be necessarily different.

[0194] Throughout this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0195] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the data written to the memory pages involved in this application are all obtained with full authorization.

[0196] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present disclosure, and will not be described in detail here.

[0197] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for processing a memory page, characterized in that: The method comprises: In the case where a first virtual address accessed by the application causes a page fault interrupt, allocating a first memory page to the first virtual address; Filling the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, where the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page; Based on the first virtual address, the filled first memory page is accessed.

2. The method according to claim 1, characterized in that Filling the first data in the first memory page includes: In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

3. The method according to claim 2, characterized in that In the case where the application enables a memory pre-filling function, before the first memory page is filled with the first data, the method further includes: Based on the running status of the application, the memory pre-filling function is periodically enabled for the application.

4. The method according to claim 2, characterized in that: In the case where the application enables a memory pre-filling function, before the first memory page is filled with the first data, the method further includes: In the case that the type of the application is a target type, the memory pre-filling function is enabled for the application, and the cache compression mode is applicable to the target type application.

5. The method according to any one of claims 1 to 4, characterized in that The accessing the filled first memory page based on the first virtual address includes: receiving a first write request from the application, wherein the first write request indicates writing second data to the first virtual address; The first data at a position corresponding to the first virtual address in the first memory page is updated to the second data.

6. The method according to claims 1-5, characterized in that: The plurality of second memory pages are all used to store task data of a same computing task of the application program, the plurality of second memory pages are all filled with the first data, and the method further includes: receiving a second write request from the application, wherein the second write request indicates writing the task data to a second virtual address; The first data at the position corresponding to the second virtual address in the plurality of second memory pages is updated to the task data.

7. The method according to any one of claims 1 to 6, characterized in that The first data are each data in the data sequence; Alternatively, the first data is the S data with the highest occurrence frequency in the data sequence, and S is greater than 0; Alternatively, the first data is R consecutive data in the data sequence, where R is greater than 0.

8. The method according to any one of claims 1 to 6, characterized in that The first data is S data with the highest occurrence frequency among a plurality of data sequences, the plurality of data sequences correspond to different cache compression modes, and S is greater than 0; Alternatively, the first data is data common to the multiple data sequences.

9. A method for processing a memory page, characterized in that: The method comprises: Acquire an allocation notification message, where the allocation notification message is used to notify a page fault interrupt caused by an application accessing a first virtual address, and a first memory page has been allocated to the first virtual address; The first memory page is filled with first data, where the first data is data in a data sequence corresponding to a cache compression mode, and the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page.

10. The method according to claim 9, characterized in that Filling the first data in the first memory page includes: In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

11. The method according to claim 10, characterized in that In the case where the application enables a memory pre-filling function, before the first memory page is filled with the first data, the method further includes: Based on the running status of the application, the memory pre-filling function is periodically enabled for the application.

12. The method according to claim 10, characterized in that In the case where the application enables a memory pre-filling function, before the first memory page is filled with the first data, the method further includes: In the case that the type of the application is a target type, the memory pre-filling function is enabled for the application, and the cache compression mode is applicable to the target type application.

13. A memory page processing device, characterized in that: The device comprises: An operating device, configured to allocate a first memory page to a first virtual address accessed by an application program by running an operating system when a page fault interrupt is induced by the first virtual address accessed by the application program; A memory filling device, used to fill the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, where the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page; A memory management device is used to access the filled first memory page based on the first virtual address.

14. The device according to claim 13, characterized in that The memory filling device is also used for: In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

15. The device according to claim 14, characterized in that The memory filling device is also used for: Based on the running status of the application, the memory pre-filling function is periodically enabled for the application.

16. The device according to claim 14, characterized in that The memory filling device is also used for: In the case that the type of the application is a target type, the memory pre-filling function is enabled for the application, and the cache compression mode is applicable to the target type application.

17. The device according to any one of claims 13 to 16, characterized in that The memory management device is used for: receiving a first write request from the application, wherein the first write request indicates writing second data to the first virtual address; The first data at a position corresponding to the first virtual address in the first memory page is updated to the second data.

18. The device according to claims 13-17, characterized in that The plurality of second memory pages are all used to store task data of a same computing task of the application program, the plurality of second memory pages are all filled with the first data, and the memory management device is further used to: receiving a second write request from the application, wherein the second write request indicates writing the task data to a second virtual address; The first data at the position corresponding to the second virtual address in the plurality of second memory pages is updated to the task data.

19. The device according to any one of claims 13 to 18, characterized in that The first data are each data in the data sequence; Alternatively, the first data is the S data with the highest occurrence frequency in the data sequence, and S is greater than 0; Alternatively, the first data is R consecutive data in the data sequence, R is greater than 0, and the first data is a hexadecimal value 0 or a value F.

20. The device according to any one of claims 13 to 18, characterized in that The first data is S data with the highest occurrence frequency among a plurality of data sequences, the plurality of data sequences correspond to different cache compression modes, and S is greater than 0; Alternatively, the first data is data common to the multiple data sequences.

21. A memory filling device, characterized in that: The device comprises: an acquisition unit, configured to acquire an allocation notification message, wherein the allocation notification message is used to notify that a first memory page has been allocated to a first virtual address for a page fault interrupt caused by an application accessing a first virtual address; A filling unit is used to fill the first memory page with first data, where the first data is data in a data sequence corresponding to a cache compression mode, and the cache compression mode is a data compression mode used when migrating data written by the application in the cache to a memory page.

22. The device according to claim 21, characterized in that The filling unit is also used for: In the case where the application starts a memory pre-filling function, the first data is filled in the first memory page, and the memory pre-filling function indicates that the first data is filled in the empty memory page before the application accesses the empty memory page.

23. An electronic device, characterized in that: The electronic device comprises a processor, and the processor is used to execute program code, so that the electronic device performs the method according to any one of claims 1 to 8.

24. A memory filling device, characterized in that: The memory filling device comprises a processor, and the processor is used to execute program code, so that the memory filling device performs the method according to any one of claims 9 to claim 12.

25. A computer-readable storage medium, characterized in that: At least one program code is stored in the storage medium, and the at least one program code is read by a processor to execute the method according to any one of claims 1 to 12.

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