Printed circuit board design device and printed circuit board design program

Abstract

An overall layout design unit (15) comprises: a neighboring block layout pattern design unit (31) that generates, for each circuit diagram group, one or more layout patterns, within the circuit diagram group, for a plurality of neighboring blocks included in the circuit diagram group; a circuit diagram group area pattern design unit (32) that generates one or more area patterns representing the areas for a plurality of circuit diagram groups on the board; and an overall layout pattern design unit (33) that generates, for each area pattern, one or more overall layout patterns in which one or more neighboring blocks included in a plurality of circuit diagram groups in the area pattern are laid out in a layout pattern in the areas for the circuit diagram groups.

Description

Printed circuit board design device and printed circuit board design program

[0001] The present disclosure relates to a printed circuit board design device and a printed circuit board design program.

[0002] Conventionally, design devices have been known that can place components that are desired to be placed close to each other on a printed circuit board so that the performance or characteristics of the electronic circuit can be fully demonstrated. For example, a design device described in Patent Document 1 includes a knowledge pattern storage unit that stores conditions for components to be placed close to each other on the printed circuit board as a knowledge pattern, a printed circuit board design information storage unit that stores components to be placed on the printed circuit board and wiring information between the components, a group classification unit that determines whether each component stored in the printed circuit board design information storage unit satisfies the knowledge pattern stored in the knowledge pattern storage unit based on the wiring information, and classifies a group of components that satisfy the knowledge pattern into one group, and a placement determination unit that regards a group of components classified into one group as one placement element and determines the placement on the printed circuit board. The placement of components other than the group is based on the connection information in the printed circuit board design information storage unit.

[0003] Japanese Patent Application Publication No. 7-200655

[0004] However, the printed circuit board design device described in Patent Document 1 does not describe how to arrange the multiple groups on a printed circuit board when they have been generated, so that the designer must consider how to arrange the multiple groups in order to minimize the circuit area and ensure that the performance or characteristics of the electronic circuit are fully exhibited, which places a heavy workload on the designer.

[0005] Therefore, an object of the present disclosure is to provide a printed circuit board design device and a printed circuit board design program that can arrange components with little work burden, a small circuit area, and in a way that allows the performance or characteristics of the electronic circuit to be fully demonstrated.

[0006] The printed circuit board design apparatus of the present disclosure includes a grouping processing unit that generates a plurality of circuit diagram groups by dividing a circuit diagram into a plurality of parts, a component classification unit that classifies components into parent parts, child parts directly or indirectly connected to the parent parts, and other parts, a proximity block generation unit that generates a plurality of proximity blocks, each including a parent part and a child part, an intra-proximity block component layout design unit that arranges components in the proximity blocks, and an overall layout design unit that executes an overall layout design process multiple times to arrange a plurality of proximity blocks included in a circuit diagram group in a plurality of circuit diagram groups. The overall layout design unit includes: a proximity block layout pattern design unit that generates, for each circuit diagram group, one or more layout patterns within the circuit diagram group for a plurality of proximity blocks included in the circuit diagram group, a circuit diagram group area pattern design unit that generates one or more area patterns representing areas of the plurality of circuit diagram groups on the board, and an overall layout pattern design unit that generates, for each area pattern, one or more overall layout patterns in which one or more proximity blocks included in the circuit diagram group are arranged in areas of the plurality of circuit diagram groups in the layout pattern.

[0007] According to the printed circuit board design device and printed circuit board design program of the present disclosure, components can be arranged with a small workload, with a small circuit area, and in a way that allows the performance or characteristics of the electronic circuit to be fully demonstrated.

[0008] 1 is a diagram showing the configuration of a printed circuit board design apparatus 1 according to an embodiment. 2 is a flowchart showing a procedure for component layout design on a printed circuit board by the printed circuit board design apparatus 1 according to an embodiment. 3 is a flowchart showing a detailed processing procedure of S1 in FIG. 2. 4 is a diagram for explaining the relationship between components. 5 is a flowchart showing a detailed processing procedure of S6 in FIG. 2. 6(a) is a diagram showing components in a proximity block A. 7(b) is a diagram showing components in a proximity block B. 8(c) is a diagram showing whether components in a proximity block A and components in a proximity block B are the same or not. 9 is a diagram showing an example of the layout of high-priority first-generation components and low-priority first-generation components. 10 is a diagram showing an example of the layout of child components. 11 is a diagram for explaining the area around a parent component PR1. 12 is a diagram showing an example of the layout of first-generation child components with the same priority. 13 is a diagram showing an example of a rectangular region SR1 of a proximity block. 14 is a diagram showing an example of a polygonal region SR2 of a proximity block. 17 is a flowchart showing a detailed processing procedure of S9 in FIG. 2 in an embodiment. (a) is a diagram showing a netlist. (b) is a diagram showing the connection relationships between components. (c) is a diagram showing an example of a power tree. (a) is a diagram showing examples of position-specified components and semi-position-specified components. (a) is a diagram showing an example of placement when the orientation is 0°. (b) is a diagram showing an example of placement when the orientation is 90°. (c) is a diagram showing an example of placement when the orientation is 180°. (d) is a diagram showing an example of placement when the orientation is 270°. (a) is a diagram showing an example of connection pins. (b) is a diagram showing virtual pins obtained from the connection pins of FIG. 17. (c) is a diagram for explaining an example of the coordinates of the virtual pins of a proximity block model. (d) is a diagram for explaining another example of the coordinates of the virtual pins of a proximity block model. (a) is a diagram showing virtual pins between proximity block model RB1 and proximity block model RB2. 13(b) is a diagram showing a virtual pin between a proximity block model RB2 and a proximity block model RB3. (a) and (b) are diagrams for explaining the ideal orientation relationship between two proximity block models. (a) and (b) are diagrams for explaining the ideal orientation relationship between two proximity block models. (b) is a diagram showing an example of a table showing the ideal orientation relationship between two proximity block models. (c) is a flowchart showing the detailed processing procedure of S505 in FIG. 13(a) and (b) are diagrams for explaining the ideal orientation relationship between two proximity block models.25A and 25B are diagrams for explaining an example of clustering of arrangement patterns; and a diagram showing the results of clustering of arrangement patterns; (a) is a diagram showing an example of the relationship between the orientations of two adjacent block models; (b) is a diagram showing another example of the relationship between the orientations of two adjacent block models; and (c) is a diagram showing an example of a score based on the relationship between the orientations of two adjacent block models; and (d) is a diagram showing another example of the relationship between the orientations of two adjacent block models. (a) is a diagram showing an example of a twisted wiring; (b) is a diagram showing an example of a non-twisted wiring; (a) is a diagram showing an example of an intersection of wiring; (b) is a diagram showing an example of a non-intersection of wiring; (a) is a diagram showing an example of a wiring path being present; and (b) is a diagram showing an example of a non-existence of wiring paths. A flowchart showing the detailed processing procedure of S604 in FIG. 25A and 25B is a diagram showing an example of selecting a representative candidate arrangement pattern for cluster A. 37 is a diagram showing an example of a layout pattern generated after the processing procedure of the flowchart of FIG. 23 is completed. FIG. 38 is a flowchart showing the detailed processing procedure of S506 of FIG. 13. FIG. 39 is a diagram showing an example of acquiring an area of ​​a circuit diagram group model including a semi-position specified component. FIG. 40 is a diagram showing an example of acquiring an area of ​​a circuit diagram group model including a semi-position specified component. FIG. 41 is a diagram showing an example of an area pattern generated after the processing procedure of the flowchart of FIG. 37 is completed. FIG. 42 is a flowchart showing the detailed procedure of S507 of FIG. 13. FIG. 43 is a diagram for explaining an example of generating an overall layout pattern. (a) and (b) are diagrams for explaining an example of adjusting the layout on a component-by-component basis. (a) and (b) are diagrams for explaining another example of adjusting the layout on a component-by-component basis. FIG. 44 is a diagram showing the hardware configuration of a printed circuit board design device 1.

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following describes embodiments with reference to the accompanying drawings. EMBODIMENTS Fig. 1 is a diagram showing the configuration of a printed circuit board design device 1 according to an embodiment.

[0010] The printed circuit board design device 1 includes a data input unit 2, a user I / F 4, a CAD (Computer Aided Design) unit 3, and a layout design unit 21.

[0011] The functions of the CAD unit 3 and the layout design unit 21 may be realized by the computer executing a printed circuit board design program stored in memory. The printed circuit board design program may be installed in memory from an external device via a network. Alternatively, the printed circuit board design program may be installed in memory via a portable recording medium.

[0012] The data input unit 2 receives data such as circuit diagrams and netlists from the outside. The circuit diagrams include image data and text data. The user I / F 4 receives operations from the designer and displays the screen.

[0013] The CAD unit 3 creates binary CAD data using the data input from the data input unit 2 in accordance with the designer's operations.

[0014] The layout design unit 21 includes a preprocessing unit 51, a grouping processing unit 8, a component classification unit 10, a neighboring block generation unit 11, a neighboring block component layout design unit 12, and an overall layout design unit 15. The preprocessing unit 51 includes a conversion unit 5, a net attribute setting unit 6, and a net point number setting unit 7. The overall layout design unit 15 includes a power tree setting unit 13, a position specification unit 14, a model generation unit 41, a neighboring block layout pattern design unit 31, a circuit diagram group area pattern design unit 32, an overall layout pattern design unit 33, and a component position adjustment unit 34.

[0015] The conversion unit 5 converts binary CAD data created based on a circuit diagram into text data, and creates a part name list of text data.

[0016] The net attribute setting unit 6 sets the attributes of nets connecting multiple components included in the circuit diagram. For example, the net attribute setting unit 6 sets the attributes of nets based on the names of nets included in the netlist. Furthermore, if the attribute of a first net connected to one end of an inductor is a power attribute, the net attribute setting unit 6 sets the attribute of a second net connected to the other end of the inductor to a power attribute regardless of the name of the second net. If the attribute of a first net connected to one end of the inductor is a ground attribute, the net attribute setting unit 6 sets the attribute of a second net connected to the other end of the inductor to a ground attribute regardless of the name of the second net.

[0017] The net score setting unit 7 sets scores for each net in response to the designer selecting a net from the list of nets displayed on the user I / F 4 and setting scores for the selected net. This is because the importance of a net in terms of electrical performance differs depending on its function, and therefore importance is set for each net.

[0018] FIG. 2 is a flowchart showing the procedure for designing the layout of components on a printed circuit board by the printed circuit board design device 1 according to the embodiment.

[0019] In S1, the pre-processing unit 51 acquires and generates data necessary for component layout design. Fig. 3 is a flowchart showing the detailed processing procedure of S1 in Fig. 2.

[0020] 3, in S101, data input unit 2 inputs data from an external device. The data includes a circuit diagram, an outline drawing, a netlist, a parts list, and an instruction manual. The circuit diagram includes image data representing components constituting a circuit and their connections, and text data representing component names, net names, and the like. For example, the circuit diagram is created in a PDF (Portable Document Format) file containing text.

[0021] In S102, the CAD unit 3 creates CAD data from the input data based on the operation by the designer via the user I / F 4.

[0022] In S103, the conversion unit 5 converts the binary CAD data into text data, which includes a list of part names and the like.

[0023] In S104, the net attribute setting unit 6 sets the attributes of the nets based on the netlist input to the data input unit 2. The net attribute setting unit 6 sets the attribute of the net to one of "power attribute," "ground attribute," and "signal attribute" based on the name of the net and the components connected to the net. The "power attribute" of a net indicates that the net transmits a power supply voltage. The "ground attribute" of a net indicates that the net transmits a ground voltage. The "signal attribute" of a net indicates that the net transmits a signal. For example, if the net name contains the string "GND," the net attribute setting unit 6 sets the attribute of the net to "ground attribute," and if the net name contains the string "VCC" or "3.3V," the net attribute setting unit 6 sets the attribute of the net to "power attribute." When the attribute of a first net connected to one end of the component "inductor" is "power attribute," the net attribute setting unit 6 sets the attribute of a second net connected to the other end of the component "inductor" to "power attribute," regardless of the name of the second net. When the attribute of a first net connected to one end of the component "inductor" is "ground attribute," the net attribute setting unit 6 sets the attribute of a second net connected to the other end of the component "inductor" to "ground attribute," regardless of the name of the second net. If the net attributes have been set in advance, the processing of S104 can be omitted.

[0024] In S105, the net score setting unit 7 sets a score for each net. For example, in response to the designer selecting a net from a list of nets displayed on the user I / F 4 and inputting a score for the selected net, the net score setting unit 7 sets a score for the selected net.

[0025] Referring again to FIG. 2 , in S2, the grouping processing unit 8 performs a process of grouping multiple components to be placed on the board to generate multiple circuit diagram groups. The grouping processing unit 8 generates multiple circuit diagram groups consisting of multiple components using a PDF-format circuit diagram containing text and the text-format component name list generated in S102. When a designer selects a partial range of the PDF-format circuit diagram containing text as a group, the grouping processing unit 8 extracts character strings from the text data of the selected range and compares the extracted character strings with the text-format component name list to identify the components belonging to the group. The components included in the selected range are identified as follows: If a character string included in the selected range is a component name registered in the text-format component name list, it can be determined that the character string represents a component included in the selected range (i.e., group). If a character string included in the selected range is not a component name registered in the text-format component name list, it can be determined that the character string does not represent a component included in the selected range (i.e., group).

[0026] In S4, the component classification unit 10 classifies all components belonging to all circuit diagram groups into parent components, child components electrically connected directly or indirectly to the parent components, and other components. The parent components are, for example, ICs. The child components are, for example, oscillators, bypass capacitors, damping resistors, electrolytic capacitors, and termination resistors.

[0027] The component classification unit 10 sets the generation of child components. The component classification unit 10 sets child components directly connected to a parent component as first-generation child components. The component classification unit 10 sets child components directly connected to a kth-generation child component as (k+1)th-generation child components, where k is a natural number greater than or equal to 1. However, the component classification unit 10 excludes connections to ground, and when a child component is connected to multiple nets, prioritizes the net attribute of the signal net. When a child component is connected to multiple components, the component is set as a child component of the next generation after the component of the youngest generation. First-generation child components are sometimes referred to as child components in the narrow sense. Second-generation child components are sometimes referred to as grandchild components. Third-generation child components are sometimes referred to as great-grandchild components. Figure 4 is a diagram for explaining the relationships between components.

[0028] Child components CH1 to CH7 in the narrow sense are directly connected to parent component PR1. Grandchild components GC1 to GC4 are directly connected to child component CH1 in the narrow sense. Grandchild component GC5 is directly connected to child component CH6 in the narrow sense. Great-grandchild component GG1 is directly connected to grandchild component GC2. Great-grandchild component GG2 is directly connected to grandchild component GC4. Grandchild components GC1 and GC3 are also directly connected to parent component PR1, but because they are connected to the ground pin of parent component PR1, they are not child components in the narrow sense.

[0029] The component classification unit 10 assigns priorities to first-generation components and classifies them into high-priority or low-priority first-generation components. High-priority first-generation components include, for example, bypass capacitors and oscillators.

[0030] The component classification unit 10 assigns priorities to second-generation and later child components according to the attributes of the nets connected to the child components. For example, the component classification unit 10 assigns the highest priority to a child component connected to a net with a signal attribute and a net with a ground attribute, assigns an intermediate priority to a child component connected to a net with a signal attribute and a net with a power supply attribute, and assigns the lowest priority to a child component connected to a net with a signal attribute and a net with a signal attribute.

[0031] In S5, the proximity block generator 11 generates a plurality of proximity blocks, each of which has as its constituent elements a parent part and a child part that is directly or indirectly connected to the parent part.

[0032] In S6, the adjacent block component layout design unit 12 determines the layout of components in the adjacent block. Fig. 5 is a flowchart showing the detailed processing procedure of S6 in Fig. 2.

[0033] In S201, the adjacent block intra-component placement design unit 12 selects an unselected adjacent block that contains the largest number of components.

[0034] In S202, if there is a nearby block that is similar to the selected nearby block among the nearby blocks for which the placement of components has already been determined, the process proceeds to S203, and if there is no such nearby block, the process proceeds to S204.

[0035] The adjacent block intra-component placement design unit 12 calculates the similarity between adjacent block A, in which the placement of components has been determined, and the selected adjacent block B as follows.

[0036] When the total number of components contained in neighboring block A is N and the total number of components contained in neighboring block A that are also contained in neighboring block B is X, the similarity R between neighboring block A and neighboring block B is calculated using the following formula. The neighboring block intra-component layout design unit 12 determines that neighboring block A and neighboring block B are similar when the similarity R is equal to or greater than a predetermined threshold. R = X / N (A1) Here, two components are considered to be the same part when they have the same product number. Next, an example of calculating the similarity will be described.

[0037] Fig. 6(a) is a diagram showing the parts in proximity block A. Fig. 6(b) is a diagram showing the parts in proximity block B. Fig. 6(c) is a diagram showing whether the parts in proximity block A and the parts in proximity block B are the same or not.

[0038] As shown in FIG. 6A, proximity block A includes IC1 as a parent component, and resistors R1, R2, R3, and R4 and capacitors C1 and C2 as child components.

[0039] As shown in FIG. 6B, the proximity block B includes an IC2 as a parent component, and resistors R101, R102, R103, and R104 and a capacitor C101 as child components.

[0040] 6(c) shows whether the components in neighboring block A and neighboring block B are identical. It shows that IC1 and IC2 are identical, R1, R2, R3, and R4 are identical to R101, R102, R103, and R104, respectively, and C1 and C101 are identical. The neighboring block component placement design unit 12 calculates the similarity between neighboring block A and neighboring block B to be 6 / 7.

[0041] In S203, the adjacent block component placement design unit 12 matches the placement of components in the selected adjacent block with the placement of the same components in a similar adjacent block.

[0042] 6, if it is determined that adjacent blocks A and B are similar, R101 is positioned so that the positional relationship of R1 relative to IC1 matches the positional relationship of R101 relative to IC2. The same applies to R102, R103, R104, and C101.

[0043] In S204, the adjacent block component placement design unit 12 determines the placement of unplaced components (i.e., components whose identical components do not exist in similar adjacent blocks) among the components of the selected adjacent block, and components in the adjacent block that are not similar to any of the adjacent blocks whose component placements have already been determined, based on priority.

[0044] The adjacent block intra-component placement design unit 12 places high-priority first-generation child components and multiple child components (high-priority child component groups) directly or indirectly connected to these high-priority first-generation child components closer to the parent component than low-priority first-generation child components and multiple child components (low-priority child component groups) directly or indirectly connected to these low-priority first-generation child components. Figure 7 is a diagram showing an example of placement of high-priority first-generation components and low-priority first-generation components.

[0045] As shown in Figure 7, high-priority first-generation child components CH1 and CH2 are placed in the first row, closest to the parent component. Low-priority first-generation child components CH3 are placed in the second row, second closest to the parent component. The first row is the position closest to the side of the parent component permitted by the design rules. The second row is the position second closest to the side of the parent component permitted by the design rules. Design rules are rules that stipulate mounting constraints, etc.

[0046] The adjacent block intra-component placement design unit 12 places child components in one high-priority component group or child components in one low-priority component group as follows.

[0047] The adjacent block intra-component placement design unit 12 places a k-th generation child component at a position farther from the parent component than a direct (k-1)th generation child component directly connected to this component, where k is a natural number equal to or greater than 2. The priority of a certain child component (hereinafter referred to as the first child component) is higher than the priority of all child components (hereinafter referred to as the second child components) that are directly connected to the first child component and that pass through one more child component than the first child component on their way to the parent component.

[0048] The adjacent block intra-component layout design unit 12 determines the layout of multiple child components of the second generation or later that are not directly related, according to the priority corresponding to the attributes of the nets to which they are connected. In other words, when there are multiple second child components as described above, the priority of each second child component is determined based on the attributes of the two nets connected to each second child component. Figure 8 shows an example of the placement of child components.

[0049] A high-priority child component group GR1 consisting of a high-priority child component CH1, and grandchild components GC1 and GC2 connected directly or indirectly to the high-priority child component CH1, and a high-priority child component group GR2 consisting of the high-priority child component CH2, and grandchild component GC3 and great-grandchild component GG1 connected directly or indirectly to the high-priority child component CH2, are arranged closer to the parent component than a low-priority child component group GR3 consisting of a low-priority child component CH3, and grandchild components GC4, GC5, and great-grandchild component GG2 connected directly or indirectly to the low-priority child component CH3.

[0050] In the high-priority child component group GR1, the grandchild component GC1 is connected to a net with a signal attribute and a net with a ground attribute, while the grandchild component GC2 is connected to a net with a signal attribute and a net with a power attribute. Therefore, the grandchild component GC1 is placed closer to the parent component PR1 than the grandchild component GC2.

[0051] In the high-priority child part group GR2, the great-grandchild part GG1 is directly connected to the grandchild part GC3 and is a direct descendant child part of the grandchild part GC3. Therefore, the grandchild part GC3 is placed closer to the parent part PR1 than the great-grandchild part GG1.

[0052] In the low-priority child component group GR3, the great-grandchild component GG2 is directly connected to the grandchild component GC4 and is a direct descendant child component of the grandchild component GC4. Therefore, the grandchild component GC4 is placed closer to the parent component PR1 than the great-grandchild component GG2. The grandchild components GC4 and GC5 are both connected to a net with a signal attribute and a net with a signal attribute. The grandchild components GC4 and GC5 are placed at approximately the same distance from the low-priority child component CH3. FIG. 9 is a diagram for explaining the area around the parent component PR1.

[0053] The first side surface LE1 of the parent part and the second side surface LE2 of the parent part are connected at a first intersection line P1, the first side surface LE1 of the parent part and the third side surface LE3 of the parent part are connected at a second intersection line P2, the second side surface LE2 of the parent part and the fourth side surface LE4 of the parent part are connected at a third intersection line P3, and the third side surface LE3 of the parent part and the fourth side surface LE4 of the parent part are connected at a fourth intersection line P4.

[0054] The surface that divides the space defined by the first extension surface ET1, which is an extension of the first side surface LE1 of the parent part toward the first intersection line P1, and the second extension surface ET2, which is an extension of the second side surface LE2 of the parent part toward the first intersection line P1, is defined as the first boundary surface BR1.

[0055] The surface that divides the space defined by the third extension surface ET3, which is an extension of the first side surface LE1 of the parent part toward the second intersection line P2, and the fourth extension surface ET4, which is an extension of the third side surface LE3 of the parent part toward the second intersection line P2, is defined as the second boundary surface BR2.

[0056] The region defined by the first side surface LE1, the first boundary surface BR1, and the second boundary surface BR2 of the parent part is defined as a first region RE1.

[0057] The third boundary surface BR3 is the surface that divides the space defined by a fifth extension surface ET5, which is an extension of the second side surface LE2 of the parent part toward the third intersection line P3, and a sixth extension surface ET6, which is an extension of the fourth side surface LE4 of the parent part toward the third intersection line P3.

[0058] The region defined by the second side surface LE2, the first boundary surface BR1, and the third boundary surface BR3 of the parent part is defined as a second region RE2.

[0059] The fourth boundary surface BR4 is the surface that bisects the space defined by the seventh extension surface ET7, which is an extension of the third side surface LE3 of the parent part toward the fourth intersection line P4, and the eighth extension surface ET8, which is an extension of the fourth side surface LE4 of the parent part toward the fourth intersection line P4.

[0060] The region defined by the third side surface LE3 of the parent part, the second boundary surface BR2, and the fourth boundary surface BR4 is defined as a third region RE3.

[0061] The region defined by the fourth side surface LE4 of the parent part, the third boundary surface BR3, and the fourth boundary surface BR4 is defined as a fourth region RE4.

[0062] In the above, the first side surface LE1 and the first boundary surface BR1 intersect at 135 degrees, and the first side surface LE1 and the second boundary surface BR2 intersect at 135 degrees, but this is not limited to this, and it is sufficient that the first side surface LE1 and the first boundary surface BR1 intersect at an angle greater than 90 degrees, and the first side surface LE1 and the second boundary surface BR2 intersect at an angle greater than 90 degrees.

[0063] The second side surface LE2 and the first boundary surface BR1 intersect at 135 degrees, and the second side surface LE2 and the third boundary surface BR3 intersect at 135 degrees, but this is not limited to this, and it is sufficient that the second side surface LE2 and the first boundary surface BR1 intersect at an angle greater than 90 degrees, and the second side surface LE2 and the third boundary surface BR3 intersect at an angle greater than 90 degrees.

[0064] The third side surface LE3 and the second boundary surface BR2 intersect at 135 degrees, and the third side surface LE3 and the fourth boundary surface BR4 intersect at 135 degrees, but this is not limited to this, and it is sufficient that the third side surface LE3 and the second boundary surface BR2 intersect at an angle greater than 90 degrees, and the third side surface LE3 and the fourth boundary surface BR4 intersect at an angle greater than 90 degrees.

[0065] The fourth side surface LE4 and the third boundary surface BR3 intersect at 135 degrees, and the fourth side surface LE4 and the fourth boundary surface BR4 intersect at 135 degrees, but this is not limited to this, and it is sufficient that the fourth side surface LE4 and the third boundary surface BR3 intersect at an angle greater than 90 degrees, and the fourth side surface LE4 and the fourth boundary surface BR4 intersect at an angle greater than 90 degrees.

[0066] The proximity block intra-component layout design unit 12 places child components connected to pins of a parent component arranged along the first side surface LE1 and child components directly or indirectly connected to the child components in the first region RE1. The proximity block intra-component layout design unit 12 places child components connected to pins of a parent component arranged along the second side surface LE2 and child components directly or indirectly connected to the child components in the second region RE2. The proximity block intra-component layout design unit 12 places child components connected to pins of a parent component arranged along the third side surface LE3 and child components directly or indirectly connected to the child components in the third region RE3. The proximity block intra-component layout design unit 12 places child components connected to pins of a parent component arranged along the fourth side surface LE4 and child components directly or indirectly connected to the child components in the fourth region RE4.

[0067] The adjacent block component placement design unit 12 places child components having the same priority on a line at the same distance from the parent component.

[0068] If it is not possible to place all child parts of the same priority on the same line in any of the four regions, the adjacent block intra-component placement design unit 12 places one or more child parts of the same priority on the line next closest to the parent part in the same region. Figure 10 is a diagram showing an example of the placement of first-generation child parts of the same priority.

[0069] Child components CH1 to CH5 are all high-priority first-generation child components or all low-priority first-generation child components, and have the same priority. In the first region RE1, child components CH2 and CH4 are placed on the first line closest to parent component PR1, and child components CH1, CH3, and CH5 are placed on the second line next closest to parent component PR1. On the second line, child component CH1 is placed across the second extension plane ET2, and child component CH5 is placed across the fourth extension plane ET4. Note that components within a proximity block can be placed not only on the front surface but also on the back surface of the board.

[0070] Referring again to FIG. 5, in S205, if all adjacent blocks have been selected, the process ends, and if there are any unselected adjacent blocks, the process returns to S201.

[0071] 2 again, in S7, the proximity block generation unit 11 sets rectangular regions SR1 for all proximity blocks. The rectangular regions SR1 are rectangular regions that surround the parent components and high-priority first-generation child components included in the proximity blocks. More specifically, the proximity block generation unit 11 sets the smallest rectangular region that surrounds the parent components, the high-priority first-generation child components, the placement locations of via holes to be placed in a later process for connection with the parent components, the placement locations of via holes to be placed in a later process for connection with the high-priority first-generation child components, and the placement locations of ground patterns or margin areas to be placed in a later process as the rectangular region SR1 of the proximity blocks.

[0072] 11 is a diagram showing an example of a rectangular region SR1 of a proximity block. The rectangular region SR1 is set to surround a parent component PR1, high-priority first-generation child components CH1, CH2, and CH4, connection vias VR1, VR2, and VR3, and a ground pattern or margin region RGH included in the proximity block.

[0073] In S8, the proximity block generator 11 sets polygon regions SR2 for all proximity blocks. The polygon regions SR2 of the proximity blocks are polygon regions that surround all components included in the proximity blocks. More specifically, the proximity block generator 11 sets, as the polygon regions SR2 of the proximity blocks, polygon regions that surround the parent components, all child components (grandchild components, great-grandchild components, and all child components subsequent to the great-grandchild components), via holes, and ground patterns or margin areas that will be arranged in later processes.

[0074] 12 is a diagram showing an example of a polygon region SR2 of a proximity block. The polygon region SR2 of the proximity block is set to surround all components PR1, CH1 to CH8, GC1 to GC3, connecting vias VR1, VR2, VR3, and the ground pattern or margin region RGH included in the proximity block.

[0075] Referring again to FIG. 2, in S9, the overall layout design unit 15 executes the overall layout design process multiple times to arrange multiple adjacent blocks included in the circuit diagram groups in the multiple circuit diagram groups.

[0076] FIG. 13 is a flowchart showing the detailed processing procedure of S9 in FIG. 2 in this embodiment.

[0077] In S501, the power tree setting unit 13 sets the relationship between the supply destination adjacent blocks and the supply source adjacent blocks for all power nets on the circuit diagram as a power tree. The power tree setting unit 13 acquires the relationship between the power nets and the adjacent blocks connected to the power nets from the connection relationship between the netlist and the adjacent blocks.

[0078] The connection relationship between two adjacent blocks can be obtained by understanding the connections between components in one adjacent block and components in the other adjacent block based on the netlist. Next, the procedure for setting the power supply tree will be described.

[0079] Fig. 14(a) is a diagram showing a netlist, Fig. 14(b) is a diagram showing the connection relationships between components, and Fig. 14(c) is a diagram showing an example of a power supply tree.

[0080] 14(a) shows a netlist. The power tree setting unit 13 references the netlist and determines that 12V power is supplied through CN1(1), F1(1), and IC1(1). The numbers in parentheses indicate pin numbers. The power tree setting unit 13 references the netlist and determines that 5V power is supplied through IC1(2), FL1(1), and R2(1). The power tree setting unit 13 references the netlist and determines that 3V power is supplied through IC2(2) and IC5(1).

[0081] 14(b) shows the connection relationships between components. Proximity block NB1 includes CN1, proximity block NB2 includes F1 and IC2, proximity block NB3 includes IC1, proximity block NB4 includes FL1 and IC3, proximity block NB5 includes R2 and IC4, and proximity block NB6 includes IC5. The first pin of CN1 is connected to the first pin of F1 and the first pin of IC1, the second pin of IC1 is connected to the first pin of FL1 and the first pin of R2, and the second pin of IC2 is connected to the first pin of IC5.

[0082] The designer specifies the source of the 12V power supply from among NB1, NB2, and NB3. The designer specifies the source of the 5V power supply from among NB3, NB4, and NB5. The designer specifies the source of the 3V power supply from among NB2 and NB6.

[0083] An example of a power supply tree is shown in Figure 14(c). This power supply tree is set up when a designer specifies NB1 as a source of 12V power, NB3 as a source of 5V power, and NB2 as a source of 3V power. As shown in Figure 14(c), 12V power is supplied from the neighboring block NB1 to the neighboring blocks NB2 and NB3, 5V power is supplied from the neighboring block NB3 to the neighboring blocks NB4 and NB5, and 3V power is supplied from the neighboring block NB2 to the neighboring block NB6.

[0084] Referring to FIG. 13, in S502, the position specification unit 14 sets position specification components whose positions on the board are determined and semi-position specification components whose positions on the board are roughly determined. The position specification unit 14 identifies the position specification components and their designated positions based on CAD ASCII data. The designated positions include coordinates on the board, placement surface, and orientation. The position specification unit 14 sets the semi-position specification components and their approximate designated positions based on specifications made by the designer via the user I / F 4. FIG. 15 is a diagram showing examples of position specification components and semi-position specification components. CN2, S1 to S8, and D2 to D4 are position specification components whose positions are specified.

[0085] IC2, IC3, IC4, IC7, CN1, CN3, CN4, and CN5 are semi-position-specified components whose approximate positions are specified.

[0086] 13, in S503, the model generation unit 41 models the circuit diagram group to create a circuit diagram group model, which is used when calculating an area on the board where the circuit diagram group is to be placed.

[0087] The circuit diagram group model includes the absolute position (hereinafter referred to as "position") of the circuit diagram group placed on the board, the size (width and height) of the circuit diagram group placed on the board, and connection information that indicates one-to-one connections between the circuit diagram group and other circuit diagram groups to which the circuit diagram group is connected. The position and size change depending on the placement.

[0088] The model generation unit 41 models the proximity blocks to create a proximity block model, which is used when placing the proximity blocks on a substrate.

[0089] The proximity block model includes information representing the absolute position of the proximity block on the substrate, the position and size of the proximity block's rectangular area, the position and size of the proximity block's polygonal area, the orientation of the proximity block on the substrate, connection information with other proximity block models connected one-to-one to the proximity block, and the placement surface of the proximity block. The position, orientation, and placement surface change depending on the placement. The orientation may be, for example, 0, 90, 180, or 270°, but is not limited to these. The placement surface is the front or back of the substrate. The polygonal area of ​​the proximity block is used when determining the placement of the proximity block during overall placement design. Next, the orientation of the proximity block NB on the substrate will be described.

[0090] 16(a) is a diagram showing an example of an arrangement when the orientation is 0°. The horizontal direction of the board is set as the X-axis, and the vertical direction of the board is set as the Y-axis. The upper side U1 and lower side B1 of the board are set parallel to the X-axis direction, and the left side L1 and right side R1 of the board are set parallel to the Y-axis direction. When the orientation of the proximity block NB is 0°, for example, the direction of the upper side U2 of the proximity block NB is parallel to the direction of the upper side U1 of the board (parallel to the X-axis), and the upper side U2 of the proximity block NB is closest to the upper side U1 of the board.

[0091] 16B is a diagram showing an example of an arrangement in which the orientation is 90°. When the orientation of the proximity block NB is 90°, for example, the orientation of the upper side surface U2 of the proximity block NB is rotated 90° clockwise from the orientation of the upper side surface U1 of the substrate.

[0092] 16C is a diagram showing an example of an arrangement in which the orientation is 180°. When the orientation of the proximity block NB is 180°, for example, the orientation of the upper side surface U2 of the proximity block NB is rotated 180° clockwise from the orientation of the upper side surface U1 of the substrate.

[0093] 16(d) is a diagram showing an example of an arrangement in which the orientation is 270°. When the orientation of the proximity block NB is 270°, for example, the orientation of the upper side surface U2 of the proximity block NB is rotated 270° clockwise from the orientation of the upper side surface U1 of the substrate.

[0094] The model generation unit 41 creates a circuit diagram group connection model that models the connections between two or more circuit diagram group models. The circuit diagram group connection model is used to score candidate area patterns for the circuit diagram group models. The circuit diagram group connection model includes a total net score and a virtual pin. The total net score is the sum of the net scores between circuit diagram group models that have connections. The virtual pin is the center of the circuit diagram group model. The virtual pin is a reference point when measuring the distance between circuit diagram group models.

[0095] The model generation unit 41 creates a proximity block connection model that models the connections between two or more proximity block models. The proximity block connection model is used for scoring candidate placement patterns of the proximity block models and for scoring candidate overall placement patterns. The proximity block connection model includes a total net score, connection pins, and virtual pins. The total net score is the sum of the net scores between adjacent blocks that have connections. The connection pin is a pin that connects two or more adjacent blocks, and the coordinates of the virtual pin are a weighted average with the net score of the connection pin coordinates as the weight. The virtual pin is a point that serves as a reference when measuring the distance between two proximity block models. The relationship between the connection pins and the virtual pins will be explained. Figure 17 is a diagram showing an example of a connection pin.

[0096] Connection pins P1 and P2 of the proximity block model RB1 are connected to connections P6 and P7 of the proximity block model RB2 via paths L1 and L2. Connection pins P3, P4, and P5 of the proximity block model RB1 are connected to connection pins P11, P12, and P13 of the proximity block model RB3 via paths L3, L4, and L5 via connection pins P8, P9, and P10 of the proximity block model RB2. Figure 18 is a diagram showing virtual pins obtained from the connection pins of Figure 17.

[0097] When each of the multiple paths connects only the connection pins of two proximity model block models, a virtual pin is set from the connection pins of the two proximity block models of the multiple paths. When each of the multiple paths connects the connection pins of three or more proximity model block models, a virtual pin is set from the connection pins of the three or more proximity block models of the multiple paths.

[0098] For the paths L1 and L2, a virtual pin VP1 of the neighboring block model RB1 and a virtual pin VP2 of the neighboring block model RB2 are defined.

[0099] For paths L3, L4, and L5, a virtual pin VP3 of the proximity block model RB1, a virtual pin VP4 of the proximity block model RB2, and a virtual pin VP5 of the proximity block model RB3 are defined. Next, a method for calculating the coordinates of the virtual pins will be described. Figure 19 is a diagram for explaining an example of the coordinates of the virtual pins of the proximity block models.

[0100] The proximity block represented by the proximity block model RB1 includes a parent part PR1 and child parts CH1 and CH2, while the proximity block represented by the proximity block model RB2 includes a parent part PR2.

[0101] The connection pin P3 (x3, y3) of the parent part PR1 is connected to the connection pin P6 (x6, y6) of the parent part PR2, and the number of points of the net connecting them is 10. The connection pin P1 (x1, y1) of the child part CH1 is connected to the connection pin P4 (x4, y4) of the parent part PR2, and the number of points of the net connecting them is 10. The connection pin P2 (x2, y2) of the child part CH2 is connected to the connection pin P5 (x5, y5) of the parent part PR2, and the number of points of the net connecting them is 10.

[0102] The coordinates (XV1, YV1) of the virtual pin VP1 of the proximity block model RB1 are calculated by the following formulas: XV1=X1*10 / 30+X2*10 / 30+X3*10 / 30...(B1) YV1=Y1*10 / 30+Y2*10 / 30+Y3*10 / 30...(B2)

[0103] The coordinates (XV2, YV2) of the virtual pin VP2 of the proximity block model RB2 are calculated by the following formulas: XV2=X4*10 / 30+X5*10 / 30+X6*10 / 30...(B3) YV2=Y4*10 / 30+Y5*10 / 30+Y6*10 / 30...(B4) Figure 20 is a diagram for explaining another example of the coordinates of the virtual pins of the proximity block model.

[0104] The example in Figure 20 differs from the example in Figure 19 in that connection pin P3 (x3, y3) of parent part PR1 and connection pin P6 (x6, y6) of parent part PR2 are connected, and the number of points in the net connecting them is 100.

[0105] The coordinates (XV1, YV1) of the virtual pin VP1 of the proximity block model RB1 are calculated by the following formulas: XV1=X1*10 / 120+X2*10 / 120+X3*100 / 120...(B5) YV1=Y1*10 / 120+Y2*10 / 120+Y3*100 / 120...(B6)

[0106] The coordinates (XV2, YV2) of the virtual pin VP2 of the adjacent block model RB2 are calculated by the following formulas: XV2=X4*10 / 120+X5*10 / 120+X6*100 / 120...(B7) YV2=Y4*10 / 120+Y5*10 / 120+Y6*100 / 120...(B8)

[0107] Fig. 21(a) is a diagram showing a virtual pin between the neighboring block model RB1 and the neighboring block model RB2, and Fig. 21(b) is a diagram showing a virtual pin between the neighboring block model RB2 and the neighboring block model RB3.

[0108] The virtual pin VP1 of the proximity block model RB1 is connected to the virtual pin VP2 of the proximity block model RB2. The virtual pin VP3 of the proximity block model RB1 is connected to the virtual pin VP4 of the proximity block model RB2. The virtual pin VP4 of the proximity block model RB2 is connected to the virtual pin VP5 of the proximity block model RB3.

[0109] 13, the model generation unit 41 sets an ideal orientation relationship between two adjacent block models. The model generation unit 41 creates a table that indicates the ideal orientation relationship between two adjacent block models that have connections and are included in the same circuit diagram group or different circuit diagram groups.

[0110] 22(a) and (b) are diagrams for explaining the ideal orientation relationship between two adjacent block models.

[0111] The proximity block represented by the proximity block model RB1 includes a parent component IC1 and child components CH1, CH2, and CH3. The proximity block represented by the proximity block model RB2 includes a parent component IC2 and child components CH4 and CH5. Child component CH1, which is connected to the right side surface of parent component IC1, is connected to child component CH5, which is connected to the upper side surface of parent component IC2, by wiring WR1. Child component CH3, which is connected to the right side surface of parent component IC1, is connected to child component CH4, which is connected to the upper side surface of parent component IC2, by wiring WR2. Thus, the right side surface R2 of the proximity block model RB1 is connected to the upper side surface U2 of the proximity block model RB2.

[0112] In Figure 22(a), the orientation of the proximity block model RB1 is represented by the orientation of the parent component IC1 and is 0 degrees. The orientation of the proximity block model RB2 is represented by the orientation of the parent component IC2 and is also 0 degrees. In Figure 22(a), the right side surface R2 of the proximity block model RB1 and the upper side surface U2 of the proximity block model RB2 do not face each other. In other words, the distance between the right side surface R2 of the connected proximity block model RB1 and the upper side surface U2 of the proximity block model RB2 is not the shortest. Therefore, the distance between the wiring WR1 and WR2 is also not the shortest.

[0113] In FIG. 22(b), similar to FIG. 22(a), the orientation of the proximity block model RB1 is represented by the orientation of the parent component IC1, and is 0 degrees. Unlike FIG. 22(a), the orientation of the proximity block model RB2 is represented by the orientation of the parent component IC2, and is 270 degrees. In FIG. 22(b), the right side surface R2 of the proximity block model RB1 and the upper side surface U2 of the proximity block model RB2 face each other at the shortest distance. That is, the orientation of the proximity block model RB1 is such that the right side surface R2 of the proximity block model RB1 is closest to the proximity block model RB2, and the orientation of the proximity block model RB2 is such that the upper side surface U2 of the proximity block model RB2 is closest to the proximity block model RB1. Therefore, the distance between the wirings WR1 and WR2 is also shortest.

[0114] FIG. 23 is a diagram for explaining the ideal orientation relationship between two adjacent block models.

[0115] The virtual pin of the adjacent block model RB1 is VP1, and the virtual pin of the adjacent block model RB2 is VP2.

[0116] Of the four side surfaces of the proximity block model RB1, the surface closest to the virtual pin VP1 is the right side surface R2, and of the four side surfaces of the proximity block model RB2, the surface closest to the virtual pin VP2 is the left side surface L2.

[0117] The right side surface R2 of the neighboring block model RB1 and the left side surface L2 of the neighboring block model RB2 face each other at the shortest distance. That is, the neighboring block model RB1 is oriented such that the right side surface R2 of the neighboring block model RB1 is closest to the neighboring block model RB2, and the neighboring block model RB2 is oriented such that the left side surface L2 of the neighboring block model RB2 is closest to the neighboring block model RB1.

[0118] 24 is a diagram showing an example of a table showing the relationship between the ideal orientations of two neighboring block models. For example, the right side of neighboring block model RB1 and the upper side of neighboring block model RB2 face each other at the shortest distance. That is, between neighboring block model RB1 and neighboring block model RB2, the ideal orientation of neighboring block model RB1 relative to neighboring block model RB2 is such that the right side of neighboring block model RB1 is closest to neighboring block model RB2, and the ideal orientation of neighboring block model RB2 relative to neighboring block model RB1 is such that the upper side of neighboring block model RB2 is closest to neighboring block model RB1.

[0119] Referring again to FIG. 13, the processing of S505 to S508 is repeated multiple times. The repetition may end after a predetermined number of executions or after a predetermined time has elapsed. Alternatively, the repetition may end when a predetermined condition is met (for example, when the total score, which will be described later, falls below a certain value). The initial processing will be described below.

[0120] In S505, the adjacent block arrangement pattern design unit 31 generates, for each circuit diagram group, one or more arrangement patterns within the circuit diagram group for the multiple adjacent blocks included in the circuit diagram group. Fig. 25 is a flowchart showing the detailed processing procedure of S505 in Fig. 13.

[0121] In S601, the neighboring block arrangement pattern design unit 31 creates multiple candidate arrangement patterns for multiple neighboring block models included in each circuit diagram group. The size of the neighboring block model is the size of the polygon area of ​​the neighboring block. The neighboring block arrangement pattern design unit 31 generates multiple candidate arrangement patterns by arbitrarily changing the position and orientation of the neighboring block model.

[0122] In S602, the adjacent block arrangement pattern design unit 31 performs clustering of the generated multiple candidate arrangement patterns. The overall arrangement design unit 15 determines whether multiple candidate arrangement patterns are included in the same cluster based on the positions of the two connecting adjacent block models. Figure 26 is a diagram for explaining an example of clustering of arrangement patterns.

[0123] 26, it is assumed that only proximity block models RB1 and RB2 are included in the circuit diagram group. If the overlapping area between proximity block model RB1 in placement pattern A and proximity block model RB1 in placement pattern B is equal to or greater than a threshold (e.g., 50% or more), and if the overlapping area between proximity block model RB2 in placement pattern A and proximity block model RB2 in placement pattern B is equal to or greater than a predetermined threshold (e.g., 50% or more), it is determined that placement pattern A and placement pattern B belong to the same cluster. FIG. 27 is a diagram showing the results of clustering placement patterns.

[0124] By clustering the six arrangement patterns A to F, it is determined that arrangement patterns A and B belong to cluster A, arrangement patterns C, E and F belong to cluster B, and arrangement pattern D belongs to cluster C.

[0125] Referring again to FIG. 25, in S603, the adjacent block arrangement pattern design unit 31 scores a plurality of candidate arrangement patterns included in each cluster.

[0126] The proximity block arrangement pattern design unit 31 performs scoring between two proximity block models (i-th set) connected by a virtual pin as follows. However, when the proximity block arrangement pattern design unit 31 refers to the power supply tree and finds that two proximity block models receive power supply voltage from a common proximity block model and also supply power supply voltage to other proximity block models, it does not perform scoring between those two proximity block models. The score Si is calculated using the following formula.

[0127] Si=(WS1*f(A1)+WS2*f(A2)+WS3*f(A3)+WS4*f(A4)+WS5*f(A5))*NS…(C1)

[0128] The first index A1 represents a score based on the distance between two adjacent block models. The first index A1 is the Manhattan distance between the virtual pins of the two adjacent block models. f(A1) is the deviation value of A1. The second index A2 represents a score based on the relationship in orientation between the two adjacent block models. f(A2) is the deviation value of A2. Figure 28(a) is a diagram showing an example of the relationship in orientation between two adjacent block models.

[0129] The proximity block represented by the proximity block model RB1 includes a parent part PR1 and a child part CH1. The proximity block represented by the proximity block model RB2 includes a parent part PR2 and a child part CH2. The child part CH1 is connected to the right side of the parent part PR1. The child part CH2 is connected to the left side of the parent part PR2. The child parts CH1 and CH2 are connected by wiring NX.

[0130] Therefore, the right side surface R2 of the neighboring block model RB1 and the left side surface L2 of the neighboring block model RB2 are connected.

[0131] In the example of Figure 28(a), the right side R2 of the proximity block model RB1 and the left side L2 of the proximity block model RB2 face each other at the shortest distance. That is, the orientation of the proximity block model RB1 is such that the right side R2 of the proximity block model RB1 is closest to the proximity block model RB2, and the orientation of the proximity block model RB2 is such that the left side L2 of the proximity block model RB2 is closest to the proximity block model RB1. Therefore, the distance between the right side R2 of the connected proximity block model RB1 and the left side L2 of the connected proximity block model RB2 is shortest. Therefore, the distance of the wiring NX is also shortest. Figure 28(b) is a diagram showing another example of the relationship between the orientations of two proximity block models.

[0132] 28(b), the orientation of the proximity block model RB1 is such that the right side R2 of the proximity block model RB1 is closest to the proximity block model RB2, but the orientation of the proximity block model RB2 is such that the right side R2 of the proximity block model RB2 is closest to the proximity block model RB1. Therefore, the distance between the right side R2 of the connected proximity block model RB1 and the left side L2 of the connected proximity block model RB2 is not shortest. As a result, the distance of the wiring NX is also not shortest.

[0133] 29 is a diagram showing an example of scores based on the relationship between the orientations of two neighboring block models. In this example, the scores for the orientations of the two neighboring blocks are shown when the right side R2 of the neighboring block model RB1 is connected to the upper side U2 of the neighboring block model RB2.

[0134] In Fig. 29, the left column shows the faces of the neighboring block model RB1 that are closest to the neighboring block model RB2. The center column shows the faces of the neighboring block model RB2 that are closest to the neighboring block model RB1. That is, in Fig. 28, the right column shows the scores when the faces in the left column of the neighboring block model RB1 and the faces in the center column of the neighboring block model RB2 face each other at the shortest distance.

[0135] When the orientation relationship is ideal, the score is the best, ie, "0." The greater the difference from the ideal orientation relationship, the higher (worse) the score becomes.

[0136] Even if the positional relationship between two neighboring block models is not horizontal or vertical, a score can be obtained based on the orientation relationship between the two neighboring block models. Figure 30 shows another example of the orientation relationship between two neighboring block models.

[0137] Assume that the upper side surface U2 of the proximity block model RB1 is connected to the right side surface R2 of the proximity block model RB2. The proximity block model RB2 is positioned to the upper right of the proximity block model RB1. The proximity block model RB1 is positioned to the lower right of the proximity block model RB2. The orientation of the proximity block model RB2 with respect to the proximity block model RB1 is determined based on the positional relationship of the virtual pin of the proximity block model RB2 with respect to the upper side surface U2, which is closest to the virtual pin of the proximity block model RB1.

[0138] The orientation of the proximity block model RB1 relative to the proximity block model RB2 is determined based on the positional relationship of the virtual pin of the proximity block model RB1 with respect to the right side surface R2 that is closest to the virtual pin of the proximity block model RB2.

[0139] 30(a), the virtual pin of the proximity block model RB2 is located above the upper side surface U2 of the proximity block model RB1, so the orientation of the proximity block model RB2 relative to the proximity block model RB1 is "up." The virtual pin of the proximity block model RB1 is located to the right of the right side surface R2 of the proximity block model RB2, so the orientation of the proximity block model RB1 relative to the proximity block model RB2 is "right."

[0140] In the example of Figure 30(b), the virtual pin of the proximity block model RB2 is not located above the upper side surface U2 of the proximity block model RB1, so the orientation of the proximity block model RB2 with respect to the proximity block model RB1 is "right." The virtual pin of the proximity block model RB1 is not located to the right with respect to the right side surface R2 of the proximity block model RB2, so the orientation of the proximity block model RB1 with respect to the proximity block model RB2 is "down." This concludes the explanation of the second indicator A2.

[0141] The third index A3 represents a score based on whether or not a twist in the wiring occurs between two adjacent block models. f(A3) is the deviation value of A3. The third index A3 is set to a smaller value when there is no twist in the wiring than when there is a twist in the wiring. The twist in the wiring can be calculated from the positional relationship of the two components to which the wiring is connected.

[0142] 31(a) is a diagram showing an example where the wiring is twisted, and FIG. 31(b) is a diagram showing an example where the wiring is not twisted.

[0143] The proximity block represented by the proximity block model RB1 includes a parent part PR1 and child parts CH1 and CH3, while the proximity block represented by the proximity block model RB2 includes a parent part PR2 and child parts CH2 and CH4.

[0144] In Fig. 31(a), the wire NY between the child parts CH1 and CH4 and the wire NX between the child parts CH3 and CH2 are twisted. In Fig. 31(b), the wire NZ between the child parts CH1 and CH2 and the wire NW between the child parts CH3 and CH4 are not twisted.

[0145] The fourth indicator A4 represents a score based on whether or not a wire connected to another neighboring block model crosses a wire between two neighboring block models. f(A4) is the deviation value of A4. The fourth indicator A4 is set to a smaller value when there is no crossing than when there is crossing. The crossing of wires is determined using virtual wires that connect virtual pins of neighboring block models with straight lines.

[0146] Fig. 32(a) is a diagram showing an example where there is crossing of wiring, and Fig. 32(b) is a diagram showing an example where there is no crossing of wiring.

[0147] The proximity block represented by the proximity block model RB1 includes a parent part PR1 and a child part CH1, and the proximity block represented by the proximity block model RB2 includes a parent part PR2 and a child part CH2.

[0148] In Fig. 32(a), the wiring NX between the child parts CH1 and CH2 intersects with the wiring NY between the other two adjacent blocks, whereas in Fig. 32(b), the wiring NX between the child parts CH1 and CH2 does not intersect with the wiring between any of the other two adjacent block models.

[0149] The fifth indicator A5 represents a score based on whether or not a wiring path consisting of only horizontal directions, only vertical directions, or a wiring path consisting of both horizontal and vertical directions and having one bend exists between the virtual pins of two adjacent block models to connect the two adjacent block models. f(A5) is the deviation value of A5. The fifth indicator A5 is set to a smaller value when a wiring path exists than when no wiring path exists.

[0150] Fig. 33(a) is a diagram showing an example where a wiring path exists, and Fig. 33(b) is a diagram showing an example where a wiring path does not exist.

[0151] 33A, there is a wiring path PT1 consisting of horizontal and vertical directions with one bend that connects the virtual pin VP1 of the neighboring block model RB1 and the virtual pin VP2 of the neighboring block model RB2. Because there is a neighboring block model RB3, it is determined that the wiring path PT2 cannot connect the two neighboring blocks RB1 and RB2.

[0152] 33(b), the wiring path PT2 is determined to be unable to connect the two adjacent block models RB1 and RB2 because of the presence of the adjacent block model RB3. The wiring path PT1 is also determined to be unable to connect the two adjacent block models RB1 and RB2 because of the presence of the adjacent block model RB4.

[0153] NS is the total net score between two adjacent block models. WS1 to WS5 are weights. The designer can change the factors they prioritize by adjusting the values ​​of WS1 to WS5. The more desirable the placement pattern, the smaller the indices A1 to A5 become.

[0154] The adjacent block arrangement pattern design unit 31 may calculate the score Si based on at least one of the indicators A1 to A5.

[0155] When there are N sets of two adjacent block models connected by a virtual pin in one circuit diagram group, the adjacent block arrangement pattern design unit 31 determines the score of the candidate arrangement pattern to be the sum SS (=ΣSi) of the N scores S1 to SN. The more desirable the candidate arrangement pattern, the smaller the value of the sum SS.

[0156] Referring again to FIG. 25, in S604, the adjacent block arrangement pattern design unit 31 selects a candidate arrangement pattern for each cluster.

[0157] Fig. 34 is a flowchart showing the detailed processing procedure of S604 in Fig. 25. Fig. 35 is a diagram showing an example of selection of candidate arrangement patterns for cluster A. As shown in Fig. 35(a), candidate arrangement patterns A, B, D, E, and F belong to cluster A.

[0158] In S901, the adjacent block arrangement pattern design unit 31 sorts the plurality of candidate arrangement patterns of the cluster in the order of the arrangement area AS. In the example of Fig. 35, the candidate arrangement patterns are sorted as B, F, D, E, and A in the order of the smallest arrangement area AS.

[0159] In S902, the adjacent block arrangement pattern design unit 31 selects one or more candidate arrangement patterns with a small arrangement area AS (i.e., arrangement area AS is equal to or smaller than a predetermined threshold ATH). As shown in Fig. 35(b), candidate arrangement patterns B, D, and F with arrangement area AS equal to or smaller than the threshold ATH are selected. If there is no candidate arrangement pattern with an arrangement area AS equal to or smaller than the predetermined threshold ATH, the candidate arrangement pattern with the smallest arrangement area AS may be selected.

[0160] In S903, the adjacent block arrangement pattern design unit 31 sorts the candidate arrangement patterns selected in S902 in order of the sum SS. In the example of Fig. 35, the candidate arrangement patterns are sorted as F, D, and B in order of the smallest sum SS.

[0161] In S904, the adjacent block arrangement pattern design unit 31 selects one or more candidate arrangement patterns with a good sum SS (i.e., the sum SS is equal to or less than a predetermined threshold STH). As shown in Fig. 35(c), candidate arrangement patterns D and F with a sum SS equal to or less than the threshold STH are selected. If there is no candidate arrangement pattern with a sum SS equal to or less than the predetermined threshold STH, the candidate arrangement pattern with the smallest sum SS may be selected.

[0162] Referring again to FIG. 25, in S605, the adjacent block arrangement pattern design unit 31 sorts the selected candidate arrangement patterns of all clusters according to the scoring results.

[0163] In S606, the adjacent block arrangement pattern design unit 31 leaves one or more candidate arrangement patterns with a good sum SS (i.e., the sum SS is equal to or less than a predetermined threshold value FSTH) from among the selected candidate arrangement patterns of all clusters. If there is no candidate arrangement pattern with a sum SS equal to or less than the predetermined threshold value FSTH, the candidate arrangement pattern with the smallest sum SS may be left.

[0164] In S607, if there is overlap in the placement positions of multiple neighboring block models in each of the one or more remaining candidate placement patterns, the neighboring block placement pattern design unit 31 removes the overlap by moving at least one of the multiple overlapping neighboring block models. Such overlap occurs because, when placing one or more neighboring block models in the area of ​​the circuit diagram group, no restriction is set so that all neighboring block models fit completely within the area of ​​the circuit diagram group. In this way, one or more placement patterns are generated.

[0165] Fig. 36 is a diagram showing an example of placement patterns generated after the processing procedure of the flowchart in Fig. 25 is completed. A plurality of desirable placement patterns are generated for a plurality of neighboring block models included in each circuit diagram group.

[0166] 13 again, in S506, the circuit diagram group area pattern design unit 32 generates one or more area patterns representing the areas of the plurality of circuit diagram groups on the board. Fig. 37 is a flowchart showing the detailed processing procedure of S506 in Fig. 13.

[0167] In S701, the circuit diagram group region pattern design unit 32 creates multiple candidate region patterns for one or more circuit diagram group models on the board. A circuit diagram group model is a rectangular region having an area equal to or greater than the sum of the areas of all components in the circuit diagram group and equal to or less than twice the sum of the areas of all components included in the circuit diagram group. The circuit diagram group model regions are acquired, excluding the regions of circuit diagram group models that include position-specified components and semi-position-specified components on the board. The circuit diagram group region pattern design unit 32 generates multiple candidate region patterns by arbitrarily varying the positions and sizes of the circuit diagram group models while satisfying the above conditions. However, if the circuit diagram group model includes a position-specified component or a semi-position-specified component, the circuit diagram group region pattern design unit 32 acquires the region of the circuit diagram group model so that it includes the specified coordinates.

[0168] 38 and 39 are diagrams showing an example of acquiring an area of ​​a circuit diagram group model including a semi-position-specified component. Acquiring an area of ​​a circuit diagram group model including a position-specified component is similar to this.

[0169] On the board PRB, an area HR of the circuit diagram group model is acquired so as to include the designated coordinates PA of the half-position designated component.

[0170] When another circuit diagram group model includes a position-specified component or a semi-position-specified component, the circuit diagram group region pattern design unit 32 acquires the region of the circuit diagram group model so that the specified coordinates are not included.

[0171] In S702, the circuit diagram group region pattern design unit 32 performs clustering of the generated candidate region patterns. Similar to the clustering of the arrangement patterns of adjacent block models, the circuit diagram group region pattern design unit 32 determines whether the multiple candidate region patterns are included in the same cluster based on the positions of the two circuit diagram group models.

[0172] In S703, the circuit diagram group area pattern design unit 32 scores a plurality of candidate area patterns in each cluster.

[0173] Scoring between two circuit diagram group models (i-th set) connected by a virtual pin is performed as follows: The score Ti is given by the following formula: Ti=(WT1*f(B1)+WT2*f(B2))*NT...(C2)

[0174] The first index B1 is the Manhattan distance between the virtual pins VP of two circuit diagram group models connected by the virtual pin. f(B1) is the deviation value of B1. The second index B2 represents the crossing of wires. f(B2) is the deviation value of B2.

[0175] WT1 and WT2 are weights. The designer can change the factors to be emphasized by adjusting the values ​​of WT1 and WT2. The more desirable the area pattern, the smaller the indices B1 and B2 become. NT is the total number of net points between two circuit diagram group models.

[0176] The circuit diagram group region pattern design unit 32 may calculate the score Ti based on one of the indicators B1 and B2.

[0177] When there are M sets of two circuit diagram group models connected by a virtual pin, the circuit diagram group region pattern design unit 32 determines the score of the candidate region pattern to be the sum SS2 (=ΣTi) of the M scores T1 to TM. The more desirable the region pattern, the smaller the value of the sum TT.

[0178] In S704, similarly to S901 to S904, the circuit diagram group area pattern design unit 32 selects a candidate area pattern for each cluster.

[0179] The circuit diagram group region pattern design unit 32 sorts the multiple candidate area patterns of the cluster in order of placement area AS2. The circuit diagram group region pattern design unit 32 selects one or more candidate area patterns with a small placement area AS2 (i.e., a placement area AS2 equal to or less than a predetermined threshold ATH2). If there is no candidate area pattern with a placement area AS2 equal to or less than the predetermined threshold ATH2, the candidate area pattern with the smallest placement area AS2 may be selected. The circuit diagram group region pattern design unit 32 sorts the selected candidate area patterns in order of sum SS2. The circuit diagram group region pattern design unit 32 selects one or more candidate area patterns with a good sum SS2 (i.e., a sum SS2 equal to or less than a predetermined threshold STH2). If there is no candidate area pattern with a sum SS2 equal to or less than the predetermined threshold STH2, the candidate area pattern with the smallest sum SS2 may be selected.

[0180] In S705, the circuit diagram group area pattern design unit 32 sorts the selected candidate area patterns of all clusters according to the scoring results.

[0181] In S706, the circuit diagram group area pattern design unit 32 leaves only one or more candidate area patterns with a good sum SS2 (i.e., the sum SS2 is equal to or less than a predetermined threshold value FSTH2) from among the selected candidate area patterns of all clusters. If there is no candidate area pattern with a sum SS2 equal to or less than the predetermined threshold value FSTH2, the candidate area pattern with the smallest sum SS2 may be left.

[0182] In S707, if there is overlap between the regions of the multiple circuit diagram group models in one or more remaining candidate region patterns, the circuit diagram group region pattern design unit 32 removes the overlap by moving at least one of the multiple overlapping circuit diagram group models, thereby determining one or more region patterns.

[0183] Fig. 40 is a diagram showing an example of an area pattern generated after the processing procedure of the flowchart of Fig. 37 is completed. Fig. 40 shows one of a plurality of patterns of the area of ​​the circuit diagram group model GRP-G and the area of ​​the GRP-H.

[0184] 13 again, in S507, for each region pattern, overall layout pattern design unit 33 generates one or more overall layout patterns in which one or more adjacent blocks included in the circuit diagram group are arranged in the regions of the plurality of circuit diagram groups in the region pattern using a layout pattern. Fig. 41 is a flowchart showing the detailed procedure of S507 in Fig. 13.

[0185] In S801, the overall layout pattern design unit 33 generates a plurality of candidate overall layout patterns by arranging, in each of the area patterns of a plurality of circuit diagram group models, proximity block models according to each of the arrangement patterns of a plurality of proximity block models included in each circuit diagram group model. The proximity block models are arranged so that the center of a proximity block model group consisting of one or more proximity block models included in the circuit diagram group model coincides with the center of the area of ​​the circuit diagram group model. As described above, a circuit diagram group model is a rectangular area having an area that is equal to or greater than the sum of the areas of all components in the circuit diagram group and is equal to or less than twice the sum of the areas of all components included in the circuit diagram group. Therefore, it may not be possible for all proximity block models included in the circuit diagram group to fit within the area of ​​the circuit diagram group model.

[0186] 42 is a diagram illustrating an example of generating a candidate overall arrangement pattern. In a certain area pattern, neighboring block models RB3 and RB4 in circuit diagram group model G are arranged in the area of ​​circuit diagram group model G using arrangement patterns G1, G2, G3, ... of circuit diagram group model G, and neighboring block models RB5 and RB6 in circuit diagram group model H are arranged in the area of ​​circuit diagram group model H using arrangement patterns H1, H2, H3, ... of circuit diagram group model H. For example, the centers of the neighboring block models consisting of neighboring block model RB3 and neighboring block model RB4 are arranged so as to coincide with the center of the area of ​​circuit diagram group model G.

[0187] For example, suppose there are 10 area patterns of circuit diagram group models, two circuit diagram group models G and H, five placement patterns of adjacent block models of circuit diagram group model G, and seven placement patterns of adjacent block models of circuit diagram group model H. The overall placement pattern design unit 33 places adjacent block models in five types of placement patterns in the area of ​​circuit diagram group model G in the area pattern of the ith (i = 1 to 10) circuit diagram group model, and places adjacent block models in seven types of placement patterns in the area of ​​circuit diagram group model H. As a result, 10 x 5 x 7 = 350 candidate overall placement patterns are generated.

[0188] In S802, overall layout pattern design unit 33 performs clustering of the generated candidate overall layout patterns. As in the clustering of layout patterns of adjacent block models within one circuit diagram group model described above, overall layout design unit 15 determines whether the candidate overall layout patterns are included in the same cluster based on the positions of two connecting adjacent block models among all adjacent block models within all circuit diagram group models.

[0189] In S803, the overall placement pattern design unit 33 scores multiple candidate overall placement patterns in each cluster. Of all the adjacent block models in all the circuit diagram group models, the overall placement pattern design unit 33 scores two adjacent block models (the i-th set) connected by a virtual pin in the same manner as the scoring between two adjacent block models connected by a virtual pin in one circuit diagram group model described above. When there are multiple sets of two adjacent block models connected by a virtual pin, the overall placement pattern design unit 33 uses the sum of the scores SS3 as the sum of the overall placement patterns. The more desirable the candidate overall placement pattern, the smaller the value of the sum SS3.

[0190] In S804, similarly to S901 to S904, global arrangement pattern design unit 33 selects a candidate global arrangement pattern for each cluster.

[0191] The overall placement pattern design unit 33 sorts the multiple candidate overall placement patterns of the cluster in order of placement area AS3. The overall placement pattern design unit 33 selects one or more candidate overall placement patterns with small placement area AS3 (i.e., placement area AS3 equal to or less than a predetermined threshold ATH3). If there is no candidate overall placement pattern with a placement area AS3 equal to or less than the predetermined threshold ATH3, the candidate overall placement pattern with the smallest placement area AS3 may be selected. The overall placement pattern design unit 33 sorts the selected candidate overall placement patterns in order of sum SS3. The overall placement pattern design unit 33 selects one or more candidate overall placement patterns with a good sum SS3 (i.e., sum SS3 equal to or less than a predetermined threshold STH3). If there is no candidate overall placement pattern with a sum SS3 equal to or less than the predetermined threshold STH3, the candidate overall placement pattern with the smallest sum SS3 may be selected.

[0192] In S805, the overall arrangement pattern design unit 33 sorts the selected candidate overall arrangement patterns of all clusters according to the scoring results.

[0193] In S806, the global arrangement pattern design unit 33 selects and retains only one or more candidate global arrangement patterns having a good sum SS3 (i.e., the sum SS3 is equal to or less than a predetermined threshold value FSTH3) from among the selected candidate global arrangement patterns of all clusters. If there is no candidate global arrangement pattern having a sum SS3 equal to or less than the predetermined threshold value FSTH3, the candidate global arrangement pattern having the smallest sum SS3 may be retained.

[0194] In S807, if there is overlap in the arrangement positions of multiple neighboring block models in one or more remaining candidate global arrangement patterns, the overall arrangement pattern design unit 33 removes the overlap by moving at least one of the overlapping neighboring block models, thereby generating one or more overall arrangement patterns.

[0195] In S508, the component position adjustment unit 34 adjusts the placement on a component-by-component basis. When the overall placement pattern design unit 33 places a first child component of a neighboring block belonging to a circuit diagram group outside the area of ​​the circuit diagram group and the position of the first child component overlaps with the position of a second child component of another neighboring block, the component position adjustment unit 34 moves the first child component or the second child component so that the positions of the first child component and the second child component do not overlap. The component position adjustment unit 34 may determine which of the first child component and the second child component to move based on priority. Figures 43(a) and 43(b) are diagrams for explaining an example of the adjustment of placement on a component-by-component basis.

[0196] As shown in FIG. 43( a), the first child component (low-priority child component) of a neighboring block A belonging to a certain circuit diagram group is placed outside the area of ​​the circuit diagram group, and the position of the first child component overlaps (interferes with) the position of the second child component (high-priority child component) of another neighboring block B.

[0197] As shown in Fig. 43(b), the component position adjustment unit 34 moves the position of the first child component (low-priority component) in proximity block A. The component position adjustment unit 34 moves the first child component to a position where the connection between the pins is closest and where it does not overlap with other components. Figs. 44(a) and (b) are diagrams for explaining another example of adjusting the placement of components.

[0198] In FIG. 44( a), similar to FIG. 43( a), a first child component (low-priority child component) of a neighboring block A belonging to a certain circuit diagram group is placed outside the area of ​​the circuit diagram group, and the position of the first child component overlaps (interferes with) the position of a second child component (high-priority child component) of another neighboring block B.

[0199] 44(b), the component position adjustment unit 34 moves the position of the first child component (low-priority component) of the adjacent block A. The component position adjustment unit 34 moves the first child component to a position where the connection between the pins is closest and where the first child component does not overlap with other components.

[0200] When the positions of two low-priority parts overlap, the part position adjustment unit 34 selects one of the low-priority parts as the part to be moved. When the positions of two high-priority parts overlap, the part position adjustment unit 34 selects one of the high-priority parts as the part to be moved. Next, the processing of S505 to S508 from the second time onwards will be described.

[0201] In step S601, which is a detailed step of step S505, the adjacent block arrangement pattern design unit 31 initially generates a plurality of adjacent block candidate arrangement patterns in which the positions and orientations of the adjacent blocks are arbitrarily changed.

[0202] From the second time onwards, the adjacent block arrangement pattern design unit 31 generates a plurality of candidate arrangement patterns for the current plurality of adjacent blocks from one or more arrangement patterns generated based on the scoring results in the previous overall arrangement design process (i.e., one or more arrangement patterns generated upon completion of S607). For example, the adjacent block arrangement pattern design unit 31 generates a plurality of candidate arrangement patterns for the current plurality of adjacent blocks by changing the position and orientation of each adjacent block in the one or more arrangement patterns generated previously.

[0203] In step S701, which is a detailed step of step S506, the circuit diagram group area pattern design unit 32 initially generates a plurality of candidate area patterns in which the position and size of the circuit diagram group model are arbitrarily changed.

[0204] From the second time onwards, the circuit diagram group region pattern design unit 32 generates a plurality of current candidate region patterns from one or more region patterns generated based on the scoring results in the previous overall layout design process (i.e., one or more region patterns generated upon completion of S707). For example, the circuit diagram group region pattern design unit 32 generates a plurality of current candidate region patterns by changing the position and size of each region in the one or more region patterns generated previously.

[0205] In step S801 of step S507, the overall layout pattern design unit 33 initially generates a plurality of candidate overall layout patterns by arranging neighboring block models in each of the layout patterns of the neighboring block models included in each circuit diagram group model in the area patterns of the plurality of circuit diagram group models. The overall layout pattern design unit 33 arranged the neighboring block models so that the center of the area of ​​the circuit diagram group model coincides with the center of a neighboring block model group consisting of one or more neighboring block models included in the circuit diagram group model.

[0206] From the second time onward, the overall placement pattern design unit 33 generates multiple candidate overall placement patterns in the current overall placement design process based on one or more overall placement patterns generated based on the scoring results in the previous overall placement design process (i.e., one or more overall placement patterns generated upon completion of S807). For example, the overall placement pattern design unit 33 generates multiple candidate overall placement patterns by arranging neighboring block models in each of the area patterns of the multiple circuit diagram group models using each of the placement patterns of the multiple neighboring block models included in each circuit diagram group model. The overall placement pattern design unit 33 may retain only those of the multiple generated candidate overall placement patterns that are dissimilar to the one or more previously generated overall placement patterns. "Similar" may mean, for example, that the positions of the neighboring blocks between the patterns overlap by 50% or more.

[0207] In S508, for the first time, if the overall layout pattern design unit 33 places a first child component of a neighboring block belonging to a circuit diagram group outside the area of ​​the circuit diagram group and the position of the first child component overlaps with the position of a second child component of another neighboring block, the component position adjustment unit 34 moves the first child component or the second child component so that the positions of the first child component and the second child component do not overlap.

[0208] From the second time onward, the component position adjustment unit 34 determines which child components to move or where to move them in the current overall layout design process based on the movements of the child components in the previous overall layout design process. For example, the component position adjustment unit 34 moves the low-priority component when a low-priority component interferes with a high-priority component in the previous overall layout design process, and moves the high-priority component when a low-priority component interferes with a high-priority component again this time. Alternatively, the component position adjustment unit 34 moves the low-priority component upward of the parent component when a low-priority component interferes with a high-priority component in the previous overall layout design process, and moves the low-priority component to the right or left when a low-priority component interferes with a high-priority component again this time.

[0209] 13 , in S509, the overall layout design unit 15 outputs the layout result. For example, the overall layout design unit 15 may output a plurality of representative layout patterns obtained by a plurality of repetitions. Alternatively, the overall layout design unit 15 may output the best of the plurality of representative layout patterns obtained by a plurality of repetitions.

[0210] 45 is a diagram showing the hardware configuration of the printed circuit board design device 1. The printed circuit board design device 1 can be realized by a known personal computer or the like. The printed circuit board design device 1 includes a processor 100, a display device 200 such as a liquid crystal display, an input device 300 such as a keyboard and a mouse, an internal storage device 400 such as a memory, an external storage device 500 such as a hard disk or a portable recording medium, and a communication device 600.

[0211] The input device 300 accepts input from a designer. The communication device 600 can receive a printed circuit board design program and data from an external device, such as via the Internet. The external storage device 500 can store the printed circuit board design program and data. The internal storage device 400 stores the printed circuit board design program and data transferred from the communication device 600 or the external storage device 500. The processor 100 displays a circuit diagram, adjacent blocks, a netlist, and the like on the display device 200. The processor 100 executes the printed circuit board design program stored in the internal storage device 400. This causes processing to be performed according to the flowchart of FIG. 2. (Modifications) The present disclosure is not limited to the above-described embodiment and includes, for example, the following modifications. (1) In the above-described embodiment, a deviation value is used to calculate the score, but the deviation value need not be used. That is, the following formula (C1A) may be used instead of formula (C1), and the following formula (C2A) may be used instead of formula (C2). Si=(WS1*A1+WS2*A2+WS3*A3+WS4*A4+WS5*A5)*NS...(C1A) Ti=(WT1*B1+WT2*B2)*NT...(C2A) (2) In the above embodiment, as shown in FIG. 18, when each of a plurality of paths connects connection pins of three or more proximity model block models, virtual pins are set from the connection pins of three or more proximity block models of the plurality of paths. As a result, as shown in FIG. 21, RB1 and RB2 are connected by a virtual pin, and RB2 and RB3 are connected by a virtual pin. The present disclosure is not limited to this. Even when each of a plurality of paths connects connection pins of three or more proximity model block models, virtual pins may be set from the connection pins of two proximity block models included in the plurality of paths. In this case, RB1 and RB2 are connected by a virtual pin, RB2 and RB3 are connected by a virtual pin, and RB1 and RB3 are connected by a virtual pin.

[0212] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0213] 1 Printed circuit board design device, 2 Data input unit, 3 CAD unit, 4 User I / F, 5 Conversion unit, 6 Net attribute setting unit, 7 Net point number setting unit, 8 Grouping processing unit, 10 Component classification unit, 11 Proximal block generation unit, 12 Proximal block component placement design unit, 13 Power tree setting unit, 14 Position specification unit, 15 Overall placement design unit, 21 Placement design unit, 31 Proximal block placement pattern design unit, 32 Circuit diagram group area pattern design unit, 33 Overall placement pattern design unit, 34 Component position adjustment unit, 41 Model generation unit, 100 Processor, 200 Display device, 300 Input device, 400 Internal storage device, 500 External storage device, 600 Communication device.

Claims

1. A system comprising: a grouping processing unit that generates a plurality of circuit diagram groups by dividing a circuit diagram into a plurality of parts; a component classification unit that classifies components into parent parts, child parts directly or indirectly connected to the parent parts, and other parts; a proximity block generation unit that generates a plurality of proximity blocks each including a parent part and the child parts; a proximity block intra-component layout design unit that arranges components within the proximity blocks; and an overall layout design unit that executes an overall layout design process a plurality of times to arrange a plurality of proximity blocks included in the circuit diagram group in a plurality of the circuit diagram groups, wherein the overall layout design unit comprises: a proximity block layout pattern design unit that generates, for each circuit diagram group, one or more layout patterns within the circuit diagram group for a plurality of proximity blocks included in the circuit diagram group; a circuit diagram group area pattern design unit that generates one or more area patterns representing areas of the plurality of the circuit diagram groups on a board; and an overall layout pattern design unit that generates, for each area pattern, one or more overall layout patterns in which one or more adjacent blocks included in the circuit diagram group are arranged in the area of ​​a plurality of the circuit diagram groups in the area pattern using the layout pattern.

2. The printed circuit board design device of claim 1, wherein the adjacent block arrangement pattern design unit generates a plurality of candidate arrangement patterns for a plurality of adjacent blocks included in the circuit diagram group, scores the plurality of candidate arrangement patterns, and generates one or more of the arrangement patterns based on the scoring results.

3. The printed circuit board design device of claim 2, wherein the adjacent block arrangement pattern design unit clusters the multiple candidate arrangement patterns based on the arrangement positions of the adjacent blocks, scores the multiple candidate arrangement patterns belonging to the same cluster, selects one or more candidate arrangement patterns based on the scoring results and the arrangement area, and generates one or more of the arrangement patterns based on the scoring results of the selected candidate arrangement patterns for the multiple clusters.

4. The printed circuit board design device of claim 3, wherein the adjacent block arrangement pattern design unit scores the candidate arrangement pattern based on at least one of a first indicator representing the distance between two adjacent blocks included in the candidate arrangement pattern, a second indicator representing the relationship in orientation of the two adjacent blocks, a third indicator representing whether or not a twist in wiring occurs between the two adjacent blocks, a fourth indicator representing whether or not a wiring connected to another adjacent block crosses the wiring between the two adjacent blocks, and a fifth indicator representing whether or not a horizontal wiring path, a vertical wiring path, or a horizontal and vertical wiring path with one bend exists to connect the two adjacent blocks.

5. A printed circuit board design device as described in claim 4, further comprising a net score setting unit which sets the net score between two components included in the circuit diagram, wherein the adjacent block arrangement pattern design unit calculates a score for the two adjacent blocks based on the first index, the second index, the third index, the fourth index, and the fifth index and the sum of the net scores between the two adjacent blocks, and scores the candidate arrangement pattern based on the sum of the scores for all sets of two connected adjacent blocks included in the candidate arrangement pattern and the area of ​​the candidate arrangement pattern.

6. The printed circuit board design device according to claim 2, wherein said adjacent block arrangement pattern design unit generates candidate arrangement patterns for said adjacent block by taking a polygonal area surrounding all components included in said adjacent block as the occupied position of said adjacent block.

7. The printed circuit board design device of claim 2, wherein the adjacent block arrangement pattern design unit generates a plurality of candidate arrangement patterns for a plurality of adjacent blocks included in the circuit diagram group in the current overall layout design process from one or more of the arrangement patterns generated based on the scoring results in the previous overall layout design process.

8. A printed circuit board design device as claimed in claim 1, further comprising a position specification section which specifies position specified components whose positions on the board are specified, and semi-position specified components whose approximate positions on the board are specified by a designer, and said circuit diagram group area pattern design section generates areas for a plurality of said circuit diagram groups in addition to areas in which said unplaced position specified components and said semi-position specified components are to be placed.

9. The printed circuit board design device according to claim 8, wherein said circuit diagram group area pattern design unit generates a plurality of candidate area patterns for a plurality of circuit diagram groups, scores said plurality of candidate area patterns, and generates one or more of said area patterns based on the scoring results.

10. A printed circuit board design device as described in claim 9, wherein the circuit diagram group area pattern design unit clusters the plurality of candidate area patterns based on the positions of the circuit diagram group areas, scores the plurality of candidate area patterns belonging to the same cluster, selects one or more candidate area patterns based on the scoring results and the placement area, scores the selected plurality of candidate area patterns, and generates the plurality of area patterns based on the scoring results.

11. The printed circuit board design device according to claim 10, wherein the circuit diagram group area pattern design unit scores the candidate area pattern based on at least one of a first index indicating the distance between the areas of two circuit diagram groups included in the candidate area pattern and a second index indicating whether wiring connected to another circuit diagram group intersects with wiring between the areas of the two circuit diagram groups.

12. The printed circuit board design device according to claim 11, further comprising a net score setting section which sets a net score between two components included in said circuit diagram, wherein said circuit diagram group area pattern design section calculates a score for one set of areas of said two circuit diagram groups based on said first index, said second index and a total sum of the net scores between said two circuit diagram groups, and scores said candidate area pattern based on the total sum of the scores for all sets of areas of two connected circuit diagram groups included in said candidate area pattern.

13. The printed circuit board design device according to claim 12, wherein the distance between the areas of the two circuit diagram groups is the Manhattan distance between the virtual pins of the two circuit diagram groups, and the virtual pin of the circuit diagram group is the center of the circuit diagram group.

14. The printed circuit board design device according to claim 9, wherein the circuit diagram group area pattern design unit generates a rectangular area having an area equal to or greater than the sum of the areas of all components included in the circuit diagram group and equal to or less than twice the sum, as a candidate area pattern for the circuit diagram group.

15. A printed circuit board design device as described in claim 9, wherein the circuit diagram group area pattern design unit generates a plurality of candidate area patterns in a current overall layout design process from one or more area patterns generated based on a scoring result in a previous overall layout design process.

16. The printed circuit board design device according to claim 1, wherein the overall layout pattern design unit generates a plurality of candidate overall layout patterns obtained by arranging a plurality of adjacent blocks included in a plurality of circuit diagram groups in each of the plurality of layout patterns for each of the one or more area patterns, scores the plurality of candidate overall layout patterns, and generates one or more of the overall layout patterns based on the scoring results.

17. The printed circuit board design device of claim 16, wherein the overall layout pattern design unit clusters the plurality of candidate overall layout patterns based on the placement positions of two adjacent blocks in two circuit diagram groups in the same or different circuit diagram groups, scores the plurality of candidate overall layout patterns belonging to the same cluster, selects one or more of the candidate overall layout patterns based on the scoring results and placement area, and generates one or more of the overall layout patterns based on the scoring results of the selected candidate overall layout patterns for the plurality of clusters.

18. The printed circuit board design device of claim 17, wherein the overall layout pattern design unit scores the candidate overall layout pattern based on at least one of a first indicator representing the distance between two adjacent blocks included in the candidate overall layout pattern, a second indicator representing the relationship in orientation of the two adjacent blocks, a third indicator representing whether or not a twist in wiring occurs between the two adjacent blocks, a fourth indicator representing whether or not a wiring connected to another adjacent block crosses the wiring between the two adjacent blocks, and a fifth indicator representing whether or not a horizontal wiring path, a vertical wiring path, or a horizontal and vertical wiring path having one bend exists to connect the two adjacent blocks.

19. The printed circuit board design device of claim 18, further comprising a net score setting unit which sets a net score between two components included in the circuit diagram, wherein the overall placement pattern design unit calculates a score for a set of the two adjacent blocks based on the first index, the second index, the third index, the fourth index, and the fifth index and a total sum of the net scores between the two adjacent blocks, and scores the candidate overall placement pattern based on the total sum of the scores for all sets of two connected adjacent blocks included in the candidate overall placement pattern.

20. The printed circuit board design device as described in claim 16, wherein the overall layout pattern design unit generates a plurality of the candidate overall layout patterns in the current overall layout design process based on one or more overall layout patterns generated based on a scoring result in a previous overall layout design process.

21. The printed circuit board design device according to claim 12 or 19, wherein one of the two proximity blocks is a first proximity block and the other of the two proximity blocks is a second proximity block, an ideal orientation relationship is when a first side of the first proximity block that is closest to the virtual pin of the first proximity block and a second side of the second proximity block that is closest to the virtual pin of the second proximity block face each other and are shortest, and the second index represents the magnitude of deviation from the ideal orientation, the coordinates of the virtual pin of the first proximity block are a weighted average of the coordinates of one or more pins of the first proximity block that are connected to the second proximity block in accordance with the number of points in the nets connecting to the pins, and the coordinates of the virtual pin of the second proximity block are a weighted average of the coordinates of one or more pins of the second proximity block that are connected to the first proximity block in accordance with the number of points in the nets connecting to the pins.

22. The printed circuit board design device of claim 1, wherein the overall layout design unit further comprises a component position adjustment unit that, when the overall layout pattern design unit places a first child component of a neighboring block belonging to the circuit diagram group outside the area of ​​the circuit diagram group and a position of the first child component overlaps with a position of a second child component of another neighboring block, moves the first child component or the second child component so that the positions of the first child component and the second child component do not overlap.

23. The printed circuit board design device according to claim 22, wherein said component position adjustment section determines the child component to be moved based on the priority of said first child component and said second child component.

24. The printed circuit board design device according to claim 23, wherein said component position adjustment section determines child components to be moved or their movement positions in the current overall layout design process based on the movements of child components in the previous overall layout design process.

25. The printed circuit board design device of claim 1, wherein the proximity block component placement design unit selects proximity blocks in order of the number of components contained therein, places components in the selected proximity blocks, and when the specifications of one or more first component groups consisting of parent components or child components of a first proximity block in which components have already been placed are identical to the specifications of one or more second component groups consisting of parent components or child components of the selected proximity block, and when the ratio of the number of the first component groups to the total number of components in the first proximity block is equal to or greater than a threshold value, makes the positional relationship of the child components of the second component group relative to the parent components of the selected proximity block the same as the positional relationship of the child components of the first component group relative to the parent components of the first proximity block.

26. The printed circuit board design device of claim 1, wherein the component classification unit classifies child components directly connected to the parent component into high priority child components and low priority child components, and the adjacent block component placement design unit places a first group of high priority child components and child components directly or indirectly connected to the high priority child components at a position closer to the parent component than a second group of low priority child components and child components directly or indirectly connected to the low priority child components.

27. A printed circuit board design device as described in claim 26, wherein the adjacent block component placement design unit places, for a plurality of child components belonging to the first group, a child component with a higher priority in a position closer to the parent component, and for a plurality of child components belonging to the second group, a child component with a higher priority in a position closer to the parent component.

28. A printed circuit board design device as described in claim 27, wherein the priority of a first child component is higher than the priority of all second child components that are directly connected to the first child component and have one more child component passing through to connect to the parent component than the first child component.

29. The printed circuit board design device according to claim 28, wherein, when there are a plurality of said second child components, a priority of each second child component is determined based on attributes of two nets connected to each second child component.

30. A first side surface of the parent part and a second side surface of the parent part are connected at a first intersecting line, and the first side surface of the parent part and a third side surface of the parent part are connected at a second intersecting line; a first boundary surface is a surface dividing a space defined by a first extension surface extending the first side surface of the parent part toward the first intersecting line and a second extension surface extending the second side surface of the parent part toward the first intersecting line; a second boundary surface is a surface dividing a space defined by a third extension surface extending the first side surface of the parent part toward the second intersecting line and a fourth extension surface extending the third side surface of the parent part toward the second intersecting line; a first region is a region defined by the first side surface of the parent part, the first boundary surface, and the second boundary surface; 2. The printed circuit board design device of claim 1, wherein the first side and the first boundary surface intersect at an angle greater than 90 degrees, and the first side and the second boundary surface intersect at an angle greater than 90 degrees, and the proximity block internal component placement design unit places in the first area a child component that is directly connected to a first pin arranged along the first side of the parent component, and a child component that is directly or indirectly connected to the child component.

31. The printed circuit board design apparatus according to claim 30, wherein the first side surface and the first boundary surface intersect at an angle of 135 degrees, and the first side surface and the second boundary surface intersect at an angle of 135 degrees.

32. A printed circuit board design device as described in claim 30, wherein, when it is not possible to place all child components having the same priority within the first region on a line that is the same distance from the parent component, the adjacent block component placement design unit places one or more child components having the same priority on a line within the first region that is the next closest distance from the parent component.

33. A printed circuit board design program causing a computer to execute the steps of: generating a plurality of circuit diagram groups by dividing a circuit diagram into a plurality of parts; classifying components into parent parts, child parts directly or indirectly connected to the parent parts, and other parts; generating a plurality of proximal blocks each including a parent part and the child parts; arranging components in the proximal blocks; and executing a total layout design process a plurality of times to arrange a plurality of proximal blocks included in the circuit diagram group in a plurality of the circuit diagram groups, the total layout design process including the steps of: generating, for each circuit diagram group, one or more arrangement patterns within the circuit diagram group for a plurality of proximal blocks included in the circuit diagram group; generating one or more area patterns representing areas of a plurality of the circuit diagram groups on a board; and generating, for each area pattern, one or more overall arrangement patterns in which the one or more proximal blocks included in the circuit diagram group are arranged in the arrangement pattern in the areas of the plurality of circuit diagram groups in the area pattern.

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