EPITAXIAL WAFER, β-Ga2O3-BASED DEVICE, AND METHOD FOR PRODUCING β-Ga2O3-BASED DEVICE

Abstract

The problem addressed is to improve the characteristics of a β-Ga2O3-based device. An epitaxial wafer (1) comprises: a Ga2O3-based substrate (2); a metal layer (3); and a β-Ga2O3 layer (4). The Ga2O3-based substrate (2) has a first main surface (21) and a second main surface (22) on the opposite side to the first main surface (21). The metal layer (3) is formed on the first main surface (21) of the Ga2O3-based substrate (2). The metal layer (3) has a plurality of openings (32). The β-Ga2O3 layer (4) covers the first main surface (21) of the Ga 2O3-based substrate (2) and the metal layer (3). The material of the metal layer (3) is a noble metal or a high-melting-point metal. The thickness (T2) of the β-Ga2O3 layer (4) is less than the thickness (T1) of the Ga2O3-based substrate (2).

Description

Epitaxial wafer, β-Ga2O3-based device, and method for manufacturing β-Ga2O3-based device

[0001] The present disclosure relates to epitaxial wafers, β-Ga ２ O ３ -based devices and β-Ga ２ O ３ This invention relates to a method for manufacturing a β-Ga-based device, and more particularly to a method for manufacturing a β-Ga-based device. ２ O ３ Epitaxial wafer including a layer, β-Ga ２ O ３ -based devices and β-Ga ２ O ３ The present invention relates to a method for manufacturing a semiconductor device.

[0002] In Patent Document 1, Ga is used as a power device. ２ O ３ and a Ga epitaxial layer formed on the substrate by epitaxial growth using the substrate as a base. ２ O ３ and a field effect transistor (β-Ga ２ O ３ Ga-based devices are disclosed. ２ O ３ Ga-based semiconductor layers ２ O ３ The crystal structure of the single crystal is a monoclinic β type.

[0003] In addition, Patent Document 1 states that the substrate is Ga ２ O ３ It is also described that the material is not limited to single crystals of the sapphire family, and that the material may be sapphire or the like.

[0004] β-Ga ２ O ３ In GaAs-based devices, ２ O ３ The characteristics may be degraded due to the influence of the substrate that serves as the base for the semiconductor layer.

[0005] Japanese Patent Application Laid-Open No. 2021-136331

[0006] The purpose of this disclosure is to ２ O ３Epitaxial wafers capable of improving the characteristics of β-Ga semiconductor devices ２ O ３ -based devices and β-Ga ２ O ３ The present invention also provides a method for manufacturing a semiconductor device.

[0007] The epitaxial wafer according to one embodiment of the present disclosure is ２ O ３ a β-Ga-based substrate, a metal layer, and ２ O ３ and a Ga layer. ２ O ３ The Ga-based substrate has a first main surface and a second main surface opposite to the first main surface. ２ O ３ The metal layer is formed on the first main surface of the β-Ga substrate. The metal layer has a plurality of openings. ２ O ３ The layer is ２ O ３ The β-Ga GaN layer covers the first main surface of the GaN substrate and the metal layer. The material of the metal layer is a noble metal or a high-melting-point metal. ２ O ３ The thickness of the Ga layer ２ O ３ The thickness is thinner than the substrate.

[0008] β-Ga according to one aspect of the present disclosure ２ O ３ The Ga-based device ２ O ３ a β-Ga-based substrate, a metal layer, and ２ O ３ The semiconductor device includes a Ga ２ O ３ The Ga-based substrate has a first main surface and a second main surface opposite to the first main surface. ２ O ３ The β-Ga-based substrate is formed on a portion of the first main surface. ２ O ３ The layer is ２ O ３ The semiconductor element covers the first main surface of the β-Ga-based substrate and the metal layer. ２ O３ The material of the metal layer is a noble metal or a high melting point metal. ２ O ３ The thickness of the Ga layer ２ O ３ The thickness is thinner than the substrate.

[0009] β-Ga according to one aspect of the present disclosure ２ O ３ The method for manufacturing a GaAs semiconductor device includes a substrate preparation step, a metal layer formation step, and an epitaxial growth step. In the substrate preparation step, a GaAs semiconductor device having a first main surface and a second main surface opposite to the first main surface is prepared. ２ O ３ In the metal layer forming step, the Ga ２ O ３ A metal layer having a plurality of openings is formed on the first main surface of the Ga substrate. ２ O ３ a β-Ga alloy covering the first main surface of the β-Ga alloy substrate and the metal layer; ２ O ３ The β-Ga layer is formed by selective lateral overgrowth using mist CVD. The material of the metal layer is a noble metal or a high-melting-point metal. ２ O ３ The thickness of the Ga layer ２ O ３ The thickness is thinner than the substrate.

[0010] 1 is a cross-sectional view of a main part of an epitaxial wafer according to the first embodiment. FIG. 2 is a plan view of a main part of the epitaxial wafer. FIG. 3 is a cross-sectional view of a main part of the epitaxial wafer according to the first embodiment. ２ O ３ 4A to 4E are cross-sectional views illustrating the main steps of the method for manufacturing the epitaxial wafer of the embodiment 1. FIG. 5 is an explanatory diagram of the epitaxial wafer of the embodiment 1. FIG. 6 is a partially cutaway perspective view illustrating the β-Ga ２ O ３ FIG. 7 is a cross-sectional view of the β-Ga GaN device. ２ O ３8 is a cross-sectional view of a main part of an epitaxial wafer according to a modification of the first embodiment. ２ O ３ FIG. 10 is a cross-sectional view of the β-Ga GaN device. ２ O ３ FIG. 11 is a plan view of the β-Ga GaN device. ２ O ３ 12 is a cross-sectional view illustrating the main steps of a method for manufacturing a β-Ga GaN device. ２ O ３ 13 is a plan view showing the main steps of a method for manufacturing a β-Ga GaN-based device according to the third embodiment. ２ O ３ FIG. 14 is a cross-sectional view of the β-Ga GaN device. ２ O ３ 15 is a plan view of a β-Ga GaN-based device according to the fourth embodiment. ２ O ３ FIG. 16 is a cross-sectional view of the β-Ga GaN device. ２ O ３ 17 is a plan view of a β-Ga GaN-based device according to the fifth embodiment. ２ O ３ 18 is a cross-sectional view of a β-Ga GaN-based device according to the sixth embodiment. ２ O ３ 19 is a cross-sectional view of a β-Ga GaN-based device according to the seventh embodiment. ２ O ３ FIG. 20 is a cross-sectional view of the β-Ga GaN device. ２ O ３ 21 is a plan view of a β-Ga GaN-based device according to the eighth embodiment. ２ O ３ FIG. 22 is a cross-sectional view of the β-Ga ２ O ３ 23A to 23C are plan views of the metal layer in the β-Ga GaN-based device. ２ O ３ 24 is a cross-sectional view illustrating a main process for explaining a method for manufacturing a β-Ga GaN-based device according to a modification of the eighth embodiment. ２ O ３ FIG. 1 is a plan view of a metal layer in a semiconductor device.

[0011] 1 to 24 described in the following embodiments 1 to 8 are schematic diagrams, and the ratios of the sizes and thicknesses of the components in the diagrams do not necessarily reflect the actual dimensional ratios.

[0012] (Embodiment 1) (1) Epitaxial Wafer and Manufacturing Method Thereof An epitaxial wafer 1 according to embodiment 1 and a manufacturing method therefor will be described below with reference to FIGS.

[0013] (1.1) Epitaxial Wafer The epitaxial wafer 1 according to the first embodiment is, as shown in FIG. ２ O ３ a β-Ga-based substrate 2, a metal layer 3, and ２ O ３ and a layer 4. ２ O ３ The metal substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The metal layer 3 is made of Ga ２ O ３ The metal layer 3 is formed on the first main surface 21 of the Ga-based substrate 2. The metal layer 3 has a plurality of openings 32. ２ O ３ It is formed on a part of the first main surface 21 of the β-Ga-based substrate 2. ２ O ３ Layer 4 is Ga ２ O ３ The epitaxial wafer 1 covers the first main surface 21 of the β-Ga substrate 2 and the metal layer 3. ２ O ３ It is an epitaxial wafer. β-Ga ２ O ３ The epitaxial wafer is β-Ga ２ O ３ A wafer containing Ga crystals ２ O ３ β-Ga on the base substrate 2 ２ O ３ Layer 4 is epitaxially grown on the wafer.

[0014] In the epitaxial wafer 1 according to the first embodiment, Ga ２ O ３ The β-Ga-based substrate 2 is ２O ３ The substrate 20 is β-Ga ２ O ３ The substrate 20 is β-Ga ２ O ３ It is a single crystal. ２ O ３ The crystal structure of the single crystal is monoclinic. ２ O ３ The first main surface 21 of the β-Ga-based substrate 2 is, for example, ２ O ３ The (010) or (001) plane of a single crystal is, but is not limited to, the (010) or (001) plane. The (010) and (001) planes are crystal planes expressed by Miller indices, where three indices are enclosed in parentheses. ２ O ３ The first main surface 21 of the β-Ga-based substrate 2 is ２ O ３ The crystal plane may be off-angled with respect to the (010) or (001) plane of the single crystal. ２ O ３ The substrate 20 is semi-insulating β-Ga ２ O ３ Semi-insulating β-Ga substrate ２ O ３ The substrate has a resistivity of 1×10 ８ Ωcm or more 1×10 １２ β-Ga below Ωcm ２ O ３ It is a circuit board.

[0015] Ga ２ O ３ When viewed from the thickness direction D10 of the substrate 2, Ga ２ O ３ The Ga-based substrate 2 has a substantially circular shape. ２ O ３ The diameter of the Ga substrate 2 is, for example, 50 mm or more and 150 mm or less. ２ O ３ The thickness T1 of the base substrate 2 is, for example, not less than 400 μm and not more than 800 μm.

[0016] The material of the metal layer 3 is, for example, a noble metal or a high-melting-point metal. For example, the material of the metal layer 3 is Pt or Au if it is a noble metal, but may be a noble metal other than Pt or Au. For example, the material of the metal layer 3 is Ta or W if it is a high-melting-point metal, but may be a high-melting-point metal other than Ta or W.

[0017] The metal layer 3 includes a plurality of metal portions 31. Each of the plurality of metal portions 31 is linear (long). The longitudinal direction of each of the plurality of metal portions 31 is defined as a first direction D11 (see FIG. 2 ), and Ga ２ O ３ In the following description, the direction perpendicular to the thickness direction D10 and the first direction D11 of the substrate 2 is defined as the second direction D12. The elongated shape is a shape that is long in one direction, and the length in that direction is longer than the length in another direction intersecting the first direction. Therefore, the length in the first direction D11 of each of the multiple metal parts 31 is longer than the length in the second direction D12.

[0018] In the metal layer 3, Ga ２ O ３ In a plan view of the substrate 2 in the thickness direction D10, a plurality of metal portions 31 are arranged at intervals in the second direction D12 (see FIG. 2). ２ O ３ In a plan view of the substrate 2 in the thickness direction D10, the metal portions 31 are arranged at intervals in a direction perpendicular to the metal portions 31. In other words, in the metal layer 3, Ga ２ O ３ The plurality of metal portions 31 are arranged in a stripe pattern in a plan view in the thickness direction D10 of the base substrate 2. The thickness of each of the plurality of metal portions 31 is, for example, 50 nm, but is not limited to 50 nm.

[0019] In the metal layer 3, a plurality of metal portions 31 and a plurality of openings 32 are arranged alternately (see FIG. 3 ). Each of the plurality of openings 32 is open on both sides in the first direction D11, but may have a shape that is not open on both sides in the first direction D11.

[0020] β-Ga ２ O ３ Layer 4 is Ga ２ O ３The epitaxial layer is epitaxially grown on the β-Ga substrate 2 as a base. ２ O ３ Layer 4 is β-Ga ２ O ３ β-Ga epitaxially grown on the substrate 20 ２ O ３ In the epitaxial wafer 1 according to the first embodiment, ２ O ３ Layer 4 is n-type β-Ga ２ O ３ n-type β-Ga ２ O ３ The layer contains n-type impurities (eg, Sn, Si, or Ge).

[0021] β-Ga ２ O ３ Layer 4 is Ga ２ O ３ The β-Ga GaN layer covers the first main surface 21 of the β-Ga GaN substrate 2 and the metal layer 3. ２ O ３ Layer 4 is Ga ２ O ３ The metal layer 3 is covered with the insulating film 212 and a plurality of portions 211 that are not covered with the metal layer 3 on the first main surface 21 of the substrate 2 .

[0022] β-Ga ２ O ３ The thickness T2 of the layer 4 is Ga ２ O ３ The thickness is thinner than the thickness T1 of the β-Ga substrate 2. ２ O ３ The thickness T2 of the layer 4 is, for example, 200 nm to 500 nm, but may be greater than 500 nm.

[0023] (1.2) Method for Manufacturing Epitaxial Wafer Hereinafter, a method for manufacturing the epitaxial wafer 1 according to the first embodiment will be described with reference to FIGS. 4A to 4E.

[0024] The method for manufacturing the epitaxial wafer 1 includes a substrate preparation step, a metal layer formation step, and an epitaxial growth step.

[0025] In the substrate preparation step, a GaAs substrate having a first main surface 21 and a second main surface 22 opposite to the first main surface 21 is prepared. ２ O ３ A substrate 2 is prepared (see FIG. 4A).

[0026] In the metal layer forming step, Ga ２ O ３ A metal layer 3 having a plurality of metal portions 31 and a plurality of openings 32 is formed on the first main surface 21 of the semiconductor substrate 2 (see FIG. 4B). That is, in the metal layer forming step, the metal layer 3 is formed in a predetermined pattern. In the metal layer forming step, for example, Ga ２ O ３ A metal material layer that will become the metal layer 3 is formed on the first main surface 21 of the base substrate 2 by a vapor deposition method or the like, and then the metal material layer is patterned using, for example, photolithography and etching techniques to form the metal layer 3 made of a part of the metal material layer. Note that in the metal layer formation step, the metal layer 3 may be formed by a vapor deposition method or the like using a metal mask or the like.

[0027] In the epitaxial growth process, Ga ２ O ３ The β-Ga alloy covering the first main surface 21 of the base substrate 2 and the metal layer 3 ２ O ３ The layer 4 is formed by Epitaxial Lateral Overgrowth (ELO) using mist CVD (Chemical Vapor Deposition) (see FIG. 4E). ELO is a crystal growth technique that combines selective growth and lateral growth. ２ O ３ Layer 4: Ga ２ O ３ The portion formed directly on the first main surface 21 of the β-Ga substrate 2 is formed by selective growth, and the portion formed on the metal layer 3 is formed by lateral growth. ２ O ３ Layer 4: Ga ２ O ３ The portion formed directly on the first main surface 21 of the Ga-based substrate 2 is ２ O ３The β-Ga alloy substrate 2 includes a plurality of first portions 401 (see FIG. 5) that correspond one-to-one to a plurality of portions 211 that are not covered with the metal layer 3 on the first main surface 21 of the β-Ga alloy substrate 2. ２ O ３ The portion of the layer 4 formed on the metal layer 3 includes a plurality of second portions 402 (see FIG. 5) that correspond one-to-one to the plurality of metal portions 31. ２ O ３ A part of the layer 4 is β-Ga ２ O ３ β-Ga during epitaxial growth of crystal ２ O ３ Layer 4C is shown, and in FIG. 4D, β-Ga ２ O ３ A part of the layer 4 is β-Ga ２ O ３ β-Ga during epitaxial growth of crystal ２ O ３ Layer 4D is shown. ２ O ３ The layer 4D is β-Ga ２ O ３ β-Ga layer grown further than layer 4C ２ O ３ layer, and β-Ga ２ O ３ It is thicker than the layer 4C and is made of β-Ga ２ O ３ 4E shows the β-Ga layers that have grown laterally from both sides of each metal portion 31 in the width direction (direction parallel to the second direction D12). ２ O ３ The β-Ga crystals are bonded together to form a β-Ga ２ O ３ The epitaxial growth step uses a mist CVD apparatus as the epitaxial growth apparatus. Alternatively, the epitaxial growth step may use, for example, molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HVPE).

[0028] As shown in FIG. 5, the β-Ga in the epitaxial wafer 1 ２ O ３The first portions 401 of the layer 4 are Ga ２ O ３ The threading dislocations A1 in the β-Ga substrate 2 ２ O ３ The dislocations A2 in the layer 4 are inherited as threading dislocations A2 in the second portion 402. ２ O ３ The threading dislocations A1 of the β-Ga substrate 2 are not inherited. ２ O ３ In the layer 4, the dislocation density of each of the second portions 402 is lower than the dislocation density of each of the first portions 401. The dislocation density is a value determined from a cross-sectional transmission electron microscope (TEM) image.

[0029] (2) β-Ga ２ O ３ (2.1) β-Ga-based devices and their manufacturing methods ２ O ３ Hereinafter, the β-Ga-based device according to the first embodiment will be referred to as a β-Ga-based device. ２ O ３ The system device 10 will be described with reference to FIGS.

[0030] β-Ga according to embodiment 1 ２ O ３ As shown in FIG. ２ O ３ a β-Ga-based substrate 2a, a metal layer 3a, and ２ O ３ The semiconductor device includes a layer 4a and a semiconductor element 5. ２ O ３ The GaAs device 10 is a chip (also called a die). ２ O ３ The substrate 2a is, for example, a Ga epitaxial wafer 1 (see FIG. 1). ２ O ３ It is a part of the Ga-based substrate 2. ２ O ３ The thickness T11 of the Ga-based substrate 2a is ２ O ３ The thickness is the same as the thickness T1 of the Ga-based substrate 2. ２ O ３ It may be thinner than the thickness T1 of the base substrate 2.

[0031] Ga ２ O ３ The substrate 2a has a first main surface 21a and a second main surface 22a opposite to the first main surface 21a.

[0032] Ga ２ O ３ The β-Ga-based substrate 2a is ２ O ３ The substrate 20a is β-Ga ２ O ３ The substrate 20a is made of β-Ga ２ O ３ It is a single crystal. ２ O ３ The crystal structure of the single crystal is monoclinic. ２ O ３ The first main surface 21a of the β-Ga-based substrate 2a is, for example, ２ O ３ The (010) or (001) plane of the single crystal is used, but is not limited to the (010) or (001) plane. ２ O ３ In the β-Ga based device 10, ２ O ３ The substrate 20a is semi-insulating β-Ga ２ O ３ Semi-insulating β-Ga substrate ２ O ３ The substrate has a resistivity of 1×10 ８ Ωcm or more 1×10 １２ β-Ga below Ωcm ２ O ３ The substrate is Ga ２ O ３ When viewed from the thickness direction D20 of the substrate 2a, Ga ２ O ３ The Ga substrate 2a is rectangular. ２ O ３ The thickness T11 of the base substrate 2a is, for example, not less than 400 μm and not more than 800 μm.

[0033] The material of the metal layer 3a is a noble metal or a high-melting-point metal. For example, the material of the metal layer 3a is Pt or Au, but may be a noble metal other than Pt or Au. For example, the material of the metal layer 3a is Ta or W, but may be a high-melting-point metal other than Ta or W.

[0034] The metal layer 3a is Ga ２ O ３ It is formed on a part of the first main surface 21a of the base substrate 2a.

[0035] β-Ga ２ O ３ The layer 4a is Ga ２ O ３ The β-Ga GaN layer covers the first main surface 21a of the β-Ga GaN substrate 2a and the metal layer 3a. ２ O ３ The layer 4a is Ga ２ O ３ The insulating film 211 covers the metal layer 3a and a plurality of portions 211a that are not covered by the metal layer 3a on the first main surface 21a of the base substrate 2a.

[0036] The semiconductor element 5 is a β-Ga ２ O ３ The semiconductor element 5 includes at least a part of the layer 4a.

[0037] β-Ga according to embodiment 1 ２ O ３ In the GaAs semiconductor device 10, the metal layer 3a includes a plurality of metal portions 31a. Each of the plurality of metal portions 31a is linear. The longitudinal direction of each of the plurality of metal portions 31a is defined as a first direction D21. ２ O ３ The direction perpendicular to the thickness direction D20 of the substrate 2a and the first direction D21 is defined as a second direction D22. ２ O ３ In a plan view of the substrate 2a in the thickness direction D20, a plurality of metal portions 31a are arranged spaced apart in the second direction D22. ２ O ３ In a plan view of the substrate 2a in the thickness direction D20, the plurality of metal portions 31a are arranged to be spaced apart in a direction (second direction D22) perpendicular to the plurality of metal portions 31a. ２ O ３ In a plan view of the substrate 2a in the thickness direction D20, the metal portions 31a are arranged in a stripe pattern. The thickness of each of the metal portions 31a is, for example, 50 nm, but is not limited to 50 nm.

[0038] In the metal layer 3 a, a plurality of metal portions 31 a and a plurality of openings 32 a are arranged alternately. Each of the plurality of openings 32 a is open on both sides in the first direction D21, but may have a shape that is not open on both sides in the first direction D21.

[0039] β-Ga ２ O ３ The layer 4a is Ga ２ O ３ The epitaxial layer is epitaxially grown on the β-Ga substrate 2a. ２ O ３ The layer 4a is made of β-Ga ２ O ３ β-Ga epitaxially grown on the substrate 20a ２ O ３ This is an epitaxial layer. ２ O ３ In the β-Ga based device 10, ２ O ３ The layer 4a is an n-type β-Ga ２ O ３ n-type β-Ga ２ O ３ The layer contains n-type impurities (for example, Sn, Si, or Ge). ２ O ３ The layer 4a is made of n-type β-Ga ２ O ３ It may also be referred to as layer 4a.

[0040] β-Ga ２ O ３ The thickness T12 of the layer 4a is Ga ２ O ３ The thickness T11 of the β-Ga substrate 2a is thinner than the thickness T11 of the β-Ga ２ O ３ The thickness T12 of the layer 4a is, for example, 200 nm or more and 500 nm or less, but may be thicker than 500 nm.

[0041] β-Ga ２ O ３ In the layer 4a, Ga ２ O ３The dislocation density of the portion of the substrate 2a that overlaps the metal portion 31a in the thickness direction D20 (the portion formed on the metal portion 31a) is ２ O ３ The portion of the substrate 2a that does not overlap the metal portion 31a in the thickness direction D20 (Ga ２ O ３ The dislocation density is smaller than that of the portion formed directly on the base substrate 2a.

[0042] β-Ga according to embodiment 1 ２ O ３ In the system device 10, the semiconductor element 5 is a metal semiconductor field effect transistor (MESFET).

[0043] 6 and 7, the semiconductor element 5 includes a drain region 51, a source region 52, a drain electrode 55, a source electrode 56, and a gate electrode 57. In Fig. 7, the source electrode 56 and the gate electrode 57 are hatched with dots. These hatches do not represent a cross section, but are added merely to make the drawings easier to see.

[0044] The drain region 51 is made of n-type β-Ga ２ O ３ n formed in layer 4a ＋ β-Ga ２ O ３ It consists of the region Ga ２ O ３ The drain region 51 has a comb shape in a plan view from the thickness direction D20 of the base substrate 2a. The drain region 51 has an elongated drain region comb bone portion whose longitudinal direction is the second direction D22, and a plurality of drain region comb teeth 512 extending from the drain region comb bone portion in the first direction D21. ＋ β-Ga ２ O ３ The carrier concentration of the region is n-type β-Ga ２ O ３ The carrier concentration is higher than that of the layer 4a.

[0045] The source region 52 is n-type β-Ga ２ O ３ n formed in layer 4a＋ β-Ga ２ O ３ It consists of the region Ga ２ O ３ The source region 52 has a comb shape in a plan view from the thickness direction D20 of the base substrate 2a. The source region 52 has an elongated source region comb bone portion with the longitudinal direction being the second direction D22, and a plurality of source region comb teeth 522 extending from the source region comb bone portion in the first direction D21. ＋ β-Ga ２ O ３ The carrier concentration of the region is n-type β-Ga ２ O ３ The carrier concentration is higher than that of the layer 4a.

[0046] The channel forming region 53 is made of n-type β-Ga ２ O ３ In the layer 4a, the channel formation region 53 is formed between the drain region 51 and the source region 52. More specifically, the channel formation region 53 is formed between the drain region comb-tooth portion 512 and the source region comb-tooth portion 522 adjacent to each other in the second direction D22.

[0047] The drain electrode 55 is formed on the drain region 51. The drain electrode 55 is made of Ga ２ O ３ The drain electrode 55 overlaps the drain region 51 in a plan view from the thickness direction D20 of the substrate 2a. ２ O ３ The drain electrode 55 has a comb shape in a plan view from the thickness direction D20 of the base substrate 2a (see FIG. 7). As shown in FIG. 7, the drain electrode 55 has an elongated drain electrode comb-like portion 551 with the second direction D22 as its longitudinal direction, and a plurality of drain electrode comb-like portions 552 extending from the drain electrode comb-like portion 551 in the first direction D21. The plurality of drain electrode comb-like portions 552 correspond one-to-one to the plurality of drain region comb-like portions 512. Ga ２ O ３In a plan view from the thickness direction D20 of the base substrate 2a, each of the plurality of drain electrode comb teeth 552 overlaps a corresponding one of the plurality of drain region comb teeth 512. The material of the drain electrode 55 is, for example, Au or Pt, but may be a metal other than Au or Pt, or may be an alloy. The drain electrode 55 is electrically connected to the drain region 51. "The drain electrode 55 is electrically connected to the drain region 51" means that the drain electrode 55 and the drain region 51 are in ohmic contact.

[0048] The source electrode 56 is formed on the source region 52. The source electrode 56 is made of Ga ２ O ３ The source electrode 56 overlaps the source region 52 in a plan view in the thickness direction D20 of the base substrate 2a. ２ O ３ The source electrode 56 has a comb shape in plan view from the thickness direction D20 of the base substrate 2a (see FIG. 7). The source electrode 56 has an elongated source electrode comb-like portion 561 with the second direction D22 as its longitudinal direction, and a plurality of source electrode comb-like portions 562 extending from the source electrode comb-like portion 561 in the first direction D21. The plurality of source electrode comb-like portions 562 correspond one-to-one to the plurality of source region comb-like portions 522. Ga ２ O ３ In a plan view from the thickness direction D20 of the base substrate 2a, each of the multiple source electrode comb teeth 562 overlaps a corresponding one of the multiple source region comb teeth 522. The material of the source electrode 56 is, for example, Au or Pt, but may be a metal other than Au or Pt, or may be an alloy. The source electrode 56 is electrically connected to the source region 52. "The source electrode 56 is electrically connected to the source region 52" means that the source electrode 56 and the source region 52 are in ohmic contact.

[0049] In the semiconductor element 5, the drain electrode comb-like portion 551 and the source electrode comb-like portion 561 face each other in the first direction D21. In addition, in the semiconductor element 5, a plurality of drain electrode comb-like portions 552 and a plurality of source electrode comb-like portions 562 are arranged at a distance from each other in the second direction D22.

[0050] The gate electrode 57 is made of n-type β-Ga ２ O ３ The gate electrode 57 is formed on the layer 4a. ２ O ３ The gate electrode 57 has a comb shape in a plan view in the thickness direction D20 of the base substrate 2a (see FIG. 7 ). The gate electrode 57 has an elongated gate electrode comb rib portion 571 with its longitudinal direction in the second direction D22 and a plurality of gate electrode comb teeth 572 extending in the first direction D21 from the gate electrode comb rib portion 571. The material of the gate electrode 57 is, for example, Au or Pt, but may be a metal other than Au or Pt, or may be an alloy.

[0051] In the semiconductor element 5, a plurality of drain electrode comb teeth 552, a plurality of gate electrode comb teeth 572, and a plurality of source electrode comb teeth 562 are aligned in the second direction D22. Therefore, the gate electrode comb teeth 572 are positioned between the drain electrode comb teeth 552 and the source electrode comb teeth 562 that are adjacent to each other in the second direction D22. The plurality of gate electrode comb teeth 572 are made of n-type β-Ga ２ O ３ The channel forming regions 53 correspond one-to-one to the channel forming regions 53 in the layer 4a. Each of the channel forming regions 53 is made of n-type β-Ga ２ O ３ This is a region between the drain region comb tooth portion 512 and the source region comb tooth portion 522 adjacent to each other in the second direction D22 in the layer 4a. ２ O ３ In a plan view from the thickness direction D20 of the substrate 2a, each of the plurality of gate electrode comb-teeth portions 572 overlaps a corresponding one of the plurality of channel formation regions 53. The semiconductor element 5 has an interlayer insulating film interposed between the gate electrode comb-teeth portion 571 and the plurality of drain electrode comb-teeth portions 552 so that the gate electrode 57 and the drain electrode 55 do not contact each other.

[0052] Ga ２ O ３ In a plan view from the thickness direction D20 of the base substrate 2a, each of the plurality of gate electrode comb-tooth portions 572 overlaps one of the plurality of metal portions 31a. ２ O ３In a plan view from the thickness direction D20 of the substrate 2a, each of the plurality of gate electrode comb teeth 572 is Ga ２ O ３ In the semiconductor device 5 according to the first embodiment, the gate electrode comb-tooth portions 572 are in one-to-one correspondence with the metal portions 31a, but this is not essential. ２ O ３ In a plan view of the substrate 2a in the thickness direction D20, each of the plurality of channel formation regions 53 overlaps one of the plurality of metal portions 31a, and is formed of Ga. ２ O ３ The first and second portions 211a do not overlap any of the plurality of portions 211a of the first main surface 21a of the base substrate 2a.

[0053] Ga ２ O ３ In a plan view of the system substrate 2a in the thickness direction D20, each of the plurality of gate electrode comb teeth 572 is offset in the second direction D22 so as not to overlap with the center in the second direction D22 of a corresponding one of the plurality of metal portions 31a. In the semiconductor element 5, the shortest distance between the gate electrode comb teeth 572 and the drain electrode comb teeth 552 adjacent to each other in the second direction D22 is shorter than the distance between the gate electrode comb teeth 572 and the source electrode comb teeth 562 adjacent to each other in the second direction D22.

[0054] (2.2) β-Ga ２ O ３ In the following, we will discuss the manufacturing method of β-Ga ２ O ３ An example of a method for manufacturing the semiconductor device 10 will be briefly described with reference to FIGS. 4A to 4E, but descriptions of steps similar to those in the method for manufacturing the epitaxial wafer 1 will be omitted where appropriate.

[0055] β-Ga ２ O ３ The method for manufacturing the semiconductor device 10 includes a substrate preparation step, a metal layer formation step, an epitaxial growth step, a drain region / source region formation step, an electrode formation step, and a dicing step.

[0056] In the substrate preparation step, a GaAs substrate having a first main surface 21 and a second main surface 22 opposite to the first main surface 21 is prepared. ２ O ３ A Ga-based substrate 2 is prepared (see FIG. 4A). ２ O ３ The β-Ga-based substrate 2 is ２ O ３ A wafer made of a substrate 20, ２ O ３ This is the wafer that will be the base substrate 2a.

[0057] In the metal layer forming step, Ga ２ O ３ A metal layer 3 having a plurality of metal portions 31 and a plurality of openings 32 is formed on the first main surface 21 of the semiconductor substrate 2 (see FIG. 4B ). The plurality of metal portions 31 and the plurality of openings 32 become the source of a plurality of metal portions 31a and a plurality of openings 32a. The width of each of the plurality of metal portions 31 in the second direction D12 is the same as the width of each of the plurality of metal portions 31a in the second direction D22. The length of each of the plurality of metal portions 31 in the first direction D11 is longer than the length of each of the plurality of metal portions 31a in the first direction D21. The width of each of the plurality of openings 32 in the second direction D12 is the same as the width of each of the plurality of openings 32a in the second direction D22. The length of each of the plurality of openings 32 in the first direction D11 is longer than the length of each of the plurality of openings 32a in the first direction D21.

[0058] In the epitaxial growth process, Ga ２ O ３ The β-Ga alloy covering the first main surface 21 of the base substrate 2 and the metal layer 3 ２ O ３ The layer 4 is formed by lateral overgrowth using mist CVD (see FIG. 4E). ２ O ３ Layer 4 is n-type β-Ga ２ O ３ layer, and β-Ga ２ O ３ This is the source of the layer 4a. In the epitaxial growth step, for example, MBE or HVPE may be used instead of the mist CVD method.

[0059] In the process of forming the drain and source regions, for example, ion implantation technology, diffusion technology, etc. are used to implant β-Ga ２ O ３ A plurality of drain regions 51 (see FIG. 6) and a plurality of source regions 52 (see FIG. 6) are formed in layer 4 .

[0060] In the electrode formation step, the drain electrode 55, the source electrode 56, and the gate electrode 57 are formed by evaporation or the like.

[0061] β-Ga ２ O ３ In the method for manufacturing the β-Ga-based device 10, the steps from the substrate preparation step to the electrode formation step are carried out to form a plurality of β-Ga ２ O ３ A wafer including the β-Ga GaN device 10 can be obtained. ２ O ３ In the method for manufacturing the β-Ga-based device 10, a plurality of β-Ga-based ２ O ３ The wafer including the β-Ga semiconductor device 10 is cut by, for example, a dicing saw or a laser dicing device, thereby forming a plurality of β-Ga semiconductor devices. ２ O ３ A system device 10 can be obtained.

[0062] (3) Advantages The epitaxial wafer 1 according to the first embodiment is a Ga ２ O ３ a β-Ga-based substrate 2, a metal layer 3, and ２ O ３ and a layer 4. ２ O ３ The metal substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The metal layer 3 is made of Ga ２ O ３ The metal layer 3 is formed on the first main surface 21 of the β-Ga alloy substrate 2. The metal layer 3 has a plurality of openings 32. ２ O ３ Layer 4 is Ga ２ O ３ The metal layer 3 is made of a noble metal or a high-melting-point metal. ２ O ３ The thickness T2 of the layer 4 is Ga ２ O３ It is thinner than the thickness T1 of the base substrate 2.

[0063] The epitaxial wafer 1 according to the first embodiment has the above-described configuration, and therefore, ２ O ３ It is possible to improve the characteristics of the β-Ga semiconductor device 10. More specifically, in the epitaxial wafer 1 according to the first embodiment, ２ O ３ The dislocation density of each of the plurality of second portions 402 corresponding to the plurality of metal portions 31 in the layer 4 is ２ O ３ The dislocation density is smaller than that of each of the plurality of first portions 401 formed directly on the first main surface 21 of the base substrate 2. Therefore, the β-Ga ２ O ３ Regarding the β-Ga based device 10, ２ O ３ The portion of the layer 4 that covers the metal layer 3 is β-Ga. ２ O ３ By laying out the functional regions susceptible to dislocations in the β-Ga GaN-based device 10, ２ O ３ This makes it possible to improve the characteristics of the system device 10. The functional region is, for example, the channel formation region 53 which is important in determining the characteristics of the MESFET that constitutes the semiconductor element 5.

[0064] The epitaxial wafer 1 according to the first embodiment is made of β-Ga ２ O ３ The portion of the layer 4 covering the metal layer 3 (each second portion 402) is ２ O ３ Since the threading dislocations A1 in the Ga-based substrate 2 are not easily inherited, ２ O ３ As the base substrate 2, a cheaper β-Ga ２ O ３ This allows the use of the substrate 20, thereby enabling cost reduction.

[0065] The epitaxial wafer 1 according to the first embodiment is made of β-Ga ２ O ３ Layer 4 is Ga ２ O３ The epitaxial wafer 1 covers the first main surface 21 of the β-Ga substrate 2 and the metal layer 3. ２ O ３ A part of layer 4 and Ga ２ O ３ Since the metal layer 3 is interposed between the first main surface 21 of the Ga-based substrate 2 and the Ga ２ O ３ When the β-Ga-based substrate 2 is polished from the second main surface 22 side to make it thinner, ２ O ３ The influence on the portion of the layer 4 formed on the metal layer 3 can be reduced. ２ O ３ This makes it easier to make the thickness T1 of the substrate 2 thinner. ２ O ３ It is possible to reduce the thermal resistance of the β-Ga semiconductor device 10. ２ O ３ This makes it possible to improve the characteristics of the semiconductor device 10.

[0066] In addition, the β-Ga according to the first embodiment ２ O ３ The Ga-based device 10 ２ O ３ a β-Ga-based substrate 2a, a metal layer 3a, and ２ O ３ The semiconductor device includes a layer 4a and a semiconductor element 5. ２ O ３ The metal substrate 2a has a first main surface 21a and a second main surface 22a opposite to the first main surface 21a. ２ O ３ It is formed on a part of the first main surface 21a of the β-Ga-based substrate 2a. ２ O ３ The layer 4a is Ga ２ O ３ The semiconductor element 5 covers the first main surface 21a of the β-Ga GaN substrate 2a and the metal layer 3a. ２ O ３ The metal layer 3a includes at least a part of the layer 4a. The material of the metal layer 3a is a noble metal or a high-melting-point metal. ２ O ３ The thickness T12 of the layer 4a is Ga ２ O３ It is thinner than the thickness T11 of the base substrate 2a.

[0067] β-Ga according to embodiment 1 ２ O ３ The system device 10 has the above-described configuration, and therefore, it is possible to improve the characteristics.

[0068] Here, the β-Ga according to embodiment 1 ２ O ３ In the semiconductor device 10, the semiconductor element 5 is a MESFET including a drain region 51, a source region 52, a channel forming region 53, a drain electrode 55, a source electrode 56, and a gate electrode 57. The drain region 51, the source region 52, and the channel forming region 53 are made of β-Ga ２ O ３ It is formed in the layer 4a. ２ O ３ In a plan view from the thickness direction D20 of the base substrate 2a, the channel formation region 53 overlaps one of the plurality of metal portions 31a.

[0069] β-Ga according to embodiment 1 ２ O ３ By providing the above-described configuration, the system device 10 can improve the characteristics of the MESFET.

[0070] In addition, the β-Ga according to the first embodiment ２ O ３ The method for manufacturing the GaAs-based device 10 includes a substrate preparation step, a metal layer formation step, and an epitaxial growth step. In the substrate preparation step, a GaAs-based device having a first main surface 21 and a second main surface 22 opposite to the first main surface 21 is prepared. ２ O ３ In the metal layer forming step, a Ga ２ O ３ A metal layer 3 having a plurality of openings 32 is formed on the first main surface 21 of the substrate 2. In the epitaxial growth step, Ga ２ O ３ The β-Ga alloy covering the first main surface 21 of the base substrate 2 and the metal layer 3 ２ O ３ The layer 4 is formed by selective lateral overgrowth using mist CVD. The material of the metal layer 3 is a noble metal or a high melting point metal. ２O ３ The thickness T2 of the layer 4 is Ga ２ O ３ It is thinner than the thickness T1 of the base substrate 2.

[0071] β-Ga according to embodiment 1 ２ O ３ According to the method for manufacturing the β-Ga based device 10, ２ O ３ This makes it possible to improve the characteristics of the semiconductor device 10.

[0072] (Modification of Embodiment 1) An epitaxial wafer 1A according to a modification of Embodiment 1 will be described with reference to Fig. 8. With regard to the epitaxial wafer 1A according to the modification, the same components as those of the epitaxial wafer 1 according to Embodiment 1 (see Figs. 1 and 2) are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0073] (1) Epitaxial Wafer The epitaxial wafer 1A according to the modified example has the same structure as the Ga epitaxial wafer 1 according to the first embodiment. ２ O ３ Instead of the Ga-based substrate 2, ２ O ３ The epitaxial wafer 1 according to the first embodiment differs from the epitaxial wafer 1 according to the first embodiment in that it includes a base substrate 2A.

[0074] Ga ２ O ３ The β-Ga GaN substrate 2A includes a sapphire substrate 24 and a β-Ga GaN layer formed on the sapphire substrate 24. ２ O ３ layer 25. ２ O ３ In the β-Ga-based substrate 2A, ２ O ３ The surface 251 of the layer 25 is Ga ２ O ３ The first main surface 21A of the Ga-based substrate 2A is formed. ２ O ３ When viewed from the thickness direction D10 of the substrate 2A, Ga ２ O ３ The substrate 2A has a substantially circular shape.

[0075] Ga ２ O ３ β-Ga in the base substrate 2A ２O ３ The thickness of the layer 25 is thinner than the thickness of the sapphire substrate 24. The thickness of the sapphire substrate 24 is, for example, 430 μm or more and 1300 μm or less. ２ O ３ The thickness of the layer 25 is, for example, not less than 0.2 μm and not more than 3 μm.

[0076] The sapphire substrate 24 has a first major surface 241 and a second major surface 242 opposite to the first major surface 241. The first major surface 241 of the sapphire substrate 24 is a c-plane, but is not limited to the c-plane and may be, for example, an m-plane. The c-plane is the (0001) plane, and the m-plane is, for example, the (1010) plane. Each of the (0001) plane and the (1010) plane is a crystal plane according to Miller indices, in which four indices are expressed in parentheses. Ga ２ O ３ In the sapphire substrate 2A, the second main surface 242 of the sapphire substrate 24 is Ga ２ O ３ This forms the second main surface 22A of the base substrate 2A.

[0077] In the epitaxial wafer 1A, β-Ga ２ O ３ The thickness T2 of the layer 4 is Ga ２ O ３ It is thinner than the thickness T1 of the base substrate 2A.

[0078] β-Ga of epitaxial wafer 1A according to modification 1 ２ O ３ In layer 4, Ga ２ O ３ The dislocation density of each of the plurality of second portions 402 corresponding to each of the plurality of metal portions 31 in the thickness direction D10 of the substrate 2A is ２ O ３ The dislocation density is smaller than that of each of the plurality of first portions 401 formed directly on the plurality of regions 211 of the first main surface 21A of the base substrate 2A.

[0079] (2) Method for Manufacturing Epitaxial Wafer Similar to the method for manufacturing the epitaxial wafer 1, the method for manufacturing the epitaxial wafer 1A includes a substrate preparation step, a metal layer formation step, and an epitaxial growth step.

[0080] In the method for manufacturing the epitaxial wafer 1A, in the substrate preparation step, a sapphire substrate 24 is prepared, and then α-Ga is deposited on the first main surface 241 of the sapphire substrate 24. ２ O ３ The layer is epitaxially grown by mist CVD, and then α-Ga ２ O ３ Annealing the layer ２ O ３ The crystal structure of the layer is changed to β-Ga ２ O ３ The layer 25 is formed by α-Ga ２ O ３ The layer is made of β-Ga ２ O ３ This converts the Ga ２ O ３ In the substrate preparation step, α-Ga is deposited on the first main surface 241 of the sapphire substrate 24. ２ O ３ The β-Ga layer is epitaxially grown on the first main surface 241 of the sapphire substrate 24 by mist CVD at a higher growth temperature than that in the case of epitaxially growing the layer by mist CVD. ２ O ３ Layer 25 may be grown epitaxially.

[0081] In the metal layer forming step, Ga ２ O ３ A metal layer 3 having a plurality of metal portions 31 and a plurality of openings 32 is formed on a first main surface 21A of a base substrate 2A.

[0082] In the epitaxial growth process, Ga ２ O ３ β-Ga covering the first main surface 21A of the base substrate 2A and the metal layer 3 ２ O ３ The layer 4 is formed by epitaxial lateral overgrowth using mist CVD. In the epitaxial growth step, for example, MBE or HVPE may be used instead of mist CVD.

[0083] (3) β-Ga ２ O ３ β-Ga-based device according to a modified example ２ O ３The structure of the β-Ga-based device is ２ O ３ The β-Ga GaN device according to the modification is substantially the same as the β-Ga GaN device 10. ２ O ３ The β-Ga-based device according to the first embodiment ２ O ３ Ga in the Ga-based device 10 ２ O ３ The β-Ga-based substrate 2a is formed on a sapphire substrate that is a part of the sapphire substrate 24. ２ O ３ β-Ga consisting of a part of the layer 25 ２ O ３ It differs in that it is composed of layers.

[0084] (4) β-Ga ２ O ３ Modified β-Ga-based device manufacturing method ２ O ３ The method for manufacturing a β-Ga-based device according to the first embodiment ２ O ３ The manufacturing method is substantially the same as that of the semiconductor device 10, except that an epitaxial wafer 1A is prepared in place of the epitaxial wafer 1 in the substrate preparation step.

[0085] (5) Advantages The epitaxial wafer 1A according to the modified example, like the epitaxial wafer 1 according to the first embodiment, ２ O ３ This makes it possible to improve the characteristics of the semiconductor device 10.

[0086] In addition, the epitaxial wafer 1A according to the modification has a β-Ga epitaxial wafer 1 ２ O ３ Since a sapphire substrate 24 that is less expensive than the substrate 20 can be used, costs can be reduced compared to the epitaxial wafer 1 .

[0087] (Embodiment 2) Hereinafter, β-Ga according to embodiment 2 will be described. ２ O ３ The β-Ga GaN-based device 10B and its manufacturing method will be described with reference to FIGS. ２ O３ Regarding the β-Ga-based device 10B, ２ O ３ The same components as those in the system device 10 (see FIGS. 6 and 7) are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0088] (1) β-Ga ２ O ３ Hereinafter, the β-Ga-based device according to the second embodiment will be referred to as a β-Ga-based device. ２ O ３ The system device 10B will be described with reference to FIGS.

[0089] β-Ga according to embodiment 2 ２ O ３ The GaAs device 10B is ２ O ３ a β-Ga-based substrate 2a, a metal layer 3a, and ２ O ３ The semiconductor device includes a layer 4a and a semiconductor element 5B.

[0090] Ga ２ O ３ The substrate 2a has a first main surface 21a and a second main surface 22a opposite to the first main surface 21a.

[0091] Ga ２ O ３ The β-Ga-based substrate 2a is ２ O ３ The substrate 20a is β-Ga ２ O ３ The substrate 20a is semi-insulating β-Ga ２ O ３ The substrate is Ga ２ O ３ When viewed from the thickness direction D20 of the substrate 2a, Ga ２ O ３ The base substrate 2a has a rectangular shape.

[0092] The material of the metal layer 3a is a noble metal or a high-melting-point metal. For example, the material of the metal layer 3a is Pt or Au, but may be a noble metal other than Pt or Au. For example, the material of the metal layer 3a is Ta or W, but may be a high-melting-point metal other than Ta or W.

[0093] The metal layer 3a is Ga２ O ３ It is formed on a part of the first main surface 21a of the base substrate 2a.

[0094] β-Ga ２ O ３ The layer 4a is Ga ２ O ３ The β-Ga GaN layer 2a covers a part of the first main surface 21a of the β-Ga GaN substrate 2a and a part of the metal layer 3a. ２ O ３ The layer 4a is Ga ２ O ３ The metal layer 3a is covered with the insulating film 211a. The insulating film 211a covers a part of each of the two portions 211a that are not covered with the metal layer 3a on the first main surface 21a of the base substrate 2a, and also covers a part of the metal layer 3a.

[0095] The semiconductor element 5B is a β-Ga ２ O ３ The semiconductor element 5B includes at least a part of the layer 4a. The semiconductor element 5B will be described later.

[0096] β-Ga ２ O ３ In the GaAs / GaAs system device 10B, the metal layer 3a includes one metal portion 31a. The metal portion 31a is linear (long). The longitudinal direction of the metal portion 31a is defined as a first direction D21 (see FIG. 10 ). ２ O ３ In the following description, a direction perpendicular to the thickness direction D20 of the base substrate 2a and the first direction D21 is defined as a second direction D22.

[0097] Ga ２ O ３ In a plan view of the substrate 2a in the thickness direction D20, the metal portion 31a is Ga. ２ O ３ The metal portion 31a is located between two portions 211a on the first main surface 21a of the β-Ga alloy substrate 2a. The metal portion 31a has a first end 310a and a second end 310b in the first direction D21. ２ O ３ In the semiconductor device 10B, the first end 310a and the second end 310b of the metal part 31a are made of β-Ga ２ O ３ It is not covered by layer 4a.

[0098] β-Ga ２ O ３ The layer 4a is Ga２ O ３ It is an epitaxial layer that is epitaxially grown on the base substrate 2a.

[0099] β-Ga ２ O ３ The layer 4a is Ga ２ O ３ The n-type semiconductor layer 2 covers a part of the first main surface 21a of the substrate 2a and a part of the metal layer 3a. ＋ β-Ga ２ O ３ Layer 41a and n ＋ β-Ga ２ O ３ n-type β-Ga formed on the layer 41a ２ O ３ and layer 42a.

[0100] n ＋ β-Ga ２ O ３ Layer 41a and n-type β-Ga ２ O ３ Each of the layers 42a contains an n-type impurity (e.g., Sn, Si, or Ge). ＋ β-Ga ２ O ３ The carrier concentration of the layer 41a is n-type β-Ga ２ O ３ The carrier concentration is higher than that of the layer 42a. ＋ β-Ga ２ O ３ The layer 41a is in ohmic contact with the metal layer 3a.

[0101] The semiconductor element 5B is a Schottky barrier diode.

[0102] The semiconductor element 5B includes a first metal electrode layer 58 made of the metal layer 3a and an n ＋ β-Ga ２ O ３ Layer 41a and n-type β-Ga ２ O ３ The second metal electrode layer 59 includes an n-type β-Ga ２ O ３ It is formed on the layer 42a and is n-type β-Ga ２ O ３ It is in Schottky contact with layer 42a.

[0103] In the semiconductor element 5B, Ga ２ O ３ In a plan view in the thickness direction D20 of the base substrate 2a, the entire second metal electrode layer 59 and a part of the first metal electrode layer 58 overlap each other.

[0104] In the semiconductor element 5B, the second metal electrode layer 59 constitutes an anode electrode, and ＋ β-Ga ２ O ３ The layer 41a and the first metal electrode layer 58 constitute a cathode electrode. In the semiconductor element 5B, the first end 310a and the second end 310b of the metal portion 31a constituting the first metal electrode layer 58 can be used as electrode pads of the cathode electrode.

[0105] (2) β-Ga ２ O ３ In the following, we will discuss the manufacturing method of β-Ga ２ O ３ An example of a method for manufacturing the β-Ga-based device 10B will be briefly described with reference to FIGS. 4A, 4B, 11, and 12. ２ O ３ The description of steps similar to those in the manufacturing method of the semiconductor device 10 will be omitted as appropriate.

[0106] β-Ga ２ O ３ The method for manufacturing the semiconductor device 10B includes a substrate preparation step, a metal layer formation step, an epitaxial growth step, an electrode layer formation step, a patterning step, and a dicing step.

[0107] In the substrate preparation step, a GaAs substrate having a first main surface 21 and a second main surface 22 opposite to the first main surface 21 is prepared. ２ O ３ A Ga-based substrate 2 is prepared (see FIG. 4A). ２ O ３ The β-Ga-based substrate 2 is ２ O ３ A wafer made of a substrate 20, ２ O ３ This is the wafer that will be the base substrate 2a.

[0108] In the metal layer forming step, Ga ２ O３ A metal layer 3 having a plurality of metal portions 31 and a plurality of openings 32 is formed on the first main surface 21 of the semiconductor substrate 2 (see FIG. 4B ). Each of the plurality of metal portions 31 becomes a metal portion 31a. The width of each of the plurality of metal portions 31 is the same as the width of the metal portion 31a in the second direction D22 (see FIG. 10 ). Furthermore, the length of each of the plurality of metal portions 31 is longer than the length of the metal portion 31a in the first direction D21 (see FIG. 10 ).

[0109] In the epitaxial growth process, Ga ２ O ３ The first main surface 21 of the substrate 2 and the metal layer 3 are covered with ＋ β-Ga ２ O ３ The layer 41 (see FIG. 11) is formed by selective lateral overgrowth using mist CVD. ＋ β-Ga ２ O ３ n-type β-Ga covering layer 41 ２ O ３ The layer 42 (see FIG. 11) is formed by mist CVD. ＋ β-Ga ２ O ３ Layer 41 is n ＋ β-Ga ２ O ３ It is the source of the layer 41a. n-type β-Ga ２ O ３ Layer 42 is n-type β-Ga ２ O ３ The epitaxial wafer 1B (see FIG. 11) is manufactured by performing the substrate preparation step, the metal layer formation step, and the epitaxial growth step. Note that in the epitaxial growth step, MBE or HVPE, for example, may be used instead of the mist CVD method. In this embodiment, n ＋ β-Ga ２ O ３ Layer 41 and n-type β-Ga ２ O ３ Layer 42 and β-Ga ２ O ３ It constitutes layer 4.

[0110] In the electrode layer forming step, a plurality of second metal electrode layers 59 (see FIG. 11) are formed by vapor deposition or the like. ２ O ３ A plurality of second metal electrode layers 59 are formed on layer 4 .

[0111] In the patterning process, for example, photolithography and etching techniques are used to pattern β-Ga. ２ O ３ By patterning the layer 4, a part of each of the plurality of metal portions 31 and Ga ２ O ３ A part of the first main surface 21 of the substrate 2 is exposed (see FIG. 12).

[0112] β-Ga ２ O ３ In the method for manufacturing the β-Ga semiconductor device 10B, a plurality of β-Ga semiconductor layers are fabricated by performing each step from the substrate preparation step to the patterning step. ２ O ３ A wafer 100B (see FIGS. 11 and 12) including the system device 10B can be obtained.

[0113] β-Ga ２ O ３ In the method for manufacturing the semiconductor device 10B, a plurality of β-Ga ２ O ３ The wafer 100B including the β-Ga GaN crystals 10B is cut by, for example, a dicing saw or a laser dicing device, thereby forming a plurality of β-Ga GaN crystals. ２ O ３ 12 indicates dicing lines.

[0114] (3) Advantages of the β-Ga according to the second embodiment ２ O ３ The GaAs device 10B is ２ O ３ a β-Ga-based substrate 2a, a metal layer 3a, and ２ O ３ The semiconductor device 5B includes a Ga layer 4a and a Ga ２ O ３ The metal substrate 2a has a first main surface 21a and a second main surface 22a opposite to the first main surface 21a.２ O ３ It is formed on a part of the first main surface 21a of the β-Ga-based substrate 2a. ２ O ３ The layer 4a is Ga ２ O ３ The semiconductor element 5B covers the first main surface 21a of the semiconductor substrate 2a and the metal layer 3a. ２ O ３ The metal layer 3a includes at least a part of the layer 4a. The material of the metal layer 3a is a noble metal or a high-melting-point metal. ２ O ３ The thickness T12 of the layer 4a is Ga ２ O ３ It is thinner than the thickness T11 of the base substrate 2a.

[0115] β-Ga according to embodiment 2 ２ O ３ Since the semiconductor device 10B has the above-described configuration, the first metal electrode layer 58 is made of Ga. ２ O ３ Compared to when the first metal electrode layer 58 and the second metal electrode layer 59 are provided on the second main surface 22a instead of the first main surface 21a of the substrate 2a, the distance between the first metal electrode layer 58 and the second metal electrode layer 59 is shorter, which reduces loss and makes it possible to improve characteristics.

[0116] Here, the β-Ga according to embodiment 2 ２ O ３ In the semiconductor device 10B, the semiconductor element 5B is a Schottky barrier diode. ２ O ３ In a plan view from the thickness direction D20 of the base substrate 2a, the entire second metal electrode layer 59 and a part of the first metal electrode layer 58 overlap each other, and the second metal electrode layer 59 constitutes an anode electrode. ＋ β-Ga ２ O ３ The layer 41a and the first metal electrode layer 58 constitute a cathode electrode. ２ O ３ The device 10B can improve the characteristics of the Schottky barrier diode.

[0117] β-Ga according to embodiment 2 ２ O ３In the semiconductor element 5B of the GaAs system device 10B, ２ O ３ When viewed in a plan view from the thickness direction D20 of the base substrate 2a, if at least a portion of the second metal electrode layer 59 and at least a portion of the first metal electrode layer 58 overlap, it is possible to improve the characteristics of the Schottky barrier diode.

[0118] (Embodiment 3) Hereinafter, β-Ga according to embodiment 3 will be described. ２ O ３ The β-Ga GaN device 10C and its manufacturing method will be described with reference to FIGS. ２ O ３ Regarding the β-Ga-based device 10C, ２ O ３ The same components as those in the system device 10 (see FIGS. 6 and 7) are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0119] (1) β-Ga ２ O ３ Hereinafter, the β-Ga-based device according to the third embodiment will be referred to as a β-Ga-based device. ２ O ３ The system device 10C will be described with reference to FIGS.

[0120] β-Ga according to embodiment 3 ２ O ３ The GaAs semiconductor device 10C is ２ O ３ a β-Ga-based substrate 2a, a metal layer 3a, and ２ O ３ The semiconductor device includes a layer 4a and a semiconductor element 5C.

[0121] Ga ２ O ３ The substrate 2a has a first main surface 21a and a second main surface 22a opposite to the first main surface 21a.

[0122] Ga ２ O ３ The β-Ga-based substrate 2a is ２ O ３ The substrate 20a is β-Ga ２ O ３ The substrate 20a is semi-insulating β-Ga ２ O ３The substrate is Ga ２ O ３ When viewed from the thickness direction D20 of the substrate 2a, Ga ２ O ３ The base substrate 2a has a rectangular shape.

[0123] The material of the metal layer 3a is a noble metal or a high-melting-point metal. For example, the material of the metal layer 3a is Pt or Au, but may be a noble metal other than Pt or Au. For example, the material of the metal layer 3a is Ta or W, but may be a high-melting-point metal other than Ta or W.

[0124] The metal layer 3a is Ga ２ O ３ It is formed on a part of the first main surface 21a of the base substrate 2a.

[0125] β-Ga ２ O ３ The layer 4a is Ga ２ O ３ The β-Ga GaN layer 2a covers a part of the first main surface 21a of the β-Ga GaN substrate 2a and a part of the metal layer 3a. ２ O ３ The layer 4a is Ga ２ O ３ The metal layer 3a is covered with the insulating film 211a. The insulating film 211a covers a part of each of the three portions 211a that are not covered with the metal layer 3a on the first main surface 21a of the base substrate 2a, and also covers a part of the metal layer 3a.

[0126] The semiconductor element 5C is a β-Ga ２ O ３ The semiconductor element 5C includes at least a part of the layer 4a. The semiconductor element 5C will be described later.

[0127] β-Ga ２ O ３ In the GaAs device 10C, the metal layer 3a includes two metal portions 31a. Each of the two metal portions 31a is linear. The longitudinal direction of the two metal portions 31a is defined as a first direction D21 (see FIG. 14 ). ２ O ３ In the following description, a direction perpendicular to the thickness direction D20 of the base substrate 2a and the first direction D21 is defined as a second direction D22.

[0128] 13, the semiconductor element 5C is a MOSFET, and includes a drain region 51, a source region 52, a channel formation region 53, a gate insulating film 54, a drain electrode 55, a source electrode 56, and a gate electrode 57. The drain region 51, the source region 52, and the channel formation region 53 are made of β-Ga ２ O ３ It is formed in layer 4a.

[0129] β-Ga ２ O ３ In the GaAs device 10C, ２ O ３ The base substrate 2a is a semi-insulating β-Ga ２ O ３ It is a circuit board.

[0130] β-Ga ２ O ３ The layer 4a is an n-type β-Ga ２ O ３ n-type β-Ga ２ O ３ The layer contains n-type impurities (e.g., Sn, Si, or Ge). ２ O ３ The layer 4a is Ga ２ O ３ The epitaxial layer is epitaxially grown on the β-Ga substrate 2a. ２ O ３ The layer 4a is made of n-type β-Ga ２ O ３ It may also be referred to as layer 4a.

[0131] The multiple metal portions 31a include a first metal portion 311 and a second metal portion 312 that are adjacent to each other in the direction in which the multiple metal portions 31a are arranged (second direction D22). As shown in Fig. 14, the first metal portion 311 has a first end 311a and a second end 311b in the first direction D21. The second metal portion 312 has a first end 312a and a second end 312b in the first direction D21.

[0132] As shown in FIG. 13, the drain region 51 is made of n-type β-Ga ２ O ３ n formed on the first metal portion 311 in the layer 4a ＋ β-Ga ２ O３ The drain region 51 is made up of n ＋ β-Ga ２ O ３ The carrier concentration of the region is n-type β-Ga ２ O ３ The drain region 51 has a carrier concentration higher than that of the layer 4a. ２ O ３ The β-Ga GaN layer 51 overlaps with the first metal portion 311 in the thickness direction D20 of the base substrate 2a. The drain region 51 is in contact with the first metal portion 311. Here, the drain region 51 is electrically connected to the first metal portion 311. In other words, the first metal portion 311 is in ohmic contact with the drain region 51. ２ O ３ In the semiconductor device 10C, the first metal portion 311 forms the drain electrode 55.

[0133] The source region 52 is n-type β-Ga ２ O ３ n formed on the second metal portion 312 in the layer 4a ＋ β-Ga ２ O ３ The source region 52 is made up of n ＋ β-Ga ２ O ３ The carrier concentration of the region is n-type β-Ga ２ O ３ The carrier concentration of the source region 52 is higher than that of the Ga ２ O ３ The source region 52 overlaps with the second metal portion 312 in the thickness direction D20 of the base substrate 2a. The source region 52 is in contact with the second metal portion 312. Here, the source region 52 is electrically connected to the source electrode 56. In other words, the second metal portion 312 is in ohmic contact with the source region 52. ２ O ３ In the semiconductor device 10C, the second metal portion 312 forms the source electrode 56.

[0134] The channel forming region 53 is made of n-type β-Ga ２ O ３ It is formed in layer 4 a between drain region 51 and source region 52 .

[0135] The gate insulating film 54 is made of n-type β-Ga ２ O ３ The gate insulating film 54 is formed on the layer 4a, the drain region 51, and the source region 52. The material of the gate insulating film 54 includes, for example, silicon oxide, hafnium oxide, aluminum nitride, silicon nitride, or aluminum oxide.

[0136] The gate electrode 57 is formed on the gate insulating film 54. The gate electrode 57 is made of Ga ２ O ３ In a plan view in the thickness direction D20 of the base substrate 2a, the gate electrode 57 is located between the drain region 51 and the source region 52. The material of the gate electrode 57 is, for example, Au or Pt, but may be a metal other than Au or Pt, or may be an alloy.

[0137] β-Ga ２ O ３ The layer 4a is formed in a shape that exposes a part of the first metal portion 311 and a part of the second metal portion 312. ２ O ３ In the semiconductor device 10C, β-Ga ２ O ３ The layer 4a is formed in a shape that exposes the first end 311a and the second end 311b of the first metal portion 311 and the first end 312a and the second end 312b of the second metal portion 312. ２ O ３ When viewed from the thickness direction D20 of the substrate 2a, ２ O ３ The layer 4a has a rectangular shape. ２ O ３ The length of the layer 4a is Ga ２ O ３ The length of the β-Ga substrate 2a is the same as the length of the β-Ga ２ O ３ The length of the layer 4a is Ga ２ O ３ The length of the substrate 2a is shorter than that of the base substrate 2a.

[0138] In the semiconductor element 5C, the first end 311a and the second end 311b of the first metal portion 311 constituting the drain electrode 55 can be used as electrode pads for the drain electrode 55. In addition, in the semiconductor element 5C, the first end 312a and the second end 312b of the second metal portion 312 constituting the source electrode 56 can be used as electrode pads for the source electrode 56.

[0139] (2) β-Ga ２ O ３ In the following, we will discuss the manufacturing method of β-Ga ２ O ３ An example of a method for manufacturing the β-Ga-based device 10C will be briefly described with reference to FIGS. 4A, 4B, 4E, 13, and 14. ２ O ３ The description of steps similar to those in the manufacturing method of the semiconductor device 10 will be omitted as appropriate.

[0140] β-Ga ２ O ３ The method for manufacturing the system device 10C includes a substrate preparation process, a metal layer formation process, an epitaxial growth process, a drain region / source region formation process, an insulating film formation process, an electrode formation process, a patterning process, and a dicing process.

[0141] In the substrate preparation step, a GaAs substrate having a first main surface 21 and a second main surface 22 opposite to the first main surface 21 is prepared. ２ O ３ A Ga-based substrate 2 is prepared (see FIG. 4A). ２ O ３ The β-Ga-based substrate 2 is ２ O ３ A wafer made of a substrate 20, ２ O ３ This is the wafer that will be the base substrate 2a.

[0142] In the metal layer forming step, Ga ２ O ３A metal layer 3 having a plurality of metal portions 31 and a plurality of openings 32 is formed on the first main surface 21 of the semiconductor substrate 2 (see FIG. 4B ). Each of the plurality of metal portions 31 becomes a metal portion 31a. The width of each of the plurality of metal portions 31 is the same as the width of the metal portion 31a in the second direction D22 (see FIGS. 13 and 14 ). Furthermore, the length of each of the plurality of metal portions 31 is longer than the length of the metal portion 31a in the first direction D21 (see FIG. 14 ).

[0143] In the epitaxial growth process, Ga ２ O ３ The β-Ga alloy covering the first main surface 21 of the base substrate 2 and the metal layer 3 ２ O ３ The layer 4 is formed by lateral overgrowth using mist CVD (see FIG. 4E). ２ O ３ Layer 4 is n-type β-Ga ２ O ３ layer, and β-Ga ２ O ３ It is the source of layer 4a. ２ O ３ Layer 4 is n-type β-Ga ２ O ３ The epitaxial wafer 1 is manufactured by performing the substrate preparation step, the metal layer formation step, and the epitaxial growth step. Note that in the epitaxial growth step, MBE or HVPE, for example, may be used instead of the mist CVD method.

[0144] In the process of forming the drain and source regions, for example, ion implantation technology, diffusion technology, etc. are used to implant β-Ga ２ O ３ A plurality of drain regions 51 (see FIG. 13) and a plurality of source regions 52 (see FIG. 13) are formed in layer 4 .

[0145] In the insulating film forming step, the gate insulating film 54 is formed by, for example, a CVD method or the like.

[0146] In the electrode formation step, a plurality of gate electrodes 57 are formed by vapor deposition or the like.

[0147] In the patterning process, for example, photolithography and etching techniques are used to pattern β-Ga.２ O ３ By patterning the layer 4, a part of each of the plurality of metal portions 31 and Ga ２ O ３ A portion of the first main surface 21 of the substrate 2 is exposed.

[0148] β-Ga ２ O ３ In the method for manufacturing the β-Ga semiconductor device 10C, a plurality of β-Ga semiconductors are fabricated by performing each step from the substrate preparation step to the patterning step. ２ O ３ A wafer including the system device 10C can be obtained.

[0149] β-Ga ２ O ３ In the method for manufacturing the semiconductor device 10C, a plurality of β-Ga ２ O ３ The wafer including the β-Ga diced semiconductor device 10C is cut by, for example, a dicing saw or a laser dicing device, thereby forming a plurality of β-Ga diced semiconductor devices. ２ O ３ A system device 10C can be obtained.

[0150] (3) Advantages of the β-Ga according to the third embodiment ２ O ３ The GaAs semiconductor device 10C is ２ O ３ a β-Ga-based substrate 2a, a metal layer 3a, and ２ O ３ The semiconductor device 5C includes a Ga layer 4a and a Ga ２ O ３ The metal substrate 2a has a first main surface 21a and a second main surface 22a opposite to the first main surface 21a. ２ O ３ It is formed on a part of the first main surface 21a of the β-Ga-based substrate 2a. ２ O ３ The layer 4a is Ga ２ O ３ The semiconductor element 5C covers the first main surface 21a of the β-GaAs substrate 2a and the metal layer 3a. ２ O ３ The metal layer 3a includes at least a part of the layer 4a. The material of the metal layer 3a is a noble metal or a high-melting-point metal. ２ O３ The thickness T12 of the layer 4a is Ga ２ O ３ It is thinner than the thickness T11 of the base substrate 2a.

[0151] β-Ga according to embodiment 3 ２ O ３ The system device 10C has the above-described configuration, and therefore, it is possible to improve the characteristics.

[0152] Here, the β-Ga according to embodiment 3 ２ O ３ In the semiconductor device 10C, the semiconductor element 5C is a MOSFET. The drain region 51, the source region 52, and the channel forming region 53 of the MOSFET are made of β-Ga ２ O ３ This allows the β-Ga ２ O ３ The system device 10C can improve the characteristics of the MOSFET that constitutes the semiconductor element 5C.

[0153] (Embodiment 4) Hereinafter, β-Ga according to embodiment 4 will be described. ２ O ３ A β-Ga GaN-based device 10D and a method for manufacturing the same will be described with reference to FIGS. ２ O ３ Regarding the β-Ga-based device 10D, ２ O ３ The same components as those in the system device 10 (see FIGS. 6 and 7) are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0154] (1) β-Ga ２ O ３ Hereinafter, the β-Ga-based device according to the fourth embodiment will be referred to as a β-Ga-based device. ２ O ３ The system device 10D will be described with reference to FIGS.

[0155] β-Ga according to embodiment 4 ２ O ３ The Ga-based device 10D is ２ O ３ a β-Ga-based substrate 2a, a metal layer 3a, and ２ O ３The semiconductor device includes a layer 4a and a semiconductor element 5D.

[0156] Ga ２ O ３ The substrate 2a has a first main surface 21a and a second main surface 22a opposite to the first main surface 21a.

[0157] Ga ２ O ３ The β-Ga-based substrate 2a is ２ O ３ The substrate 20a is β-Ga ２ O ３ The substrate 20a is semi-insulating β-Ga ２ O ３ The substrate is Ga ２ O ３ When viewed from the thickness direction D20 of the substrate 2a, Ga ２ O ３ The base substrate 2a has a rectangular shape.

[0158] The material of the metal layer 3a is a noble metal or a high-melting-point metal. For example, the material of the metal layer 3a is Pt or Au, but may be a noble metal other than Pt or Au. For example, the material of the metal layer 3a is Ta or W, but may be a high-melting-point metal other than Ta or W.

[0159] The metal layer 3a is Ga ２ O ３ It is formed on a part of the first main surface 21a of the base substrate 2a.

[0160] β-Ga ２ O ３ The layer 4a is Ga ２ O ３ The β-Ga GaN layer 2a covers a part of the first main surface 21a of the β-Ga GaN substrate 2a and a part of the metal layer 3a. ２ O ３ The layer 4a is Ga ２ O ３ The metal layer 3a is covered with the insulating film 211a. The insulating film 211a covers a part of each of the three portions 211a that are not covered with the metal layer 3a on the first main surface 21a of the base substrate 2a, and also covers a part of the metal layer 3a.

[0161] The semiconductor element 5D is a β-Ga ２ O ３The semiconductor element 5D includes at least a part of the layer 4a. The semiconductor element 5D will be described later.

[0162] β-Ga ２ O ３ In the GaAs system device 10D, the metal layer 3a includes two metal portions 31a and two metal portions 31b (see FIG. 16). Each of the two metal portions 31a and the two metal portions 31b is linear (long). One end of each of the two metal portions 31a is connected to one of the two metal portions 31b, and the other end of each of the two metal portions 31a is connected to the other metal portion 31b. The longitudinal direction of the two metal portions 31a is defined as a first direction D21 (see FIG. 16), and the GaAs system device 10D includes two metal portions 31a and two metal portions 31b (see FIG. 16). ２ O ３ In the following description, a direction perpendicular to the thickness direction D20 of the base substrate 2a and the first direction D21 is defined as a second direction D22.

[0163] 15, the semiconductor element 5D is a MOSFET, and includes a drain region 51, a source region 52, a channel formation region 53, a gate insulating film 54, a drain electrode 55, a source electrode 56, and a gate electrode 57. The drain region 51, the source region 52, and the channel formation region 53 are made of β-Ga ２ O ３ It is formed in layer 4a.

[0164] β-Ga ２ O ３ In the GaAs device 10D, ２ O ３ The base substrate 2a is a semi-insulating β-Ga ２ O ３ It is a circuit board.

[0165] β-Ga ２ O ３ In the semiconductor device 10D, β-Ga ２ O ３ The layer 4a is Ga ２ O ３ The semi-insulating β-Ga ２ O ３ layer 43a and a semi-insulating β-Ga ２ O ３ n-type β-Ga formed on the layer 43a ２ O３ and layer 44a.

[0166] The drain region 51 is made of n-type β-Ga ２ O ３ n formed in layer 44a ＋ β-Ga ２ O ３ It consists of n-type β-Ga ２ O ３ The n-type layer 44a and the n-type layer 51 that constitute the drain region 51 ＋ β-Ga ２ O ３ Each of the regions contains an n-type impurity (e.g., Sn, Si, or Ge). The drain region 51 contains Ga ２ O ３ In the thickness direction D20 of the base substrate 2a, the metal portion 31a overlaps with a part of one of the two metal portions 31a.

[0167] The source region 52 is n-type β-Ga ２ O ３ n formed in layer 44a ＋ β-Ga ２ O ３ It consists of n-type β-Ga ２ O ３ The n-type layer 44a and the n-type layer 52 that constitute the source region 52 ＋ β-Ga ２ O ３ Each of the regions contains an n-type impurity (e.g., Sn, Si, or Ge). ２ O ３ In the thickness direction D20 of the base substrate 2a, the metal portion 31a overlaps with a part of the remaining one of the two metal portions 31a.

[0168] The channel forming region 53 is made of n-type β-Ga ２ O ３ It is formed between the drain region 51 and the source region 52 in the layer 44a.

[0169] The gate insulating film 54 is made of n-type β-Ga ２ O ３The gate insulating film 54 is formed on the layer 4a, the drain region 51, and the source region 52. The material of the gate insulating film 54 includes, for example, silicon oxide, hafnium oxide, aluminum nitride, silicon nitride, or aluminum oxide.

[0170] The gate electrode 57 is formed on the gate insulating film 54. The gate electrode 57 is made of Ga ２ O ３ In a plan view in the thickness direction D20 of the base substrate 2a, the gate electrode 57 is located between the drain region 51 and the source region 52. The material of the gate electrode 57 is, for example, Au or Pt, but may be a metal other than Au or Pt, or may be an alloy.

[0171] The drain electrode 55 is formed on the drain region 51. The drain electrode 55 is electrically connected to the drain region 51.

[0172] The source electrode 56 is formed on the source region 52. The source electrode 56 is electrically connected to the source region 52.

[0173] The metal layer 3a is β-Ga ２ O ３ It has an exposed portion that is not covered by the layer 4a. ２ O ３ In the semiconductor device 10D, β-Ga ２ O ３ The layer 4a is formed in a shape that exposes the two metal portions 31b. ２ O ３ When viewed from the thickness direction D20 of the substrate 2a, ２ O ３ The layer 4a has a rectangular shape. ２ O ３ The length of the layer 4a is Ga ２ O ３ The length of the β-Ga substrate 2a is the same as the length of the β-Ga ２ O ３ The length of the layer 4a is Ga ２ O ３ It is shorter than the length of the base substrate 2a and shorter than the length of each metal portion 31a.

[0174] β-Ga ２ O３ The GaAs system device 10D further includes two heat sinks 6. The two heat sinks 6 are disposed on the exposed portions of the metal layer 3a. More specifically, the two heat sinks 6 correspond one-to-one to the two metal portions 31b of the metal layer 3a and are disposed on the corresponding metal portions 31b. Each of the two heat sinks 6 is plate-shaped. ２ O ３ When viewed from above in the thickness direction D20 of the base substrate 2a, each of the two heat sinks 6 has a rectangular shape with its longitudinal direction aligned in the second direction D22. The material of the two heat sinks 6 includes, for example, aluminum, copper, an aluminum alloy, or a copper alloy.

[0175] (2) β-Ga ２ O ３ In the following, we will discuss the manufacturing method of β-Ga ２ O ３ An example of a method for manufacturing the β-Ga-based device 10D will be briefly described with reference to FIGS. 4A, 15, and 16. ２ O ３ The description of steps similar to those in the manufacturing method of the semiconductor device 10 will be omitted as appropriate.

[0176] β-Ga ２ O ３ The method for manufacturing the system device 10D includes a substrate preparation process, a metal layer formation process, an epitaxial growth process, a drain region / source region formation process, an insulating film formation process, an electrode formation process, a patterning process, a dicing process, and a bonding process.

[0177] In the substrate preparation step, a GaAs substrate having a first main surface 21 and a second main surface 22 opposite to the first main surface 21 is prepared. ２ O ３ A Ga-based substrate 2 is prepared (see FIG. 4A). ２ O ３ The β-Ga-based substrate 2 is ２ O ３ A wafer made of a substrate 20, ２ O ３ This is the wafer that will be the base substrate 2a.

[0178] In the metal layer forming step, Ga ２ O ３A metal layer 3 that will become a metal layer 3 a is formed on the first main surface 21 of the base substrate 2 .

[0179] In the epitaxial growth process, Ga ２ O ３ The semi-insulating β-Ga alloy covers the first main surface 21 of the base substrate 2 and the metal layer 3. ２ O ３ The layer is formed by selective lateral overgrowth using mist CVD, and a semi-insulating β-Ga ２ O ３ n-type β-Ga covering layer ２ O ３ The semi-insulating β-Ga layer is formed by mist CVD. ２ O ３ The layer is semi-insulating β-Ga ２ O ３ This is the source of the layer 43a. ２ O ３ The layer is n-type β-Ga ２ O ３ This is the source of the layer 44a. In the epitaxial growth step, for example, MBE or HVPE may be used instead of the mist CVD method.

[0180] In the process of forming the drain and source regions, for example, ion implantation technology, diffusion technology, etc. are used to implant n-type β-Ga ２ O ３ A plurality of drain regions 51 (see FIG. 15) and a plurality of source regions 52 (see FIG. 15) are formed in the layer.

[0181] In the insulating film forming step, a plurality of gate insulating films 54 are formed by, for example, a CVD method or the like.

[0182] In the electrode formation step, a plurality of drain electrodes 55, a plurality of source electrodes 56, and a plurality of gate electrodes 57 are formed by evaporation or the like.

[0183] In the patterning process, for example, photolithography and etching techniques are used to pattern β-Ga. ２ O ３ By patterning the layer, a part of the metal layer 3 and the Ga ２ O ３ A portion of the first main surface 21 of the substrate 2 is exposed.

[0184] β-Ga ２ O ３ In the method for manufacturing the semiconductor device 10D, a dicing step is performed after the patterning step, and then two heat sinks 6 are bonded to the exposed portions of the metal layer 3a.

[0185] (3) Advantages of the β-Ga according to the fourth embodiment ２ O ３ The GaAs device 10D is ２ O ３ a β-Ga-based substrate 2a, a metal layer 3a, and ２ O ３ The semiconductor device 5D includes a Ga layer 4a and a Ga ２ O ３ The metal substrate 2a has a first main surface 21a and a second main surface 22a opposite to the first main surface 21a. ２ O ３ It is formed on a part of the first main surface 21a of the β-Ga-based substrate 2a. ２ O ３ The layer 4a is Ga ２ O ３ The semiconductor element 5D covers the first main surface 21a of the β-Ga GaN substrate 2a and the metal layer 3a. ２ O ３ The metal layer 3a includes at least a part of the layer 4a. The material of the metal layer 3a is a noble metal or a high-melting-point metal. ２ O ３ The thickness T12 of the layer 4a is Ga ２ O ３ It is thinner than the thickness T11 of the base substrate 2a.

[0186] β-Ga according to embodiment 4 ２ O ３ The system device 10D has the above-described configuration, and therefore, it is possible to improve the characteristics.

[0187] Here, the β-Ga according to embodiment 4 ２ O ３ In the semiconductor device 10D, the semiconductor element 5D is a MOSFET. The drain region 51, the source region 52, and the channel forming region 53 of the MOSFET are made of β-Ga ２ O ３ The β-Ga according to the fourth embodiment is formed in the layer 4a. ２ O ３The system device 10D includes a heat sink 6 placed on the exposed portion of the metal layer 3a, which enables improved heat dissipation and improves the characteristics of the MOSFET that constitutes the semiconductor element 5D.

[0188] (Embodiment 5) Hereinafter, β-Ga according to embodiment 5 will be described. ２ O ３ The β-Ga GaN-based device 10E according to the fifth embodiment will be described with reference to FIG. ２ O ３ Regarding the β-Ga-based device 10E, ２ O ３ The same components as those in the system device 10B (see FIGS. 9 and 10) are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0189] β-Ga according to embodiment 5 ２ O ３ The β-GaAs semiconductor device 10E is similar to the β-GaAs semiconductor device 10A according to the second embodiment in that it includes two semiconductor elements 5B and further includes a heat dissipation layer 7 and a heat sink 8. ２ O ３ This is different from the system device 10B.

[0190] The heat dissipation layer 7 is formed on the semiconductor element 5B and has electrical insulation properties. The heat dissipation layer 7 is formed on a part of the second metal electrode layer 59 of each of the two semiconductor elements 5B and on the β-Ga ２ O ３ The heat dissipation layer 7 covers the layer 4a. The heat dissipation layer 7 contains an AlN filler. The heat dissipation layer 7 is formed, for example, by applying a material containing the AlN filler by spin coating or the like and then curing it.

[0191] The heat sink 8 is disposed on the heat dissipation layer 7. The heat sink 8 is plate-shaped. ２ O ３ In a plan view from the thickness direction D20 of the base substrate 2a, the heat sink 8 has a rectangular shape with the longitudinal direction aligned with the second direction D22. The material of the heat sink 8 includes, for example, aluminum, copper, an aluminum alloy, or a copper alloy.

[0192] β-Ga according to embodiment 5 ２ O ３The heat dissipation layer 7 and the heat sink 8 of the semiconductor device 10E can improve heat dissipation.

[0193] (Embodiment 6) Hereinafter, β-Ga according to embodiment 6 will be described. ２ O ３ The β-Ga GaN-based device 10F according to the sixth embodiment will be described with reference to FIG. ２ O ３ Regarding the β-Ga-based device 10F, ２ O ３ The same components as those in the system device 10D (see FIGS. 15 and 16) are denoted by the same reference numerals and the description thereof will be omitted as appropriate.

[0194] β-Ga according to embodiment 6 ２ O ３ The β-Ga-based device 10F is similar to the β-Ga-based device 10A according to the fourth embodiment in that it further includes a heat dissipation layer 7 and a heat sink 8. ２ O ３ This is different from the system device 10D.

[0195] The heat dissipation layer 7 is formed on the semiconductor element 5D and has electrical insulation properties. The heat dissipation layer 7 covers a portion of each of the drain electrode 55, the source electrode 56, and the gate electrode 57 of the semiconductor element 5D. The heat dissipation layer 7 contains an AlN filler. The heat dissipation layer 7 is formed, for example, by applying a material containing the AlN filler by spin coating or the like and then curing it.

[0196] The heat sink 8 is disposed on the heat dissipation layer 7. The heat sink 8 is plate-shaped. ２ O ３ In a plan view from the thickness direction D20 of the base substrate 2a, the heat sink 8 has a rectangular shape with the longitudinal direction aligned with the second direction D22. The material of the heat sink 8 includes, for example, aluminum, copper, an aluminum alloy, or a copper alloy.

[0197] β-Ga according to embodiment 6 ２ O ３ The system device 10F includes the heat dissipation layer 7 and the heat sink 8, thereby making it possible to improve heat dissipation.

[0198] (Embodiment 7) Hereinafter, β-Ga according to embodiment 7 will be described. ２ O ３ The β-Ga GaN device 10G according to the seventh embodiment will be described with reference to FIGS. ２ O ３ Regarding the β-Ga-based device 10G, ２ O ３ The same components as those in the system device 10C (see FIGS. 13 and 14) are denoted by the same reference numerals and the description thereof will be omitted as appropriate.

[0199] β-Ga according to embodiment 7 ２ O ３ The β-Ga-based device 10G is the same as the β-Ga-based device 10 of the third embodiment in that it includes a semiconductor element 5G instead of the semiconductor element 5C of the third embodiment. ２ O ３ This is different from the system device 10C.

[0200] β-Ga according to embodiment 7 ２ O ３ The β-Ga-based device 10G is similar to the β-Ga-based device 10G according to the third embodiment in that the metal layer 3a includes three metal portions 31a arranged in the second direction D22, and the central metal portion 31a in the second direction D22 of the three metal portions 31a constitutes the gate electrode 57. ２ O ３ This is different from the system device 10C.

[0201] In addition, β-Ga according to embodiment 7 ２ O ３ The system device 10G includes a gate insulating film 54 covering the gate electrode 57. The material of the gate insulating film 54 includes, for example, silicon oxide, hafnium oxide, aluminum nitride, silicon nitride, or aluminum oxide.

[0202] β-Ga according to embodiment 7 ２ O ３ In the β-Ga system device 10G, ２ O ３ The layer 4 a also covers the gate insulating film 54 .

[0203] In addition, β-Ga according to embodiment 7 ２ O ３The β-Ga-based device 10G is similar to the β-Ga-based device 10A according to the third embodiment in that it further includes a heat dissipation layer 7 and a heat sink 8. ２ O ３ 20, the heat dissipation layer 7 and the heat sink 8 are omitted from the illustration.

[0204] The heat dissipation layer 7 is formed on the semiconductor element 5G and has electrical insulation properties. The heat dissipation layer 7 is formed on the drain region 51, the source region 52, the channel formation region 53, and the β-Ga ２ O ３ The heat dissipation layer 7 covers the layer 4a. The heat dissipation layer 7 contains an AlN filler. The heat dissipation layer 7 is formed, for example, by applying a material containing the AlN filler by spin coating or the like and then curing it.

[0205] The heat sink 8 is disposed on the heat dissipation layer 7. The heat sink 8 is plate-shaped. ２ O ３ In a plan view from the thickness direction D20 of the base substrate 2a, the heat sink 8 has a rectangular shape with the longitudinal direction aligned with the second direction D22. The material of the heat sink 8 includes, for example, aluminum, copper, an aluminum alloy, or a copper alloy.

[0206] β-Ga according to embodiment 7 ２ O ３ The system device 10G is provided with the heat dissipation layer 7 and the heat sink 8, thereby making it possible to improve heat dissipation.

[0207] (Embodiment 8) Hereinafter, β-Ga according to embodiment 8 will be described. ２ O ３ The β-Ga GaN-based device 10H and a method for manufacturing the same will be described with reference to FIGS. 21, 22, 23A, 23B, and 23C. ２ O ３ Regarding the β-Ga-based device 10H, ２ O ３ The same components as those in the system device 10B (see FIGS. 9 and 10) are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0208] (1) β-Ga ２ O ３Hereinafter, the β-Ga-based device according to the eighth embodiment will be referred to as a β-Ga-based device. ２ O ３ The system device 10H will be described with reference to FIG.

[0209] β-Ga according to embodiment 8 ２ O ３ The β-Ga-based device 10H is a β-Ga-based device according to the second embodiment. ２ O ３ Ga of the system device 10B ２ O ３ The β-GaAs semiconductor device according to the second embodiment has a heat sink 9 instead of the β-GaAs semiconductor substrate 2a. ２ O ３ This is different from the system device 10B.

[0210] In addition, β-Ga according to embodiment 8 ２ O ３ In the semiconductor device 10H, the shape of the metal layer 3a is the same as that of the β-Ga ２ O ３ The shape of the metal layer 3a of the semiconductor device 10B is different from that of the semiconductor device 10B.

[0211] The heat sink 9 is plate-shaped. ２ O ３ In a plan view from the thickness direction D20 of the base substrate 2a, the heat sink 9 has a rectangular shape with the longitudinal direction aligned with the second direction D22. The material of the heat sink 9 includes, for example, aluminum, copper, an aluminum alloy, or a copper alloy.

[0212] (2) β-Ga ２ O ３ β-Ga-based device manufacturing method according to embodiment 8 ２ O ３ A method for manufacturing the semiconductor device 10H will be described with reference to FIGS. 22, 23A, 23B, and 23C.

[0213] β-Ga according to embodiment 8 ２ O ３ The method for manufacturing the β-Ga GaN-based device 10H is the same as that of the second embodiment. ２ O ３ Similar to the method for manufacturing the semiconductor device 10B, the method includes a substrate preparation step, a metal layer formation step, an epitaxial growth step, an electrode layer formation step, a patterning step, and a dicing step.

[0214] β-Ga according to embodiment 8 ２ O ３ The method for manufacturing the β-Ga GaN-based device 10H is different from the method for manufacturing the β-Ga GaN-based device 10H according to the second embodiment in that it further includes a laser lift-off step and a bonding step. ２ O ３ This differs from the manufacturing method of the semiconductor device 10B in that the laser lift-off process and the bonding process are performed, for example, between the patterning process and the dicing process.

[0215] The substrate preparation step, metal layer formation step, epitaxial growth step, electrode layer formation step, and patterning step are substantially the same as those in the second embodiment, and therefore, the description thereof will be omitted as appropriate. In the metal layer formation step, as shown in FIG. 22, a metal layer 3 having a plurality of openings 32 arranged in a two-dimensional array is formed by etching a Ga ２ O ３ The metal layer 3 is formed on the substrate 2 (see FIG. 4A). The metal layer 3 is the source of the metal layer 3a. Each of the plurality of openings 32 is square. The metal layer 3 is in a lattice pattern.

[0216] In the epitaxial growth process, Ga ２ O ３ The first main surface 21 of the substrate 2 and the metal layer 3 are covered with ＋ β-Ga ２ O ３ The layer 41 (see FIG. 11) is formed by selective lateral overgrowth using mist CVD. ＋ β-Ga ２ O ３ n-type β-Ga covering layer 41 ２ O ３ The layer 42 (see FIG. 11) is formed by mist CVD. ＋ β-Ga ２ O ３ Layer 41 is n ＋ β-Ga ２ O ３ It is the source of the layer 41a. n-type β-Ga ２ O ３ Layer 42 is n-type β-Ga ２ O ３The epitaxial wafer 1B (see FIG. 11) is manufactured by performing the substrate preparation step, the metal layer formation step, and the epitaxial growth step. Note that in the epitaxial growth step, MBE or HVPE, for example, may be used instead of the mist CVD method. In this embodiment, n ＋ β-Ga ２ O ３ Layer 41 and n-type β-Ga ２ O ３ Layer 42 and β-Ga ２ O ３ It constitutes layer 4.

[0217] In the electrode layer forming step, a metal electrode layer 590 (see FIG. 23A) is formed by vapor deposition or the like. ２ O ３ A metal electrode layer 590 is formed on layer 4. The metal electrode layer 590 will become the second metal electrode layer 59.

[0218] In the patterning process, for example, photolithography and etching techniques are used to pattern β-Ga. ２ O ３ By patterning the layer 4, a part of the metal layer 3 and the Ga ２ O ３ A portion of the first main surface 21 of the substrate 2 is exposed.

[0219] In the laser lift-off process, Ga ２ O ３ Laser light LB1 (see FIG. 23A) was irradiated from the second main surface 22 side of the substrate 2 to form Ga ２ O ３ The β-Ga substrate 2 is ２ O ３ Peel off layer 4 (see Figure 23B).

[0220] In the bonding step, the exposed surface of the metal layer 3 and the β-Ga ２ O ３ A heat sink 9 is bonded to the exposed surface of layer 4 (see Figure 23C).

[0221] β-Ga according to embodiment 8 ２ O ３In the method for manufacturing the β-Ga-based device 10H, a dicing process is performed after the bonding process, thereby forming a plurality of β-Ga ２ O ３ A system device 10H is obtained.

[0222] β-Ga according to embodiment 8 ２ O ３ According to the method for manufacturing the β-Ga semiconductor device 10H, ２ O ３ This makes it possible to improve the heat dissipation of the system device 10H.

[0223] β-Ga according to embodiment 8 ２ O ３ In the metal layer 3 formed in the method for manufacturing the semiconductor device 10H, each of the openings 32 arranged in a two-dimensional array may have a circular shape as shown in FIG.

[0224] (Modifications) Embodiments 1 to 8 are merely examples of various embodiments of the present disclosure. Various modifications can be made to Embodiments 1 to 8 depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0225] For example, in the epitaxial wafer 1, 1A, a plurality of openings 32 in the metal layer 3 may be arranged in a two-dimensional array as shown in FIG. ２ O ３ Ga is deposited on the second main surfaces 22 and 22A of the substrates 2 and 2A. ２ O ３ When polishing the Ga-based substrates 2 and 2A, ２ O ３ This makes it easier to make the substrates 2 and 2A thinner.

[0226] In addition, β-Ga ２ O ３ In the GaAs devices 10, 10D, 10E, and 10F, the metal layer 3 may have a plurality of openings 32 arranged in a two-dimensional array as shown in FIG. ２ O ３ This makes it easier to make the base substrate 2a thinner, and improves heat dissipation.

[0227] Also, Ga ２ O ３ The β-Ga-based substrate 2 is２ O ３ Not limited to the substrate 20, for example, β-(Ga ｘ , Al １－ｘ ) ２ O ３ The substrate (where 0<x<1) may also be Ga ２ O ３ The β-Ga-based substrate 2 is ２ O ３ The substrate 20 is not limited to the above. For example, α-Ga ２ O ３ Substrate or α-(Ga ｘ , Al １－ｘ ) ２ O ３ The substrate (where 0<x<1) may also be Ga ２ O ３ The base substrate 2 may contain impurities such as Fe or Al.

[0228] In addition, β-Ga ２ O ３ In the semiconductor device 10, the semiconductor element 5 is a MESFET, but ２ O ３ Instead of the layer 4a, β-Ga ２ O ３ layer and β-Ga ２ O ３ The β-(Ga ｘ , Al １－ｘ ) ２ O ３ A structure including a layer (where 0<x<1) may be adopted, and a HEMT (High Electron Mobility Transistor) may be formed as the semiconductor element 5 instead of the MESFET.

[0229] β-Ga ２ O ３ The transistors constituting the semiconductor elements of the system device are not limited to MESFETs or MOSFETs, but may be, for example, HEMTs.

[0230] In addition, β-Ga ２ O ３ The FET that constitutes the semiconductor element of the system device is β-Ga ２ O ３This is not limited to lateral FETs in which the drain and source electrodes are formed on a layer, but also to FETs in which the drain and source electrodes are formed on a β-Ga ２ O ３ The FETs may be vertical FETs arranged so as to overlap in the thickness direction of the layers.

[0231] In addition, β-Ga ２ O ３ In the method for manufacturing the Ga-based device 10H, ２ O ３ Instead of the Ga-based substrate 2, ２ O ３ A substrate 2A may also be used.

[0232] (Aspects) The following aspects are disclosed in this specification.

[0233] The epitaxial wafer (1; 1A) according to the first aspect is Ga ２ O ３ A β-Ga-based substrate (2; 2A), a metal layer (3), and ２ O ３ and a layer (4). ２ O ３ The metal substrate (2; 2A) has a first main surface (21; 21A) and a second main surface (22; 22A) opposite to the first main surface (21; 21A). ２ O ３ The metal layer (3) is formed on the first main surface (21; 21A) of the β-Ga-based substrate (2; 2A). The metal layer (3) has a plurality of openings (32). ２ O ３ Layer (4) is Ga ２ O ３ The first main surface (21; 21A) of the β-Ga-based substrate (2; 2A) and the metal layer (3) are covered with the metal layer (3). The material of the metal layer (3) is a noble metal or a high-melting-point metal. ２ O ３ The thickness (T2) of the layer (4) is Ga ２ O ３ It is thinner than the thickness (T1) of the base substrate (2; 2A).

[0234] According to this aspect, β-Ga ２ O ３ This makes it possible to improve the characteristics of the system device.

[0235] In the epitaxial wafer (1; 1A) according to the second aspect, in the first aspect, the metal layer (3) includes a plurality of metal portions (31). Each of the plurality of metal portions (31) is linear. In the metal layer (3), Ga ２ O ３ In a plan view in the thickness direction (D10) of the base substrate (2; 2A), a plurality of metal portions (31) and a plurality of openings (32) are arranged alternately.

[0236] According to this aspect, Ga ２ O ３ Ga is deposited on the second main surface (22; 22A) of the Ga-based substrate (2; 2A). ２ O ３ When polishing the Ga-based substrate (2; 2A), ２ O ３ This makes it easier to make the substrate (2; 2A) thinner.

[0237] The epitaxial wafer (1; 1A) according to the third aspect is based on the first aspect, in which a plurality of openings (32) are arranged in a two-dimensional array in the metal layer (3).

[0238] According to this aspect, Ga ２ O ３ Ga is deposited on the second main surface (22; 22A) of the Ga-based substrate (2; 2A). ２ O ３ When polishing the Ga-based substrate (2; 2A), ２ O ３ This makes it easier to make the substrate (2; 2A) thinner.

[0239] In the epitaxial wafer (1) according to the fourth aspect, in any one of the first to third aspects, Ga ２ O ３ The β-Ga-based substrate (2) ２ O ３ A substrate (20).

[0240] According to this aspect, Ga ２ O ３ This makes it easier to prepare the substrate (2).

[0241] In the epitaxial wafer (1A) according to the fifth aspect, in any one of the first to third aspects, Ga ２ O ３The β-Ga-based substrate (2A) is a sapphire substrate (24) and a β-Ga-based GaN layer (25) formed on the sapphire substrate (24). ２ O ３ and a layer (25). ２ O ３ In the β-Ga-based substrate (2A), ２ O ３ The surface (251) of the layer (25) is Ga ２ O ３ It constitutes the first main surface (21A) of the base substrate (2A).

[0242] According to this aspect, it is possible to reduce costs.

[0243] β-Ga according to the sixth aspect ２ O ３ The system devices (10; 10B; 10C; 10D; 10E; 10F; 10G) are Ga ２ O ３ A β-Ga-based substrate (2a), a metal layer (3a), and ２ O ３ The semiconductor device includes a layer (4a) and semiconductor elements (5; 5B; 5C; 5D; 5G). ２ O ３ The metal substrate (2a) has a first main surface (21a) and a second main surface (22a) opposite to the first main surface (21a). ２ O ３ It is formed on a part of the first main surface (21a) of the β-Ga-based substrate (2a). ２ O ３ The layer (4a) is Ga ２ O ３ The semiconductor elements (5; 5B; 5C; 5D; 5G) cover the first main surface (21a) of the β-Ga-based substrate (2a) and the metal layer (3a). ２ O ３ The material of the metal layer (3a) is a noble metal or a high-melting-point metal. ２ O ３ The thickness (T12) of the layer (4a) is Ga ２ O ３ It is thinner than the thickness (T11) of the base substrate (2a).

[0244] According to this aspect, β-Ga ２ O ３It is possible to improve the characteristics of the system devices (10; 10B; 10C; 10D; 10E; 10F; 10G).

[0245] β-Ga according to the seventh aspect ２ O ３ In the sixth aspect of the semiconductor device (10; 10C; 10D; 10E; 10F; 10G), the metal layer (3a) includes a plurality of metal portions (31a). Each of the plurality of metal portions (31a) is linear. In the metal layer (3a), Ga ２ O ３ In a plan view from the thickness direction (D20) of the base substrate (2a), the plurality of metal portions (31a) are arranged spaced apart in a direction perpendicular to each other.

[0246] According to this aspect, it is possible to improve the heat dissipation performance.

[0247] β-Ga according to the eighth aspect ２ O ３ In a seventh aspect of the semiconductor device (10), the semiconductor element (5) is a MESFET including a drain region (51), a source region (52), a channel-forming region (53), a drain electrode (55), a source electrode (56), and a gate electrode (57). The drain region (51), the source region (52), and the channel-forming region (53) are made of β-Ga ２ O ３ It is formed in the layer (4a). ２ O ３ In a plan view in the thickness direction (D20) of the base substrate (2a), the channel forming region (53) overlaps one of the plurality of metal portions (31a).

[0248] According to this embodiment, it is possible to improve the characteristics of the MESFET that constitutes the semiconductor element (5).

[0249] β-Ga according to the ninth aspect ２ O ３ In the eighth aspect of the GaAs-based device (10), ２ O ３ The base substrate (2a) is a semi-insulating β-Ga ２ O ３ The substrate is β-Ga ２ O ３The layer (4a) is an n-type β-Ga ２ O ３ The drain region (51) is an n-type β-Ga ２ O ３ n formed in the layer (4a) ＋ β-Ga ２ O ３ The drain region (51) is comb-shaped. The source region (52) is n-type β-Ga ２ O ３ n formed in the layer (4a) ＋ β-Ga ２ O ３ The source region (52) is comb-shaped. The drain electrode (55) is formed on the drain region (51). The drain electrode (55) is made of Ga ２ O ３ The source electrode (56) is formed on the source region (52) and has a comb shape overlapping the drain region (51) when viewed from above in the thickness direction (D20) of the substrate (2a). ２ O ３ The gate electrode (57) has a comb shape overlapping the source region (52) when viewed from the thickness direction (D20) of the substrate (2a). ２ O ３ The gate electrode (57) is formed on the layer (4a). ２ O ３ The semiconductor substrate (2a) has a comb-like shape in a plan view in the thickness direction (D20) thereof. The drain electrode (55) has a drain electrode comb bone (551) and a plurality of drain electrode comb teeth (552) extending from the drain electrode comb bone (551). The source electrode (56) has a source electrode comb bone (561) and a plurality of source electrode comb teeth (562) extending from the source electrode comb bone (561). The gate electrode (57) has a gate electrode comb bone (571) and a plurality of gate electrode comb teeth (572) extending from the gate electrode comb bone (571). The drain electrode comb bone (551) and the source electrode comb bone (561) face each other in a first direction (D21). The plurality of drain electrode comb teeth (552), the plurality of gate electrode comb teeth (572), and the plurality of source electrode comb teeth (562) are Ga. ２ O３ The Ga atoms are aligned in the thickness direction (D20) of the substrate (2a) and in a second direction (D22) perpendicular to the first direction (D21). ２ O ３ In a plan view in the thickness direction (D20) of the base substrate (2a), each of the plurality of gate electrode comb-tooth portions (572) overlaps one of the plurality of metal portions (31a).

[0250] According to this aspect, it is possible to improve the stability of the operation of the MESFET constituting the semiconductor element (5), and also to achieve a high breakdown voltage.

[0251] β-Ga according to the tenth aspect ２ O ３ In the ninth aspect of the semiconductor device (10), each of the plurality of gate electrode comb teeth (572) is Ga ２ O ３ The metal portion (31a) is offset in the second direction (D22) so as not to overlap the center of the metal portion (31a) in the second direction (D22) when viewed in a plan view from the thickness direction (D20) of the base substrate (2a).

[0252] According to this embodiment, it is possible to further improve the characteristics of the semiconductor element (5).

[0253] β-Ga according to the eleventh aspect ２ O ３ In the sixth embodiment of the system device (10; 10D; 10E; 10F), the metal layer (3) has a plurality of openings (32) arranged in a two-dimensional array.

[0254] According to this aspect, Ga ２ O ３ This makes it easier to make the substrate (2a) thinner, and improves heat dissipation.

[0255] β-Ga according to the twelfth aspect ２ O ３ In the Ga system device (10B), in the sixth aspect, the semiconductor element (5B) is a Schottky barrier diode. ２ O ３ The base substrate (2a) is a semi-insulating β-Ga ２ O ３The substrate is β-Ga ２ O ３ The layer (4a) is Ga ２ O ３ The first main surface (21a) of the substrate (2a) and the metal layer (3a) are covered with ＋ β-Ga ２ O ３ Layer (41a) and n ＋ β-Ga ２ O ３ n-type β-Ga formed on the layer (41a) ２ O ３ layer (42a). ＋ β-Ga ２ O ３ The layer (41a) is in ohmic contact with the metal layer (3a). The semiconductor element (5B) has a first metal electrode layer (58) made of the metal layer (3a) and an n ＋ β-Ga ２ O ３ Layer (41a) and n-type β-Ga ２ O ３ The second metal electrode layer (59) is made of n-type β-Ga ２ O ３ The n-type β-Ga ２ O ３ In the semiconductor element (5B), Ga is in Schottky contact with the layer (42a). ２ O ３ In a plan view in the thickness direction (D20) of the semiconductor substrate (2a), at least a part of the second metal electrode layer (59) and at least a part of the first metal electrode layer (58) overlap. In the semiconductor element (5B), the second metal electrode layer (59) constitutes an anode electrode, and ＋ β-Ga ２ O ３ The layer (41) and the first metal electrode layer (58) constitute the cathode electrode.

[0256] According to this aspect, it is possible to improve the characteristics of the Schottky barrier diode that constitutes the semiconductor element (5B).

[0257] β-Ga according to the thirteenth aspect ２ O ３In the seventh aspect of the semiconductor device (10C; 10D; 10F; 10G), the semiconductor element (5C; 5D; 5G) is a MOSFET including a drain region (51), a source region (52), a channel-forming region (53), a gate insulating film (54), a drain electrode (55), a source electrode (56), and a gate electrode (57). The drain region (51), the source region (52), and the channel-forming region (53) are made of β-Ga ２ O ３ It is formed in layer (4a).

[0258] According to this aspect, it is possible to improve the characteristics of the MOSFET that constitutes the semiconductor element (5C; 5D; 5G).

[0259] β-Ga according to the fourteenth aspect ２ O ３ In the thirteenth aspect of the Ga-based device (10C), ２ O ３ The base substrate (2a) is a semi-insulating β-Ga ２ O ３ The substrate is β-Ga ２ O ３ The layer (4a) is n-type β-Ga ２ O ３ The plurality of metal portions (31a) include a first metal portion (311) and a second metal portion (312) adjacent to each other in the direction in which the plurality of metal portions (31a) are arranged. The drain region (51) is a β-Ga ２ O ３ n formed on the first metal portion (311) in the layer (4a) ＋ β-Ga ２ O ３ The source region (52) is made of β-Ga ２ O ３ n formed on the second metal portion (312) in the layer (4a) ＋ β-Ga ２ O ３ The first metal portion (311) constitutes the drain electrode (55). The second metal portion (312) constitutes the source electrode (56). The gate insulating film (54) is made of β-Ga ２ O ３The gate electrode (57) is formed on the gate insulating film (54). The gate electrode (57) is made of Ga ２ O ３ In plan view from the thickness direction (D20) of the substrate (2a), the β-Ga GaN layer is located between the drain region (51) and the source region (52). ２ O ３ The layer (4a) is formed in a shape that exposes a part of the first metal portion (311) and a part of the second metal portion (312).

[0260] β-Ga according to the fifteenth aspect ２ O ３ In the thirteenth aspect of the β-Ga system device (10D), ２ O ３ The layer (4a) is a semi-insulating β-GaAs layer in contact with the metal layer (3a). ２ O ３ layer (43a) and a semi-insulating β-Ga ２ O ３ n-type β-Ga formed on the layer (43a) ２ O ３ The drain region (51) includes an n-type β-Ga ２ O ３ n formed in layer (44a) ＋ β-Ga ２ O ３ The source region (52) is made of n-type β-Ga ２ O ３ n formed in layer (44a) ＋ β-Ga ２ O ３ The gate insulating film (54) is made of n-type β-Ga ２ O ３ The gate electrode (57) is formed on the gate insulating film (54). The gate electrode (57) is made of Ga ２ O ３ In a plan view in the thickness direction (D20) of the substrate (2a), the drain electrode (55) is located between the drain region (51) and the source region (52). The drain electrode (55) is formed on the drain region (51). The source electrode (56) is formed on the source region (52).

[0261] β-Ga according to the sixteenth aspect ２ O ３ In a fifteenth aspect, the semiconductor device (10D) further comprises a heat sink (6). ２ O ３ The metal layer (3a) has an exposed portion that is not covered by the layer (4a). A heat sink (6) is disposed on the exposed portion of the metal layer (3a).

[0262] According to this aspect, it is possible to improve the heat dissipation performance.

[0263] β-Ga according to the seventeenth aspect ２ O ３ In a sixth aspect, the semiconductor device (10E; 10F; 10G) further comprises a heat dissipation layer (7) and a heat sink (8). The heat dissipation layer (7) is formed on the semiconductor element (5B; 5D; 5G) and has electrical insulation properties. The heat sink (8) is disposed on the heat dissipation layer (7). The heat dissipation layer (7) contains an AlN filler.

[0264] According to this aspect, it is possible to improve the heat dissipation performance.

[0265] β-Ga according to the eighteenth aspect ２ O ３ The method for manufacturing the GaAs / GaAs-based devices (10; 10B; 10C; 10D; 10E; 10F; 10G; 10H) includes a substrate preparation step, a metal layer formation step, and an epitaxial growth step. In the substrate preparation step, a GaAs / GaAs-based device having a first main surface (21) and a second main surface (22) opposite to the first main surface (21) is prepared. ２ O ３ In the metal layer forming step, a Ga-based substrate (2; 2A) is prepared. ２ O ３ A metal layer (3) having a plurality of openings (32) is formed on a first main surface (21; 21A) of a Ga-based substrate (2; 2A). ２ O ３ β-Ga covering the first main surface (21; 21A) of the β-Ga-based substrate (2; 2A) and the metal layer (3) ２ O ３The layer (4) is formed by selective lateral overgrowth using mist CVD. The material of the metal layer (3) is a noble metal or a high melting point metal. ２ O ３ The thickness (T12) of the layer (4) is Ga ２ O ３ It is thinner than the thickness (T11) of the base substrate (2; 2A).

[0266] According to this aspect, β-Ga ２ O ３ It is possible to improve the characteristics of the system devices (10; 10B; 10C; 10D; 10E; 10F; 10G; 10H).

[0267] β-Ga according to the nineteenth aspect ２ O ３ In an eighteenth aspect, the method for manufacturing a Ga-based device (10H) further includes a laser lift-off step and a bonding step. ２ O ３ Laser light (LB1) was irradiated from the second main surface (22; 22A) side of the Ga-based substrate (2; 2A). ２ O ３ The β-Ga-based substrate (2; 2A) is covered with a metal layer (3) and ２ O ３ In the bonding process, the exposed surface of the metal layer (3) and the β-Ga ２ O ３ A heat sink (9) is bonded to the exposed surface of layer (4).

[0268] According to this aspect, β-Ga ２ O ３ This makes it possible to improve the heat dissipation of the system device (10H).

[0269] 1, 1A Epitaxial wafer 2, 2a Ga ２ O ３ System board 2A Ga ２ O ３ Sapphire substrate 21, 21A First main surface 21a First main surface 211, 211a Part 22, 22A Second main surface 22a Second main surface 24 Sapphire substrate 241 First main surface 242 Second main surface 25 β-Ga ２ O ３Layer 3, 3a Metal layer 31, 31a Metal part 311 First metal part 312 Second metal part 32 Opening part 4, 4a β-Ga ２ O ３ Layer 41, 41a n ＋ β-Ga ２ O ３ Layer 42, 42a n-type β-Ga ２ O ３ Layer 401 First part 402 Second part 4C β-Ga ２ O ３ Layer 4D β-Ga ２ O ３ Layer 43 Semi-insulating β-Ga ２ O ３ Layer 44 n-type β-Ga ２ O ３ Layers 5, 5B, 5C, 5D, 5G Semiconductor element 51 Drain region 52 Source region 53 Channel formation region 54 Gate insulating film 55 Drain electrode 551 Drain electrode comb-bone portion 552 Drain electrode comb-teeth portion 56 Source electrode 561 Source electrode comb-bone portion 562 Source electrode comb-teeth portion 57 Gate electrode 571 Gate electrode comb-bone portion 572 Gate electrode comb-teeth portion 58 First metal electrode layer (cathode electrode) 59 Second metal electrode layer (anode electrode) 6 Heat sink 7 Heat dissipation layer 8 Heat sink 9 Heat sink 10, 10B, 10C, 10D, 10E, 10F, 10G, 10H β-Ga ２ O ３ System device A1 Threading dislocation A2 Threading dislocation D10, D20 Thickness direction D11, D21 First direction D12, D22 Second direction LB1 Laser light T1 Thickness T2 Thickness T11 Thickness T12 Thickness

Claims

1. A GaAs semiconductor device having a first main surface and a second main surface opposite to the first main surface. ２ O ３ a Ga-based substrate; ２ O ３ a metal layer formed on the first main surface of a Ga-based substrate, the metal layer having a plurality of openings; ２ O ３ The β-Ga GaN layer covering the first main surface of the GaN-based substrate and the metal layer. ２ O ３ a layer, the material of the metal layer being a noble metal or a high melting point metal, ２ O ３ The thickness of the Ga ２ O ３ The epitaxial wafer is thinner than the substrate.

2. The metal layer includes a plurality of metal portions, each of the plurality of metal portions being linear, and the Ga ２ O ３ The epitaxial wafer according to claim 1 , wherein the metal portions and the openings are arranged alternately in a plan view in a thickness direction of the substrate.

3. The epitaxial wafer according to claim 1, wherein the plurality of openings are arranged in a two-dimensional array in the metal layer.

4. The Ga ２ O ３ The substrate is β-Ga ２ O ３ The epitaxial wafer according to any one of claims 1 to 3, which is a substrate.

5. The Ga ２ O ３ The β-GaAs-based substrate comprises a sapphire substrate and a β-GaAs-based substrate formed on the sapphire substrate. ２ O ３ and a Ga layer. ２ O ３ In the case of the β-Ga-based substrate, ２ O ３ The surface of the Ga layer ２ O ３ The epitaxial wafer according to claim 1 , which constitutes the first main surface of a substrate.

6. A GaAs semiconductor device having a first main surface and a second main surface opposite to the first main surface. ２ O ３ a Ga-based substrate; ２ O ３ a metal layer formed on a portion of the first main surface of the Ga-based substrate; ２ O ３ The β-Ga GaN layer covering the first main surface of the GaN-based substrate and the metal layer. ２ O ３ a semiconductor element; and ２ O ３ The material of the metal layer is a noble metal or a high melting point metal, and the β-Ga ２ O ３ The thickness of the Ga ２ O ３ The thickness of the β-Ga ２ O ３ System devices.

7. The metal layer includes a plurality of metal portions, each of the plurality of metal portions being linear, and the Ga ２ O ３ 7. The β-GaAs semiconductor device according to claim 6, wherein the plurality of metal parts are arranged at intervals in a direction perpendicular to each other in a plan view from a thickness direction of the semiconductor substrate. ２ O ３ System devices.

8. The semiconductor element is a MESFET including a drain region, a source region, a channel forming region, a drain electrode, a source electrode, and a gate electrode, and the drain region, the source region, and the channel forming region are formed of the β-Ga ２ O ３ The Ga ２ O ３ 8. The β-GaAs semiconductor device according to claim 7, wherein the channel formation region overlaps one of the plurality of metal portions in a plan view in the thickness direction of the substrate. ２ O ３ System devices.

9. The Ga ２ O ３ The base substrate is semi-insulating β-Ga ２ O ３ A substrate, ２ O ３ The layer is n-type β-Ga ２ O ３ the drain region is a comb-shaped layer, and the n-type β-Ga ２ O ３ n formed in the layer ＋ Type β-Ga ２ O ３ The source region is comb-shaped, and the n-type β-Ga ２ O ３ n formed in the layer ＋ Type β-Ga ２ O ３ a drain electrode formed on the drain region, ２ O ３ The source electrode has a comb shape overlapping the drain region when viewed from above in the thickness direction of the Ga-based substrate, and the source electrode is formed on the source region. ２ O ３ The gate electrode has a comb shape overlapping the source region when viewed from a plane in the thickness direction of the n-type β-GaAs substrate, ２ O ３ The Ga ２ O ３ a gate electrode having a gate electrode comb bone portion and a plurality of gate electrode comb teeth portions extending from the source electrode comb bone portion; the gate electrode having a gate electrode comb bone portion and a plurality of gate electrode comb teeth portions extending from the gate electrode comb bone portion; the drain electrode comb bone portion and the source electrode comb bone portion face each other in a first direction; and the plurality of drain electrode comb teeth portions, the plurality of gate electrode comb teeth portions and the plurality of source electrode comb teeth portions are arranged to face each other in a first direction; ２ O ３ are aligned in the thickness direction of the Ga-based substrate and in a second direction perpendicular to the first direction, ２ O ３ 9. The β-GaAs semiconductor device according to claim 8, wherein each of the plurality of gate electrode comb teeth overlaps one of the plurality of metal portions in a plan view in the thickness direction of the semiconductor substrate. ２ O ３ System devices.

10. Each of the plurality of gate electrode comb teeth is ２ O ３ 10. The β-GaAs / GaAs alloy semiconductor substrate according to claim 9, wherein the β-GaAs / GaAs alloy semiconductor substrate is offset in the second direction so as not to overlap with a center of the one metal portion in the second direction in a plan view in the thickness direction of the alloy substrate. ２ O ３ System devices.

11. The β-GaAs layer according to claim 6, wherein the metal layer has a plurality of openings arranged in a two-dimensional array. ２ O ３ System devices.

12. The semiconductor element is a Schottky barrier diode, and the Ga ２ O ３ The base substrate is semi-insulating β-Ga ２ O ３ A substrate, ２ O ３ The layer is ２ O ３ a first main surface of the semiconductor substrate and the metal layer, the first main surface being in ohmic contact with the metal layer; ＋ Type β-Ga ２ O ３ layer, and ＋ Type β-Ga ２ O ３ The n-type β-Ga ２ O ３ a first metal electrode layer made of the metal layer; ＋ Type β-Ga ２ O ３ layer, and the n-type β-Ga ２ O ３ layer, and the n-type β-Ga ２ O ３ The n-type β-Ga ２ O ３ a second metal electrode layer in Schottky contact with the Ga layer, ２ O ３ When viewed from above in a thickness direction of the substrate, at least a portion of the second metal electrode layer overlaps with at least a portion of the first metal electrode layer, the second metal electrode layer constitutes an anode electrode, and the n ＋ Type β-Ga ２ O ３ The β-GaAs layer and the first metal electrode layer constitute a cathode electrode. ２ O ３ System devices.

13. The semiconductor element is a MOSFET including a drain region, a source region, a channel formation region, a gate insulating film, a drain electrode, a source electrode, and a gate electrode, and the drain region, the source region, and the channel formation region are formed by the β-Ga ２ O ３ The β-Ga as claimed in claim 7, ２ O ３ System devices.

14. The Ga ２ O ３ The base substrate is semi-insulating β-Ga ２ O ３ A substrate, ２ O ３ The layer is n-type β-Ga ２ O ３ a layer, the plurality of metal portions including a first metal portion and a second metal portion adjacent to each other in a direction in which the plurality of metal portions are arranged, the drain region being the β-Ga ２ O ３ n metal portions formed on the first metal portion in the layer ＋ Type β-Ga ２ O ３ The source region is made of the β-Ga ２ O ３ n metal portions formed on the second metal portions in the layer ＋ Type β-Ga ２ O ３ a gate insulating film formed of the β-GaAs layer, the first metal portion forming the drain electrode, the second metal portion forming the source electrode, ２ O ３ the gate electrode is formed on the gate insulating film, and the Ga ２ O ３ the β-GaAs layer is located between the drain region and the source region when viewed from above in the thickness direction of the substrate, ２ O ３ The β-GaAs layer according to claim 13, wherein the layer is formed in a shape that exposes a part of the first metal portion and a part of the second metal portion. ２ O ３ System devices.

15. The β-Ga ２ O ３ The layer is a semi-insulating β-Ga ２ O ３ layer, and the semi-insulating β-Ga ２ O ３ The n-type β-Ga ２ O ３ a drain region including the n-type β-Ga ２ O ３ n formed in the layer ＋ Type β-Ga ２ O ３ The source region is made of the n-type β-Ga ２ O ３ n formed in the layer ＋ Type β-Ga ２ O ３ The gate insulating film is made of the n-type β-Ga ２ O ３ the gate electrode is formed on the gate insulating film, and the Ga ２ O ３ 14. The β-GaAs semiconductor layer according to claim 13, wherein the β-GaAs semiconductor layer is located between the drain region and the source region in a plan view from the thickness direction of the semiconductor substrate, the drain electrode is formed on the drain region, and the source electrode is formed on the source region. ２ O ３ System devices.

16. A heat sink is further provided, and the metal layer is ２ O ３ 16. The β-GaAs semiconductor device of claim 15, further comprising: an exposed portion of the metal layer that is not covered by the metal layer; and the heat sink is disposed on the exposed portion of the metal layer. ２ O ３ System devices.

17. The β-GaAs semiconductor device according to claim 6, further comprising: a heat dissipation layer formed on the semiconductor element and having electrical insulation; and a heat sink disposed on the heat dissipation layer, the heat dissipation layer including an AlN filler. ２ O ３ System devices.

18. A GaAs semiconductor device having a first main surface and a second main surface opposite to the first main surface. ２ O ３ a substrate preparation step of preparing a Ga-based substrate; ２ O ３ forming a metal layer having a plurality of openings on the first main surface of the Ga-based substrate; ２ O ３ A β-Ga alloy is provided covering the first main surface of the β-Ga-based substrate and the metal layer. ２ O ３ and forming an epitaxial growth step of forming a layer by selective lateral overgrowth using a mist CVD method, the material of the metal layer being a noble metal or a high melting point metal, the β-Ga ２ O ３ The thickness of the Ga ２ O ３ The thickness of the β-Ga ２ O ３ A method for manufacturing a system device.

19. The Ga ２ O ３ The Ga-based substrate is irradiated with laser light from the second main surface side. ２ O ３ The metal layer and the β-Ga ２ O ３ a laser lift-off process for removing the β-Ga GaN layer from the exposed surface of the metal layer and the β-Ga GaN layer; ２ O ３ and bonding a heat sink to the exposed surface of the layer. ２ O ３ A method for manufacturing a system device.

Images