Sequencing chip, manufacturing method and base calling method

Abstract

Provided in the present application are a sequencing chip, a manufacturing method, a base calling method, a device and a storage medium. The sequencing chip comprises a signal sensing layer, a signal storage layer and a signal recognition layer, wherein the signal sensing layer comprises a sensing structure and a sensing electrode, the sensing structure receiving a physical signal generated by a group, and generating an analog signal according to the physical signal; the signal storage layer comprises a memory and a storage electrode, the memory storing a digital signal; the signal recognition layer comprises a digital-to-analog converter, a recognition circuit and a recognition electrode, the recognition circuit processing the digital signal to recognize base information; and the sensing structure, the memory and the recognition circuit are electrically connected by means of the sensing electrode, the storage electrode and the recognition electrode. In the present application, a sequencing chip of a brand-new framework is designed, and signal collection, analog-to-digital conversion and storage and a base calling algorithm are integrated into the sequencing chip, thereby reducing the information transmission cost and making throughput configuration and amplification of a sequencing system more flexible.

Description

Sequencing chip, preparation method and base recognition method Technical Field

[0001] The present application relates to the field of base recognition, and in particular to a sequencing chip, a manufacturing method, and a base recognition method. Background Art

[0002] Existing high-throughput sequencers amplify nucleic acid fragments and then transfer them to a sequencing substrate or amplify them directly on the sequencing substrate. Sequencing reagents are then added to the sequencing substrate to carry out biochemical reactions such as base synthesis and excision. The signal reporter group generates light or electrical signals that are captured by the sequencing instrument. The base sequence is then obtained through algorithm calculations performed by the sequencing instrument's internal computer.

[0003] Common sequencing substrates include surface-based and semiconductor integrated circuits. The former typically captures fluorescence signals through a microscope's optical system, while semiconductor chips utilize internal integrated circuits to collect and convert electrical or optical signals into analog-to-digital data. Neither approach directly calculates base sequence.

[0004] Specifically, Figure 1 illustrates how sequencing systems in the prior art perform sequencing. An image sensor converts received light or telecommunications analog signals into digital signals. Internal memory stores the digital signals, which are then transmitted via high-speed transmission lines to an onboard processing unit to create an image. The image is then transmitted via high-speed circuits to a server computer, which deconstructs, processes, and analyzes the image information. The light signal generated by the signal reporter group undergoes layer-by-layer conversion and transmission, where it is processed into light intensity information. This information is then calculated into base information, stored as a sequence, and a final report is generated. After the final report is generated, the sequence is analyzed based on the report to obtain the desired final result.

[0005] Existing sequencing systems are complex, requiring signals to pass through multiple devices and high-speed circuits for transmission. This results in long transmission paths, high latency, and data-prone errors. These systems are also costly and energy-intensive. As the number of optoelectronic receiving arrays increases, the information becomes too large for efficient transmission, creating a bottleneck.

[0006] Summary of the Invention

[0007] In order to solve the defects of complex sequencing systems, long transmission paths and long transmission time, the present application provides a sequencing chip with a new structure, a production method and a base recognition method.

[0008] The present application provides a sequencing chip, which includes a signal sensing layer, a signal storage layer, and a signal recognition layer;

[0009] The signal sensing layer includes a sensing structure supporting the sample to be detected, and a photoelectric sensor arranged corresponding to the sensing structure. The optical signal generated by each sample to be detected is received by the photoelectric sensor and converted into an analog signal;

[0010] The signal storage layer includes a memory, and the memory caches digital signals;

[0011] The signal recognition layer includes a digital-to-analog converter and a recognition circuit. The digital-to-analog converter receives the analog signal and converts the analog signal into the digital signal. The recognition circuit further compares the cached digital signal with a preset signal threshold and confirms the base information corresponding to the optical signal.

[0012] Preferably, the sensing structure includes detection sites arranged in an array on the surface of the signal sensing layer, and the photoelectric sensors correspond to the detection sites one by one.

[0013] Preferably, the signal sensing layer, the signal storage layer, and the signal recognition layer are stacked in a direction away from the sample to be detected, and the sequencing chip further comprises a first storage electrode formed on a side of the signal storage layer close to the sample to be detected, a second storage electrode formed on a side of the signal storage layer away from the sample to be detected, and a first recognition electrode formed on a side of the signal recognition layer close to the signal storage layer;

[0014] The photosensor is electrically connected to the digital-to-analog converter via the first storage electrode, and the second storage electrode electrically connects the memory to the first identification electrode.

[0015] Preferably, the sequencing chip further includes a first insulating layer, and the first insulating layer is filled between the signal sensing layer and the signal recognition layer.

[0016] Preferably, the sequencing chip further includes a second insulating layer, and the second insulating layer is filled between the signal storage layer and the signal recognition layer.

[0017] Preferably, the sequencing chip further comprises a substrate, in which a substrate circuit is provided, and a side of the substrate close to the sample to be detected is provided with support positions corresponding to the signal sensing layer, the signal storage layer and the signal recognition layer, respectively. The signal sensing layer, the signal storage layer and the signal recognition layer are respectively mounted on the support positions and are respectively electrically connected to the substrate circuit.

[0018] Preferably, the sequencing chip further includes a third insulating layer, and the third insulating layer is filled between the substrate and the signal sensing layer, the signal storage layer, and the signal recognition layer.

[0019] The present invention also provides a method for manufacturing a sequencing chip, the method comprising:

[0020] The photoelectric sensor is deposited on a first substrate, and a patterned array structure is provided on the surface of the first substrate to form the signal sensing layer:

[0021] depositing the memory in a second substrate to form the signal storage layer;

[0022] Depositing the digital-to-analog converter and the recognition circuit on a third substrate to form the signal recognition layer;

[0023] The signal sensing layer, the signal storage layer and the signal recognition layer are sequentially stacked and bonded to form the sequencing chip.

[0024] Preferably, the signal sensing layer, the signal storage layer and the signal recognition layer are sequentially stacked and bonded, comprising:

[0025] Thinning the signal sensing layer to form a first sensing through hole on a side of the signal sensing layer facing away from the array structure, and leading an electrical connection line connected to the sensing structure through the first sensing through hole to form a sensing electrode electrically connected to the photosensor;

[0026] Thinning opposite sides of the signal storage layer to form a first storage through hole on one side of the signal storage layer and a second storage through hole on the other side thereof, and forming a first storage electrode electrically connected to the digital-to-analog converter through the first storage through hole and a second storage electrode electrically connected to the memory through the second storage through hole;

[0027] bonding a side of the signal storage layer corresponding to the first storage electrode to a side of the signal sensing layer facing away from the sample to be detected, and electrically connecting the sensing electrode and the first storage electrode;

[0028] Thinning the signal recognition layer to expose a first recognition through hole on one side of the signal recognition layer, and leading out a first recognition electrode electrically connected to the recognition module circuit through the first recognition through hole;

[0029] The side of the signal recognition layer corresponding to the first recognition electrode is bonded to the side of the signal storage layer away from the signal sensing layer, and the second storage electrode is electrically connected to the first recognition electrode.

[0030] Preferably, the step of electrically connecting the sensing electrode and the first storage electrode includes:

[0031] heating the sensing electrode and the first storage electrode to fuse the sensing electrode and the first storage electrode;

[0032] The step of electrically connecting the second storage electrode and the first identification electrode comprises:

[0033] The second storage electrode and the first identification electrode are heated to fuse the second storage electrode and the first identification electrode.

[0034] The present application also provides a method for manufacturing the above-mentioned sequencing chip, comprising:

[0035] Depositing the photoelectric sensor on a first substrate, and providing a patterned array structure on the surface of the first substrate to form the signal sensing layer;

[0036] depositing the memory in a second substrate to form the signal storage layer;

[0037] Depositing the digital-to-analog converter and the recognition circuit on a third substrate to form the signal recognition layer;

[0038] connecting the second substrate and the third substrate so that the signal recognition layer is electrically connected to the signal recognition layer;

[0039] An electrical connector is provided on a side of the third substrate close to the second substrate, so that the electrical connector is spaced apart from the second substrate and has a height relative to the third substrate greater than that of the second substrate;

[0040] The side of the first substrate facing away from the array structure is connected to the electrical connection member, so that the second substrate is located between the first substrate and the second substrate.

[0041] Preferably, connecting the second substrate and the third substrate includes:

[0042] The signal storage layer is flipped onto the signal identification layer so that the side of the signal storage layer facing away from the array structure is closely connected to the signal identification layer.

[0043] Preferably, connecting the side of the first substrate facing away from the array structure to the electrical connector includes:

[0044] The signal sensing layer is mounted above the signal identification layer, and the electrical connection member is sandwiched between the signal sensing layer and the signal identification layer, so that the signal sensing layer is electrically connected to the signal identification layer via the electrical connection member.

[0045] Preferably, the manufacturing method further comprises a sealing step:

[0046] An insulating material is filled between the signal recognition layer and the signal sensing layer to encapsulate the electrical connection component and the signal storage layer between the signal recognition layer and the signal sensing layer.

[0047] Preferably, the sealing step includes:

[0048] An insulating material is filled between the signal storage layer and the signal identification layer to form a first insulating layer.

[0049] Preferably, the sealing step further comprises:

[0050] An insulating material is filled between the signal sensing layer and the signal recognition layer to form a second insulating layer.

[0051] Preferably, the signal recognition layer and the signal storage layer are electrically connected by forming metal bumps for welding.

[0052] The present application also provides another method for manufacturing the above-mentioned sequencing chip, comprising:

[0053] Providing a substrate, depositing a substrate circuit in the substrate, and forming a plurality of support positions on one side of the substrate, wherein the plurality of support positions are electrically connected to the substrate circuit respectively;

[0054] Depositing the photoelectric sensor on a first substrate, and providing a patterned array structure on the surface of the first substrate to form the signal sensing layer;

[0055] depositing the memory in a second substrate to form the signal storage layer;

[0056] Depositing the digital-to-analog converter and the recognition circuit on a third substrate to form the signal recognition layer;

[0057] The signal sensing layer, the signal storage layer and the signal identification layer are respectively mounted on the supporting positions and are electrically connected to the corresponding supporting positions.

[0058] Preferably, after the steps of respectively installing the signal sensing layer, the signal storage layer and the signal recognition layer on the support positions and electrically connecting them to the corresponding support positions, the manufacturing method further comprises:

[0059] An insulating material is filled between the substrate and the signal sensing layer, the signal storage layer and the signal identification layer to form a third insulating layer.

[0060] The present application also provides a base recognition method based on a sequencing chip, the base recognition method comprising performing in the sequencing chip:

[0061] Sensing step: using a photoelectric sensor to receive an optical signal generated by the sample to be detected, and generating an analog signal according to the optical signal;

[0062] Conversion and storage step: converting the analog signal into a digital signal and caching the digital signal; and

[0063] Identification step: comparing the cached digital signal with a preset signal threshold to determine the base information corresponding to the optical signal.

[0064] Preferably, the base recognition method further comprises: an additional mechanism connected to the sequencing chip generates nucleic acid sequence information according to the base information, and generates a detection report according to the nucleic acid sequence information.

[0065] This application designs a sequencing chip with a completely new architecture, integrating signal acquisition, analog-to-digital conversion and storage, and base recognition algorithms into the sequencing chip. This allows the sequencing chip to directly perform base recognition, eliminating the need for a complex system to transmit the converted digital signal to an external computing unit before a series of algorithms can identify the base sequence. This eliminates the need for high-speed transmission paths, reducing transmission time and information transmission costs. Furthermore, the sequencing chip integrates most base recognition-related functions, allowing for convenient access to different throughputs by adjusting the number of sequencing chips mounted, making the configuration and amplification of throughput in the sequencing system more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] FIG1 is a flow chart of a method for performing base recognition by a sequencing system in the prior art.

[0067] FIG2 is a schematic diagram of the structure of the sequencing chip in Example 1 of the present invention.

[0068] FIG3 is a flow chart of manufacturing a sequencing chip in Example 1 of the present invention.

[0069] FIG4 is a schematic structural diagram corresponding to step 104 in Example 1 of the present invention.

[0070] FIG5 is another structural diagram corresponding to step 104 in embodiment 1 of the present invention.

[0071] FIG6 is a schematic diagram of the structure of the sequencing chip in Example 2 of the present invention.

[0072] FIG7 is a flow chart of manufacturing a sequencing chip in Example 2 of the present invention.

[0073] FIG8 is a schematic structural diagram of the first packaging structure in Embodiment 2 of the present invention.

[0074] FIG9 is a schematic diagram of a structure in which metal bumps are added to the first surface of the signal recognition layer in Example 2 of the present invention.

[0075] FIG10 is a schematic diagram of the structure formed in step 206 in Example 2 of the present invention.

[0076] FIG11 is a schematic diagram of the structure of the sequencing chip in Example 3 of the present invention.

[0077] FIG12 is a flow chart of manufacturing a sequencing chip in Example 3 of the present invention.

[0078] FIG13 is a schematic structural diagram of the signal sensing layer in Example 3 of the present invention.

[0079] FIG14 is a schematic diagram of the structure formed after step 308 in Example 3 of the present invention.

[0080] FIG15 is a flow chart of the base recognition method in Example 4 of the present invention. DETAILED DESCRIPTION

[0081] Embodiments of the present invention provide a sequencing chip. A signal sensing layer, a signal storage layer, and a signal recognition layer are bonded together into a complete wafer, i.e., a sequencing chip. This sequencing chip can perform base calling. Alternatively, a signal sensing chip, a signal storage chip, and a signal recognition chip are integrated into a single chip, i.e., a sequencing chip, using a novel packaging method. This sequencing chip can also perform base calling.

[0082] The signal sensing layer or signal sensing chip includes a sensing structure and a sensing electrode. The sensing structure is used to receive the physical signal (such as light, electricity, etc.) generated by the sample to be detected (such as a group sample) and generate an analog signal based on the physical signal. Specifically, the sensing structure can be a photodiode, which can receive the physical signal generated by the group, that is, the light signal or the electrical signal, and further convert the light signal or the electrical signal into an analog signal.

[0083] The sample to be tested can include any of a number of components. For example, it can contain nucleic acid macromolecules (e.g., DNA, RNA, etc.), proteins, etc. The sample can be analyzed to determine nucleic acid sequence, DNA-DNA hybridization, single nucleotide polymorphisms, protein interactions, peptide interactions, antigen-antibody interactions, glucose monitoring, cholesterol monitoring, etc.

[0084] In some embodiments, the sample to be detected is a nucleic acid, such as DNA. A DNA biomolecule can be, but is not limited to, a DNA nanoball (single-stranded concatemer) that hybridizes with a labeled probe (e.g., in DNB sequencing by ligation or cPAL methods) or with a complementary growing chain (e.g., in DNB sequencing by synthesis methods) or with both; or hybridizes with a single DNA molecule (e.g., in single molecule sequencing); or hybridizes with a cloned DNA molecule population, such as generated in bridge PCR-based sequencing. Therefore, the “biomolecule,” “DNA macromolecule,” or “nucleic acid macromolecule” mentioned can include more than one molecule (e.g., a DNA cluster of a cloned population of DNA molecules or a DNB associated with multiple growing complementary chains).

[0085] For example, a biological sample (eg, DNA macromolecules, oligonucleotides, or nucleotides) associated with a fluorescent or chemiluminescent dye can be placed over a photodiode.

[0086] In the case of fluorescence, the dye can be irradiated with excitation light from an excitation light source. The excitation light can correspond to light of any suitable type or intensity, such as visible light, infrared light (IR), ultraviolet light (UV), etc. The excitation light can also come from any suitable light source, such as a light emitting diode (LED), a lamp, a laser, a combination thereof, etc. When the dye is irradiated with excitation light of a specific wavelength, the biological sample can absorb the light and then emit light of a different wavelength. For example, the biological sample can absorb excitation light with a wavelength of 450nm, but emit light with a wavelength of 550nm. In other words, when the dye is irradiated with light of a characteristic different wavelength (i.e., the excitation light source), it can emit fluorescence of a characteristic wavelength.

[0087] In the case of chemiluminescence, the light detected by the photodiode does not require an additional excitation light source. Instead, the biological sample may emit light due to a chemical or enzymatic reaction between the biological sample and the chemiluminescent dye (or other solution), resulting in light emission due to the breaking or forming of chemical bonds.

[0088] For both fluorescence and chemiluminescence, the photodiode can detect the intensity of the emitted light and convert it into an electrical signal based on the light intensity, which can be provided to the signal storage layer via the sensing electrode. The signal sensing layer or signal sensing chip also includes a row and column selection circuit to control the transmission of specific photodiode signals.

[0089] The signal storage layer or signal storage chip includes a memory and a storage electrode. The memory is used to store the analog or digital signals generated by the signal sensing layer or signal sensing chip and the signal recognition layer or signal recognition chip. The memory specifically stores the circuit structure of analog signals and / or digital signal functions.

[0090] The signal recognition layer or chip converts the analog signal generated by the signal sensing layer or chip into a digital signal. After the digital signal is buffered by the memory, the signal recognition layer or chip further processes and identifies the digital signal into the required information, such as comparing the digital signal with a preset signal threshold and confirming the base information corresponding to the optical signal. The signal recognition layer or chip includes a digital-to-analog converter, a recognition circuit, and a recognition electrode.

[0091] The present invention also provides a method for manufacturing a sequencing chip, as shown in FIG3 , which includes the following steps:

[0092] Fabricating the signal sensing layer: A photoelectric sensor device and corresponding control circuitry are formed on the first substrate. Conventional semiconductor processing techniques (e.g., chemical vapor deposition) can be used to deposit a passivation layer above the photoelectric sensor on the first substrate. Etching techniques are then used to form array sites (e.g., array-excluded grooves) in the passivation layer to form a sensing structure for receiving the sample to be detected. Preferably, these sites correspond one-to-one to the photoelectric sensors.

[0093] Produce the above-mentioned signal storage layer: form a storage device on the second substrate, and guide the signal to both sides of the wafer through metal wiring.

[0094] Producing the above-mentioned signal recognition layer: depositing the recognition logic circuit in a third substrate to form the signal recognition layer.

[0095] The signal sensing layer, the signal storage layer and the signal recognition layer are stacked and bonded in sequence to form the sequencing chip.

[0096] The order of manufacturing the signal sensing layer, the signal storage layer and the signal recognition layer can be selected according to requirements.

[0097] In this embodiment, the above-mentioned first substrate, second substrate, and third substrate are preferably wafers, and the signal sensing layer, signal storage layer, and signal recognition are bonded into a complete wafer chip through wafer bonding, which can then be cut and packaged into chips that can be sequenced as needed.

[0098] In this embodiment, a novel sequencing chip architecture is designed, integrating signal acquisition, analog-to-digital conversion and storage, and base recognition algorithms into the chip, resulting in a semiconductor integrated sequencing chip that directly outputs biochemical signals as base sequences. This embodiment enables the sequencing chip to directly perform base recognition, eliminating the need for a complex system to transmit the converted digital signal to an external computing unit for base sequence identification through a series of algorithms. This eliminates the need for high-speed transmission paths, reducing transmission time and costs. This approach also enables more flexible configuration of throughput and amplification within the sequencing system.

[0099] Based on the above basic structure, three implementation methods of the embodiments of the present invention are described in detail below through specific embodiments:

[0100] Example 1

[0101] This embodiment provides a sequencing chip. FIG2 schematically shows a structural diagram of the sequencing chip in this embodiment. The sequencing chip includes a signal sensing layer 11 , a signal storage layer 12 , and a signal recognition layer 13 .

[0102] The signal sensing layer 11 has a sample detection site 113 on a surface 111 on a side close to the sample to be detected. A sensing electrode 114 is formed on a side of the signal sensing layer 11 away from the sample to be detected and is electrically connected to the detection site 113. The signal sensing layer 11, the signal storage layer 12, and the signal recognition layer 13 are stacked in a direction away from the sample to be detected. The storage electrode includes a first storage electrode 122 formed on a side of the signal storage layer close to the sample to be detected, and a second storage electrode 123 formed on a side of the signal storage layer 12 away from the sample to be detected. The recognition electrode includes a first recognition electrode 132 formed on a side of the signal recognition layer 13 close to the signal storage layer 12.

[0103] For the signal sensing layer 11, it includes a first storage through hole, which is used to lead out the electrical connection line 112 of the sensing structure to form a sensing electrode; for the signal storage layer, it includes a first storage through hole and a second storage through hole, the first storage through hole is used to lead out the electrical connection line connected to the memory to the first surface to form a first storage electrode, and the second storage through hole is used to lead out the electrical connection line connected to the memory to the second surface to form a second storage electrode; for the signal identification layer, it includes a first identification through hole, which is used to lead out the electrical connection line connected to the identification circuit to the first surface to form a first identification electrode.

[0104] In this embodiment, the sensing electrode 114 is electrically connected to the first storage electrode 122 , and the second storage electrode 123 is electrically connected to the first identification electrode 132 .

[0105] In this embodiment, the sample detection sites 113 can be used to modify the surface of the signal sensing layer on the one hand, and can also facilitate the adsorption of the to-be-detected groups on the surface of the signal sensing layer according to the shape of the detection sites 113 on the other hand.

[0106] This embodiment also provides a method for manufacturing the sequencing chip of this embodiment. FIG3 schematically shows a schematic diagram of the method of this embodiment, which includes:

[0107] Step 101: Make a signal sensing layer.

[0108] Through step 101, the image sensor device is formed on the silicon substrate using conventional semiconductor processes such as photolithography, etching, ion implantation, and thin film. The signal sensing layer 11 is formed. In particular, in order to allow the biological sample to be tested to be specifically combined with the surface of the signal sensing layer wafer, the corresponding position of the signal sensing layer can be patterned by photolithography, and then the required chemical bonds are deposited on the surface of the signal sensing layer wafer by chemical vapor deposition. At the same time, the etching method can also be used to etch a pattern on the surface of the signal sensing layer wafer to expose the high dielectric constant layer inside the signal sensing layer. The high dielectric constant layer and silicon oxide or nitride have different adsorption forces in the solvent for the sample to be tested, and selective adsorption is performed to achieve the subsequent sequencing steps. At the same time, the signal sensing layer uses through holes to lead the electrical signal connection lines of the metal layer such as copper inside the chip to the electrical connection lines of the sensing structure to form sensing electrodes. Among them, the figure mark 112 schematically shows the electrical connection lines in the signal sensing layer 11.

[0109] Step 102: Make a signal storage layer.

[0110] In step 102, conventional semiconductor processes such as photolithography, etching, ion implantation, and thin film deposition are used to deposit memory cells on a silicon substrate to form a signal storage layer 12. Simultaneously, through-holes are used in the storage layer to lead electrical signal connection lines from the copper or other metal layers within the chip to the storage structure, forming storage electrodes. The storage electrodes can be located on both sides of the storage layer. Reference numeral 121 schematically illustrates the electrical connection lines forming the storage electrodes in the signal storage layer 12.

[0111] Step 103: Make a signal recognition layer.

[0112] In step 103, conventional semiconductor processes such as photolithography, etching, ion implantation, and thin film processing are used to implement logic operation devices on a silicon substrate to form a signal recognition layer 13. At the same time, through-holes are used in the signal recognition layer to lead the electrical signal connection lines of the copper or other metal layers inside the chip to the electrical connection lines of the signal storage structure to connect to the recognition electrodes 132 corresponding to the storage electrodes of the signal storage layer.

[0113] It should be understood that in this embodiment, the execution order of steps 101 , 102 and 103 can be set according to actual needs.

[0114] In this embodiment, a substrate 14 may be further manufactured. The substrate 14 is connected to the second surface of the signal recognition layer 13, and can provide better support for the signal sensing layer, the signal storage layer 12 and the signal recognition layer 13, and lead out the signal.

[0115] In step 104, the wafers obtained in steps 101 to 103 are bonded together through a wafer bonding process. The special bonding enables the reserved sensing electrode on the side of the signal sensing layer facing away from the sample to be detected to be connected to the storage electrode of the storage layer wafer to form an electrical signal transmission path. After bonding, the wafer is thinned to the standard wafer thickness to facilitate subsequent processing. After the first two layers of wafers are bonded, the signal recognition wafer in step 103 is subjected to the same wafer bonding process to bond the side of the signal recognition wafer with the exposed signal recognition electrode to the storage layer. During bonding, the signal recognition electrode needs to be aligned with the storage layer electrode to form a signal path. Figures 4 and 5 show schematic diagrams of bonding three layers of wafers in sequence.

[0116] In an embodiment of the present invention, three layers of wafers with different functions are combined together through a bonding process to obtain a sequencing chip that can realize sensing, storage, and computing in one. This solves the complexity of the instrument end and the transmission problems. At the same time, by increasing the ratio of the sequencing area to the total area, the sequencing cost will be greatly reduced.

[0117] The method further includes forming a biological pattern layer on the first surface of the signal sensing layer.

[0118] FIG2 is a schematic structural diagram of a sequencing chip formed by the method shown in FIG3 , wherein reference numeral 113 schematically shows a biological pattern layer in this embodiment.

[0119] In particular, in order to allow the biological sample to be tested to be specifically combined with the surface of the signal sensing layer wafer, the signal sensing layer can be patterned at the corresponding position through a photolithography process, and then the required chemical bonds can be deposited on the surface of the signal sensing layer wafer through chemical vapor deposition. At the same time, an etching method can also be used to etch a pattern on the surface of the signal sensing layer wafer to expose the high dielectric constant layer inside the signal sensing layer. The high dielectric constant layer and silicon oxide or nitride have different adsorption forces on the sample to be tested in the solvent, thereby selectively adsorbing it to achieve subsequent sequencing steps.

[0120] In this embodiment, a thinner sequencing chip can be manufactured. This sequencing chip has stronger processing performance and contains more effective components, that is, the sequencing area accounts for a higher proportion of the total area of ​​the sequencing chip.

[0121] Example 2

[0122] This embodiment provides a sequencing chip, as shown in Figure 6, which includes a signal sensing chip (layer) 21, a signal storage chip (layer) 22, and a signal recognition chip (layer) 23. Based on the aforementioned basic structure, in this embodiment, the sensing electrode is formed on the side of the signal sensing chip (layer) 21 away from the sample to be detected, and the signal sensing chip (layer) 21, the signal storage chip (layer) 22, and the signal recognition chip (layer) 23 are stacked in a direction away from the sample to be detected. The storage electrode includes a first storage electrode formed on the side of the signal storage chip (layer) 22 away from the signal sensing layer, and the recognition electrode includes a first recognition electrode and a second recognition electrode formed on the side of the signal recognition chip (layer) 23 close to the signal sensing chip (layer) 21. The sensing electrode is electrically connected to the second recognition electrode, and the first storage electrode is electrically connected to the first recognition electrode.

[0123] In a specific embodiment, the sequencing chip further includes a first insulating layer, which is filled between the signal sensing chip (layer) 21 and the signal recognition chip (layer) 23. Through the first insulating layer, a sealing structure can be formed between the signal sensing chip (layer) 21 and the signal recognition chip (layer) 23.

[0124] In a specific embodiment, the sequencing chip further includes a second insulating chip (layer) 26, which is filled between the signal storage chip (layer) and the signal identification chip (layer). Through the second insulating chip (layer) 26, a sealing structure can be formed between the signal storage chip (layer) 22 and the signal identification chip (layer) 23.

[0125] This embodiment also provides a method for manufacturing the sequencing chip of this embodiment. FIG7 schematically shows a schematic diagram of the method of this embodiment, which includes:

[0126] Step 201: Make a signal sensing chip (layer).

[0127] A signal sensing chip (layer) 21 is formed through step 201 . In this embodiment, a sample detection site 20 is provided on the signal sensing chip (layer) 21 . The site 20 receives a sensing signal at a specific position to achieve optical sensing.

[0128] Step 202: Make a signal storage chip (layer) 22.

[0129] Step 203: Make a signal recognition chip (layer) 23.

[0130] It should be understood that in this embodiment, the execution order of steps 201 , 202 and 203 can be set according to actual needs.

[0131] Step 204: flip-chip the signal storage chip (layer) 22 onto the signal identification chip (layer) 23, so that the side of the signal storage chip (layer) 22 facing away from the sample to be detected is connected to the side of the signal identification chip (layer) 23 close to the sample to be detected, so that the first storage electrode on the surface of the signal storage chip (layer) 22 facing away from the sample to be detected is electrically connected to the first identification electrode on the surface of the signal identification chip (layer) 23 close to the sample to be detected.

[0132] Specifically, as shown in Figure 8, a metal bump 27 is added to the surface of the signal storage chip (layer) 22 facing away from the sample to be detected, the second surface of the signal storage chip (layer) 22 is flipped to the first surface of the signal identification chip (layer) 23, and the first storage electrode and the first identification electrode are welded through the metal bump 27. The metal bump 27 electrically connects the signal storage chip (layer) 22 and the signal identification chip (layer) 23 together.

[0133] In a specific embodiment, step 204 may further include a sealing step:

[0134] Step 205 : Fill the insulating material between the signal storage chip (layer) and the signal identification chip (layer) to form a first insulating layer.

[0135] In this embodiment, the signal storage chip (layer) and the signal identification chip (layer) can be sealed by the first insulating layer to protect the circuit structure therebetween.

[0136] In another specific implementation, step 206 may be directly executed after step 204 .

[0137] Step 206: forming an electrical connector electrically connected to the second recognition electrode on the side of the signal recognition chip (layer) close to the sample to be detected, wherein the height of the electrical connector relative to the signal recognition layer is greater than that of the signal recognition layer.

[0138] Step 207 : Mount the signal sensing chip (layer) 21 above the signal identification chip (layer) 23 , sandwich the electrical connector between the signal sensing chip (layer) 21 and the signal identification chip (layer) 23 , and electrically connect the sensing electrode to the second identification electrode via the electrical connector.

[0139] Specifically, as shown in FIG9 , the electrical connector may be a metal bump 24 . As shown in FIG10 , the sensing electrode and the second identification electrode are welded via the metal bump 4 .

[0140] In a specific embodiment, the sealing step may further include:

[0141] Step 208 : Fill the insulating material between the signal sensing chip (layer) and the signal identification chip (layer) to form a second insulating layer.

[0142] The reference numeral 26 represents the second insulating layer in this embodiment.

[0143] In this embodiment, the signal sensing chip (layer) and the signal identification chip (layer) can be sealed by the second insulating layer 26 to protect the circuit structure therebetween.

[0144] This embodiment can further add metal bumps (i.e., large bumps 25 in the figure) on the side of the signal sensing chip (layer) 21 facing away from the sample to be detected, so that the entire sequencing chip in this embodiment can be electrically connected to other external structures.

[0145] In this embodiment, the final sequencing chip is shown in FIG6 .

[0146] This embodiment can reduce the complexity and production cost of the sequencing chip manufacturing process, shorten data transmission time, and improve overall processing performance. The sequencing chip contains a moderate amount of active ingredients, that is, the sequencing area accounts for a moderate proportion of the total area of ​​the sequencing chip. By adopting an advanced packaging process, the precision requirements for processing machines are lower, and the material cost is lower, and the complexity of the overall process steps is greatly reduced.

[0147] Example 3

[0148] This embodiment provides a sequencing chip, as shown in Figure 11, which includes a signal sensing chip (layer) 31, a signal storage chip (layer) 32, and a signal recognition chip (layer) 33. On the basis of the aforementioned basic structure, further, in this embodiment, the sequencing chip also includes a substrate 34, in which a substrate circuit 341 is provided. The side of the substrate 34 close to the sample to be detected is respectively formed with support positions corresponding to the signal sensing chip (layer) 31, the signal storage chip (layer) 32, and the signal recognition chip (layer) 33, and the signal sensing chip (layer) 31, the signal storage chip (layer) 32, and the signal recognition chip (layer) 33 are respectively installed on the support positions.

[0149] The sensing electrode is formed on the side of the signal sensing chip (layer) 31 close to the substrate 34. The storage electrode includes a first storage electrode and a second storage electrode formed on the side of the signal storage chip (layer) 32 close to the substrate 34. The identification electrode includes a first identification electrode formed on the side of the signal identification chip (layer) 33 close to the substrate 34. The sensing electrode, the first storage electrode, the second storage electrode, and the first identification electrode are electrically connected to the substrate circuit respectively.

[0150] In a specific embodiment, the sequencing chip further includes a third insulating layer 35 , which is filled between the substrate 34 and the signal sensing chip (layer) 31 , the signal storage chip (layer) 32 , and the signal recognition chip (layer) 33 .

[0151] In this embodiment, the third insulating layer can seal the substrate and the signal sensing chip (layer), the signal storage chip (layer) and the signal identification chip (layer), thereby protecting the circuit structure therein.

[0152] This embodiment also provides a method for manufacturing the sequencing chip of this embodiment. FIG12 schematically shows a schematic diagram of the method of this embodiment, which includes:

[0153] Step 301: Make a signal sensing chip (layer).

[0154] Figure 13 schematically shows a schematic diagram of the signal sensing chip (layer) 31 manufactured in this embodiment. In this embodiment, the sensing structure 31 specifically includes an image sensor chip 311, a site 316, and a redistribution layer 312. The redistribution layer 312 is arranged with a redistribution line 313, and the signal sensing chip (layer) also includes a through hole 315.

[0155] The redistribution lines 313 are led out to the second surface of the signal sensing layer through the through holes 315 to form sensing electrodes. The sensing electrodes are specifically used to send analog signals.

[0156] Step 302: Make a signal storage chip (layer).

[0157] A signal storage chip (layer) 32 is formed through step 302. The structure of the signal storage chip (layer) can refer to the aforementioned signal sensing layer. Similarly, the redistribution line is led out to the second surface of the signal sensing layer through the through hole in the signal sensing chip (layer) to form a first storage electrode and a second storage electrode. The first storage electrode is used to receive an analog signal and transmit the analog signal to a digital-to-analog converter. The converted digital signal is cached by the memory of the signal storage layer, and the second storage electrode sends the digital signal.

[0158] Step 303: Make a signal recognition chip (layer).

[0159] A signal identification chip (layer) 33 is formed through step 303. The structure of the signal identification chip can refer to the aforementioned signal sensing layer. Similarly, the redistribution line is led out to the surface of the signal identification layer through the through hole in the signal identification chip (layer) to form a first identification electrode, which is used to receive the cached digital signal.

[0160] Step 304: Make a substrate.

[0161] Specifically, a substrate is manufactured, a plurality of support positions are formed on one side of the substrate, and a substrate circuit electrically connected to the plurality of support positions is provided in the substrate.

[0162] In step 304 , a substrate 34 is formed.

[0163] It should be understood that in this embodiment, the execution order of steps 301 , 302 , 303 and 304 can be set according to actual needs.

[0164] Step 305: Mount the signal sensing chip (layer), signal storage chip (layer) and signal identification chip (layer) on the supporting positions respectively, and electrically connect the sensing electrode, first storage electrode and second storage electrode to the corresponding supporting positions respectively.

[0165] Specifically, supporting positions such as metal bumps may be provided at the first storage electrode and the second storage electrode, and the first storage electrode and the second substrate electrode, and the second storage electrode and the third substrate electrode may be connected by welding.

[0166] Specifically, a support position such as a metal bump can be provided at the first identification electrode, the signal identification chip (layer) 33 can be flipped onto the substrate 34, and the first identification electrode and the fourth substrate electrode can be connected by welding.

[0167] It should be understood that in this embodiment, the execution order of steps 305, 306, 307 and 308 can be set according to actual needs.

[0168] The structure formed after step 305 is shown in FIG. 14 .

[0169] In a specific implementation, step 305 may further include:

[0170] Step 309 : Filling insulating material between the substrate and the signal sensing chip (layer), the signal storage chip (layer) and the signal identification chip (layer) to form a third insulating layer.

[0171] The entire chip can be sealed by the third insulating layer 35 , thereby better protecting the internal structure of the entire chip.

[0172] In a specific implementation, step 309 may further include:

[0173] Step 310 : Deposit a photoelectric sensor on the first surface of the signal sensing layer.

[0174] In step 310 , but not limited to, surface grinding, etching, and other processes, the protective layer on the first surface of the sequencing chip is removed to expose the photosensor.

[0175] The sequencing chip finally formed in this embodiment is shown in FIG11 .

[0176] This embodiment can greatly reduce the complexity and production cost of the sequencing chip manufacturing process, and can effectively reduce information transmission costs and shorten base recognition time. Due to the further simplification of the processing technology, the machine precision and material requirements used in the processing equipment are further reduced.

[0177] Example 4

[0178] This embodiment provides a base recognition method, which is implemented based on the sequencing chip of embodiment 1, 2, or 3. As shown in FIG15 , the base recognition method includes:

[0179] Step 401: generating a physical signal (optical signal) through a receiving group of a signal sensing layer, and generating an analog signal according to the physical signal;

[0180] Step 402: The analog signal is converted into a digital signal by the signal recognition layer. After the digital signal is cached by the signal storage layer, the digital signal is compared with a preset signal threshold and confirmed to correspond to the optical signal to identify the base information;

[0181] Step 403: Store the digital signal via the signal storage layer.

[0182] In a specific implementation, step 403 may further include the following steps:

[0183] Step 404: Generate a nucleic acid sequence based on the base information;

[0184] Step 405: Generate a test report based on the nucleic acid sequence.

[0185] In this embodiment, a sequencing chip with a new architecture is used to integrate the software calculation process of base recognition into a chip, and a series of functions such as signal sensing, signal storage, and signal processing can be inherited on the same chip, which greatly reduces the data processing time and improves the efficiency of base recognition.

[0186] Although the above describes specific embodiments of the present invention, it should be understood by those skilled in the art that these are merely illustrative and that various changes or modifications may be made to these embodiments without departing from the principles and essence of the present invention. Therefore, the scope of protection of the present invention is defined by the appended claims.

Claims

1. A sequencing chip, characterized in that: The sequencing chip includes a signal sensing layer, a signal storage layer and a signal recognition layer; The signal sensing layer includes a sensing structure supporting the sample to be detected, and a photoelectric sensor arranged corresponding to the sensing structure, and the optical signal generated by each sample to be detected is received by the photoelectric sensor and converted into an analog signal; The signal storage layer includes a memory, and the memory caches digital signals; The signal recognition layer includes a digital-to-analog converter and a recognition circuit. The digital-to-analog converter receives the analog signal and converts the analog signal into the digital signal. The recognition circuit further compares the cached digital signal with a preset signal threshold and confirms the base information corresponding to the optical signal.

2. The sequencing chip according to claim 1, wherein: The sensing structure includes detection sites arranged in an array on the surface of the signal sensing layer, and the photoelectric sensors correspond to the detection sites one by one.

3. The sequencing chip according to claim 1, wherein: The signal sensing layer, the signal storage layer and the signal recognition layer are stacked in a direction away from the sample to be detected, and the sequencing chip further comprises a first storage electrode formed on a side of the signal storage layer close to the sample to be detected, a second storage electrode formed on a side of the signal storage layer away from the sample to be detected, and a first recognition electrode formed on a side of the signal recognition layer close to the signal storage layer; The photoelectric sensor is electrically connected to the digital-to-analog converter via the first storage electrode, and the second storage electrode electrically connects the memory to the first identification electrode.

4. The sequencing chip according to claim 1, wherein: The signal sensing layer, the signal storage layer and the signal recognition layer are stacked in a direction away from the sample to be detected, an electrical connector is sandwiched between the signal sensing layer and the signal recognition layer, and the signal storage layer is electrically connected to the signal sensing layer via the signal recognition layer and the electrical connector in turn.

5. The sequencing chip according to claim 4, characterized in that: The sequencing chip also includes a first insulating layer, which is filled between the signal sensing layer and the signal recognition layer.

6. The sequencing chip according to claim 4, characterized in that: The sequencing chip also includes a second insulating layer, which is filled between the signal storage layer and the signal recognition layer.

7. The sequencing chip according to claim 1, characterized in that: The sequencing chip also includes a substrate, in which a substrate circuit is provided, and a side of the substrate close to the sample to be detected is provided with support positions corresponding to the signal sensing layer, the signal storage layer and the signal recognition layer, respectively. The signal sensing layer, the signal storage layer and the signal recognition layer are respectively mounted on the support positions and are respectively electrically connected to the substrate circuit.

8. The sequencing chip according to claim 7, characterized in that: The sequencing chip further includes a third insulating layer, and the third insulating layer is filled between the substrate and the signal sensing layer, the signal storage layer and the signal recognition layer.

9. A method for preparing a sequencing chip, characterized in that: include: A photoelectric sensor is deposited in a first substrate, and a patterned array structure is arranged on the surface of the first substrate to form a signal sensing layer, wherein the photoelectric sensor is configured to receive an optical signal of a sample to be detected and convert it into an analog signal: depositing a memory in the second substrate to form a signal storage layer, the memory being configured to buffer a digital signal; Depositing a digital-to-analog converter and a recognition circuit in a third substrate to form a signal recognition layer, wherein the digital-to-analog converter is configured to receive the analog signal and convert the analog signal into the digital signal, and the recognition circuit is configured to compare the cached digital signal with a preset signal threshold and confirm the base information corresponding to the optical signal; The signal sensing layer, the signal storage layer and the signal recognition layer are sequentially stacked and bonded to form the sequencing chip.

10. The manufacturing method according to claim 9, characterized in that: The signal sensing layer, the signal storage layer and the signal recognition layer are sequentially stacked and bonded, including: Thinning the signal sensing layer to form a first sensing through hole on a side of the signal sensing layer away from the array structure, and leading an electrical connection line connected to the sensing module through the first sensing through hole to form a sensing electrode connected to the photoelectric sensor; Thinning opposite sides of the signal storage layer to form a first storage through hole on one side of the signal storage layer and a second storage through hole on the other side, and forming a first storage electrode electrically connected to the digital-to-analog converter through the first storage through hole and a second storage electrode electrically connected to the memory through the second storage through hole; Bonding a side of the signal storage layer corresponding to the first storage electrode to a side of the signal sensing layer away from the sample to be detected, and electrically connecting the sensing electrode to the first storage electrode; Thinning the signal recognition layer to expose a first recognition through hole on one side of the signal recognition layer, and leading out a first recognition electrode electrically connected to the recognition circuit through the first recognition through hole; The side of the signal recognition layer corresponding to the first recognition electrode is bonded to the side of the signal storage layer away from the signal sensing layer, and the second storage electrode is electrically connected to the first recognition electrode.

11. The method according to claim 10, characterized in that: The step of electrically connecting the sensing electrode and the first storage electrode comprises: heating the sensing electrode and the first storage electrode to fuse the sensing electrode with the first storage electrode; The step of electrically connecting the second storage electrode and the first identification electrode comprises: The second storage electrode and the first identification electrode are heated to fuse the second storage electrode with the first identification electrode.

12. A method for preparing a sequencing chip, characterized in that: include: Depositing a photoelectric sensor in a first substrate and providing a patterned array structure on a surface of the first substrate to form a signal sensing layer, wherein the photoelectric sensor is configured to receive an optical signal of a sample to be detected and convert it into an analog signal; A memory is deposited in the second substrate to form a signal storage layer, wherein the memory is configured to cache data. word signal; Depositing a digital-to-analog converter and a recognition circuit in a third substrate to form a signal recognition layer, wherein the digital-to-analog converter is configured to receive the analog signal and convert the analog signal into the digital signal, and the recognition circuit is configured to compare the cached digital signal with a preset signal threshold and confirm the base information corresponding to the optical signal; Connecting the second substrate to the third substrate so that the signal recognition layer is electrically connected to the signal recognition layer; An electrical connection member is arranged on a side of the third substrate close to the second substrate, so that the electrical connection member is spaced apart from the second substrate and has a height relative to the third substrate greater than that of the second substrate; The side of the first substrate facing away from the array structure is connected to the electrical connection member, so that the second substrate is located between the first substrate and the second substrate.

13. The method according to claim 12, characterized in that: Connecting the second substrate to the third substrate includes: The signal storage layer is flipped onto the signal identification layer, so that the side of the signal storage layer away from the array structure is closely connected to the signal identification layer.

14. The method according to claim 12, characterized in that: Connecting a side of the first substrate facing away from the array structure to the electrical connector includes: The signal sensing layer is mounted above the signal identification layer, the electrical connection member is sandwiched between the signal sensing layer and the signal identification layer, and the signal sensing layer is electrically connected to the signal identification layer via the electrical connection member.

15. The manufacturing method according to claim 12, characterized in that: Also includes the sealing step: An insulating material is filled between the signal recognition layer and the signal sensing layer to encapsulate the electrical connection member and the signal storage layer between the signal recognition layer and the signal sensing layer.

16. The method of claim 15, wherein: The sealing step comprises: An insulating material is filled between the signal storage layer and the signal identification layer to form a first insulating layer.

17. The method of claim 16, wherein: The sealing step further comprises: An insulating material is filled between the signal sensing layer and the signal identification layer to form a second insulating layer.

18. The manufacturing method according to claim 12, characterized in that: The signal recognition layer and the signal storage layer are electrically connected by forming metal bumps for welding.

19. A method for preparing a sequencing chip, characterized in that: include: Providing a substrate, depositing a substrate circuit in the substrate, and forming a plurality of supporting positions on one side of the substrate, wherein the plurality of supporting positions are electrically connected to the substrate circuit respectively; Depositing a photoelectric sensor in a first substrate and providing a patterned array structure on a surface of the first substrate to form a signal sensing layer, wherein the photoelectric sensor is configured to receive an optical signal of a sample to be detected and convert it into an analog signal; depositing a memory in the second substrate to form a signal storage layer, the memory being configured to buffer a digital signal; Depositing a digital-to-analog converter and a recognition circuit in a third substrate to form a signal recognition layer, wherein the digital-to-analog converter is configured to receive the analog signal and convert the analog signal into the digital signal, and the recognition circuit is configured to compare the cached digital signal with a preset signal threshold and confirm the base information corresponding to the optical signal; The signal sensing layer, the signal storage layer and the signal identification layer are respectively mounted on the supporting positions and are electrically connected to the corresponding supporting positions respectively.

20. The method of claim 19, wherein: After the step of installing the signal sensing layer, the signal storage layer and the signal identification layer on the support positions respectively and electrically connecting them to the corresponding support positions respectively, the method further includes: An insulating material is filled between the substrate and the signal sensing layer, the signal storage layer and the signal identification layer to form a third insulating layer.

21. A base recognition method based on a sequencing chip, characterized in that: The base recognition method comprises performing in the sequencing chip: Sensing step: using a photoelectric sensor to receive an optical signal generated by the sample to be detected, and generating an analog signal according to the optical signal; Conversion and storage step: converting the analog signal into a digital signal and caching the digital signal; as well as Identification step: comparing the cached digital signal with a preset signal threshold to determine the base information corresponding to the optical signal.

22. The base recognition method according to claim 21, characterized in that: The base recognition method further comprises: The additional mechanism connected to the sequencing chip generates nucleic acid sequence information according to the base information, and generates a detection report according to the nucleic acid sequence information.

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