Method for manufacturing lower electrode of phase change memory

Abstract

The present invention belongs to the field of the manufacturing of semiconductor integrated circuits. Provided is a method for manufacturing a lower electrode of a phase change memory. The method of the present invention comprises: a semiconductor component providing step, involving: providing a semiconductor component, which comprises a substrate and a silicon oxide layer formed on the substrate, wherein the silicon oxide layer is provided with a first opening, the lower portion of the first opening being filled with a conductive material, and the upper portion of the first opening forming a second opening; a titanium nitride layer forming step, involving: using a PVD process to form a titanium nitride layer on the upper surface of the semiconductor component, wherein the titanium nitride layer is formed on the upper surface of the silicon oxide layer and fills the second opening; and a lower electrode forming step, involving: using a CMP process to remove a portion of the titanium nitride layer that is located on the upper surface of the silicon oxide layer, such that a portion of the titanium nitride layer that fills the second opening forms a lower electrode. By means of the method of the present invention, the manufacturing speed of the lower electrode of the phase change memory can be greatly increased without affecting the film thickness uniformity and the resistance uniformity of the lower electrode.

Description

Method for manufacturing lower electrode of phase change memory Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a lower electrode of a phase change memory. Background Art

[0002] In the prior art, the lower electrode of a phase-change memory is typically manufactured using a CVD (chemical vapor deposition) process. As shown in Figure 7, a TiN (titanium nitride) layer 6 is formed on the upper surface of a semiconductor component 10 using the CVD process, and the second opening 5 of the semiconductor component 10 is also filled with TiN. A CMP (chemical mechanical polishing) process is then used to remove the TiN layer from the upper surface of the semiconductor component 10, leaving only the TiN layer in the second opening 5, thereby forming the lower electrode 7.

[0003] However, the speed of manufacturing the bottom electrode by using the CVD process is relatively slow, and it usually takes about 15 minutes to form the TiN layer 6 . Technical issues

[0004] The present invention aims to provide a method for manufacturing a lower electrode of a phase change memory capable of improving the manufacturing speed. Technical Solutions

[0005] The manufacturing method of the present invention comprises:

[0006] The semiconductor component providing step includes providing a semiconductor component, the semiconductor component comprising: a substrate, a silicon oxide layer formed on the substrate, a first opening being formed in the silicon oxide layer, a conductive material being filled in the lower portion of the first opening, and a second opening being formed in the upper portion of the first opening;

[0007] A titanium nitride layer forming step: forming a titanium nitride layer on the upper surface of the semiconductor component using a physical vapor deposition process, wherein the titanium nitride layer is formed on the upper surface of the silicon oxide layer and fills the second opening;

[0008] The step of forming a lower electrode is as follows: using a chemical mechanical polishing process to remove the portion of the titanium nitride layer located on the upper surface of the silicon oxide layer, so that the portion of the titanium nitride layer filled in the second opening forms the lower electrode. Beneficial effects

[0009] The manufacturing method of the present invention can greatly improve the manufacturing speed of the lower electrode of the phase change memory without affecting the film thickness uniformity and resistance uniformity of the lower electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] 1 is a flow chart of a method for manufacturing a lower electrode of a phase change memory according to the present invention;

[0011] FIG2 is a schematic diagram of a PVD (physical vapor deposition) system used in the manufacturing method of the present invention;

[0012] 3 is a flow chart of a TiN layer forming step in the manufacturing method of the present invention;

[0013] 4 to 6 are schematic cross-sectional views of a semiconductor device at various stages of the manufacturing method of the present invention; and

[0014] FIG. 7 is a cross-sectional view of a semiconductor component in a method for manufacturing a lower electrode of a phase change memory according to the prior art.

[0015] Explanation of symbols

[0016] 10 semiconductor components

[0017] 1 substrate

[0018] 2 Silicon oxide layer

[0019] 3 First Opening

[0020] 4 Conductive materials

[0021] 5 Second opening

[0022] 6 TiN layer

[0023] 7 Lower electrode

[0024] 100 PVD system

[0025] 11 Chamber

[0026] 12 Ti (titanium) target

[0027] 13 base

[0028] 14 wafers

[0029] 15 Air supply device

[0030] 16 DC magnetron device

[0031] 17 Vacuum device Best Mode for Carrying Out the Invention

[0032] The following describes a method for manufacturing a lower electrode of a phase change memory according to the present invention with reference to FIG. 1 to FIG. 6 .

[0033] As shown in FIG1 , the method for manufacturing the lower electrode of a phase change memory of the present invention includes: a semiconductor component providing step S100 , a TiN layer forming step S200 , and a lower electrode forming step S300 . Each step will be described in detail below.

[0034] First, referring to Figure 4, the semiconductor component providing step S100 is described: a semiconductor component 10 is provided, and the semiconductor component 10 includes: a substrate 1, a silicon oxide layer 2 formed on the substrate 1, a first opening 3 is opened in the silicon oxide layer 2, the lower part of the first opening 3 is filled with a conductive material 4, and a second opening 5 is formed on the upper part of the first opening 3.

[0035] The semiconductor component 10 can be formed using methods commonly used in the art, which will not be described in detail here. In this embodiment, the conductive material 4 can be tungsten. However, the present invention is not limited thereto. In other embodiments, the conductive material 4 can also be other materials.

[0036] Preferably, the aspect ratio of the second opening 5 is 1:1.5. This is more conducive to subsequent filling by the PVD process. However, the present invention is not limited thereto, and the aspect ratio of the second opening 5 can also be other values ​​as long as the second opening 5 can be filled by the PVD process.

[0037] In this embodiment, the second opening 5 has a depth of 450 angstroms and a width of 600 angstroms. In a subsequent CMP process, the top of the silicon oxide layer 2 will be removed by approximately 50 angstroms, so the final depth of the second opening 5 is approximately 400 angstroms. However, the present invention is not limited thereto, and the depth and width of the second opening 5 may also be other values.

[0038] Referring now to FIG. 5 , the TiN layer forming step S200 is described. A TiN layer 6 is formed on the upper surface of the semiconductor component 10 using a PVD process. The TiN layer 6 is formed on the upper surface of the silicon oxide layer 2 and fills the second opening 5. In this embodiment, the thickness of the formed TiN layer 6 is 400 angstroms. However, the present invention is not limited thereto, and the TiN layer 6 may have any thickness suitable for forming the bottom electrode.

[0039] The TiN layer 6 can be formed by a PVD method commonly used in the art. In this embodiment, as shown in FIG2 , the PVD system 100 used in the PVD process includes: a chamber 11, a Ti target 12 arranged at the top of the chamber 11, a base 13 arranged at the bottom of the chamber 11, a wafer 14 placed on the base 13, a gas supply device 15 for ventilating the chamber 11, a DC magnetron device 16 electrically connected to the Ti target 12, and an exhaust device 17 for extracting gas from the chamber 11.

[0040] In this embodiment, the gas supply device 5 is used to introduce argon and nitrogen into the chamber 11 and control their flow rates. The DC magnetron device 16 is used to discharge electricity into the argon gas in the chamber 11, ionizing it into argon ions. The DC magnetron device 16 can also control the deposition power (DEP power) and the pulsed DC duty cycle (PDC duty).

[0041] As shown in FIG3 , the PVD process of this embodiment includes:

[0042] Ventilation step S201 : introducing argon gas and nitrogen gas into the chamber 11 through the gas supply device 15 .

[0043] Ignition step S202 : discharging the argon gas in the chamber 11 through the DC magnetron device 16 to ionize the argon gas into argon ions. The nitrogen gas nitrides the surfaces of the wafer 14 and the Ti target 12 , forming a TiN film on the surface of the Ti target 12 .

[0044] Deposition step S203 : Ar ions bombard the Ti target 12 , bombarding Ti ions in the Ti target 12 and TiN molecules in the TiN film, and depositing them on the upper surface of the wafer 14 to form a TiN layer 6 .

[0045] Temperature reduction step S204 : the DC magnetron device 16 stops discharging to the argon gas in the chamber 11 , and the gas supply device 15 continues to introduce argon gas and nitrogen gas into the chamber 11 , thereby reducing the temperature of the wafer 14 .

[0046] In the exhaust step S205 , the gas supply device 15 stops supplying argon and nitrogen into the chamber 11 , and the argon and nitrogen in the chamber 11 are exhausted by the exhaust device 17 , thereby restoring the chamber 11 to a vacuum state.

[0047] The above method can significantly improve manufacturing speed. Experimental results show that the PVD process only takes about 25 seconds to form the TiN layer 6. This significantly improves manufacturing speed compared to the 15 minutes required by the existing CVD process. Furthermore, the thickness uniformity and resistance uniformity of the TiN layer 6 formed using the PVD process were compared with those of the TiN layer formed using the CVD process. The experimental results show that the thickness uniformity and resistance uniformity of the TiN layer 6 formed using the PVD process are no less than those of the TiN layer formed using the CVD process.

[0048] 6 , the lower electrode forming step S300 is described below: a CMP process is used to remove the portion of the TiN layer 6 located on the upper surface of the silicon oxide layer 2, so that the portion of the TiN layer 6 filling the second opening 5 forms the lower electrode 7. A CMP process commonly used in the art can be used to remove the portion of the TiN layer 6 located on the upper surface of the silicon oxide layer 2, and a detailed description thereof will not be repeated here. Industrial Applicability

[0049] By means of the method for manufacturing the lower electrode of the phase change memory of the present invention, the manufacturing speed of the lower electrode of the phase change memory can be greatly improved without affecting the uniformity of the film thickness and the uniformity of the resistance of the lower electrode.

Claims

1. A method for manufacturing a lower electrode of a phase change memory, comprising: Semiconductor component providing step S100: providing a semiconductor component (10), the semiconductor component (10) comprising: a substrate (1), a silicon oxide layer (2) formed on the substrate (1), a first opening (3) being formed in the silicon oxide layer (2), a conductive material (4) being filled at the bottom of the first opening (3), and a second opening (5) being formed at the top of the first opening (3); Titanium nitride layer forming step S200: using a physical vapor deposition process to form a titanium nitride layer (6) on the upper surface of the semiconductor component (10), wherein the titanium nitride layer (6) is formed on the upper surface of the silicon oxide layer (2) and fills the second opening (5); Lower electrode forming step S300: using a chemical mechanical polishing process to remove the portion of the titanium nitride layer (6) located on the upper surface of the silicon oxide layer (2), so that the portion of the titanium nitride layer (6) filled in the second opening (5) forms the lower electrode (7).

2. The method for manufacturing the lower electrode of the phase change memory according to claim 1, characterized in that: The physical vapor deposition system (100) used in the physical vapor deposition process comprises: a chamber (11), a titanium target material (12) arranged at the top of the chamber (11), a base (13) arranged at the bottom of the chamber (11), a wafer (14) placed on the base (13), a gas supply device (15) for ventilating the chamber (11), a DC magnetron device (16) electrically connected to the titanium target material (12), and a gas extraction device (17) for extracting gas from the chamber (11). The physical vapor deposition process comprises: Ventilation step S201: introducing argon gas and nitrogen gas into the chamber (11) through the gas supply device (15); Ignition step S202: discharging the argon gas in the chamber (11) through the DC magnetron device (16) to ionize the argon gas into argon ions, and the nitrogen gas nitriding the surfaces of the wafer (14) and the titanium target (12), thereby forming a titanium nitride film on the surface of the titanium target (12); Deposition step S203: the argon ions bombard the titanium target (12), bombarding titanium ions in the titanium target (12) and titanium nitride molecules in the titanium nitride film, and depositing them on the upper surface of the wafer (14), thereby forming the titanium nitride layer (6); Temperature reduction step S204: the DC magnetron device (6) stops discharging to the argon gas in the chamber (11), and the gas supply device (15) continues to introduce argon gas and nitrogen gas into the chamber (11), thereby reducing the temperature of the wafer (14); Pumping step S205: the gas supply device (15) stops introducing argon and nitrogen into the chamber (11), and the argon and nitrogen in the chamber (11) are pumped out by the pumping device (17), thereby restoring the chamber (11) to a vacuum state.

3. The method for manufacturing the lower electrode of the phase change memory according to claim 1, characterized in that: The second opening (5) has a depth-to-width ratio of 1:1.5.

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