Signal processing circuit and memory

Abstract

The present disclosure provides a signal processing circuit and a memory. The signal processing circuit comprises: a pulse stretching circuit which is used for stretching the pulse width of an address signal by means of a command signal to generate an address stretched signal; and an address decoding circuit which has an input end coupled to an output end of the pulse stretching circuit, and is used for decoding the address stretched signal to generate an address decoded signal.

Description

Signal processing circuit and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 27, 2023, with application number 202310776136.0 and application name “Signal Processing Circuit and Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to, but is not limited to, a signal processing circuit and a memory. Background Art

[0003] In memory, command and address signals are used to indicate the command operation to be performed and the address at which the operation is to be performed. For example, command and address signals are used to instruct the execution of a precharge command for some or all rows in a target BA (memory bank) within a target BG (memory bank group). Before the command and address signals reach the target BA of the target BG, they undergo a series of processing.

[0004] In the prior art, an address decoding circuit is provided in the memory, and the address decoding circuit is used to receive an address signal and decode the address signal to obtain an address decoding signal, and then execute a command on the memory according to the address decoding signal and a command signal.

[0005] However, the above solution may result in command execution errors.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide a signal processing circuit and a memory to reduce the error rate of command execution.

[0008] In a first aspect, an embodiment of the present disclosure provides a signal processing circuit, comprising:

[0009] Pulse stretching circuit and address decoding circuit;

[0010] The pulse stretching circuit is used to receive a command signal and an address signal, and stretch the pulse width of the address signal according to the command signal to generate an address stretching signal;

[0011] An input terminal of the address decoding circuit is coupled to an output terminal of the pulse stretching circuit, and is configured to receive the address stretching signal, decode the address stretching signal, and generate an address decoding signal corresponding to the address signal.

[0012] In a second aspect, the present disclosure provides a memory comprising the signal processing circuit described in the first aspect.

[0013] Embodiments of the present disclosure provide a signal processing circuit and memory. A pulse stretching circuit is configured to receive a command signal and an address signal, and to stretch the pulse width of the address signal using the command signal to generate an address stretching signal. An input of an address decoding circuit is coupled to an output of the pulse stretching circuit, and is configured to receive the address stretching signal, decode the address stretching signal, and generate an address decoding signal corresponding to the address signal. The present disclosure can perform pulse stretching on an address signal to increase the pulse width of the address signal. Pulse stretching can provide more timing margin for address decoding, helping to ensure command sampling accuracy and improving the success rate of command execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a schematic diagram of decoding address information of a memory provided by the prior art;

[0015] FIG2 is a schematic structural diagram of a signal processing circuit provided by an embodiment of the present disclosure;

[0016] FIG3 is a schematic diagram of input terminal connections of a first trigger provided by an embodiment of the present disclosure;

[0017] FIG4 is a schematic diagram of expanding an address signal through a command signal according to an embodiment of the present disclosure;

[0018] FIG5 is a schematic diagram showing the connection of the input terminals of another first trigger provided by an embodiment of the present disclosure;

[0019] FIG6 is a schematic diagram of another embodiment of the present disclosure providing an embodiment of expanding an address signal through a command signal;

[0020] 7 and 8 are schematic structural diagrams of two other signal processing circuits provided by embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0022] The terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present disclosure described herein can, for example, be implemented in an order other than that illustrated or described herein.

[0023] In addition, the terms "comprises" and "having" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, product or apparatus.

[0024] The embodiments of the present disclosure are applicable to memory devices, which are any semiconductor devices used for data storage and access. For example, DRAM (Dynamic Random Access Memory) may include, but is not limited to, SDRAM (Synchronous Dynamic Random Access Memory), which may include, but is not limited to, DDR (Double Data Rate SDRAM) 1 to DDR6 and LPDDR (Low Power Double Data Rate SDRAM) 1 to LPDDR6.

[0025] The memory described above can provide external data storage and data access functions, which rely on command signals and address signals. As shown in Figure 1, the address signal needs to be decoded by the address decoding circuit provided in the memory to obtain an address decoding signal. The address decoding signal and the command signal are used together to execute the command operation.

[0026] The address signal is transmitted over long distances, which may cause skew or increased skew between the signals of multiple bits in the address signal. Skew between multiple bit signals refers to the temporal offset of the pulses of the multiple bit signals. A greater skew indicates less pulse overlap time between the multiple bit signals, while a smaller skew indicates more pulse overlap time between the multiple bit signals.

[0027] In some scenarios, an external circuit sends a CA (Command Address) signal to the memory, which carries both the external command signal and the external address signal. For example, for a PRE (precharge) command, pins 1 through 5 of the memory receive the external PRE command signal in the CA signal, and pins 6 through 11 of the memory receive the address signal in the CA signal, with each pin corresponding to a single bit.

[0028] After receiving the external command signal, the memory processes it to obtain a command signal and processes the external address signal to obtain an address signal. Therefore, both the command signal and the address signal can be multi-bit signals. For the PRE command, the address signal includes a 5-bit BGBA signal. Before long-distance transmission, the rising and falling edges of these 5-bit BGBA signals are aligned, and the pulse overlap time between these 5-bit BGBA signals is relatively long. In other words, the skew between these 5-bit signals is relatively small.

[0029] However, after long-distance transmission, the rising edges of the 5-bit BGBA signals are no longer aligned, and / or the falling edges are no longer aligned, and the pulse overlap time between the 5-bit BGBA signals is reduced, that is, the skew between the 5-bit signals increases.

[0030] After the long-distance transmission causes the skew between multiple bits of the address signal to increase, the pulse width of the address signal will be reduced when decoding the address signal, resulting in errors in subsequent command sampling and further command execution errors.

[0031] It should be noted that the skew between the signals of the multiple bits in the above-mentioned address signal will increase with the increase of the signal transmission distance, and / or, the smaller the pulse width of the address signal, the greater the impact of the above-mentioned skew, thereby causing a greater probability of command execution error. For example, in 1N mode, the pulse width of the command signal and the pulse width of the address signal are both 1TCK (1 clock cycle), and the sampling period of both is 1TCK. In 2N mode, the pulse width of the command signal and the pulse width of the address signal are both 2TCK, and the sampling period of both is 2TCK. Therefore, compared with the 2N mode, the pulse width of the 1N mode is smaller, and the command execution error caused by the above-mentioned skew is more likely to occur.

[0032] In order to solve the above technical problems, the embodiment of the present disclosure can perform pulse stretching on the address signal to increase the pulse width of the address signal. When the address signal after pulse stretching is transmitted over a long distance, even if the pulse overlap time between signals of different bits is reduced due to the above-mentioned skew, the reduced pulse overlap time is still sufficient to ensure correct command sampling. In other words, pulse stretching can provide more pulse width margin for address decoding, and even if the address decoding reduces its pulse width, the command sampling accuracy can still be guaranteed. Not only can the command execution success rate be guaranteed in low-frequency scenarios, but the command execution success rate can also be improved in high-frequency scenarios.

[0033] The embodiment of the present disclosure can better improve the command sampling accuracy and command execution success rate in the 1N mode with a smaller pulse width.

[0034] It can be understood that the coupling involved in the embodiments of the present disclosure can be a direct connection or an indirect connection, wherein a direct connection means that the two circuits are connected only through a circuit connection line, and an indirect connection means that both circuits are connected to another circuit to achieve a connection between the two circuits through the other circuit.

[0035] FIG2 is a schematic diagram of a signal processing circuit according to an embodiment of the present disclosure, which may be provided in a memory. Referring to FIG2 , the signal processing circuit includes: a pulse stretching circuit and an address decoding circuit;

[0036] The pulse stretching circuit is used to receive the command signal and the address signal, and stretch the pulse width of the address signal according to the command signal to generate an address stretching signal;

[0037] The input end of the address decoding circuit is coupled to the output end of the pulse stretching circuit, and is used for receiving the address stretching signal, decoding the address stretching signal, and generating an address decoding signal corresponding to the address signal.

[0038] In the embodiment of the present disclosure, the command signal includes but is not limited to at least one of the following: a PRE command signal, a REF (Refresh) command signal, or an RFM (Refresh Management) command signal.

[0039] The PRE command signal is used to precharge any row in any BG, any BA, or any other memory cell, raising the voltages of both the BL (bit line) and BLB (complementary bit line) in the row to a reference voltage. The PRE command signal corresponds to an address signal, which includes a BG address signal, a BA address signal, and a row address signal.

[0040] The above-mentioned REF command signals are used to refresh data in the memory, including REFsb (Refresh Same Bank, specified memory bank refresh) command signal, REFab (Refresh All Bank, full memory bank refresh) command signal, SREF (Self Refresh, self refresh) command signal and AREF (Auto Refresh, automatic refresh) command signal.

[0041] The REFsb command signal is used to refresh the data of the specified BA of all BGs in the memory. Therefore, it does not carry the BG address signal, but carries the BA address signal.

[0042] The REFab command signal is used to refresh data for all BAs of all BGs in the memory, and therefore, does not carry BG address signals and BA address signals. The above-mentioned RFM command signal is used to manage data refresh for the memory, and is divided into two types: RFMsb (Refresh Management Same Bank, specified memory bank refresh management) command signal and RFMab (Refresh Management All Bank, full memory bank refresh management) command signal. Similarly, the RFMsb command signal is used to manage data refresh for the specified BA of all BGs in the memory, and therefore, does not carry BG address signals, but does carry BA address signals. The RFMab command signal is used to manage data refresh for all BAs of all BGs in the memory, and therefore, does not carry BG address signals and BA address signals.

[0043] In addition, the address signal includes at least one of the following: a BG address signal and a BA address signal. The BG address signal can be a multi-bit BG address signal, and the BA address signal can also be a multi-bit BA address signal. For some command signals, the corresponding address signal includes not only the BG address signal but also the BA address signal. For example, the aforementioned PRE command signal. For some command signals, the corresponding address signal includes only the BA address signal, for example, the aforementioned REFsb command signal and the aforementioned RFMsb command signal.

[0044] In summary, the disclosed embodiments are applicable to command execution scenarios involving command signals that carry address signals. In such scenarios, the address signal can be pulse-stretched to obtain an address-stretched signal, which can be used together with the command signal to execute the command. In command execution scenarios involving command signals that do not carry address signals, the address signal does not have pulses. Therefore, the results of pulse stretching the address signal and not performing pulse stretching are the same. However, for circuit uniformity, a pulse stretching circuit is provided before the address decoding circuit.

[0045] It is understood that when the pulse width of the address signal is stretched using the command signal, the pulse width of the stretched address signal is correlated with the frequency of the command signal. That is, the pulse width of the stretched address signal is the same as the time interval between two adjacent pulses of the command signal. For example, when the command signal is sent every 2 TCKs, the pulse width of the address signal can be stretched to 2 TCKs; when the command signal is sent every 5 TCKs, the pulse width of the address signal can be stretched to 5 TCKs. The above-mentioned address stretch signal generation process includes two cases.

[0046] In the first case, when a rising edge appears in the command signal and the rising edge samples the valid level of the address stretch signal, a pulse of the address stretch signal starts; when the next rising edge appears in the command signal and the rising edge does not sample the valid level of the address stretch signal, the pulse of the address stretch signal ends.

[0047] In the second case, when a falling edge appears in the command signal and the falling edge samples the valid level of the address stretch signal, a pulse of the address stretch signal starts; when the next rising edge appears in the command signal and the falling edge does not sample the valid level of the address stretch signal, the pulse of the address stretch signal ends.

[0048] In some embodiments, the pulse stretching circuit may include a first trigger, which may be any trigger, for example, a DFF (D flip-flop). Therefore, the disclosed embodiment can achieve pulse stretching of the address signal using a simple trigger, thereby reducing circuit complexity as much as possible. The clock input of the first trigger includes two clock inputs: a positive phase clock input and a negative phase clock input. The signal received by the positive phase clock input is opposite in phase to the signal received by the negative phase clock input. The positive phase clock input is used to sample data using the rising edge of the received signal, and the negative phase clock input is used to sample data using the falling edge of the received signal.

[0049] In the embodiment of the present disclosure, the in-phase clock input terminal of the first flip-flop is used to receive the stretch control signal, and the inverting clock input terminal of the first flip-flop is used to receive the inverted signal of the stretch control signal.

[0050] The stretch control signal may be the command signal or the inverted signal of the command signal. When the stretch control signal received at the in-phase clock input of the first flip-flop is the command signal, the inverted signal of the stretch control signal received at the inverted clock input of the first flip-flop is the inverted signal of the command signal. When the stretch control signal received at the in-phase clock input of the first flip-flop is the inverted signal of the command signal, the inverted signal of the stretch control signal received at the inverted clock input of the first flip-flop is the command signal.

[0051] 3 or 5 , the first flip-flop DFF1 further includes a data input terminal D for receiving an address signal. Therefore, under the control of the stretch control signal, the first flip-flop DFF1 can stretch the pulse width of the address signal to generate and output a stretched address signal through the output terminal Q.

[0052] To obtain the inverted signal of the command signal, the signal processing circuit of the embodiment of the present disclosure may include an inverter in addition to the first flip-flop. To ensure that the command signal and its inverted signal reach the first flip-flop simultaneously, a transfer gate (TG) may be provided to transmit the input signal. The time required for the transfer gate to transmit the input signal is the same as the time required for the inverter to invert the input signal.

[0053] When the stretch control signal is a command signal, as shown in FIG3 , the input terminal of the inverter INV is used to receive the command signal, and the output terminal of the inverter INV is coupled to the inverting clock input terminal CLKB of the first flip-flop DFF1, for outputting the inverted signal of the command signal to the first flip-flop DFF1. In this case, the input terminal of the transmission gate TG is used to receive the command signal, and the output terminal of the transmission gate TG is coupled to the non-inverting clock input terminal CLK of the first flip-flop DFF1, for outputting the command signal as the stretch control signal to the first flip-flop DFF1.

[0054] Based on the circuit shown in FIG3 , FIG4 is a schematic diagram of expanding an address signal through a command signal provided by an embodiment of the present disclosure.

[0055] As shown in Figure 3 , since the command signal is input to the non-inverting input terminal CLK of the first flip-flop DFF1, the command signal can pulse stretch the address signal via its rising edge. As shown in Figure 4 , when the command signal experiences a rising edge at time t1, the first flip-flop DFF1 samples the address signal and outputs a high-level address-stretched signal. When the command signal experiences the next rising edge at time t2, the first flip-flop DFF1 samples the address signal and outputs a low-level address-stretched signal.

[0056] As shown in Figure 3 , since the inverted signal of the command signal is input to the inverting input terminal CLKB of the first flip-flop DFF1, the inverted signal of the command signal can also perform pulse stretching on the address signal via its falling edge. As shown in Figure 4 , when the inverted signal of the command signal experiences a falling edge at time t1, the first flip-flop DFF1 samples the address signal and outputs a high-level address-stretched signal. When the inverted signal of the command signal experiences the next falling edge at time t2, the first flip-flop DFF1 samples the address signal and outputs a low-level address-stretched signal.

[0057] As can be seen from Figure 4 above, the first trigger can achieve pulse stretching of the address signal through the command signal or the inverted signal of the command signal, so that the pulse width of the address stretching signal is the same as the time interval between two adjacent rising edges of the command signal, or the same as the time interval between two adjacent falling edges of the inverted signal of the command signal.

[0058] When the stretch control signal is the inverted signal of the command signal, as shown in FIG5 , the input of the inverter INV is used to receive the command signal, and the output of the inverter INV is coupled to the non-inverting clock input CLK of the first flip-flop DFF1, for transmitting the inverted signal of the command signal to the first flip-flop DFF1 as the stretch control signal. In this case, the input of the transmission gate TG is used to receive the command signal, and the output of the transmission gate TG is coupled to the inverted clock input CLKB of the first flip-flop DFF1, for transmitting the command signal to the first flip-flop DFF1.

[0059] Based on the circuit shown in FIG5 , FIG6 is a schematic diagram of expanding an address signal through a command signal provided by an embodiment of the present disclosure.

[0060] As shown in Figure 5 , since the inverted signal of the command signal is input to the non-inverting input terminal CLK of the first flip-flop DFF1, the inverted signal of the command signal can pulse stretch the address signal via its rising edge. As shown in Figure 6 , when the inverted signal of the command signal experiences a rising edge at time t3, the first flip-flop DFF1 samples the address signal and outputs a high-level address-stretched signal. When the inverted signal of the command signal experiences the next rising edge at time t4, the first flip-flop DFF1 samples the address signal and outputs a low-level address-stretched signal.

[0061] As shown in Figure 5 , since the command signal is input to the inverting input terminal CLKB of the first flip-flop DFF1, the command signal can also stretch the address signal through its falling edge. As shown in Figure 6 , when the command signal experiences a falling edge at time t3, the first flip-flop DFF1 samples the address signal and outputs a high-level address-stretched signal. When the command signal experiences the next falling edge at time t4, the first flip-flop DFF1 samples the address signal and outputs a low-level address-stretched signal.

[0062] As can be seen from Figure 6 above, the first trigger can achieve pulse stretching of the address signal through the inverted signal of the command signal or the command signal, so that the pulse width of the address stretching signal is the same as the time interval between two adjacent rising edges of the inverted signal of the command signal, or the same as the time interval between two adjacent falling edges of the command signal.

[0063] In some embodiments, referring to FIG. 7 or FIG. 8 , the signal processing circuit further includes a preprocessing circuit. The preprocessing circuit has a first output terminal and a second output terminal. The first output terminal of the preprocessing circuit is coupled to an input terminal of the pulse stretching circuit for receiving a command signal, and the second output terminal of the preprocessing circuit is coupled to an input terminal of the pulse stretching circuit for receiving an address signal. The preprocessing circuit is configured to receive a command address signal (CA signal) sent by an external circuit, and to decode and amplify the CA signal to obtain a command signal and an address signal. In this way, the preprocessing circuit can output the command signal to the pulse stretching circuit via the first output terminal, and output the address signal to the pulse stretching circuit via the second output terminal.

[0064] Specifically, the CA signal includes multiple bit signals, some of which can be referred to as external command signals, and others as external address signals. The preprocessing circuit has multiple input terminals for receiving external command signals and external address signals, respectively, to decode and amplify the external command signals as command signals, and to amplify the external address signals as address signals. The decoding here is a conventional decoding operation and can be implemented using a conventional decoder. For example, a 5-bit signal can be decoded into a 32-bit signal.

[0065] The above-mentioned amplification can be understood as amplifying the amplitude of the received signal to obtain a full-amplitude signal.

[0066] The embodiment of the present disclosure can achieve amplification of the CA signal through the above-mentioned preprocessing circuit, thereby avoiding internal processing errors caused by signal attenuation and helping to further improve the accuracy of command execution.

[0067] In some embodiments, as shown in FIG7 , the signal processing circuit may further include: a synchronization circuit. The two input terminals of the synchronization circuit are respectively coupled to the output terminal of the address decoding circuit and the first output terminal of the preprocessing circuit, and are used to synchronize the address decoding signal and the command signal. The synchronization here can be understood as matching the address decoding signal and the command signal that were previously independently transmitted by the synchronization circuit, so that the subsequent processing circuit of the memory can match and merge the address decoding signal and the command signal. The address decoding signal is used to indicate the address targeted when executing the corresponding command signal. After synchronization by the synchronization circuit, the correspondence between the address decoding circuit and the command signal can be guaranteed to be accurate, which helps to further improve the accuracy of command execution.

[0068] The synchronization circuit may also include a second flip-flop. A data input terminal of the second flip-flop is coupled to an output terminal of the address decoding circuit to receive an address decoding signal output by the address decoding circuit. A clock input terminal of the second flip-flop is coupled to the first output terminal of the preprocessing circuit.

[0069] The second flip-flop may also be a DFF. The clock input terminal of the second flip-flop may be: a non-inverting clock input terminal of the second flip-flop, or a reversed clock input terminal of the second flip-flop.

[0070] As can be seen in Figure 7, the input of the synchronization circuit is directly connected to the first output of the preprocessing circuit. However, the disclosed embodiment introduces a pulse stretching circuit and an address decoding circuit. When the preprocessing circuit outputs both an address signal and a command signal, the delay introduced by the pulse stretching circuit and the address decoding circuit can cause the command signal to arrive at the synchronization circuit earlier than the address decoding signal. In this case, the synchronization accuracy of the synchronization circuit will be poor.

[0071] To address the above issues, as shown in FIG8 , the signal processing circuit further includes a delay circuit. The input of the delay circuit is coupled to the first output of the preprocessing circuit. The first output is the output of the preprocessing circuit for outputting a command signal. Thus, the preprocessing circuit can output the command signal to the delay circuit.

[0072] The output of the delay circuit is coupled to the input of the synchronization circuit and is configured to delay the command signal before outputting it to the synchronization circuit to match the delay introduced by the pulse stretching circuit and the address decoding circuit (referred to as the first delay). The first delay is the sum of the delay introduced by the pulse stretching circuit and the delay introduced by the address decoding circuit.

[0073] The delay circuit includes an even number of inverters connected in series, thereby ensuring that the output signal of the delay circuit is in phase with the input signal of the delay circuit. For example, the number of inverters included in the delay circuit can be determined based on the first delay, so that the second delay of the delay circuit is as close as possible to the first delay. Ideally, the first delay and the second delay are the same. Therefore, the number of inverters in the delay circuit can be calculated by dividing the first delay by the delay of one inverter and rounding the result.

[0074] In summary, the disclosed embodiments can ensure that the address decode signal and the command signal arrive at the synchronization circuit as simultaneously as possible through the delay circuit shown in FIG8 , based on the simultaneous output of the command signal and the address signal by the preprocessing circuit. This improves the synchronization accuracy of the synchronization circuit for the address decode signal and the delayed signal.

[0075] In some embodiments, a post-processing circuit may be coupled to the synchronization circuit, and the post-processing circuit may include an even number of inverters connected in series, which is used to perform wave rectification or delay matching on the command signal and address stretching signal output by the synchronization circuit before executing the command operation.

[0076] It should be noted that the signal processing circuit in the embodiments of the present disclosure is used to process each bit of the address signal. If the address signal has multiple bits, then each bit corresponds to a corresponding signal processing circuit. For example, if the address signal is a 5-bit BGBA signal, then five of the above signal processing circuits are required to perform the above processing on each of the 5-bit BGBA signals.

[0077] An embodiment of the present disclosure further provides a memory comprising the aforementioned signal processing circuit.

[0078] The detailed description of the memory can refer to the detailed description of the aforementioned signal processing circuit, which will not be repeated here.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0080] For ease of explanation, the above description has been made with reference to specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations are possible. The above embodiments are selected and described to better explain the principles and practical applications, so that those skilled in the art can better utilize the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A signal processing circuit, comprising: Pulse stretching circuit and address decoding circuit; The pulse stretching circuit is used to receive a command signal and an address signal, and stretch the pulse width of the address signal through the command signal to generate an address stretching signal; The input end of the address decoding circuit is coupled to the output end of the pulse stretching circuit, and is used for receiving the address stretching signal, decoding the address stretching signal, and generating an address decoding signal corresponding to the address signal.

2. The signal processing circuit according to claim 1, wherein: The pulse stretching circuit comprises a first trigger (DFF1); The in-phase clock input terminal (CLK) of the first trigger (DFF1) is used to receive a widening control signal, and the widening control signal is the command signal or an inverted signal of the command signal. The data input terminal (D) of the first trigger (DFF1) is used to receive the address signal. The first trigger (DFF1) is used to widen the pulse width of the address signal under the control of the widening control signal, and generate and output the address widening signal through the output terminal (Q).

3. The signal processing circuit according to claim 2, wherein: The pulse stretching circuit also includes an inverter (INV) and a transmission gate (TG); The input end of the inverter (INV) is used to receive the command signal, and the output end of the inverter (INV) is coupled to the inverting clock input end (CLKB) of the first flip-flop (DFF1); The input end of the transmission gate (TG) is used to receive the command signal, and the output end of the transmission gate (TG) is coupled to the in-phase clock input end (CLK) of the first flip-flop (DFF1).

4. The signal processing circuit according to claim 2, wherein: The pulse stretching circuit also includes an inverter (INV) and a transmission gate (TG); The input end of the inverter (INV) is used to receive the command signal, and the output end of the inverter (INV) is coupled to the in-phase clock input end (CLK) of the first flip-flop (DFF1); The input end of the transmission gate (TG) is used to receive the command signal, and the output end of the transmission gate (TG) is coupled to the inverting clock input end (CLKB) of the first flip-flop (DFF1).

5. The signal processing circuit according to any one of claims 1 to 4, wherein: The signal processing circuit further includes: a preprocessing circuit; The first output terminal of the preprocessing circuit is coupled to the input terminal of the pulse stretching circuit for receiving the command signal, and the second output terminal of the preprocessing circuit is coupled to the input terminal of the pulse stretching circuit for receiving the command signal. The preprocessing circuit is used for receiving the command address signal, decoding and amplifying the command address signal to obtain the command signal and the address signal.

6. The signal processing circuit according to claim 5, wherein: Also includes: A synchronization circuit, wherein two input terminals of the synchronization circuit are respectively coupled to the output terminal of the address decoding circuit and the first output terminal of the preprocessing circuit, and is used for synchronizing the address decoding signal with the command signal.

7. The signal processing circuit according to claim 6, wherein: The synchronization circuit includes a second trigger, a data input terminal of the second trigger is coupled to the output terminal of the address decoding circuit, and a clock input terminal of the second trigger is coupled to the first output terminal of the pre-processing circuit.

8. The signal processing circuit according to claim 6 or 7, wherein: Also includes: A delay circuit, wherein the input end of the delay circuit is coupled to the first output end of the preprocessing circuit, and the output end of the delay circuit is coupled to the input end of the synchronization circuit, and is used to delay the command signal and output it to the synchronization circuit to match the delay introduced by the pulse stretching circuit and the address decoding circuit.

9. The signal processing circuit according to any one of claims 1 to 8, wherein: The address signal includes at least one of the following: a memory bank group address signal and a memory bank address signal; the command signal includes at least one of the following: a precharge command signal, a refresh command signal and a refresh management command signal. 10 . A memory comprising the signal processing circuit according to claim 1 .

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