Anti-single-event-burnout sic JFET device structure, and preparation method

Abstract

Disclosed in the present invention are an anti-single-event-burnout high-voltage trench-type SiC JFET device structure, and a preparation method. A cell of the new anti-single-event-burnout trench-type SiC JFET structure comprises: a metal drain electrode, an N+ substrate region, an N- drift region, metal gate electrodes, a P-type doped region formed by means of implanting ions into the bottom and side wall of a gate trench, a current spreading layer, an N+ source region, and a metal source electrode connected to the source region. The P-type doped region, as a whole, is connected to a gate electrode, wherein the interior of the P-type doped region is composed of P-type regions having different doping concentrations, and a heavily doped region is located at a corner of the gate trench. Regional P-type doping distribution in the present invention improves the electric-field situation in a device, and can effectively alleviate a local high-temperature situation in the device which is caused by heavy ion implantation, and a relatively good anti-single-event-burnout capability is achieved. Moreover, in the structure, a buffer layer is additionally provided in a drift region, thereby further improving the anti-single-event-burnout capability of the device.

Description

A SiC JFET device structure and preparation method resistant to single event burnout

[0001] This application claims priority to a Chinese patent application filed with the Patent Office of China on June 30, 2023, with application number 202310798197.7 and invention name “A SiC JFET device structure and preparation method resistant to single-particle burnout”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of semiconductor device technology, and more particularly to a SiC JFET device structure and a method for preparing the same. This device structure can be applied in the aerospace field, enabling the device to have a strong resistance to single-event burnout. Background Art

[0003] Silicon carbide (SiC) is a wide-bandgap semiconductor material. In addition to its large bandgap width, it also has the advantages of high breakdown field strength, high thermal conductivity, high carrier saturation mobility, and strong radiation resistance. It is particularly suitable for the harsh application environments of high temperature, high pressure, high current, high frequency, and strong radiation involved in modern power electronic systems. It has broad application prospects in rail transportation, new energy vehicles, photovoltaic power generation, aerospace and other fields.

[0004] Figure 8 is a schematic diagram of a traditional trench SiC JFET device structure. The main structure includes: a drain metal 1 on the back of the device cell structure, a SiC N+ substrate region 2, an N-drift region 3, an "L"-type P+ gate region 13, an N-type source region 10, a source metal 11, and a gate metal 12.

[0005] SiC Junction Field Effect Transistor (JFET) does not have the reliability and low mobility issues caused by the SiC / SiO2 gate oxide layer. At the same time, SiC JFET is a unipolar device, so it is very suitable for use in high-temperature, high-frequency and high-power switching tubes. However, there are high-energy charged particles from radiation sources such as cosmic rays and solar flares in the space environment. Although the intensity of the rays is low, the energy is high. When passing through semiconductor devices, they will produce ionization effects, triggering single event effects (SEE), which pose a serious threat to spacecraft. For SiC JFET, the incidence of various high-energy radiation particles will affect the internal characteristics of the device, and then cause the occurrence of single event burnout (SEB), resulting in device failure or damage. Therefore, it can be seen that single event burnout reinforcement design for devices and improving the ability to resist single events are major issues that need to be urgently addressed in the application of devices in the aerospace field.

[0006] Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the shortcomings of the existing technology and provide a SiC JFET device structure and preparation method that is resistant to single-particle burnout, so as to solve the problem of single-particle burnout of SiC devices caused by heavy ion bombardment in space applications.

[0008] The technical solution of the present invention is:

[0009] Firstly,

[0010] A single-event burnout-resistant SiC JFET device structure comprises: a drain metal, a SiC N+ substrate region, an N-lightly doped drift region, a first layer of P-type doped region, a second layer of P-type doped region, an N-type current spreading layer, a P-type gate region, an N-type source region, a source metal, and a gate metal;

[0011] The drain metal, SiC N+ substrate region and N- lightly doped drift region are arranged in sequence from bottom to top. In the middle of the N- lightly doped drift region, an N-type current spreading layer and an N-type source region are arranged in sequence from bottom to top.

[0012] The second layer of P-type doped region is located above the N-lightly doped drift region, and the first layer of P-type doped region is located above the second layer of P-type doped region;

[0013] The first layer of P-type doping region and the second layer of P-type doping region are arranged outside the N-type current spreading layer;

[0014] The P-type gate region is located outside the N-type current spreading layer, and the P-type gate region is located between the first layer of P-type doped region and the N-type source region in the vertical direction;

[0015] The source metal is arranged above the N-type source region; the gate metal is arranged outside the P-type gate region and in a partial region above the first layer of P-type doped region.

[0016] Preferably, the widths of the first layer of P-type doping region and the second layer of P-type doping region are the same.

[0017] Preferably, the thickness of the first P-type doping region is not less than 0.5 μm.

[0018] Preferably, the bottom of the N-type current spreading layer is flush with the bottom of the first P-type doped region.

[0019] Preferably, the doping concentration and thickness of the first layer of P-type doping region are greater than those of the second layer of P-type doping region.

[0020] Preferably, the first layer of P-type doping region includes: a P-type heavily doped region, a first P-type doping region and a second P-type doping region;

[0021] The P-type heavily doped region, the first P-type doped region and the second P-type doped region are arranged in sequence from the inside to the outside; the P-type heavily doped region is adjacent to the N-type current spreading layer.

[0022] Preferably, the width of the P-type doping region is more than 1 / 3 of the first layer of P-type doping region on one side, and the doping concentration of the P-type heavily doped region is greater than the doping concentration of the first P-type doping region and the second P-type doping region.

[0023] Preferably, the doping concentration of the first P-type doping region is not greater than the doping concentration of the second P-type doping region.

[0024] Secondly,

[0025] A method for preparing a SiC JFET device structure resistant to single event burnout, comprising:

[0026] Step 1: epitaxially growing a first layer of N-drift region on a SiC N+ substrate region;

[0027] Step 2: forming a first layer of N-type implantation region on the first layer of N-drift region by high-energy ion implantation; the doping concentration of the formed first layer of N-type implantation region is higher than that of the first layer of N-drift region;

[0028] Step 3: Use a photomask to mask a portion of the upper surface of the first layer N-type implantation region, and perform ion implantation to form a P-type implantation region;

[0029] Step 4: Based on the P-type implantation region formed in the above step 3, multiple ion implantations are performed on part of the P-type implantation region by using multiple photolithography and controlling the ion implantation energy to form a P-type heavily doped region, a first P-type doped region, and a second P-type doped region with different doping concentrations; a portion of the P-type implantation region located below the P-type heavily doped region, the first P-type doped region, and the second P-type doped region serves as a P-type lightly doped region;

[0030] Step 5: Based on the above step 4, epitaxial growth is performed again on the surface of the first layer of N-type implanted region to obtain a second layer of N-type drift region, where the second layer of N-type drift region covers the P-type heavily doped region, the first P-type doped region and the second P-type doped region;

[0031] Step 6: Perform ion implantation on the upper surface of the second layer N-type drift region to form an N+ implantation region as an N-type source region;

[0032] Step 7: performing gate trench etching on the second layer of N-type drift region to expose a portion of the upper surface of the P-type heavily doped region and to expose the entire upper surfaces of the first P-type doped region and the second P-type doped region;

[0033] Step 8: Use a photomask to block the exposed upper surface portions of the P-type heavily doped region, the first P-type doped region, and the second P-type doped region, and perform ion implantation on the trench sidewalls of the second layer of the N-type drift region to form a P-type gate region and obtain an N-type current spreading layer.

[0034] Step 9: Perform backside thinning and metal sputtering to form a drain metal on the surface of the SiC N+ substrate region; perform front side metal deposition to form a gate metal on the surface of the N-type source region, and form a source metal on the outside of the P-type gate region, the P-type heavily doped region, the first P-type doped region, and the second P-type doped region.

[0035] Thirdly,

[0036] A single-event burnout-resistant SiC JFET device structure comprises: a drain metal, a SiC N+ substrate region, an N-lightly doped drift region, a P-type doped region, an N-type current spreading layer, a P-type gate region, an N-type source region, a source metal, and a gate metal;

[0037] The drain metal, SiC N+ substrate region and N- lightly doped drift region are arranged in sequence from bottom to top. In the middle of the N- lightly doped drift region, an N-type current spreading layer and an N-type source region are arranged in sequence from bottom to top.

[0038] The P-type doped region is located above the N-lightly doped drift region, and the P-type doped region is arranged outside the N-type current spreading layer;

[0039] The P-type gate region is located outside the N-type current spreading layer, and the P-type gate region is located between the P-type doping region and the N-type source region in a vertical direction;

[0040] The source metal is arranged above the N-type source region; the gate metal is arranged outside the P-type gate region and in a portion of the region above the P-type doped region.

[0041] Preferably, the thickness of the P-type doping region is not less than 1.0 μm to 1.5 μm.

[0042] Preferably, the bottom of the N-type current spreading layer is higher than the bottom of the P-type doping region.

[0043] Preferably, the P-type doping region includes: a P-type heavily doped region, a first P-type doping region and a second P-type doping region;

[0044] The P-type heavily doped region, the first P-type doped region and the second P-type doped region are arranged in sequence from the inside to the outside; the P-type heavily doped region is adjacent to the N-type current spreading layer.

[0045] Preferably, the width of the P-type heavily doped region is more than 1 / 3 of the single-sided P-type doped region, and the doping concentration of the P-type heavily doped region is greater than the doping concentration of the first P-type doping region and the second P-type doping region.

[0046] Preferably, the doping concentration of the first P-type doping region is not greater than the doping concentration of the second P-type doping region.

[0047] Fourthly,

[0048] A method for preparing a SiC JFET device structure resistant to single event burnout, comprising:

[0049] Epitaxially growing a first N-drift region on the SiC N+ substrate region;

[0050] forming a first layer of N-type implantation region on the first layer of N-drift region by high-energy ion implantation; the doping concentration of the formed first layer of N-type implantation region is higher than that of the first layer of N-drift region;

[0051] Using a photomask to mask a portion of the upper surface of the first layer N-type implantation region, and performing ion implantation to form a P-type implantation region;

[0052] On the basis of the P-type implantation region, multiple ion implantations are performed on the P-type implantation region by using multiple photolithography and controlling the ion implantation energy to form a P-type heavily doped region, a first P-type doped region, and a second P-type doped region with different doping concentrations;

[0053] Epitaxial growth is again performed on the surface of the first layer of N-type implanted region to obtain a second layer of N-type drift region, wherein the second layer of N-type drift region covers the P-type heavily doped region, the first P-type doped region and the second P-type doped region;

[0054] Ion implantation is performed on the upper surface of the second layer of N-type drift region to form an N+ implantation region as an N-type source region;

[0055] Performing gate trench etching on the second layer of N-type drift region to expose a portion of the upper surface of the P-type heavily doped region and to expose the entire upper surfaces of the first P-type doped region and the second P-type doped region;

[0056] Using a photomask to block the exposed upper surface portions of the P-type heavily doped region, the first P-type doped region, and the second P-type doped region, ion implantation is performed on the trench sidewalls of the second layer N-type drift region to form a P-type gate region and obtain an N-type current spreading layer;

[0057] Backside thinning and metal sputtering are performed to form a drain metal on the surface of the SiC N+ substrate region; metal is deposited on the front side to form a gate metal on the surface of the N-type source region, and a source metal is formed outside the P-type gate region, the P-type heavily doped region, the first P-type doped region, and the second P-type doped region.

[0058] The advantages of the present invention compared with the prior art are:

[0059] Based on the traditional trench-type SiC JFET, the present invention performs a zoned design of doping concentration for key locations in the P-type doped region at the bottom of the gate trench. A heavily doped and relatively wide P-type heavily doped region is added at the contact position between the P-type doped region and the N-drift region in the device channel region, so that the PN junction formed by the P-type heavily doped region and the N-drift region bears part of the high electric field intensity caused by heavy ion incidence, which can effectively improve the local electric field concentration caused by heavy ion incidence; the second P-type doped region in the P-type doped region can reduce the lateral electric field distribution without changing the breakdown voltage. At the same time, combined with the design of the P-type lightly doped region below, the electric field inside the P-type doped region can be diffused to the surrounding areas, further alleviating the problem of uneven distribution inside the P-type doped region. Through the above design, when a single-particle effect occurs, the occurrence of local high electric field concentration inside the device can be alleviated, the temperature distribution inside the device can be improved, and the device can achieve good resistance to single-particle burnout. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] FIG1 is a schematic structural diagram of a device according to the present invention;

[0061] FIG2 is a curve showing the change of electric field distribution with heavy ion incident distance for the structure of the present invention and the conventional trench SiC JFET device after heavy ion incident for 100 ps;

[0062] FIG3 is a curve showing the change of lattice temperature with heavy ion incident distance for the structure of the present invention and the conventional trench SiC JFET device after heavy ion incident for 1 ns;

[0063] FIG4 is a curve showing the change of lattice temperature over time for the structure of the present invention and the conventional trench SiC JFET device after heavy ion incidence;

[0064] FIG5 is a schematic flow diagram of a method for preparing a structure of the present invention;

[0065] FIG6 is a SiC JFET reinforcement structure for adjusting the distribution of the P-type doping region to resist single event burnout according to the present invention;

[0066] FIG7 is a SiC JFET reinforcement structure for resisting single-particle burnout by adding an additional buffer layer structure based on the present invention;

[0067] Figure 8 shows the structure of a conventional trench SiC JFET. DETAILED DESCRIPTION

[0068] Figure 1 shows a novel SiC JFET device structure resistant to single-event burnout (SEB). This structure differs primarily from conventional structures in the P-type doping region. In this invention, the P-type doping region consists of a P-type doping region and a P-type gate region 9 on the sidewalls of the gate trench. The P-type gate region at the bottom of the conventional gate trench is extended downward and partitioned with different doping concentrations to achieve improved SEB resistance. Furthermore, an N-type CSL 8 is added to the channel region to enhance the device's forward conduction capability.

[0069] The present invention discloses a SiC JFET device structure resistant to single-event burnout, as shown in FIG1 , comprising: a drain metal 1 on the back side of the device cell structure, a SiC N+ substrate region 2, an N- lightly doped drift region 3, a first layer of P-type doped region, a second layer of P-type doped region (i.e., a P-type lightly doped region 4), an N-type current spreading layer 8, a P-type gate region 9, an N-type source region 10, a source metal 11, and a gate metal 12. The drain metal 1, SiC N+ substrate region 2 and N- lightly doped drift region 3 are arranged in sequence from bottom to top, and an N-type current spreading layer 8 and an N-type source region 10 are arranged in the middle of the N- lightly doped drift region 3; the second layer of P-type doped region is located above the N- lightly doped drift region 3, and the first layer of P-type doped region is located above the second layer of P-type doped region; the first layer of P-type doped region and the second layer of P-type doped region are arranged outside the N-type current spreading layer 8; the P-type gate region 9 is located outside the N-type current spreading layer 8, and the P-type gate region 9 is located vertically between the first layer of P-type doped region and the N-type source region 10; the source metal 11 is arranged above the N-type source region 10; the gate metal 12 is arranged outside the P-type gate region 9 and in a partial area above the first layer of P-type doped region.

[0070] The width of the first layer P-type doping region and the second layer P-type doping region are the same. The thickness of the first layer P-type doping region is not less than 0.5 μm. The bottom of the N-type current spreading layer 8 is flush with the bottom of the first layer P-type doping region.

[0071] The doping concentration and thickness of the first layer P-type doping region are both greater than those of the second layer P-type doping region.

[0072] The first layer of P-type doped region includes: a P-type heavily doped region 5, a first P-type doped region 6 and a second P-type doped region 7; the P-type heavily doped region 5, the first P-type doped region 6 and the second P-type doped region 7 are arranged in sequence from the inside to the outside; the P-type heavily doped region 5 is adjacent to the N-type current spreading layer 8.

[0073] The width of the P-type doping region 5 is more than 1 / 3 of the width of the first P-type doping region on one side, and the doping concentration of the heavily P-type doping region 5 is greater than the doping concentrations of the first P-type doping region 6 and the second P-type doping region 7. The doping concentration of the first P-type doping region 6 is not greater than the doping concentration of the second P-type doping region 7.

[0074] A method for preparing a SiC JFET device structure resistant to single event burnout, comprising:

[0075] Step 1: epitaxially growing a first layer of N-drift region on the SiC N+ substrate region 2;

[0076] Step 2: forming a first layer of N-type implantation region on the first layer of N-drift region by high-energy ion implantation; the doping concentration of the formed first layer of N-type implantation region is higher than that of the first layer of N-drift region;

[0077] Step 3: Using a photomask to mask a portion of the upper surface of the first layer N-type implant region, ion implantation is performed to form a P-type implant region; symmetrical P-type implant regions are formed on both sides of the device by ion implantation, and the width of the P-type implant region on one side is less than or equal to the width of the remaining unmasked first layer N-type implant region;

[0078] Step 4: Based on the P-type implantation region formed in the above step 3, multiple ion implantations are performed on part of the P-type implantation region by using multiple photolithography and controlling the ion implantation energy to form a P-type heavily doped region 5, a first P-type doped region 6, and a second P-type doped region 7 with different doping concentrations; a portion of the P-type implantation region located below the P-type heavily doped region 5, the first P-type doped region 6, and the second P-type doped region 7 serves as the P-type lightly doped region 4;

[0079] Step 5: Based on the above step 4, epitaxial growth is performed again on the surface of the first layer of N-type implanted region to obtain a second layer of N-type drift region with higher concentration, and the second layer of N-type drift region covers the P-type heavily doped region 5, the first P-type doped region 6 and the second P-type doped region 7;

[0080] Step 6: Perform ion implantation on the upper surface of the second N-type drift region with a higher concentration to form an N+ implantation region as the N-type source region 10;

[0081] Step 7: performing gate trench etching on the second layer of N-type drift region above the P-type doped regions on both sides of the cell structure, exposing a portion of the upper surface of the P-type heavily doped region 5 and fully exposing the upper surfaces of the first P-type doped region 6 and the second P-type doped region 7;

[0082] Step 8: Use a photomask to block the exposed upper surface portions of the P-type heavily doped region 5, the first P-type doped region 6, and the second P-type doped region 7, and perform ion implantation on the trench sidewalls of the second layer of the N-type drift region to form a P-type gate region 9 and obtain an N-type current spreading layer 8;

[0083] Step 9: Perform backside thinning and metal sputtering to form a drain metal 1 on the surface of the SiC N+ substrate region 2; perform front side metal deposition to form a gate metal 12 on the surface of the N-type source region 10, and form a source metal 11 on the outside of the P-type gate region 9, the P-type heavily doped region 5, the first P-type doped region 6, and the second P-type doped region 7.

[0084] The present invention discloses a SiC JFET device structure resistant to single-event burnout, as shown in FIG6 , comprising: a drain metal 1, a SiC N+ substrate region 2, an N- lightly doped drift region 3, a P-type doped region, an N-type current spreading layer 8, a P-type gate region 9, an N-type source region 10, a source metal 11, and a gate metal 12. The drain metal 1, SiC N+ substrate region 2 and N- lightly doped drift region 3 are arranged in sequence from bottom to top. In the middle of the N- lightly doped drift region 3, an N-type current spreading layer 8 and an N-type source region 10 are arranged in sequence from bottom to top; the P-type doped region is located above the N- lightly doped drift region 3, and the P-type doped region is arranged on the outside of the N-type current spreading layer 8; the P-type gate region 9 is located on the outside of the N-type current spreading layer 8, and the P-type gate region 9 is located vertically between the P-type doped region and the N-type source region 10; the source metal 11 is arranged above the N-type source region 10; the gate metal 12 is arranged on the outside of the P-type gate region 9 and in a partial area above the P-type doped region.

[0085] The thickness of the P-type doped region is no less than 1.0 μm to 1.5 μm. The bottom of the N-type current spreading layer 8 is higher than the bottom of the P-type doped region. The P-type doped region includes: a P-type heavily doped region 5, a first P-type doped region 6, and a second P-type doped region 7; the P-type heavily doped region 5, the first P-type doped region 6, and the second P-type doped region 7 are arranged in sequence from the inside to the outside; the P-type heavily doped region 5 is adjacent to the N-type current spreading layer 8.

[0086] The width of the P-type heavily doped region 5 is more than 1 / 3 of the width of the single-sided P-type doped region, and the doping concentration of the P-type heavily doped region 5 is greater than the doping concentrations of the first P-type doping region 6 and the second P-type doping region 7. The doping concentration of the first P-type doping region 6 is not greater than the doping concentration of the second P-type doping region 7.

[0087] A method for preparing a SiC JFET device structure resistant to single event burnout, comprising:

[0088] Epitaxially growing a first layer of N-drift region on the SiC N+ substrate region 2;

[0089] forming a first layer of N-type implantation region on the first layer of N-drift region by high-energy ion implantation; the doping concentration of the formed first layer of N-type implantation region is higher than that of the first layer of N-drift region;

[0090] Using a photomask to mask a portion of the upper surface of the first layer N-type implantation region, and performing ion implantation to form a P-type implantation region;

[0091] On the basis of the P-type implantation region, multiple ion implantations are performed on the P-type implantation region by using multiple photolithography and controlling the ion implantation energy to form a P-type heavily doped region 5, a first P-type doped region 6, and a second P-type doped region 7 with different doping concentrations;

[0092] Epitaxial growth is again performed on the surface of the first layer of N-type implanted region to obtain a second layer of N-type drift region, which covers the P-type heavily doped region 5, the first P-type doped region 6 and the second P-type doped region 7;

[0093] Ion implantation is performed on the upper surface of the second layer of N-type drift region to form an N+ implantation region as an N-type source region 10;

[0094] Perform gate trench etching on the second layer of N-type drift region to expose part of the upper surface of the P-type heavily doped region 5 and expose the entire upper surfaces of the first P-type doped region 6 and the second P-type doped region 7;

[0095] Use a photomask to block the exposed upper surface portions of the P-type heavily doped region 5, the first P-type doped region 6, and the second P-type doped region 7, and perform ion implantation on the trench sidewalls of the second layer N-type drift region to form a P-type gate region 9 and obtain an N-type current spreading layer 8;

[0096] Backside thinning and metal sputtering are performed to form drain metal 1 on the surface of SiC N+ substrate region 2. Metal deposition is performed on the front side to form gate metal 12 on the surface of N-type source region 10, and source metal 11 is formed outside P-type gate region 9, P-type heavily doped region 5, first P-type doped region 6, and second P-type doped region 7. The device structure shown in Figure 6 is obtained after the preparation is completed.

[0097] Example

[0098] As shown in Figure 2, TCAD simulation software was used to simulate the internal electric field distribution of the device after heavy ion injection. During the simulation, the particles were incident vertically from the P gate region of the JFET device, which is the sensitive position of the trench JFET to particle injection. The particle injection energy was LET = 75.5 MeV / mg / cm 2 , the bias voltage when the particle is incident is V DS =500V. By comparing the electric field distribution of the two device structures, it can be seen that the traditional trench JFET device is affected by the impact of particle incidence, and generally generates a high peak electric field at the junction of the N-drift region and the N+ substrate. Excessive electric field strength may cause the local temperature of the device to be too high, resulting in a single particle burnout effect in the device. In the structure proposed by the present invention, due to the partitioned design of the gate area, the electric field is shared by the gate P-type region and the N-drift region, as well as the junction of the N-drift region and the N+ substrate. The electric field peak is significantly reduced, which has a better effect of strengthening against single particle burnout.

[0099] SiC-based N-type heavily doped substrate region 2; drain metal electrode 1 on the back of the N-type heavily doped substrate region 2; N-lightly doped drift region 3 on the upper part of the N-type heavily doped substrate region 2; P-type lightly doped region 4 located at the bottom of the gate trench and above the N-drift region 3; a first layer of P-type doped region composed of the P-type heavily doped region 5, the first P-type doped region 6 and the second P-type doped region 7, which is located above the P-type lightly doped region 4 and has the same width as the P-type lightly doped region 4. The thickness of the first layer of P-type doped region is greater than the P-type lightly doped region 4 and is not less than 0.5μm. The width of the P-type doped region 5 adjacent to the N-drift region 3 accounts for more than 1 / 3 of the single-sided P-type injection region, and the doping concentration is the highest among the P-type injection regions, so as to ensure the improvement effect of the three on the local high electric field caused by heavy ion incidence; N-type current spreading layer (Current Spreading Layer The CSL (Current Layer) 8 is located in the middle neck of the device, and its doping concentration is slightly higher than the N-drift region doping concentration 3; the P-type gate region 9 is distributed on both sides of the CSL region 8 and is located above the P-type heavily doped region 5; the N-type source region 10 is located above the CSL region 8 of the device; the source metal 11 is above the N-type source region 10; and the gate metal 12 fills the gate trenches on both sides of the device cell structure.

[0100] The doping concentrations of the three P-type regions, namely the P-type heavily doped region 5, the first P-type doped region 6 and the second P-type doped region 7, are different. The doping concentrations of the P-type heavily doped region 5 and the second P-type doped region 7 are significantly higher than that of the first P-type doped region 6. The doping concentration of the P-type heavily doped region 5 is the highest among the three, so as to ensure the device's ability to resist single-particle burnout.

[0101] The lateral widths of the three P-type regions—the heavily P-type doped region 5, the first P-type doped region 6, and the second P-type doped region 7—are unequal. To ensure the device's resistance to single-event burnout, the heavily P-type doped region 5 should be located below the bottom corner of the gate trench and should be no less than one-third the overall width of the P-type doped region at the bottom of the single-sided gate trench.

[0102] The bottom of the N-type CSL region 8 is flush with the bottom of the first layer of P-type doped region, so as to improve the forward conduction capability of the device.

[0103] FIG3 shows the curves of the lattice temperature change with the incident distance of the structure of the present invention and the traditional trench-type SiC JFET device after 1 ns of heavy ion incidence. The temperature at each position of the structure of the present invention is significantly lower than that of the traditional structure, the overall temperature distribution inside the device is more uniform, and the two peak temperatures are reduced by about half. FIG4 shows the curves of the lattice temperature change with time of the structure of the present invention and the traditional trench-type SiC JFET device after heavy ion incidence. The lattice temperature of the device of the traditional structure cannot be restored immediately after the radiation process ends, and the device temperature remains at a relatively high temperature level, indicating that the device has been bombarded with heavy ions and has suffered irreversible radiation damage; while the lattice temperature of the device of the structure of the present invention drops rapidly after the heavy ion radiation process ends, and can be restored to the lower temperature level before the radiation occurs. Therefore, the SiC JFET structure proposed in the present invention has a better reinforcement effect against single-particle burnout.

[0104] FIG5 is a schematic diagram of the process flow of the method for fabricating a SiC JFET structure resistant to single-particle burnout in the present invention, and FIG5 is a schematic diagram of the process flow of each step in the fabrication of the present invention. The fabrication method includes the following steps:

[0105] 1. Epitaxially grow the first N-drift region 3 on the N+ substrate layer 2. The thickness of the N-drift region is 8μm to 12μm, and the doping concentration is 3e15cm -3 ~1e16cm -3 , as shown in ① in Figure 5;

[0106] 2. Nitrogen (N) ion implantation is performed on the N-drift region to form an N-type region with a higher doping concentration of 1e16 cm -3 ~5e16cm -3 , as shown in ② in Figure 5;

[0107] 3. Use a photomask to partially block the film, then perform aluminum (Al) ion implantation to form two centrally symmetrical P-type implantation regions with an implantation depth of 1.0 μm to 1.5 μm and a doping concentration of 1e17 cm -3 ~5e17cm -3 , as shown in ③ in Figure 5;

[0108] 4. Using multiple photolithography with different photomasks and controlling the high-energy ion implantation energy, multiple aluminum (Al) ion implantations are performed to form P-type implant regions with different doping concentrations. The implantation depth is between 0.6 μm and 1.0 μm. The doping concentration of the P-type heavily doped region 5 near the channel region is the highest, at 5e18 cm -3 ~5e19cm -3 , as shown in ④ in Figure 5;

[0109] 5. Based on the above step 4, a second layer of drift region with higher concentration is epitaxially grown on the surface of the first layer of N-drift region. The N-type doping concentration is the same as that implanted in step 2, which is 1e16 cm -3 ~5e16cm -3 , as shown in ⑤ in Figure 5;

[0110] 6. Nitrogen (N) ion implantation is performed on the second drift region with a higher concentration to form an N+ heavily doped N-type source region 10 with a doping concentration of 1e18 cm -3 ~1e20cm -3 , as shown in ⑥ in Figure 5;

[0111] 7. Make a mask medium and perform gate trench etching through photolithography and etching processes, as shown in Figure 5 (7);

[0112] 8. Use a photomask to block the P region and perform P-type ion implantation on the trench sidewall to form a complete P+ gate region with a doping concentration of 1e18cm -3 ~1e19cm -3 , as shown in ⑧ in Figure 5;

[0113] 9. Thin the back side and sputter metal to form an ohmic contact for the drain. Deposit metal on the front side to form the gate and source, as shown in ⑨ in Figure 5.

[0114] Another embodiment of the present invention, as shown in Figure 6, does not include the P-type lightly doped region 4. Without changing the doping concentration of other P-type regions, the original first layer of P-type doped regions (the P-type heavily doped region 5, the first P-type doped region 6, and the second P-type doped region 7) is thickened downward, thereby achieving the same single-event burnout resistance. The thickness of the first layer of P-type doped regions is not less than 1.0 μm to 1.5 μm. The bottom of the N-type current spreading layer 8 is higher than the bottom of the first layer of P-type doped regions.

[0115] As shown in FIG7 , the present invention can add one or more N-type buffer layers (N Buffer Layer) at the junction of the N+ substrate and the epitaxial N-drift region in the device structure to change the electric field distribution of the device and further enhance the device's resistance to single event burnout.

[0116] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention are within the scope of protection of the technical solutions of the present invention. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0117] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A SiC JFET device structure resistant to single-particle burnout, characterized in that: include: Drain metal (1), SiC N+ substrate region (2), N-lightly doped drift region (3), a first layer of P-type doping region, a second layer of P-type doping region, an N-type current spreading layer (8), a P-type gate region (9), an N-type source region (10), a source metal (11) and a gate metal (12); A drain metal (1), a SiC N+ substrate region (2) and an N-lightly doped drift region (3) are sequentially arranged from bottom to top, and an N-type current spreading layer (8) and an N-type source region (10) are sequentially arranged in the middle of the N-lightly doped drift region (3) from bottom to top; The second layer of P-type doping region is located above the N-lightly doped drift region (3), and the first layer of P-type doping region is located above the second layer of P-type doping region; The first layer of P-type doping region and the second layer of P-type doping region are arranged outside the N-type current spreading layer (8); The P-type gate region (9) is located outside the N-type current spreading layer (8), and the P-type gate region (9) is located between the first layer of P-type doping region and the N-type source region (10) in the vertical direction; The source metal (11) is arranged above the N-type source region (10); and the gate metal (12) is arranged outside the P-type gate region (9) and in a partial region above the first layer of the P-type doped region.

2. A SiC JFET device structure resistant to single event burnout according to claim 1, characterized in that: The widths of the first layer of P-type doping region and the second layer of P-type doping region are the same.

3. The SiC JFET device structure resistant to single event burnout according to claim 1, characterized in that: The thickness of the first P-type doping region is not less than 0.5 μm.

4. The SiC JFET device structure resistant to single event burnout according to claim 1, characterized in that: The bottom of the N-type current spreading layer (8) is flush with the bottom of the first layer of P-type doping region.

5. A SiC JFET device structure resistant to single event burnout according to any one of claims 2 to 4, characterized in that: The doping concentration and thickness of the first layer P-type doping region are greater than those of the second layer P-type doping region.

6. The SiC JFET device structure resistant to single event burnout according to claim 5, characterized in that: The first layer of P-type doping region comprises: a P-type heavily doped region (5), a first P-type doping region (6) and a second P-type doping region (7); The P-type heavily doped region (5), the first P-type doped region (6) and the second P-type doped region (7) are arranged in sequence from the inside to the outside; the P-type heavily doped region (5) is adjacent to the N-type current spreading layer (8).

7. A SiC JFET device structure resistant to single event burnout according to claim 6, characterized in that: The width of the P-type heavily doped region (5) accounts for more than 1 / 3 of the width of the first layer of the P-type doped region on one side, and the doping concentration of the P-type heavily doped region (5) is greater than the doping concentrations of the first P-type doped region (6) and the second P-type doped region (7).

8. The SiC JFET device structure resistant to single event burnout according to claim 7, characterized in that: The doping concentration of the first P-type doping region (6) is not greater than the doping concentration of the second P-type doping region (7).

9. A method for preparing a SiC JFET device structure resistant to single particle burnout, characterized in that: include: Epitaxially growing a first layer of N-drift region on the SiC N+ substrate region (2); Forming a first layer of N-type implantation region on the first layer of N-drift region by high energy ion implantation; The doping concentration of the formed first layer N-type implantation region is higher than that of the first layer N-drift region; Using a photomask to cover a portion of the upper surface of the first layer N-type implantation region, and performing ion implantation to form a P-type implantation region; On the basis of the P-type injection region, multiple ion implantations are performed on part of the P-type injection region by means of multiple photolithography and control of ion implantation energy to form a P-type heavily doped region (5), a first P-type doped region (6) and a second P-type doped region (7) with different doping concentrations; a part of the P-type injection region located below the P-type heavily doped region (5), the first P-type doped region (6) and the second P-type doped region (7) is used as a P-type lightly doped region (4); Epitaxial growth is again performed on the surface of the first layer of N-type implanted region to obtain a second layer of N-type drift region, wherein the second layer of N-type drift region covers the P-type heavily doped region (5), the first P-type doped region (6) and the second P-type doped region (7); On the upper surface of the second layer N-type drift region, ion implantation is performed to form an N+ implantation region as an N-type source Polar region (10); Performing gate trench etching on the second layer N-type drift region to expose a portion of the upper surface of the P-type heavily doped region (5) and to expose the entire upper surfaces of the first P-type doped region (6) and the second P-type doped region (7); Using a photoresist to block the exposed upper surface portions of the P-type heavily doped region (5), the first P-type doped region (6) and the second P-type doped region (7), ion implantation is performed on the sidewalls of the trench of the second layer N-type drift region to form a P-type gate region (9) and obtain an N-type current spreading layer (8); Back side thinning and metal sputtering treatment are performed to form a drain metal (1) on the surface of the SiC N+ substrate region (2); front side metal deposition is performed to form a gate metal (12) on the surface of the N-type source region (10), and a source metal (11) is formed on the outer sides of the P-type gate region (9), the P-type heavily doped region (5), the first P-type doped region (6) and the second P-type doped region (7).

10. A SiC JFET device structure resistant to single-particle burnout, characterized in that: include: Drain metal (1), SiC N+ substrate region (2), N-lightly doped drift region (3), P-type doping region, N-type current spreading layer (8), P-type gate region (9), N-type source region (10), source metal (11) and gate metal (12); A drain metal (1), a SiC N+ substrate region (2) and an N-lightly doped drift region (3) are sequentially arranged from bottom to top, and an N-type current spreading layer (8) and an N-type source region (10) are sequentially arranged in the middle of the N-lightly doped drift region (3) from bottom to top; The P-type doping region is located above the N-lightly doped drift region (3), and the P-type doping region is arranged outside the N-type current spreading layer (8); The P-type gate region (9) is located outside the N-type current spreading layer (8), and the P-type gate region (9) is located between the P-type doping region and the N-type source region (10) in the vertical direction; The source metal (11) is arranged above the N-type source region (10); and the gate metal (12) is arranged outside the P-type gate region (9) and in a partial region above the P-type doped region.

11. A SiC JFET device structure resistant to single event burnout according to claim 10, characterized in that: The thickness of the P-type doping region is not less than 1.0 μm to 1.5 μm.

12. A SiC JFET device structure resistant to single event burnout according to claim 11, characterized in that: The bottom of the N-type current spreading layer (8) is higher than the bottom of the P-type doping region.

13. A SiC JFET device structure resistant to single event burnout according to claim 12, characterized in that: The P-type doping region comprises: a P-type heavily doped region (5), a first P-type doping region (6) and a second P-type doping region (7); The P-type heavily doped region (5), the first P-type doped region (6) and the second P-type doped region (7) are arranged in sequence from the inside to the outside; the P-type heavily doped region (5) is adjacent to the N-type current spreading layer (8).

14. A SiC JFET device structure resistant to single event burnout according to claim 13, characterized in that: The width of the P-type heavily doped region (5) is more than 1 / 3 of the width of the single-side P-type doped region, and the doping concentration of the P-type heavily doped region (5) is greater than the doping concentrations of the first P-type doping region (6) and the second P-type doping region (7).

15. A SiC JFET device structure resistant to single event burnout according to any one of claims 13 or 14, characterized in that: The doping concentration of the first P-type doping region (6) is not greater than the doping concentration of the second P-type doping region (7).

16. A method for preparing a SiC JFET device structure resistant to single particle burnout, characterized in that: include: Epitaxially growing a first layer of N-drift region on the SiC N+ substrate region (2); Forming a first layer of N-type implantation region on the first layer of N-drift region by high energy ion implantation; The doping concentration of the formed first layer N-type implantation region is higher than that of the first layer N-drift region; Using a photomask to cover a portion of the upper surface of the first layer N-type implantation region, and performing ion implantation to form a P-type implantation region; On the basis of the P-type implantation region, multiple ion implantations are performed on the P-type implantation region by means of multiple photolithography and control of ion implantation energy to form a P-type heavily doped region (5), a first P-type doped region (6) and a second P-type doped region (7) with different doping concentrations; Epitaxial growth is again performed on the surface of the first layer of N-type implanted region to obtain a second layer of N-type drift region, wherein the second layer of N-type drift region covers the P-type heavily doped region (5), the first P-type doped region (6) and the second P-type doped region (7); On the upper surface of the second layer N-type drift region, ion implantation is performed to form an N+ implantation region as an N-type source Polar region (10); Performing gate trench etching on the second layer N-type drift region to expose a portion of the upper surface of the P-type heavily doped region (5) and to expose the entire upper surfaces of the first P-type doped region (6) and the second P-type doped region (7); Using a photoresist to block the exposed upper surface portions of the P-type heavily doped region (5), the first P-type doped region (6) and the second P-type doped region (7), ion implantation is performed on the sidewalls of the trench of the second layer N-type drift region to form a P-type gate region (9) and obtain an N-type current spreading layer (8); Back side thinning and metal sputtering treatment are performed to form a drain metal (1) on the surface of the SiC N+ substrate region (2); front side metal deposition is performed to form a gate metal (12) on the surface of the N-type source region (10), and a source metal (11) is formed on the outer sides of the P-type gate region (9), the P-type heavily doped region (5), the first P-type doped region (6) and the second P-type doped region (7).

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