Method and apparatus for establishing pcie optical interconnection link, and device, medium and system

Abstract

The present application relates to the technical field of signal transmission. Disclosed are a method and apparatus for establishing a peripheral component interconnect express (PCIe) optical interconnection link, and a device, a non-volatile readable storage medium and a system. The method comprises: acquiring an upstream data signal which is transmitted by means of an electrical path, and detecting whether there is an electrical idle ordered set in the upstream data signal (S11); if there is an electrical idle ordered set, recording the current link rate, and by means of counting the electrical idle ordered set, determining whether the current sending of the electrical idle ordered set has been completed (S12); and when the current sending of the electrical idle ordered set has been completed, generating a target signal sequence of a corresponding rate according to the link rate, and sending the target signal sequence to an opposite end by means of a PCIe optical interconnection link, such that the opposite end maintains stable operation on the basis of the target signal sequence (S13). A PCIe optical interconnection link can be established, and the success rate of establishing the PCIe optical interconnection link can be increased, thereby avoiding the problem of a link establishment failure caused by an electrical idle state during link establishment.

Description

PCIe optical interconnection link establishment method, device, equipment, medium and system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on June 28, 2023, with application number 202310771673.6, and application name “PCIe optical interconnection link establishment method, device, equipment, medium and system”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of signal transmission technology, and in particular to a method, device, equipment, non-volatile readable storage medium and system for establishing a PCIe optical interconnection link. Background Art

[0004] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard primarily used to expand computer system bus data throughput and improve device communication speeds. Currently, PCIe data signals are primarily transmitted via electrical interconnects, such as PCB (Printed Circuit Board)-grade copper wires and cables. With the continuous advancement of the PCIe protocol, the loss caused by electrical interconnects has become increasingly prominent, and the signal transmission distance achievable through electrical interconnects has gradually decreased. Low-loss optical interconnects are a preferred solution. However, since the corresponding optical module standards were not developed specifically for the PCIe protocol, some settings in the PCIe protocol are incompatible with existing optical module standards. A major problem is that the optical module receiver requires some time to stabilize after receiving a burst signal. During this period, the backend cannot extract the clock signal from the data. This means that the PCIe optical interconnect link establishment process can fail due to the electrical idle state. Therefore, how to establish a PCIe optical interconnect link is a pressing issue.

[0005] Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a method, apparatus, device, and non-volatile readable storage medium for establishing a PCIe optical interconnect link, which can establish a PCIe optical interconnect link and improve the success rate of PCIe optical interconnect link establishment. The specific solution is as follows:

[0007] In a first aspect, the present application discloses a method for establishing a PCIe optical interconnect link, which is applied to a pre-created bypass module, comprising:

[0008] Acquire an upstream data signal transmitted by the electrical path, and detect whether an electrical idle character sequence exists in the upstream data signal;

[0009] If there is an electrical idle character sequence, the current link rate is recorded, and the number of electrical idle character sequences is counted to determine whether the electrical idle character sequence has been sent.

[0010] When the electrical idle character sequence is completed, a target signal sequence of the corresponding rate is generated according to the link rate, and the target signal sequence is sent to the other end through the PCIe optical interconnection link so that the other end can maintain stable operation based on the target signal sequence.

[0011] Optionally, record the current link rate, including:

[0012] According to the sending rate of the electrical idle character sequence, the link rate of the current PCIe optical interconnect link is determined and recorded.

[0013] Optionally, determining whether the electrical idle character sequence is completely sent by counting the electrical idle character sequence includes:

[0014] By counting the electrical idle character sequence; the electrical idle character sequence is used to indicate that the transmitter is about to enter the electrical idle state;

[0015] When the count value reaches the target value set by the PCIe protocol, it is determined that the current electrical idle character sequence is sent completely; otherwise, it is determined that the current electrical idle character sequence is not sent completely.

[0016] Optionally, after detecting whether an electrical idle character sequence exists in the upstream data signal, the method further includes:

[0017] If it is determined that there is no electrical idle character sequence in the upstream data signal, the upstream data signal is directly transmitted through the PCIe optical interconnect link;

[0018] After determining whether the electrical idle character sequence is sent completely by counting the electrical idle character sequence, the method further includes:

[0019] If it is determined that the electrical idle character sequence has not been sent completely, the upstream data signal is directly transmitted through the PCIe optical interconnection link.

[0020] Optionally, generating a target signal sequence of a corresponding rate according to the link rate includes:

[0021] The target rate is determined based on the link rate according to a preset increase or decrease range, and a target signal sequence is generated according to the target rate.

[0022] Optionally, sending the target signal sequence to the peer end through the PCIe optical interconnect link includes:

[0023] The target signal sequence is converted from electrical to optical by the local optical transmitting component and then sent to the optical receiving component at the other end through the PCIe optical interconnection link.

[0024] Optionally, the peer maintains stable operation based on the target signal sequence, including:

[0025] The optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain a target signal sequence, and forwards the target signal sequence to the termination device in the bypass module at the opposite end so that the transimpedance amplifier in the optical module at the opposite end maintains stable operation.

[0026] Optionally, the optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain a target signal sequence, including:

[0027] The optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain an electrical signal;

[0028] Detecting whether a target signal sequence exists in the electrical signal;

[0029] If the target signal sequence exists, the step of forwarding the target signal sequence to the termination device in the bypass module at the opposite end is performed.

[0030] Optionally, after detecting whether the target signal sequence exists in the electrical signal, the method further includes:

[0031] If the target signal sequence does not exist, the electrical signal is directly forwarded to the terminal device.

[0032] Optionally, before detecting whether the target signal sequence exists in the electrical signal, the method further includes:

[0033] Detecting the presence of an electrical idle character sequence in an electrical signal;

[0034] If the electrical idle character sequence does not exist, the step of detecting whether the target signal sequence exists in the electrical signal is performed.

[0035] Optionally, after detecting whether an electrical idle character sequence exists in the electrical signal, the method further includes:

[0036] If an electrical idle character sequence exists, the current link rate is determined based on the electrical idle character sequence and recorded;

[0037] Counting the electrical idle character sequence and judging whether the electrical idle character sequence has been sent out according to the count value;

[0038] If the electrical idle character sequence is sent completely, the target signal sequence is ready to be received.

[0039] Optionally, after determining whether the electrical idle character sequence is completely sent according to the count value, the method further includes:

[0040] If the electrical idle character sequence is not sent completely, the electrical signal is directly forwarded to the terminal device.

[0041] Optionally, the bypass module is integrated with the local optical transmitting component and the local optical receiving component in the optical module.

[0042] Optionally, the bypass module is connected to the host and the optical module as an independent device.

[0043] Optionally, the bypass module is integrated in a PCIe signal repeater, and the PCIe signal repeater is connected to the host and the optical module respectively.

[0044] Optionally, the bypass module includes a pattern generator, a data signal gate, a pattern detection controller, and a termination device;

[0045] The pattern detection controller is configured to obtain an upstream data signal transmitted by the electrical path, detect whether an electrical idle character sequence exists in the upstream data signal, record a current link rate, determine whether the electrical idle character sequence has been sent by counting the electrical idle character sequences, control data transmission of the data signal selector, and control the pattern generator to generate a pattern;

[0046] The pattern generator is configured to generate a target signal sequence of a corresponding rate according to a link rate;

[0047] The data signal selector is configured to obtain an upstream data signal transmitted by the electrical path and send a target signal sequence to the opposite end via the PCIe optical interconnect link;

[0048] The termination device is configured to store the target signal sequence sent by the opposite end.

[0049] Optionally, the pattern detection controller is further configured to receive an electrical signal sent by the opposite end after being photoelectrically converted by the optical receiving component, and control a signal transmission channel of the data signal selector;

[0050] The data signal selector is also configured to receive the electrical signal sent by the opposite end after photoelectric conversion by the optical receiving component, and forward it to the termination device when the electrical signal is the target signal sequence, and forward it to the terminal device when the electrical signal is not the target signal sequence.

[0051] Optionally, the pattern detection controller supports identifying patterns associated with electrical idle states during PCIe link training.

[0052] Optionally, the signal rate supported by the data signal selector covers the signal rate specified by the PCIe protocol.

[0053] In a second aspect, the present application discloses a PCIe optical interconnect link establishment device, comprising:

[0054] a detection module configured to obtain an upstream data signal transmitted by the electrical path and detect whether an electrical idle character sequence exists in the upstream data signal;

[0055] The recording module is configured to record the current link rate if an electrical idle character sequence exists, and determine whether the electrical idle character sequence has been sent by counting the electrical idle character sequence;

[0056] The sequence sending module is configured to generate a target signal sequence of a corresponding rate according to the link rate when the electrical idle character sequence is completed, and send the target signal sequence to the opposite end through the PCIe optical interconnection link so that the opposite end can maintain stable operation based on the target signal sequence.

[0057] In a third aspect, the present application discloses an electronic device, comprising:

[0058] a memory configured to store a computer program;

[0059] The processor is configured to execute a computer program to implement the aforementioned PCIe optical interconnect link establishment method.

[0060] In a fourth aspect, the present application discloses a computer non-volatile readable storage medium configured to store a computer program; wherein the computer program implements the aforementioned PCIe optical interconnect link establishment method when executed by a processor.

[0061] In a fifth aspect, the present application discloses a PCIe optical interconnection link system, comprising a host, an optical module, and the aforementioned bypass module; the bypass module comprises a pattern generator, a data signal gate, a pattern detection controller, and a termination device;

[0062] The data signal selector is respectively connected to the host, the optical transmitting component and the optical receiving component in the optical module, the pattern generator and the termination device;

[0063] The code pattern detection controller is connected to the host, the data signal selector, the optical receiving component and the code pattern generator respectively.

[0064] In the present application, an upstream data signal transmitted by an electrical path is obtained, and whether an electrical idle character sequence exists in the upstream data signal is detected; if an electrical idle character sequence exists, the current link rate is recorded, and whether the electrical idle character sequence is completely sent is determined by counting the electrical idle character sequences; when the electrical idle character sequence is completely sent, a target signal sequence of a corresponding rate is generated according to the link rate, and the target signal sequence is sent to the opposite end through the PCIe optical interconnect link, so that the opposite end maintains stable operation based on the target signal sequence.

[0065] It can be seen that by determining whether the link is about to enter the electrical idle state based on the electrical idle character sequence, and after entering the electrical idle state, maintaining the working state of the local and receiving ends by generating a target signal sequence of the corresponding rate, the impact of burst signals on the transimpedance amplifier can be avoided, and a PCIe link can be established between a host such as a server and an external device through an optical fiber. The problem of link establishment failure caused by the electrical idle state during the establishment of the PCIe optical interconnection link is avoided. In other words, the problem of the interconnection link existing in a burst mode from no data transmission to high-speed data signal transmission when the link exits the electrical idle state is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0067] FIG1 is a flow chart of a method for establishing a PCIe optical interconnection link provided by the present application;

[0068] FIG2 is a schematic diagram of the structure of an optional bypass module provided in this application;

[0069] FIG3 is a flow chart of an optional transmitting-end PCIe optical interconnection method provided by the present application;

[0070] FIG4 is a flow chart of an optional receiving-end PCIe optical interconnection method provided by the present application;

[0071] FIG5 is a schematic diagram of the structure of an optional PCIe optical interconnect system provided by the present application;

[0072] FIG6 is a schematic diagram of the structure of another optional PCIe optical interconnect system provided by the present application;

[0073] FIG7 is a schematic diagram of the structure of another optional PCIe optical interconnect system provided by the present application;

[0074] FIG8 is a schematic structural diagram of a PCIe optical interconnect link establishment device provided by the present application;

[0075] FIG9 is a structural diagram of an electronic device provided in this application. DETAILED DESCRIPTION

[0076] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0077] In the prior art, since the corresponding standards for optical modules are not formulated for the PCIe protocol, some settings in the PCIe protocol are incompatible with the existing optical module standards. The main problem is that the optical module receiving end needs a period of time to work stably after receiving a burst signal. During this period before stable operation, the back end cannot extract the clock signal from the data, that is, the optical module cannot cope with the sudden high-speed signal transmission after the electrical idle state, resulting in the failure of directly using the optical module to build the PCIe optical interconnection path. In order to overcome the above technical problems, the present application proposes a PCIe optical interconnection link establishment method, which can establish a PCIe optical interconnection link, improve the success rate of PCIe optical interconnection link establishment, and avoid the problem of link establishment failure caused by the electrical idle state during the PCIe optical interconnection link establishment process.

[0078] The present application discloses a method for establishing a PCIe optical interconnect link, as shown in FIG1 , which is applied to a pre-created bypass module. The method may include the following steps:

[0079] Step S11: acquiring an upstream data signal transmitted by the electrical path, and detecting whether an electrical idle character sequence exists in the upstream data signal.

[0080] In this embodiment, the upstream data signal transmitted by the electrical path is first obtained, and then the upstream data signal is detected to determine whether an electrical idle character sequence exists. It is understood that the establishment of a PCIe interconnect link involves a link training process, and the entire interconnect link must be able to correctly transmit signals during the link training process in order for the link to be successfully established. During the link training process, the link will enter the electrical idle (Electrical Idle, EI) state multiple times. After entering the EI state, no data signal will be transmitted in the interconnect link. Thereafter, when the transmitter (Tx) needs to transmit data, it will send a corresponding character sequence (OrderedSets) to wake up the receiver (Rx) to continue the link training process. Optionally, before entering the EI state, the transmitter needs to send several electrical idle character sequences (Electrical Idle Ordered Sets, EIOS) defined by the PCIe protocol to the receiver before entering the EI state. When the transmitter wants to exit the EI state, it needs to send several electrical idle exit character sequences (Electrical Idle Exit Ordered Sets, EIEOS) defined by the PCIe protocol to the peer device before exiting the EI state. Specifically, it can be determined whether the upstream data signal contains an electrical idle character sequence based on the characteristics of the electrical idle character sequence defined by the PCIe protocol.

[0081] In this embodiment, after detecting whether an electrical idle character sequence exists in the upstream data signal, the method may further include: if it is determined that the upstream data signal does not contain an electrical idle character sequence, directly transmitting the upstream data signal via the PCIe optical interconnect link. Specifically, if the upstream data signal does not contain an electrical idle character sequence, it indicates that the link is in a normal data transmission process. In this case, the upstream data signal may be directly transmitted to the peer end via the PCIe optical interconnect link.

[0082] Step S12: If there is an electrical idle character sequence, the current link rate is recorded, and the electrical idle character sequence is counted to determine whether the electrical idle character sequence has been sent.

[0083] In this embodiment, if an electrical idle character sequence is detected, it can be indicated that the link is about to enter the idle state. At this time, the current link rate is recorded, and by counting the electrical idle character sequence, it is determined whether the electrical idle character sequence is completely sent. It can be understood that if the electrical idle character sequence is completely sent, it indicates that the idle state has been entered; otherwise, it indicates that it is still in the preparation stage for entering the idle state.

[0084] In this embodiment, recording the current link rate may include determining and recording the link rate of the current PCIe optical interconnect link based on the transmission rate of the electrical idle character sequence. The link rate, or link transmission rate, refers to the speed at which a host or router sends data on a link. Therefore, the link rate of the current PCIe optical interconnect link may be determined and recorded based on the transmission rate of the electrical idle character sequence.

[0085] In this embodiment, determining whether the current electrical idle character sequence has been sent by counting the electrical idle character sequence may include: counting the electrical idle character sequence; the electrical idle character sequence is used to indicate that the transmitting end is about to enter the electrical idle state; determining that the current electrical idle character sequence has been sent successfully when the count value reaches a target value set by the PCIe protocol; otherwise, determining that the current electrical idle character sequence has not been sent successfully. That is, the total number of electrical idle character sequences sent each time the electrical idle state is entered is fixed, namely, the target value set by the PCIe protocol. Therefore, the electrical idle character sequence can be counted and then determined to be sent successfully based on the count value. If the count value reaches the target value, the current electrical idle character sequence is considered completed; otherwise, the current electrical idle character sequence is considered not completed.

[0086] In this embodiment, after determining whether the electrical idle sequence has been completely transmitted by counting the electrical idle sequence, the method may further include: if it is determined that the electrical idle sequence has not been completely transmitted, directly transmitting the upstream data signal via the PCIe optical interconnect link. Specifically, if the electrical idle sequence has not been completely transmitted, it indicates that the link is in the electrical idle sequence transmission process. In this case, the upstream data signal, including the electrical idle sequence, may be directly transmitted to the peer end via the PCIe optical interconnect link.

[0087] Step S13: When the electrical idle character sequence is completed, a target signal sequence of a corresponding rate is generated according to the link rate, and the target signal sequence is sent to the peer end through the PCIe optical interconnection link so that the peer end can maintain stable operation based on the target signal sequence.

[0088] In this embodiment, when it is determined that the electrical idle character sequence has completed transmission, a target signal sequence of a corresponding rate is generated according to the link rate, and the target signal sequence is sent to the opposite end through the PCIe optical interconnect link, so that the opposite end maintains stable operation by continuously receiving the target signal sequence. It is understandable that the main reason why the link establishment fails due to the electrical idle state during the establishment of the PCIe optical interconnect link is that the link stores a sudden change in data rate when it changes from the electrical idle state to the normal data transmission state. However, the trans-impedance amplifier (TIA) at the receiving end of the optical module takes a while to work stably after receiving the burst signal. During this period before stable operation, the TIA cannot accurately convert the front-end photocurrent signal into a correct voltage signal, and thus cannot extract the clock signal from the data, thereby causing the link establishment to fail. In this embodiment, the target signal sequence is used to keep the trans-impedance amplifier in a normal working state, thereby avoiding the problem of link establishment failure caused by the electrical idle state.

[0089] In this embodiment, generating a target signal sequence of a corresponding rate based on the link rate may include: determining a target rate based on the link rate within a preset range of increase or decrease, and generating the target signal sequence based on the target rate. Specifically, the target rate may be obtained by appropriately decreasing, increasing, or maintaining the link rate. The target rate may be selected as long as the difference from the link rate is not so great as to require a period of time for the transimpedance amplifier to adapt. In some cases, a minimum rate within the allowable range may be selected to avoid link establishment failures and conserve resources.

[0090] In this embodiment, transmitting the target signal sequence to the peer end via a PCIe optical interconnect link may include: performing electrical-to-optical conversion on the target signal sequence using a local optical transmitter assembly, and then transmitting the target signal sequence to the peer end's optical receiver assembly via the PCIe optical interconnect link. Specifically, the optical transmitter assembly converts the target signal sequence's electrical signal into an optical signal, and then transmits the optical signal to the peer end via an optical fiber. It should be understood that the terms "local" and "peer end" in this embodiment are merely different perspectives. The same applies to the transmitting and receiving ends. However, each terminal will correspond to an identical bypass module to implement the aforementioned steps.

[0091] Related technologies also employ clock data recovery circuits, which, when faced with burst signals, can send a local reference clock as input data to a phase adjustment module to ensure that the CDR (Clock Data Recovery) module can recover the correct clock signal. While this solves the problem of correctly recovering clock data when data signals are disordered to a certain extent, it still faces stability issues caused by the TIA's inability to respond quickly in burst mode, which can still lead to link establishment failure during link training. In this embodiment, by detecting the EIOS sequence that signals the entry into the electrical idle state during link training at the transmitting end and utilizing a generated target signal sequence at a corresponding rate, the optical link formed by the optical module and optical fiber at both the transmitting and receiving ends of the link maintains the same high-speed transmission active state as before entering the electrical idle state, preventing the receiving end from entering the normal data transmission state from the electrical idle state. This maintains the TIA at the receiving end of the optical module in a stable operating mode, completing the link training process and establishing a PCIe optical interconnect link between the transmitting and receiving ends.

[0092] In this embodiment, maintaining stable operation of the peer end based on the target signal sequence may include: the optical receiving component at the peer end performs photoelectric conversion on the received optical signal to obtain the target signal sequence, and forwarding the target signal sequence to the termination device in the bypass module at the peer end, so that the transimpedance amplifier in the optical module at the peer end maintains stable operation. Specifically, after photoelectric conversion, the target signal sequence is extracted from the electrical signal, and the transimpedance amplifier at the peer end can continue to operate based on the target signal sequence.

[0093] In this embodiment, the optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain a target signal sequence, which includes the following steps: the optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain an electrical signal; detecting whether the target signal sequence exists in the electrical signal; if the target signal sequence exists, forwarding the target signal sequence to the termination device in the bypass module at the opposite end; if the target signal sequence does not exist, directly forwarding the electrical signal to the terminal device. That is, first detecting whether it is the target signal sequence; if it is not the target signal sequence, it may be normal data information or an electrical idle character sequence, and then it can be directly sent to the terminal device.

[0094] In this embodiment, before detecting whether the target signal sequence exists in the electrical signal, the method further includes: detecting whether the electrical idle character sequence exists in the electrical signal; if the electrical idle character sequence does not exist, executing the step of detecting whether the target signal sequence exists in the electrical signal; if the electrical idle character sequence exists, determining the current link rate based on the electrical idle character sequence and recording it; counting the electrical idle character sequence, and judging whether the electrical idle character sequence has been sent based on the count value; if the electrical idle character sequence has been sent, preparing to receive the target signal sequence; if the electrical idle character sequence has not been sent, directly forwarding the electrical signal to the terminal device. That is, since the electrical idle character sequence will be transmitted before the target signal sequence, each time the opposite end receives the signal, it can first detect the electrical idle character sequence and then detect the target signal sequence, thereby improving detection efficiency. In addition, the above method is applicable to establishing an optical interconnection link under the CXL (Compute Express Link) protocol specification based on the PCIe5.0 protocol.

[0095] As can be seen from the above, in this embodiment, an upstream data signal transmitted by an electrical path is obtained, and whether an electrical idle character sequence is present in the upstream data signal is detected. If an electrical idle character sequence is present, the current link rate is recorded, and the number of electrical idle character sequences is counted to determine whether the electrical idle character sequence has been sent. When the electrical idle character sequence has been sent, a target signal sequence of a corresponding rate is generated based on the link rate, and the target signal sequence is sent to the peer end via the PCIe optical interconnect link, so that the peer end maintains stable operation based on the target signal sequence.

[0096] It can be seen that by determining whether the link is about to enter the electrical idle state based on the electrical idle character sequence, and after entering the electrical idle state, maintaining the working state of the local and receiving ends by generating a target signal sequence of the corresponding rate, the impact of burst signals on the transimpedance amplifier can be avoided, and a PCIe link can be established between a host such as a server and an external device through an optical fiber. The failure of the link establishment due to the electrical idle state during the establishment of the PCIe optical interconnection link is avoided. In other words, the problem of the interconnection link existing in a burst mode from no data transmission to high-speed data signal transmission when the link exits the electrical idle state is solved.

[0097] Based on the above embodiments, the present application also provides an optional bypass module structure, which includes a code generator, a data signal selector, a code detection controller and a termination device; wherein the code detection controller is configured to obtain the upstream data signal transmitted by the electrical path, detect whether there is an electrical idle character sequence in the upstream data signal, record the current link rate, determine whether the electrical idle character sequence is sent by counting the electrical idle character sequence, control the data transmission of the data signal selector, and control the code generator to generate a code pattern; the code generator is configured to generate a target signal sequence of a corresponding rate according to the link rate; the data signal selector is configured to obtain the upstream data signal transmitted by the electrical path, and send the target signal sequence to the opposite end through the PCIe optical interconnect link; the termination device is configured to store the target signal sequence sent by the opposite end.

[0098] For example, as shown in Figure 2, 1 is a bypass module, 101 is a pattern generator, 102 is a data signal selector, 103 is an optical transmitter assembly, 104 is a pattern detection controller, 105 is an optical receiver assembly, 106 is a termination device, 201 is an electrical path connecting the bypass module, and 301 is an optical fiber connecting the optical transmitter assembly and the optical receiver assembly. When a device transmits a signal via optical fiber 301, bypass module 1 receives the upstream signal via the receiving path (Rx) of electrical path 201. The received signal enters data signal selector 102 and pattern detection controller 104. Pattern detection controller 104 controls pattern generator 101 and data signal selector 102. The signal output by data signal selector 102 is then converted into an optical signal by optical transmitter assembly 103 and finally transmitted outward via optical fiber 301.

[0099] In this embodiment, the pattern detection controller is further configured to receive an electrical signal sent by the peer end after undergoing photoelectric conversion by the optical receiving component, and to control the signal transmission channel of the data signal selector. The data signal selector is further configured to receive an electrical signal sent by the peer end after undergoing photoelectric conversion by the optical receiving component, and to forward it to the termination device if the electrical signal is a target signal sequence, and to forward it to the terminal device if the electrical signal is not a target signal sequence. That is, when the device receives a signal via optical fiber 301, the received signal undergoes photoelectric conversion by the optical receiving component 105 and is then input to the data signal selector 102 and pattern detection controller 104. The pattern detection controller 104 controls the data signal selector 102 to transmit the input signal to the termination device 106 or to transmit it through the electrical path 201.

[0100] In this embodiment, the pattern detection controller supports identifying patterns associated with the electrical idle state during PCIe link training. Specifically, the pattern detection controller 104 must be able to identify patterns associated with the electrical idle state during PCIe link training, including but not limited to ASIC (Application Specific Integrated Circuit) chips, ARM (Advanced RISC Machine) chips, or FPGA (Field Programmable Gate Array) chips, to implement pattern detection and control the data signal selector.

[0101] In this embodiment, the signal rates supported by the data signal gate include those specified by the PCIe protocol. That is, the data signal gate 102 is used to select and pass signals, and the supported signal rates must cover those specified by the PCIe protocol, including but not limited to ASIC chips, ARM chips, or FPGA chips, to implement the signal gating function.

[0102] In this embodiment, the pattern generator 101 can generate a pattern that complies with the PCIe protocol rate, including but not limited to an ASIC chip, an ARM chip, or an FPGA chip, etc., to maintain the normal operation of the receiving end optical module.

[0103] Based on the above embodiment, the present application also provides an optional transmitting-end PCIe optical interconnection method, as shown in FIG3 , including the following steps:

[0104] 1. The upstream data signal is first transmitted to the data signal selector and pattern detection controller inside the bypass module;

[0105] 2. The pattern detection controller detects whether there is an EIOS sequence in the upstream signal. If the pattern detection controller detects an EIOS sequence in the upstream signal, it means that the transmitter is about to enter the electrical idle state. At this time, the pattern detection controller needs to determine the current link rate based on the EIOS sequence and count the EIOS sequences. If the pattern detection controller detects no EIOS sequence in the upstream signal, it means that the transmitter has not entered the electrical idle state. The pattern detection controller controls the data signal selector to directly transmit the upstream data signal.

[0106] 3. If the EIOS sequence reaches the number set by the PCIe protocol, the transmitter and receiver will enter the electrical idle state after completing the transmission and reception of this EIOS sequence. After the last EIOS sequence is directly transmitted through the data signal selector, the pattern detection controller controls the pattern generator to generate a signal with the same link rate. The data signal selector is then controlled to transmit the signal generated by the pattern generator to ensure that the link still has high-speed signal transmission.

[0107] 4. If the EIOS sequence does not reach the number set by the PCIe protocol, the peer device needs to wait for the sender to send several EIOS sequences before entering the electrical idle state. The pattern detection controller controls the data signal selector to directly transmit the upstream data signal. At this time, the data signal is the EIOS sequence.

[0108] 5. Finally, the electrical signal transmitted through the data signal selector is converted from electrical to optical by the optical transmitting component and then transmitted to the receiving end via optical fiber.

[0109] Based on the above embodiment, the present application also provides an optional receiving-end PCIe optical interconnection method, as shown in FIG4 , including the following steps:

[0110] 1. First, the optical receiving component converts the received optical signal into an electrical signal and transmits it to the data signal selector and pattern detection controller;

[0111] 2. The pattern detection controller detects whether the signal contains the EIOS sequence and the signal sequence generated by the pattern generator. If the pattern detection controller detects that the signal does not contain the EIOS sequence and the signal sequence generated by the pattern generator, it indicates that the transmitter is in a normal link training state or a normal data transmission state. Then, the pattern detection controller controls the data signal selector to directly transmit the electrical signal data.

[0112] 3. If the pattern detection controller detects an EIOS sequence in the signal, it means that the transmitter is about to enter the electrical idle state. At this time, the pattern detection controller needs to determine the current link rate based on the EIOS sequence and count the EIOS sequences.

[0113] 4. If the number of EIOS sequences reaches the number set by the PCIe protocol, it means that the transmitter has entered the electrical idle state and will no longer send training sequences or data. At this time, after the pattern detection controller transmits the last EIOS sequence, it controls the data signal selector to connect the signal to the termination device.

[0114] Accordingly, the embodiment of the present application also discloses a PCIe optical interconnection link system, which includes: a host, an optical module and the aforementioned bypass module; the bypass module includes a pattern generator, a data signal gate, a pattern detection controller and a termination device;

[0115] The data signal selector is respectively connected to the host, the optical transmitting component and the optical receiving component in the optical module, the pattern generator and the termination device;

[0116] The code pattern detection controller is connected to the host, the data signal selector, the optical receiving component and the code pattern generator respectively.

[0117] In this embodiment, the bypass module can be integrated with the local optical transmitting component and the optical receiving component in the optical module. For example, Figure 5 shows a schematic diagram of the structure of a PCIe optical interconnection system built by an optional PCIe optical interconnection link establishment device. The bypass module 1 is integrated with the optical transmitting component 103 and the optical receiving component 105 in the optical module 2. The chip directly connected to the server host and the bypass module 1 can be a CPU (Central Processing Unit), PCIe Switch, PCIe Retimer, PCIe Redriver, etc. The chip or device directly connected to the terminal device and the bypass module 1 can be a GPU (Graphics Processing Unit), SSD (Solid State Drive), DRAM (Dynamic Random Access Memory), PCIe Switch, PCIe Retimer, PCIe Redriver, etc.

[0118] In this embodiment, the bypass module can also be connected to the host and optical module as an independent device. For example, Figure 6 shows a schematic diagram of the PCIe optical interconnect system structure using an optional PCIe optical interconnect link establishment device. The bypass module 1 is located between the host and optical module 2 as an independent device. The chip directly connected to the server host and bypass module 1 can be a CPU, PCIe switch, PCIe retimer, PCIe redriver, etc. The chip or device directly connected to the bypass module 1 of the terminal device can be a GPU, SSD, DRAM, PCIe switch, PCIe retimer, PCIe redriver, etc.

[0119] In this embodiment, the bypass module can also be integrated into a PCIe signal repeater, which is connected to the host and the optical module respectively. For example, Figure 7 shows a schematic diagram of the structure of a PCIe optical interconnection system constructed using an optional PCIe optical interconnection link establishment device. The bypass module 1 is integrated into three types of PCIe signal relay devices 5: a PCIe switch, a PCIe retimer, and a PCIe redriver. The core chip directly connected to the server host and the PCIe signal relay device 5 can be a CPU, etc. The chip or device directly connected to the PCIe signal relay device 5 of the terminal device can be a GPU, SSD, DRAM, PCIe switch, PCIe retimer, PCIe redriver, etc.

[0120] It can be seen that the bypass module has a flexible integration form. It can be placed between the host and the optical module as a separate device, or it can be integrated into chips such as optical modules or PCIe signal repeaters.

[0121] Accordingly, the embodiment of the present application further discloses a PCIe optical interconnection link establishment device, as shown in FIG8 , which includes:

[0122] The detection module 31 is configured to obtain an upstream data signal transmitted by the electrical path and detect whether an electrical idle character sequence exists in the upstream data signal;

[0123] The recording module 32 is configured to record the current link rate if an electrical idle character sequence exists, and determine whether the electrical idle character sequence has been sent by counting the electrical idle character sequence;

[0124] The sequence sending module 33 is configured to generate a target signal sequence of a corresponding rate according to the link rate when the electrical idle character sequence is completed, and send the target signal sequence to the opposite end through the PCIe optical interconnection link so that the opposite end can maintain stable operation based on the target signal sequence.

[0125] As can be seen from the above, the upstream data signal transmitted by the electrical path is obtained, and whether the upstream data signal contains an electrical idle character sequence is detected; if the electrical idle character sequence exists, the current link rate is recorded, and the electrical idle character sequence is counted to determine whether the electrical idle character sequence has been sent; when the electrical idle character sequence is sent, a target signal sequence of the corresponding rate is generated according to the link rate, and the target signal sequence is sent to the other end through the PCIe optical interconnect link, so that the other end can maintain stable operation based on the target signal sequence.

[0126] It can be seen that by determining whether the link is about to enter the electrical idle state based on the electrical idle character sequence, and after entering the electrical idle state, maintaining the working state of the local and receiving ends by generating a target signal sequence of the corresponding rate, the impact of burst signals on the transimpedance amplifier can be avoided, and a PCIe link can be established between a host such as a server and an external device through an optical fiber. The failure of the link establishment due to the electrical idle state during the establishment of the PCIe optical interconnection link is avoided. In other words, the problem of the interconnection link existing in a burst mode from no data transmission to high-speed data signal transmission when the link exits the electrical idle state is solved.

[0127] In some optional embodiments, the recording module 32 may specifically include:

[0128] The link rate determination unit is configured to determine and record the link rate of the current PCIe optical interconnect link according to the sending rate of the electrical idle character sequence.

[0129] In some optional embodiments, the recording module 32 may specifically include:

[0130] The counting unit is configured to count an electrical idle character sequence; the electrical idle character sequence is used to indicate that the transmitting end is about to enter an electrical idle state;

[0131] The determination unit is configured to determine that the current electrical idle character sequence is completely sent when the count value reaches the target value set by the PCIe protocol; otherwise, determine that the current electrical idle character sequence is not completely sent.

[0132] In some optional embodiments, the PCIe optical interconnection link establishment device may specifically include:

[0133] The first direct transmission unit is configured to, after detecting whether an electrical idle character sequence exists in the upstream data signal, directly transmit the upstream data signal through the PCIe optical interconnect link if it is determined that the upstream data signal does not have an electrical idle character sequence;

[0134] The second direct transmission unit is configured to directly transmit the upstream data signal through the PCIe optical interconnection link if it is determined that the electrical idle character sequence has not been completely sent.

[0135] In some optional embodiments, the sequence sending module 33 may specifically include:

[0136] The rate determination unit is configured to determine a target rate according to a preset increase or decrease range based on the link rate, and generate a target signal sequence according to the target rate.

[0137] In some optional embodiments, the sequence sending module 33 may specifically include:

[0138] The sequence sending unit is configured to perform electrical-optical conversion on the target signal sequence through the local optical transmitting component and then send it to the optical receiving component at the opposite end through the PCIe optical interconnection link.

[0139] In some optional embodiments, the PCIe optical interconnection link establishment device may specifically include:

[0140] The target signal sequence acquisition unit is configured to obtain a target signal sequence after the optical receiving component at the opposite end performs photoelectric conversion on the received optical signal, and forward the target signal sequence to the termination device in the bypass module at the opposite end so that the transimpedance amplifier in the optical module at the opposite end maintains stable operation.

[0141] In some optional embodiments, the target signal sequence acquisition unit may specifically include:

[0142] The electrical signal acquisition unit is configured to perform photoelectric conversion on the received optical signal by the optical receiving component at the opposite end to obtain an electrical signal;

[0143] a target signal sequence detection unit, configured to detect whether a target signal sequence exists in the electrical signal;

[0144] The execution unit is configured to execute the step of forwarding the target signal sequence to the termination device in the bypass module at the opposite end if the target signal sequence exists.

[0145] In some optional embodiments, the target signal sequence acquisition unit may specifically include:

[0146] The forwarding unit is configured to directly forward the electrical signal to the terminal device if the target signal sequence does not exist.

[0147] In some optional embodiments, the target signal sequence acquisition unit may specifically include:

[0148] an electrical idle character sequence detection unit, configured to detect whether there is an electrical idle character sequence in the electrical signal before detecting whether there is a target signal sequence in the electrical signal;

[0149] The execution unit is configured to execute the step of detecting whether a target signal sequence exists in the electrical signal if the electrical idle character sequence does not exist.

[0150] In some optional embodiments, the target signal sequence acquisition unit may specifically include:

[0151] a recording unit configured to determine and record a current link rate based on the electrical idle character sequence if the electrical idle character sequence exists;

[0152] a judging unit configured to count the electrical idle character sequence and judge whether the electrical idle character sequence has been sent out according to the count value;

[0153] The preparation unit is configured to prepare to receive the target signal sequence if the current electrical idle character sequence is sent completely.

[0154] In some optional embodiments, the target signal sequence acquisition unit may specifically include:

[0155] The forwarding unit is configured to directly forward the electrical signal to the terminal device if the electrical idle character sequence is not completely sent.

[0156] In some optional embodiments, the bypass module may be integrated with the local optical transmitting component and the local optical receiving component in the optical module.

[0157] In some optional embodiments, the bypass module can be specifically connected to the host and the optical module as an independent device.

[0158] In some optional embodiments, the bypass module may be specifically integrated into a PCIe signal repeater, and the PCIe signal repeater is connected to the host and the optical module respectively.

[0159] In some optional embodiments, the bypass module may specifically include a pattern generator, a data signal gate, a pattern detection controller, and a termination device;

[0160] The pattern detection controller is configured to obtain an upstream data signal transmitted by the electrical path, detect whether an electrical idle character sequence exists in the upstream data signal, record a current link rate, determine whether the electrical idle character sequence has been sent by counting the electrical idle character sequences, control data transmission of the data signal selector, and control the pattern generator to generate a pattern;

[0161] The pattern generator is configured to generate a target signal sequence of a corresponding rate according to a link rate;

[0162] The data signal selector is configured to obtain an upstream data signal transmitted by the electrical path and send a target signal sequence to the opposite end via the PCIe optical interconnect link;

[0163] The termination device is configured to store the target signal sequence sent by the opposite end.

[0164] In some optional embodiments, the pattern detection controller is further configured to receive an electrical signal sent by the opposite end after being photoelectrically converted by the optical receiving component, and control a signal transmission channel of the data signal selector;

[0165] The data signal selector is also configured to receive the electrical signal sent by the opposite end after photoelectric conversion by the optical receiving component, and forward it to the termination device when the electrical signal is the target signal sequence, and forward it to the terminal device when the electrical signal is not the target signal sequence.

[0166] In some optional embodiments, the pattern detection controller supports identifying patterns associated with electrical idle states during PCIe link training.

[0167] In some optional embodiments, the signal rate supported by the data signal strobe covers the signal rate specified by the PCIe protocol.

[0168] The embodiment of the present application further discloses an electronic device, as shown in FIG9 . The content in the figure cannot be considered as any limitation on the scope of use of the present application.

[0169] Figure 9 is a schematic diagram of the structure of an electronic device 40 provided in an embodiment of the present application. The electronic device 40 may include at least one processor 41, at least one memory 42, a power supply 43, a communication interface 44, an input / output interface 45, and a communication bus 46. The memory 42 is configured to store a computer program, which is loaded and executed by the processor 41 to implement the relevant steps of the PCIe optical interconnect link establishment method disclosed in any of the aforementioned embodiments.

[0170] In this embodiment, the power supply 43 is configured to provide operating voltage for each hardware device on the electronic device 40; the communication interface 44 can create a data transmission channel between the electronic device 40 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of this application, and is not specifically limited here; the input and output interface 45 is configured to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0171] In addition, the memory 42, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include an operating system 421, a computer program 422 and data 423 including upstream data signals, etc. The storage method can be temporary storage or permanent storage.

[0172] The operating system 421 is configured to manage and control the hardware devices and computer program 422 on the electronic device 40 to enable the processor 41 to calculate and process the massive amount of data 423 in the memory 42. The operating system 421 can be Windows Server (a Windows server), NetWare (a network operating system), Unix (an operating system), Linux (an operating system kernel), etc. In addition to including a computer program that can be configured to implement the PCIe optical interconnect link establishment method performed by the electronic device 40 as disclosed in any of the aforementioned embodiments, the computer program 422 can also include computer programs that can be configured to perform other specific tasks.

[0173] An embodiment of the present application also discloses a computer non-volatile readable storage medium, in which computer executable instructions are stored. When the computer executable instructions are loaded and executed by a processor, the steps of the PCIe optical interconnection link establishment method disclosed in any of the aforementioned embodiments are implemented.

[0174] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0175] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM (Compact Disc Read-Only Memory), or any other form of non-volatile readable storage medium known in the art.

[0176] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0177] The above is a detailed introduction to the PCIe optical interconnection link establishment method, device, equipment and non-volatile readable storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A method for establishing a high-speed serial computer expansion bus standard PCIe optical interconnection link, characterized in that: Applies to pre-built bypass modules, including: Acquire an upstream data signal transmitted by the electrical path, and detect whether an electrical idle character sequence exists in the upstream data signal; If the electrical idle character sequence exists, the current link rate is recorded, and by counting the electrical idle character sequence, it is determined whether the electrical idle character sequence is sent completely; When the electrical idle character sequence is sent, a target signal sequence of a corresponding rate is generated according to the link rate, and the target signal sequence is sent to the opposite end through the PCIe optical interconnect link so that the opposite end maintains stable operation based on the target signal sequence.

2. The PCIe optical interconnection link establishment method according to claim 1, characterized in that: The recording of the current link rate includes: According to the sending rate of the electrical idle character sequence, the link rate of the current PCIe optical interconnect link is determined and recorded.

3. The PCIe optical interconnection link establishment method according to claim 1, characterized in that: The step of judging whether the current electrical idle character sequence has been sent by counting the electrical idle character sequence comprises: By counting the electrical idle character sequence; the electrical idle character sequence is used to indicate that the transmitting end will enter the electrical idle state; When the count value reaches the target value set by the PCIe protocol, it is determined that the current electrical idle character sequence is sent completely; otherwise, it is determined that the current electrical idle character sequence is not sent completely.

4. The PCIe optical interconnection link establishment method according to claim 1, characterized in that: After detecting whether there is an electrical idle character sequence in the upstream data signal, the method further includes: If it is determined that there is no electrical idle character sequence in the upstream data signal, directly transmitting the upstream data signal through the PCIe optical interconnect link; After counting the electrical idle character sequence to determine whether the current electrical idle character sequence has been sent, the method further includes: If it is determined that the electrical idle character sequence has not been completely sent, the upstream data signal is directly transmitted through the PCIe optical interconnection link.

5. The PCIe optical interconnection link establishment method according to claim 1, characterized in that: Generating a target signal sequence of a corresponding rate according to the link rate comprises: A target rate is determined based on the link rate according to a preset increase or decrease range, and a target signal sequence is generated according to the target rate.

6. The PCIe optical interconnection link establishment method according to claim 1, characterized in that: The step of sending the target signal sequence to the opposite end through a PCIe optical interconnection link comprises: The target signal sequence is converted from electrical to optical by a local optical transmitting component and then sent to an optical receiving component at the opposite end through the PCIe optical interconnection link.

7. The PCIe optical interconnection link establishment method according to claim 1, characterized in that: The opposite end maintains stable operation based on the target signal sequence, including: The optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain the target signal sequence, and forwards the target signal sequence to the termination device in the bypass module at the opposite end so that the transimpedance amplifier in the optical module at the opposite end maintains stable operation.

8. The method for establishing a PCIe optical interconnection link according to claim 7, characterized in that: The optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain the target signal sequence, including: The optical receiving component at the opposite end performs photoelectric conversion on the received optical signal to obtain an electrical signal; detecting whether the target signal sequence exists in the electrical signal; If the target signal sequence exists, the step of forwarding the target signal sequence to the termination device in the bypass module at the opposite end is performed.

9. The PCIe optical interconnection link establishment method according to claim 8, characterized in that: After detecting whether the target signal sequence exists in the electrical signal, the method further includes: If the target signal sequence does not exist, the electrical signal is directly forwarded to the terminal device.

10. The method for establishing a PCIe optical interconnection link according to claim 8, characterized in that: Before detecting whether the target signal sequence exists in the electrical signal, the method further includes: detecting whether there is an electrical idle character sequence in the electrical signal; If the electrical idle character sequence does not exist, the step of detecting whether the target signal sequence exists in the electrical signal is performed.

11. The method for establishing a PCIe optical interconnection link according to claim 10, characterized in that: After detecting whether there is an electrical idle character sequence in the electrical signal, the method further includes: If the electrical idle character sequence exists, determining the current link rate according to the electrical idle character sequence and recording it; Counting the electrical idle character sequence, and judging whether the electrical idle character sequence has been sent out according to the count value; If the electrical idle character sequence is sent completely, the target signal sequence is ready to be received.

12. The PCIe optical interconnection link establishment method according to claim 11, characterized in that: After judging whether the electrical idle character sequence is sent according to the count value, the method further includes: If the electrical idle character sequence is not completely sent, the electrical signal is directly forwarded to the terminal device.

13. The PCIe optical interconnection link establishment method according to claim 1, characterized in that: The bypass module is integrated with the local optical transmitting component and the local optical receiving component in the optical module.

14. The PCIe optical interconnection link establishment method according to claim 1, characterized in that: The bypass module is connected to the host and the optical module respectively as an independent device.

15. The PCIe optical interconnection link establishment method according to claim 1, characterized in that: The bypass module is integrated in the PCIe signal repeater, and the PCIe signal repeater is connected to the host and the optical module respectively.

16. The method for establishing a PCIe optical interconnection link according to any one of claims 1 to 15, characterized in that: The bypass module includes a pattern generator, a data signal gate, a pattern detection controller and a termination device; The code detection controller is configured to obtain the upstream data signal transmitted by the electrical path, detect the whether there is an electrical idle character sequence in the upstream data signal, recording the current link rate, judging whether the electrical idle character sequence is sent completely by counting the electrical idle character sequence, controlling the data transmission of the data signal selector, and controlling the pattern generator to generate a pattern; The code pattern generator is configured to generate a target signal sequence of a corresponding rate according to the link rate; The data signal selector is configured to obtain an upstream data signal transmitted by the electrical path, and send the target signal sequence to the opposite end through the PCIe optical interconnect link; The termination device is configured to store a target signal sequence sent by the opposite end.

17. The method for establishing a PCIe optical interconnection link according to claim 16, characterized in that: The code detection controller is also configured to receive the electrical signal sent by the opposite end after being photoelectrically converted by the optical receiving component, and control the signal transmission channel of the data signal selector; The data signal selector is also configured to receive an electrical signal sent by the opposite end after photoelectric conversion by an optical receiving component, and forward it to the termination device when the electrical signal is a target signal sequence, and forward it to the terminal device when the electrical signal is not a target signal sequence.

18. The method for establishing a PCIe optical interconnection link according to claim 16, characterized in that: The pattern detection controller supports identification of patterns associated with electrical idle states during PCIe link training.

19. The method for establishing a PCIe optical interconnection link according to claim 16, wherein: The signal rate supported by the data signal selector covers the signal rate specified by the PCIe protocol.

20. A PCIe optical interconnection link establishment device, characterized in that: include: A detection module is configured to obtain an upstream data signal transmitted by the electrical path, and detect whether an electrical idle character sequence exists in the upstream data signal; A recording module is configured to record the current link rate if the electrical idle character sequence exists, and determine whether the electrical idle character sequence has been sent by counting the electrical idle character sequence; The sequence sending module is configured to generate a target signal sequence of a corresponding rate according to the link rate when the electrical idle character sequence is completed, and send the target signal sequence to the opposite end through the PCIe optical interconnection link so that the opposite end can maintain stable operation based on the target signal sequence.

21. An electronic device, characterized in that: include: a memory configured to store a computer program; A processor is configured to execute the computer program to implement the PCIe optical interconnect link establishment method according to any one of claims 1 to 19.

22. A computer non-volatile readable storage medium, characterized in that: The device is configured to store a computer program; wherein when the computer program is executed by a processor, the method for establishing a PCIe optical interconnection link as claimed in any one of claims 1 to 19 is implemented.

23. A PCIe optical interconnect link system, characterized in that: It comprises a host, an optical module and a bypass module as claimed in any one of claims 1 to 19; the bypass module comprises a pattern generator, a data signal selector, a pattern detection controller and a termination device; The data signal selector is respectively connected to the host, the optical transmitting component and the optical receiving component in the optical module, the code generator and the terminal device; The code detection controller is connected to the host, the data signal selector, the light receiving component and the code generator respectively.

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