Semiconductor encapsulation structure

Abstract

A semiconductor encapsulation structure, comprising: a substrate (206), an integrated circuit chip (203) arranged on the substrate (206), and a cover structure (201) covering the integrated circuit chip (203), wherein a first thermal interface material (202) fills the space between the inner side of the cover structure (201) and the integrated circuit chip (203); a blocking structure (207) for blocking the first thermal interface material (202) is arranged on the inner side of the cover structure (201); the blocking structure (207) comprises a blocking layer (207a); the blocking layer (207a) extends from a side wall of the integrated circuit chip (203) to the inner side of the cover structure (201); and a first space is formed between an inner wall of the blocking layer (207a) and the side wall of the integrated circuit chip (203). The semiconductor encapsulation structure can solve the problem in the prior art whereby an encapsulation structure deforms during a temperature cycling process and a large tensile stress is generated at a connection interface of a thermal interface material and a chip, which cause layering as a result; and bubbles in the thermal interface material can enter a side wall dam area along the flowing thermal interface material during an encapsulation process, which provides a path for the discharge of the bubbles, thereby reducing the generation of voids, and improving the encapsulation reliability.

Description

A semiconductor packaging structure

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on Chinese patent application CN2023108028610 filed on June 30, 2023, entitled “A Semiconductor Packaging Structure,” and claims the priority of the patent application, all of the contents disclosed therein are incorporated into this disclosure by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of semiconductor chip packaging and testing, and in particular, to a semiconductor packaging structure. Background Art

[0004] With the continuous evolution of chip manufacturing processes, advanced packaging technologies such as 2D, 2.5D, and 3D have increased the functionality and speed of chip packaging, while consuming increasing power and volume. Heat dissipation issues are becoming increasingly prominent. To address this, many projects currently use Indium thermal interface materials (TIMs) and their alloys, which have high thermal conductivity. While this has addressed the heat dissipation issue, reliability issues such as delamination, high void rates, and poor coverage have emerged, seriously impacting product performance. Figure 1 illustrates a semiconductor packaging solution from related art. As shown in Figure 1, during high and low temperature cycling, the entire package structure deforms due to differences in material properties such as the coefficient of thermal expansion (CTE) and Young's modulus between the metal lid, metal TIM, chip, and substrate. This creates stress at the TIM-chip interface. Analysis of actual production slices shows that during cooling, the TIM contracts, forming the shape shown in Figure 1. This generates significant tensile stress at the TIM-chip interface, leading to delamination.

[0005] Regarding the problem in related technologies where the packaging structure deforms during temperature cycling, large tensile stress is generated at the interface between the TIM and the chip, leading to delamination, for which no solution has yet been proposed.

[0006] Summary of the Invention

[0007] The embodiments of the present disclosure provide a semiconductor packaging structure to at least solve the problem in the related art that the packaging structure is deformed during temperature cycling, and a large tensile stress is generated at the interface between the TIM and the chip, resulting in delamination.

[0008] According to an embodiment of the present disclosure, a semiconductor package structure is provided, comprising: a substrate 206, an integrated circuit chip 203 disposed on the substrate 206, and a lid structure 201 covering the integrated circuit chip 203, wherein a first TIM 202 is filled between the inner side of the lid structure 201 and the integrated circuit chip 203, wherein:

[0009] A blocking structure 207 for blocking the first TIM 202 is provided on the inner side of the lid structure 201. The blocking structure 207 includes a blocking layer 207a, wherein the blocking layer 207a extends from the sidewall of the integrated circuit chip 203 to the inner side of the lid structure 201, wherein a first space is formed between the inner wall of the blocking layer 207a and the sidewall of the integrated circuit chip 203. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1 is a schematic diagram of a semiconductor packaging structure in the related art;

[0011] FIG2 is a schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure;

[0012] FIG3 is a perspective schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure;

[0013] FIG4 is a schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure, wherein the barrier layer is a hook type;

[0014] 5 is a horizontal cross-sectional view of the package structure along line AA′ in FIG. 4 according to an embodiment of the present disclosure;

[0015] 6 is a horizontal cross-sectional view of the package structure along line BB' in FIG. 4 according to an embodiment of the present disclosure;

[0016] FIG7 is a schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure, wherein the barrier layer is a vertical sidewall;

[0017] FIG8 is a schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure, wherein the barrier layer has a right-angled sidewall. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0019] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] In this embodiment, a semiconductor package structure is provided. FIG2 is a schematic diagram of a semiconductor package result according to an embodiment of the present disclosure. As shown in FIG2 , the semiconductor package structure includes: a substrate 206, an integrated circuit chip 203 disposed on the substrate 206, and a lid structure 201 covering the integrated circuit chip 203. A first TIM 202 is filled between the inner side of the lid structure 201 and the integrated circuit chip 203. A blocking structure 207 is disposed on the inner side of the lid structure 201 for blocking the first TIM 202. The blocking structure 207 includes a blocking layer 207a. The blocking layer 207a extends from the sidewall of the integrated circuit chip 203 to the inner side of the lid structure 201 and is used to surround the first TIM 202. A first space is formed between the inner wall of the blocking layer 207a and the sidewall of the integrated circuit chip 203. The blocking layer 207a can prevent the first TIM 202 from overflowing and control the overflow height of the first TIM 202.

[0021] The semiconductor package structure disclosed above and in the following embodiments can effectively reduce TIM material failure during reliability testing. Compared to related semiconductor package structures, this semiconductor package structure incorporates a barrier structure that prevents TIM overflow. This barrier effectively addresses the issue of TIM-die interface delamination, reducing TIM thickness and improving reliability.

[0022] Figure 3 shows a schematic diagram of the effect of the semiconductor package structure blocking TIM according to an embodiment of the present disclosure. As shown in Figure 3, the blocking structure can effectively prevent TIM from overflowing.

[0023] Figures 2 and 3 also show examples of other components of the semiconductor package structure. In this example, the semiconductor package structure includes a substrate stack structure that transmits functional signals to the PCB board, and the substrate has many stacked layers. The integrated circuit chip 203 can be interconnected with the substrate 206 through micro-bumps, and the bottom filler 204 is filled between the micro-bumps. The substrate 206 can be formed by laminating an intermediate core layer, a dielectric layer, and metal traces. Specifically, one or more dielectric layers and metal trace layers can be arranged above and below the intermediate core layer. One or more integrated circuit chips 203 are arranged on the package substrate 206, for example, by flip-chip placement. The integrated circuit chip 203 can include a logic control chip, a memory chip, and a dummy chip. This part can also be a 2.5D packaged COWoS (Chip on Wafer on Substrate) and InFO_OS (Integrated Fan Out Wafer Level Package On Organic Substrate) chip structure.

[0024] In one embodiment, the lid structure 201 is a cover structure. The edge of the lid structure 201 has a protruding portion, which is covered above the integrated circuit chip 203 through the protruding portion, and a cavity is formed between the protruding portion and the side wall of the integrated circuit chip 203. The protruding portion of the lid structure 201 can be bonded to the substrate 206 by an adhesive material 205, which plays a role in controlling the warping of the packaging substrate, protecting the chip and dissipating heat. The lid structure 201 contacts the chip 203 through the thermal interface material 202, and the chip 203 is interconnected with the substrate 206 through micro-bumps. Underfill material 204 is filled between the micro-bumps to absorb the stress generated during high and low temperature processes. The lid structure 201 and the barrier structure 207 can be stamped and the material can be metal.

[0025] In one embodiment, a second TIM may be filled in the first space, where the second TIM surrounds the contact surface between the integrated circuit chip 203 and the first TIM 202. The second TIM and the first TIM 202 may be the same or different TIMs.

[0026] In one embodiment, the distance from the second end of the barrier layer 207a to the inner side of the lid structure 201 (or the surface of the first TIM 202 adjacent to the lid structure 201) is greater than or equal to one-third of the total thickness of the integrated circuit chip 203. This allows the depth of the TIM filled in the first space to be greater than or equal to one-third of the total thickness of the integrated circuit chip 203.

[0027] In some embodiments, as shown in Figures 2 and 3 , the first end of the barrier layer 207a is fixed to the inner side of the lid structure 201. For example, the first end of the barrier layer 207a can be fixed to the inner side of the lid structure 201 by welding. The second end of the barrier layer 207a can be directly connected / coupled to the sidewall of the integrated circuit chip 203, or indirectly connected / coupled to the sidewall of the integrated circuit chip 203 through another object. For example, in one embodiment, the barrier structure 207 may further include a sealing gasket 207b (see Figures 5-6 and 8-9 ), wherein the second end of the barrier layer 207a is coupled to the sidewall of the integrated circuit chip 203 via the sealing gasket 207b. In other words, the second end of the barrier layer 207a is a certain distance from the sidewall of the integrated circuit chip 203, and the sealing gasket 207b fills this distance, thereby enclosing the TIM and preventing it from overflowing. The sealing gasket 207b can be made of a rubber material with good elasticity.

[0028] In one embodiment, sealing gasket 207b extends along the barrier layer to surround the chip, as shown in Figure 6. The sealing gasket and barrier layer structures can fix the TIM material in a certain space. During the reliability process, when the TIM becomes fluid, it is unlikely to flow out of the specified area, thus ensuring the thickness and uniformity of the TIM material.

[0029] In various embodiments of the present disclosure, the barrier layer 207a can extend from the first end to the second end along any path, that is, the barrier layer 207a can be of any shape. Figures 4-8 show enlarged schematic diagrams of the barrier structure 207 according to embodiments of the present disclosure, wherein the barrier layer 207a is shown as three specific examples 207a1, 207a2, and 207a3.

[0030] In the example of Figures 4-6 , barrier layer 207a1 is substantially perpendicular to the sidewall of integrated circuit chip 203 at its second end. "Substantially perpendicular" means perpendicular within an acceptable tolerance and does not necessarily require a 90-degree angle. In the example of Figure 4 , the outer wall of barrier layer 207a forms an acute angle with the inner side of lid structure 201 at its first end, meaning barrier layer 207a1 has a hook-shaped design. The second end of barrier layer 207a1 contacts the sidewall of integrated circuit chip 203 via sealing gasket 207b. A first space is formed between the inner wall of barrier layer 207a1, the first TIM 202, and the integrated circuit chip 203, and is filled with second TIM 207c.

[0031] In the example of FIG4 , sealing gasket 207b completely fills the gap between the second end of barrier layer 207a1 and the sidewall of integrated circuit chip 203. Specifically, sealing gasket 207b's width H1-a should completely fill the gap between the second end of barrier layer 207a1 and the sidewall of chip 203 after assembly. TIM 207c surrounds the interface between integrated circuit chip 203 and TIM 202 and extends downward along the interface, forming a fill height H3 between the first and second ends of the barrier layer. H3 is greater than or equal to one-third of the total thickness of integrated circuit chip 203.

[0032] In the example of FIG4 , the barrier structure 207 further includes a support structure 207d disposed between the outer wall of the barrier layer 207a and the inner side of the lid structure 201. One end of the support structure 207d is connected to the inner side of the lid structure 201, and the other end is connected to the outer wall of the barrier layer 207a. In other words, the support structure 207d is disposed around the barrier layer 207a1 to enhance the bonding strength between the barrier layer 207a and the lid structure 201. The barrier layer 207a1 and the support structure 207d may be integral or separate structures.

[0033] Barrier layer 207a1 and lid structure 201 can be fused together by welding. Figure 5 is a horizontal cross-sectional view of the package structure along line AA' in Figure 4 according to an embodiment of the present disclosure. As shown in Figure 5, the second end of barrier layer 207a1 contacts the sidewall of chip 203 via sealing gasket 207b. Figure 6 is a horizontal cross-sectional view of the package structure along line BB' in Figure 4 according to an embodiment of the present disclosure. As shown in Figure 6, the space between the inner wall of barrier layer 207a and the sidewalls of TIM 202 and chip 203 is filled with TIM 207c.

[0034] In another example, the barrier layer 207a2 can be approximately parallel to the sidewalls of the integrated circuit chip 203 at its second end. Approximately parallel means parallel within an allowable error range. As shown in FIG7 , the barrier layer 207a2 comprises vertical sidewalls that surround the chip area. In the example of FIG7 , the barrier structure 207 further includes a sealing gasket 207b. The second end of the barrier layer / vertical sidewall 207a2 contacts the sidewalls of the integrated circuit chip 203 via the sealing gasket 207b. The sealing gasket 207b completely fills the distance between the lower extension of the vertical sidewall 207a2 and the integrated circuit chip 203. In other words, the sealing gasket's width H1-b should completely fill the distance between the vertical sidewall 207a2 and the integrated circuit chip 203 after assembly. The first space formed between the inner wall of the vertical sidewall 207a2 and the TIM 202 and the sidewalls of the integrated circuit chip 203 is filled with a second TIM 207c. The second TIM 207c can be made of the same or different materials as the first TIM 202. Similarly, the first end of the vertical sidewall 207a2 is fixed to the inner side of the lid structure 201, and the distance from the second end of the vertical sidewall 207a2 to the inner side of the lid structure 201 is greater than or equal to one-third of the total thickness of the integrated circuit chip 203. This ensures that the fill height H3 of the second TIM 207c is greater than or equal to one-third of the total thickness of the integrated circuit chip 203.

[0035] In another example, as shown in FIG8 , barrier layer 207a3 includes a first barrier sublayer and a second barrier sublayer. One end of the first barrier sublayer serves as the first end of barrier layer 207a3, the other end of the first barrier sublayer connects to one end of the second barrier sublayer, and the other end of the second barrier sublayer serves as the second end of barrier layer 207a3. The first and second barrier sublayers are perpendicular to each other, and the first barrier layer is perpendicular to the lid structure 201, while the second barrier layer is perpendicular to the sidewalls of the integrated circuit chip 203. In other words, barrier layer 207a3 has rectangular sidewalls. As shown in FIG8 , barrier structure 207 further includes a sealing gasket 207b. The second end of barrier layer 207a3 contacts the sidewalls of the integrated circuit chip 203 via the sealing gasket 207b. Specifically, the width H1-c of sealing gasket 207b is sufficient to fill the distance between the second end of the rectangular sidewall 207a3 and the sidewalls of the integrated circuit chip 203 after assembly. A second TIM 207c fills the first space formed between the inner wall of the rectangular sidewall 207a3 and the sidewalls of the TIM 202 and the integrated circuit chip 203. The TIM 207c surrounds the contact surface between the integrated circuit chip 203 and the TIM 202 and extends downward along the contact surface to form a fill height H3 that is greater than or equal to approximately one-third of the total thickness of the integrated circuit chip 203.

[0036] It should be noted that the blocking layer 207a can extend from the first end to the second end along any trajectory. The above-mentioned hook-type blocking layer 207a1, vertical side wall 207a2, and right-angled side wall 207a3 are only three typical embodiments of the blocking layer. The specific structure of the blocking layer 207a is not limited to the above three methods.

[0037] The semiconductor package structures in various embodiments of the present disclosure require design tolerances during design to ensure implementation during the assembly process. In various embodiments, the width of the sealing gasket 207b is equal to or greater than the distance from the second end of the barrier layer 207a to the chip sidewall. Furthermore, the barrier layer span H2 on the inner side of the lid structure is greater than or equal to the chip width, which facilitates mounting the lid structure on the substrate.

[0038] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0039] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0040] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A semiconductor package structure, comprising: A substrate (206), an integrated circuit chip (203) disposed on the substrate (206), and a lid structure (201) covering the integrated circuit chip (203), wherein a first thermal interface material TIM (202) is filled between the inner side of the lid structure (201) and the integrated circuit chip (203), wherein: A blocking structure (207) for blocking the first TIM (202) is arranged on the inner side of the lid structure (201), and the blocking structure (207) comprises a blocking layer (207a), wherein the blocking layer (207a) extends from the side wall of the integrated circuit chip (203) to the inner side of the lid structure (201), wherein a first space is formed between the inner wall of the blocking layer (207a) and the side wall of the integrated circuit chip (203).

2. The semiconductor package structure according to claim 1, wherein: A first end of the barrier layer (207a) is fixed on the inner side of the lid structure (201).

3. The semiconductor package structure according to claim 1 or 2, wherein: The barrier structure (207) further comprises a sealing gasket (207b), wherein the second end of the barrier layer (207a) is coupled to the side wall of the integrated circuit chip (203) through the sealing gasket (207b).

4. The semiconductor package structure according to claim 3, wherein: The barrier layer (207a) is perpendicular to the sidewall of the integrated circuit chip (203) at the second end.

5. The semiconductor package structure according to claim 4, wherein: The outer wall of the barrier layer (207a) forms an acute angle with the inner side of the lid structure (201) at the first end.

6. The semiconductor package structure according to claim 3, wherein: The barrier layer (207a) is parallel to the side wall of the integrated circuit chip (203) at the second end.

7. The semiconductor package structure according to claim 3, wherein: The blocking layer (207a) comprises a first blocking sublayer and a second blocking sublayer, wherein one end of the first blocking sublayer is the first end of the blocking layer (207a), the other end of the first blocking sublayer is connected to one end of the second blocking sublayer, and the other end of the second blocking sublayer is the second end of the blocking layer (207a), wherein the first blocking sublayer and the second blocking sublayer are perpendicular, and the first blocking sublayer is perpendicular to the lid structure (201), and the second blocking sublayer is perpendicular to the side wall of the integrated circuit chip (203).

8. The semiconductor package structure according to claim 3, wherein: The first space is filled with a second TIM (207c), and the second TIM (207c) surrounds the contact surface between the integrated circuit chip (203) and the first TIM (202).

9. The semiconductor package structure according to claim 8, wherein: The distance from the second end of the barrier layer (207a) to the inner side of the lid structure (201) is greater than or equal to one third of the total thickness of the integrated circuit chip (203).

10. The semiconductor package structure according to claim 1, wherein: The blocking structure (207) further comprises a supporting structure (207d) arranged between the outer wall of the blocking layer (207a) and the inner side of the lid structure (201), wherein: One end of the support structure (207d) is connected to the inner side of the lid structure (201), and the other end is connected to the outer wall of the barrier layer (207a).

11. The semiconductor package structure according to claim 9, wherein: The barrier layer (207a) and the support structure (207d) are an integral structure or a separate structure.

12. The semiconductor package structure according to any one of claims 3 to 11, wherein: The width of the sealing gasket (207b) is equal to the distance from the second end of the barrier layer (207a) to the side wall of the integrated circuit chip (203).

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