Pseudo-differential capacitance measurement circuit and measurement method

Abstract

Disclosed in the present invention are a pseudo-differential capacitance measurement circuit and measurement method. The circuit comprises: a first sampling unit, which comprises a first charging unit and a first charge transfer unit that are respectively connected to a reference capacitor Cf; a second sampling unit, which comprises a second charging unit and a second charge transfer unit that are respectively connected to a capacitor Cs to be measured; a first conversion unit; a second conversion unit; a storage unit, which comprises a first storage capacitor CM1 and a second storage capacitor CM2; a modulation unit, which comprises a first modulation capacitor Cmod1 and a second modulation capacitor Cmod2; a control unit, which comprises several switches; and a comparator, a first input end and a second input end of which are respectively connected to the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2, and an output end of which is connected to the control unit. In the capacitance measurement circuit and measurement method in the present invention, a pseudo-differential structure is used, thereby achieving a very high suppression capability for common-mode interference, ensuring the chip performance, and improving the measurement precision.

Description

Pseudo-differential capacitance detection circuit and detection method

[0001] The present invention claims priority to Chinese patent application number 202310800101.6 filed with the Patent Office of China on June 30, 2023, entitled “Pseudo-differential capacitance detection circuit and detection method”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention belongs to the technical field of capacitance detection, and in particular relates to a pseudo-differential capacitance detection circuit and a detection method. Background Art

[0003] In existing technologies, capacitance detection systems typically use a reference voltage to charge the capacitor to be tested. An integrator is then used to convert the capacitance information into a voltage signal, which is then output by the integrator. Finally, an ADC is used to convert the voltage signal into a digital output. This structure has a clear operating principle and facilitates analysis of the impact of various components. However, the test process is complex, requiring each stage to complete before proceeding to the next. This slows down the entire system and increases its average power consumption. Furthermore, the integrator's output voltage is related to the integrating capacitor, which can be subject to process variations, leading to gain errors in the voltage-capacitance relationship.

[0004] Another capacitance detection system with faster detection speed requires the use of an off-chip Cmod capacitor as an integrating capacitor to quantify the detected capacitance. The comparator detection point is located on the upper plate of Cmod and is easily affected by external interference signals.

[0005] Therefore, in order to solve the above technical problems, it is necessary to provide a pseudo differential capacitance detection circuit and detection method.

[0006] Summary of the Invention

[0007] In view of this, an object of the present invention is to provide a pseudo-differential capacitance detection circuit and detection method to perform quantitative detection on a capacitance to be measured.

[0008] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows:

[0009] A pseudo-differential capacitance detection circuit, comprising:

[0010] A first sampling unit includes a first charging unit and a first charge transfer unit respectively connected to the reference capacitor Cf, the first charging unit is used to charge the reference capacitor Cf, and the first charge transfer unit is used to inject and / or extract charge into the reference capacitor Cf;

[0011] The second sampling unit includes a second charging unit and a second charge transfer unit respectively connected to the capacitor to be measured Cs, the second charging unit is used to charge the capacitor to be measured Cs, and the second charge transfer unit is used to inject and / or extract charge into the capacitor to be measured Cs;

[0012] A first conversion unit, configured to convert a charge signal on the reference capacitor Cf into a first voltage signal;

[0013] A second conversion unit, configured to convert the charge signal on the capacitor Cs to be measured into a second voltage signal;

[0014] a storage unit, comprising a first storage capacitor Cm1 connected to the first conversion unit and a second storage capacitor Cm2 connected to the second conversion unit, for storing the first voltage signal and the second voltage signal respectively;

[0015] A modulation unit, comprising a first modulation capacitor Cmod1 and a second modulation capacitor Cmod2;

[0016] A control unit connected between the storage unit and the modulation unit, comprising a plurality of switches;

[0017] A comparator, wherein the first input terminal and the second input terminal are respectively connected to the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2, and the output terminal is connected to the control unit. The comparator obtains a control signal according to the modulated voltage of the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to control the control unit.

[0018] In one embodiment, the first charging unit includes a first switch S1, a first end of the first switch S1 is connected to a reference voltage Vref, a second end of the first switch S1 is connected to a first end of a reference capacitor Cf, and a second end of the reference capacitor Cf is connected to a ground potential;

[0019] The second charging unit includes a second switch S2 , a first end of the second switch S2 is connected to a reference voltage Vref, a second end of the second switch S2 is connected to a first end of a capacitor to be measured Cs, and a second end of the capacitor to be measured Cs is connected to the ground potential.

[0020] In one embodiment, the first charge transfer unit includes a first charge injection unit and a first charge extraction unit; the first charge injection unit includes a first current source Idac1 and a third switch S3, wherein the input end of the first current source Idac1 is connected to a power supply voltage, the output end is connected to a first end of the third switch S3, and the second end of the third switch S3 is connected to a first end of a reference capacitor Cf; the first charge extraction unit includes a second current source Idac2 and a fourth switch S4, wherein the first end of the fourth switch S4 is connected to the first end of the reference capacitor Cf, the second end is connected to the input end of the second current source Idac2, and the output end of the second current source Idac2 is connected to the ground potential;

[0021] The second charge transfer unit includes a second charge injection unit and a second charge extraction unit; the second charge injection unit includes a third current source Idac3 and a fifth switch S5, the input end of the third current source Idac3 is connected to the power supply voltage, the output end is connected to the first end of the fifth switch S5, and the second end of the fifth switch S5 is connected to the first end of the capacitor to be measured Cs; the second charge extraction unit includes a fourth current source Idac4 and a sixth switch S6, the first end of the sixth switch S6 is connected to the first end of the capacitor to be measured Cs, and the second end is connected to the input end of the fourth current source Idac4, and the output end of the fourth current source Idac4 is connected to the ground potential.

[0022] In one embodiment, the third current provided by the third current source Idac3 is n times the first current provided by the first current source Idac1 , and the fourth current provided by the fourth current source Idac4 is n times the second current provided by the second current source Idac2 , where n is a capacitance compensation factor.

[0023] In one embodiment, the first conversion unit includes a first buffer, a seventh switch S7, and an eighth switch S8. The first end of the seventh switch S7 is connected to the first end of the reference capacitor Cf, and the second end is connected to the first input end of the first buffer. The second input end and the output end of the first buffer are respectively connected to the first end of the eighth switch S8.

[0024] The second conversion unit includes a second buffer, a ninth switch S9, and a tenth switch S10, wherein a first end of the ninth switch S9 is connected to a first end of the capacitor Cs to be measured, and a second end is connected to a first input end of the second buffer, and a second input end and an output end of the second buffer are respectively connected to a first end of the tenth switch S10;

[0025] A first end of the first storage capacitor Cm1 is connected to a second end of the eighth switch S8, and a second end thereof is connected to the ground potential;

[0026] A first end of the second storage capacitor Cm2 is connected to a second end of the tenth switch S10 , and a second end thereof is connected to the ground potential.

[0027] In one embodiment, the control unit includes an eleventh switch S11, a twelfth switch S12, a thirteenth switch S14, and a fourteenth switch S14;

[0028] The first end of the eleventh switch S11 is connected to the first end of the first storage capacitor Cm1, and the second end is connected to the first end of the first modulation capacitor Cmod1;

[0029] The first end of the twelfth switch S12 is connected to the first end of the first storage capacitor Cm1, and the second end is connected to the first end of the second modulation capacitor Cmod2;

[0030] The first end of the thirteenth switch S13 is connected to the first end of the second storage capacitor Cm2, and the second end is connected to the first end of the first modulation capacitor Cmod1;

[0031] The first end of the fourteenth switch S14 is connected to the first end of the second storage capacitor Cm2, and the second end is connected to the first end of the second modulation capacitor Cmod2;

[0032] The second end of the first modulation capacitor Cmod1 and the second end of the second modulation capacitor Cmod2 are both connected to the ground potential.

[0033] In one embodiment, the circuit further includes a D flip-flop connected to a comparator, wherein a first input terminal of the comparator is connected to a first terminal of a first modulation capacitor Cmod1, a second input terminal is connected to a first terminal of a second modulation capacitor Cmod2, an output terminal of the comparator is connected to an input terminal D of the D flip-flop, and an output terminal Q of the D flip-flop is used to output a control signal to control the thirteenth switch S13 and / or the fourteenth switch S14.

[0034] In one embodiment, the first storage capacitor Cm1 , the second storage capacitor Cm2 , the first modulation capacitor Cmod1 , and the second modulation capacitor Cmod2 are all on-chip capacitors, and the reference capacitor Cf is an on-chip capacitor or an off-chip capacitor.

[0035] In one embodiment, the first storage capacitor Cm1, the second storage capacitor Cm2, the first modulation capacitor Cmod1, the second modulation capacitor Cmod2, the reference capacitor Cf and the capacitor to be measured Cs satisfy: Cmod1<Cs, Cmod2<Cs; Cmod1 / Cm1≥100; Cmod2 / Cm2≥100; Cmod1 / (Cm1+Cf)=0.1~10; Cmod2 / (Cm2+Cs)=0.05~10; Cmod1 / (Cm2+Cs)=0.05~10; Cmod2 / (Cm1+Cf)=0.1~10.

[0036] In one embodiment, the sizes of the first storage capacitor Cm1, the second storage capacitor Cm2, the first modulation capacitor Cmod1, the second modulation capacitor Cmod2, the reference capacitor Cf and the measured capacitor Cs are: Cs = 0 ~ 200pF; Cf = 5 ~ 50pF; Cm1 = Cm2 = 10 ~ 1000fF; Cmod1 = Cmod2 = 1 ~ 100pF.

[0037] In one embodiment, the size of the measured capacitor Cs is: Cs=Dutycycle(Q)*Cf*(n+1), where Dutycycle(Q) is the duty cycle of the control signal output by the comparator, and the capacitance compensation factor n=Idac3 / Idac1=Idac4 / Idac2.

[0038] Another embodiment of the present invention provides a technical solution as follows:

[0039] A pseudo-differential capacitance detection method, the method comprising:

[0040] Charge the reference capacitor Cf and the capacitor to be measured Cs respectively;

[0041] Inject or extract charge into the reference capacitor Cf and the capacitor to be measured Cs respectively;

[0042] Converting the charge signal on the reference capacitor Cf and the charge signal on the measured capacitor Cs into a first voltage signal and a second voltage signal respectively, and storing them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively;

[0043] Transfer the charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 to the first modulation capacitor Cmod1 or the second modulation capacitor Cmod2, and modulate the first voltage signal and the second voltage signal respectively through the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2;

[0044] Compare the voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to obtain a control signal Q;

[0045] The size of the capacitance to be measured Cs is obtained according to the duty cycle of the control signal Q, the reference capacitance Cf, and the current ratio of injecting or extracting charges.

[0046] In one embodiment, the method includes several quantization cycles, each of which includes the following steps:

[0047] Charge the reference capacitor Cf and the capacitor to be measured Cs respectively;

[0048] Injecting charges into the reference capacitor Cf and the capacitor to be measured Cs through the first current and the third current respectively;

[0049] Converting the charge signal on the reference capacitor Cf and the charge signal on the measured capacitor Cs into a first voltage signal and a second voltage signal respectively, and storing them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively;

[0050] Transferring the charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 to the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2, respectively, and modulating the first voltage signal and the second voltage signal through the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2;

[0051] Compare the voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to obtain a control signal Q1;

[0052] Charge the reference capacitor Cf and the capacitor to be measured Cs respectively;

[0053] Extracting charges from the reference capacitor Cf and the capacitor to be measured Cs through the second current and the fourth current respectively;

[0054] Converting the charge signal on the reference capacitor Cf and the charge signal on the measured capacitor Cs into a first voltage signal and a second voltage signal respectively, and storing them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively;

[0055] Transferring the charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 to the second modulation capacitor Cmod2 and the first modulation capacitor Cmod1, respectively, and modulating the first voltage signal and the second voltage signal through the second modulation capacitor Cmod2 and the first modulation capacitor Cmod1, respectively;

[0056] The voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 are compared to obtain a control signal Q2.

[0057] In one embodiment, the method further includes:

[0058] If the control signal Q1 is at a high level, the first voltage signal and the second voltage signal are modulated by the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 respectively; if the control signal Q1 is at a low level, the first voltage signal is modulated by the first modulation capacitor Cmod1; and,

[0059] If the control signal Q2 is high, the first voltage signal and the second voltage signal are modulated respectively by the second modulation capacitor Cmod2 and the first modulation capacitor Cmod1; if the control signal Q2 is low, the first voltage signal is modulated by the second modulation capacitor Cmod2.

[0060] In one embodiment, the size of the measured capacitor Cs is: Cs=Dutycycle(Q)*Cf*(n+1), where Dutycycle(Q) is the duty cycle of the control signal Q output by the comparator, the capacitance compensation multiple n=Idac3 / Idac1=Idac4 / Idac2, Idac1, Idac2, Idac3, Idac4 are the sizes of the first current, the second current, the third current and the fourth current respectively, and these four currents can be selected from the IDAC array according to different ratios.

[0061] The present invention has the following beneficial effects:

[0062] The capacitance detection circuit and detection method of the present invention adopt a pseudo-differential structure, which has a strong suppression capability for common-mode interference, ensures chip performance, and improves detection accuracy;

[0063] In addition, the reference capacitor, storage capacitor and modulation capacitor are all on-chip capacitors, which avoids the problem of external interference on the off-chip capacitors and reduces the number of PADs required for the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0065] FIG1 is a schematic diagram of a module of a pseudo-differential capacitance detection circuit in the present invention;

[0066] FIG2 is a schematic diagram of a pseudo-differential capacitance detection circuit according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0068] Referring to FIG1 , the present invention discloses a pseudo-differential capacitance detection circuit, comprising:

[0069] A first sampling unit includes a first charging unit and a first charge transfer unit respectively connected to the reference capacitor Cf, the first charging unit is used to charge the reference capacitor Cf, and the first charge transfer unit is used to inject and / or extract charge into the reference capacitor Cf;

[0070] The second sampling unit includes a second charging unit and a second charge transfer unit respectively connected to the capacitor to be measured Cs, the second charging unit is used to charge the capacitor to be measured Cs, and the second charge transfer unit is used to inject and / or extract charge into the capacitor to be measured Cs;

[0071] A first conversion unit, configured to convert a charge signal on the reference capacitor Cf into a first voltage signal;

[0072] A second conversion unit, configured to convert the charge signal on the capacitor Cs to be measured into a second voltage signal;

[0073] a storage unit, comprising a first storage capacitor Cm1 connected to the first conversion unit and a second storage capacitor Cm2 connected to the second conversion unit, for storing the first voltage signal and the second voltage signal respectively;

[0074] a modulation unit, comprising a first modulation capacitor Cmod1 and a second modulation capacitor Cmod2, for modulating the first voltage signal or the second voltage signal to quantify the ratio of the reference capacitance Cf to the capacitance to be measured Cs;

[0075] A control unit connected between the storage unit and the modulation unit, comprising a plurality of switches;

[0076] A comparator, wherein the first input terminal and the second input terminal are respectively connected to the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2, and the output terminal is connected to the control unit. The comparator obtains a control signal according to the modulated voltage of the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to control the control unit.

[0077] The present invention also discloses a pseudo-differential capacitance detection method, comprising:

[0078] Charge the reference capacitor Cf and the capacitor to be measured Cs respectively;

[0079] Inject or extract charge into the reference capacitor Cf and the capacitor to be measured Cs respectively;

[0080] Converting the charge signal on the reference capacitor Cf and the charge signal on the measured capacitor Cs into a first voltage signal and a second voltage signal respectively, and storing them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively;

[0081] Transfer the charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 to the first modulation capacitor Cmod1 or the second modulation capacitor Cmod2, and modulate the first voltage signal and the second voltage signal respectively through the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2;

[0082] Compare the voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to obtain a control signal Q;

[0083] The size of the capacitance to be measured Cs is obtained according to the duty cycle of the control signal Q, the reference capacitance Cf, and the current ratio of injecting or extracting charges.

[0084] The present invention adopts a pseudo-differential structure and quantizes the measured capacitance Cs through the reference capacitance Cf, thereby obtaining the capacitance value of the measured capacitance Cs; after converting the charge signal into a voltage signal, the output result of the comparator is used to control the switching of the switch for quantization.

[0085] The present invention will be further described below with reference to specific embodiments.

[0086] 2 is a schematic diagram of a pseudo-differential capacitance detection circuit according to a specific embodiment of the present invention, which includes a first sampling unit 11, a second sampling unit 21, a first conversion unit 12, a second conversion unit 22, a storage unit 30, a modulation unit 40, a control unit 50, and a comparator 60. The circuits and principles of each unit are described in detail below.

[0087] The first sampling unit 11 includes a first charging unit 111 and a first charge transfer unit 112 respectively connected to the reference capacitor Cf. The first charging unit is used to charge the reference capacitor Cf, and the first charge transfer unit is used to inject and / or extract charge from the reference capacitor Cf.

[0088] Illustratively, the first charging unit 111 in this embodiment includes a first switch S1 , a first end of the first switch S1 is connected to a reference voltage Vref, a second end of the first end of the reference capacitor Cf is connected to a first end of the reference capacitor Cf, and a second end of the reference capacitor Cf is connected to ground potential.

[0089] In this embodiment, the first charge transfer unit 112 includes a first charge injection unit and a first charge extraction unit.

[0090] in:

[0091] The first charge injection unit includes a first current source Idac1 and a third switch S3, wherein the input end of the first current source Idac1 is connected to the power supply voltage AVDD, the output end is connected to the first end of the third switch S3, and the second end of the third switch S3 is connected to the first end of the reference capacitor Cf;

[0092] The first charge extraction unit includes a second current source Idac2 and a fourth switch S4. The first end of the fourth switch S4 is connected to the first end of the reference capacitor Cf, and the second end is connected to the input end of the second current source Idac2. The output end of the second current source Idac2 is connected to the ground potential.

[0093] The second sampling unit 21 includes a second charging unit 211 and a second charge transfer unit 212 respectively connected to the capacitor to be measured Cs. The second charging unit is used to charge the capacitor to be measured Cs, and the second charge transfer unit is used to inject and / or extract charge into the capacitor to be measured Cs.

[0094] Illustratively, the second charging unit 211 in this embodiment includes a second switch S2 , a first end of the second switch S2 is connected to the reference voltage Vref, a second end of the second switch S2 is connected to the first end of the capacitor to be measured Cs, and a second end of the capacitor to be measured Cs is connected to the ground potential.

[0095] In this embodiment, the second charge transfer unit 212 includes a second charge injection unit and a second charge extraction unit, wherein:

[0096] The second charge injection unit includes a third current source Idac3 and a fifth switch S5. The input end of the third current source Idac3 is connected to the power supply voltage AVDD, and the output end is connected to the first end of the fifth switch S5. The second end of the fifth switch S5 is connected to the first end of the capacitor to be measured Cs. The second charge extraction unit includes a fourth current source Idac4 and a sixth switch S6. The first end of the sixth switch S6 is connected to the first end of the capacitor to be measured Cs, and the second end is connected to the input end of the fourth current source Idac4. The output end of the fourth current source Idac4 is connected to the ground potential.

[0097] In a preferred embodiment, the third current provided by the third current source Idac3 is n times the first current provided by the first current source Idac1, and the fourth current provided by the fourth current source Idac4 is n times the second current provided by the second current source Idac2, where n is a capacitance compensation factor, which can be adjusted according to the ratio of the reference capacitor Cf and the capacitor to be measured Cs to adapt to the accuracy requirements.

[0098] The first conversion unit 12 is configured to convert the charge signal on the reference capacitor Cf into a first voltage signal.

[0099] Illustratively, the first conversion unit 12 in this embodiment includes a first buffer Buffer1, a seventh switch S7, and an eighth switch S8. The first end of the seventh switch S7 is connected to the first end of the reference capacitor Cf, and the second end is connected to the first input end of the first buffer Buffer1. The second input end and the output end of the first buffer Buffer1 are respectively connected to the first end of the eighth switch S8.

[0100] The second conversion unit 22 is configured to convert the charge signal on the capacitor Cs to be measured into a second voltage signal.

[0101] Illustratively, the second conversion unit 22 in this embodiment includes a second buffer Buffer2, a ninth switch S9, and a tenth switch S10. The first end of the ninth switch S9 is connected to the first end of the capacitor to be measured Cs, and the second end is connected to the first input end of the second buffer Buffer2. The second input end and the output end of the second buffer Buffer2 are respectively connected to the first end of the tenth switch S10.

[0102] The storage unit 30 includes a first storage capacitor Cm1 connected to the first conversion unit and a second storage capacitor Cm2 connected to the second conversion unit, which are used to store the first voltage signal and the second voltage signal respectively.

[0103] Illustratively, in this embodiment, the first end of the first storage capacitor Cm1 is connected to the second end of the eighth switch S8, and the second end is connected to the ground potential; the first end of the second storage capacitor Cm2 is connected to the second end of the tenth switch S10, and the second end is connected to the ground potential.

[0104] The modulation unit 40 includes a first modulation capacitor Cmod1 and a second modulation capacitor Cmod2, and is configured to modulate the first voltage signal or the second voltage signal to quantify the ratio of the reference capacitance Cf to the capacitance to be measured Cs.

[0105] The control unit 50 is connected between the storage unit and the modulation unit and includes a plurality of switches.

[0106] Illustratively, the control unit in this embodiment includes an eleventh switch S11, a twelfth switch S12, a thirteenth switch S14, and a fourteenth switch S15, wherein:

[0107] A first end of the eleventh switch S11 is connected to the first end of the first storage capacitor Cm1, and a second end of the eleventh switch S11 is connected to the first end of the first modulation capacitor Cmod1;

[0108] A first end of the twelfth switch S12 is connected to the first end of the first storage capacitor Cm1, and a second end of the twelfth switch S12 is connected to the first end of the second modulation capacitor Cmod2;

[0109] A first end of the thirteenth switch S13 is connected to the first end of the second storage capacitor Cm2, and a second end thereof is connected to the first end of the first modulation capacitor Cmod1;

[0110] A first end of the fourteenth switch S14 is connected to the first end of the second storage capacitor Cm2, and a second end thereof is connected to the first end of the second modulation capacitor Cmod2;

[0111] The second end of the first modulation capacitor Cmod1 and the second end of the second modulation capacitor Cmod2 are both connected to the ground potential.

[0112] The comparator COMP60 has a first input terminal and a second input terminal connected to the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 respectively, and an output terminal connected to the control unit. The comparator obtains a control signal based on the modulated voltage of the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to control the control unit 50.

[0113] Preferably, the detection circuit in this embodiment further includes a D flip-flop connected to the comparator, the first input terminal of the comparator COMP is connected to the first terminal of the first modulation capacitor Cmod1, the second input terminal is connected to the first terminal of the second modulation capacitor Cmod2, the output terminal of the comparator COMP is connected to the input terminal D of the D flip-flop, and the output terminal Q of the D flip-flop is used to output a control signal Q to control the thirteenth switch S13 and / or the fourteenth switch S14.

[0114] In this embodiment, the first storage capacitor Cm1, the second storage capacitor Cm2, the first modulation capacitor Cmod1, the second modulation capacitor Cmod2, and the reference capacitor Cf are all on-chip capacitors. In other embodiments, the reference capacitor Cf may also be an off-chip capacitor.

[0115] In the present invention, in order to avoid external interference outside the chip, by setting the capacitance of each capacitor, the capacitance of the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 can be controlled within a certain range (such as 100pF), so that the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 can be set inside the chip.

[0116] Specifically, the size of each capacitor in the present invention satisfies the following formula: Cmod1<Cs, Cmod2<Cs; Cmod1 / Cm1≥100; Cmod2 / Cm2≥100; Cmod1 / (Cm1+Cf)=0.1~10; Cmod2 / (Cm2+Cs)=0.05~10; Cmod1 / (Cm2+Cs)=0.05~10; Cmod2 / (Cm1+Cf)=0.1~10.

[0117] Preferably, the sizes of the capacitors are: Cs=0-200 pF; Cf=5-50 pF; Cm1=Cm2=10-1000 fF; Cmod1=Cmod2=1-100 pF.

[0118] For example, the sizes of the capacitors in this embodiment are: Cs=0-200 pF; Cf=10 pF; Cm1=Cm2=100 fF; Cmod1=Cmod2=10 pF.

[0119] The pseudo differential capacitance detection method of the present invention includes:

[0120] Charge the reference capacitor Cf and the capacitor to be measured Cs respectively;

[0121] Inject or extract charge into the reference capacitor Cf and the capacitor to be measured Cs respectively;

[0122] Converting the charge signal on the reference capacitor Cf and the charge signal on the measured capacitor Cs into a first voltage signal and a second voltage signal respectively, and storing them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively;

[0123] Transfer the charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 to the first modulation capacitor Cmod1 or the second modulation capacitor Cmod2, and modulate the first voltage signal and the second voltage signal respectively through the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2;

[0124] Compare the voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to obtain a control signal Q;

[0125] The size of the capacitance to be measured Cs is obtained according to the duty cycle of the control signal Q, the reference capacitance Cf, and the current ratio of injecting or extracting charges.

[0126] The following describes in detail the detection method of the capacitance to be measured Cs by the pseudo-differential capacitance detection circuit in this embodiment.

[0127] The capacitance detection method in this embodiment includes several quantization cycles, each of which includes the following steps:

[0128] S1. Charge the reference capacitor Cf and the capacitor to be measured Cs respectively.

[0129] The first switch S1 and the second switch S2 are closed, and the reference capacitor Cf and the capacitor to be measured Cs are charged respectively by the reference voltage Vref. After the charging is completed, the first switch S1 and the second switch S2 are turned off.

[0130] S2. Inject charges into the reference capacitor Cf and the capacitor to be measured Cs through the first current and the third current respectively.

[0131] Close the third switch S3 and the fifth switch S5 to inject charge into the reference capacitor Cf and the measured capacitor Cs through the first current source Idac1 and the third current source Idac3 respectively. The first current and the third current are two currents in the Source current array respectively, and the third current is n times the first current.

[0132] S3 . Convert the charge signal on the reference capacitor Cf and the charge signal on the capacitor to be measured Cs into a first voltage signal and a second voltage signal respectively, and store them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively.

[0133] While injecting charge into the reference capacitor Cf and the measured capacitor Cs, the seventh switch S7 to the tenth switch S10 are closed simultaneously. After a certain period of time, the third switch S3 and the fifth switch S5 are turned off. After the voltages on the first storage capacitor Cm1 and the second storage capacitor Cm2 stabilize, the seventh switch S7 to the tenth switch S10 are turned off.

[0134] In this way, the charge signals on the reference capacitor Cf and the measured capacitor Cs are converted into first and second voltage signals respectively by the first and second buffers Buffer1 and Buffer2, and stored in the first and second storage capacitors Cm1 and Cm2 respectively.

[0135] S4. Transfer the charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 to the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 respectively, and modulate the first voltage signal and the second voltage signal through the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2.

[0136] The eleventh switch S11 is closed to transfer the charge in the first storage capacitor Cm1 to the first modulation capacitor Cmod1, and the first voltage signal is modulated by the first modulation capacitor Cmod1; the fourteenth switch S14 is controlled by the control signal Q1. If the control signal Q1 is at a high level, the fourteenth switch 14 is closed to transfer the charge in the second storage capacitor Cm2 to the second modulation capacitor Cmod2, and the second voltage signal is modulated by the second modulation capacitor Cmod2. If the control signal Q1 is at a low level, the fourteenth switch 14 is turned off.

[0137] S5 . Compare the voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to obtain a control signal Q1 .

[0138] The voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 are compared by a comparator, and the compared signals are input into a D flip-flop, so as to finally obtain a control signal Q1.

[0139] S6. Charge the reference capacitor Cf and the capacitor to be measured Cs respectively.

[0140] This step is identical to step S1 and will not be described again here.

[0141] S7. Draw charges from the reference capacitor Cf and the capacitor to be measured Cs through the second current and the fourth current respectively.

[0142] Close the fourth switch S4 and the sixth switch S6 to extract charge from the reference capacitor Cf and the measured capacitor Cs through the second current source Idac2 and the fourth current source Idac4, respectively. The second current and the fourth current are two currents in the Source current array, and the fourth current is n times the second current.

[0143] S8 , converting the charge signal on the reference capacitor Cf and the charge signal on the measured capacitor Cs into a first voltage signal and a second voltage signal respectively, and storing them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively.

[0144] While extracting charge from the reference capacitor Cf and the measured capacitor Cs, the seventh switch S7 to the tenth switch S10 are closed simultaneously. After a certain period of time, the fourth switch S4 and the sixth switch S6 are turned off. After the voltages on the first storage capacitor Cm1 and the second storage capacitor Cm2 stabilize, the seventh switch S7 to the tenth switch S10 are turned off.

[0145] In this way, the charge signals on the reference capacitor Cf and the measured capacitor Cs are converted into first and second voltage signals respectively by the first and second buffers Buffer1 and Buffer2, and stored in the first and second storage capacitors Cm1 and Cm2 respectively.

[0146] S9. Transfer the charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 to the second modulation capacitor Cmod2 and the first modulation capacitor Cmod1 respectively, and modulate the first voltage signal and the second voltage signal respectively through the second modulation capacitor Cmod2 and the first modulation capacitor Cmod1.

[0147] The twelfth switch S12 is closed to transfer the charge in the first storage capacitor Cm1 to the second modulation capacitor Cmod2, and the first voltage signal is modulated by the second modulation capacitor Cmod1; the thirteenth switch S13 is controlled by the control signal Q2. If the control signal Q2 is at a high level, the thirteenth switch S13 is closed to transfer the charge in the second storage capacitor Cm2 to the first modulation capacitor Cmod1, and the second voltage signal is modulated by the first modulation capacitor Cmod1. If the control signal Q2 is at a low level, the thirteenth switch S13 is turned off.

[0148] S10 , comparing the voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to obtain a control signal Q2 .

[0149] The voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 are compared by a comparator, and the compared signals are input into a D flip-flop, so as to finally obtain a control signal Q2.

[0150] The above steps S1 to S10 constitute a quantization cycle. After multiple quantization cycles, the duty cycle of the control signal Q can be obtained. Then, the size of the capacitance to be measured Cs can be obtained based on the duty cycle of the control signal Q, the reference capacitance Cf, and the current ratio of the injected or extracted charge. Specifically, Cs = Dutycycle(Q)*Cf*(n+1);

[0151] Wherein, Dutycycle(Q) is the duty cycle of the control signal Q output by the comparator, the capacitance compensation factor n=Idac3 / Idac1=Idac4 / Idac2, and Idac1, Idac2, Idac3, and Idac4 are the magnitudes of the first current, the second current, the third current, and the fourth current, respectively.

[0152] It can be seen from the above technical solutions that the present invention has the following advantages:

[0153] The capacitance detection circuit and detection method of the present invention adopt a pseudo-differential structure, which has a strong suppression capability for common-mode interference, ensures chip performance, and improves detection accuracy;

[0154] In addition, the reference capacitor, storage capacitor and modulation capacitor are all on-chip capacitors, which avoids the problem of external interference on the off-chip capacitors and reduces the number of PADs required for the module.

[0155] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0156] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A pseudo-differential capacitance detection circuit, characterized in that: The circuit comprises: A first sampling unit, comprising a first charging unit and a first charge transfer unit respectively connected to the reference capacitor Cf, the first charging unit comprising a device for charging the reference capacitor Cf, and the first charge transfer unit for injecting and / or extracting charge from the reference capacitor Cf; A second sampling unit, comprising a second charging unit and a second charge transfer unit respectively connected to the capacitor to be measured Cs, the second charging unit comprising a device for charging the capacitor to be measured Cs, and the second charge transfer unit for injecting and / or extracting charge into the capacitor to be measured Cs; A first conversion unit, used for converting a charge signal on the reference capacitor Cf into a first voltage signal; A second conversion unit, used for converting the charge signal on the capacitor Cs to be measured into a second voltage signal; A storage unit, comprising a first storage capacitor Cm1 connected to the first conversion unit and a second storage capacitor Cm2 connected to the second conversion unit, for storing the first voltage signal and the second voltage signal respectively; A modulation unit, comprising a first modulation capacitor Cmod1 and a second modulation capacitor Cmod2; A control unit, connected between the storage unit and the modulation unit, comprising a plurality of switches; A comparator, wherein the first input terminal and the second input terminal are respectively connected to the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2, and the output terminal is connected to the control unit. The comparator obtains a control signal according to the modulated voltage of the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to control the control unit.

2. The pseudo differential capacitance detection circuit according to claim 1, characterized in that: The first charging unit comprises a first switch S1, a first end of the first switch S1 is connected to a reference voltage Vref, a second end of the first switch S1 is connected to a first end of a reference capacitor Cf, and a second end of the reference capacitor Cf is connected to a ground potential; The second charging unit includes a second switch S2, a first end of the second switch S2 is connected to a reference voltage Vref, a second end of the second switch S2 is connected to a first end of a capacitor to be measured Cs, and a second end of the capacitor to be measured Cs is connected to a ground potential.

3. The pseudo differential capacitance detection circuit according to claim 1, characterized in that: The first charge transfer unit includes a first charge injection unit and a first charge extraction unit; the first charge injection unit includes a first current source Idac1 and a third switch S3, the input end of the first current source Idac1 is connected to the power supply voltage, the output end is connected to the first end of the third switch S3, and the second end of the third switch S3 is connected to the first end of the reference capacitor Cf; the first charge extraction unit includes a second current source Idac2 and a fourth switch S4, the first end of the fourth switch S4 is connected to the first end of the reference capacitor Cf, the second end is connected to the input end of the second current source Idac2, and the output end of the second current source Idac2 is connected to the ground potential; The second charge transfer unit includes a second charge injection unit and a second charge extraction unit; the second charge injection unit includes a third current source Idac3 and a fifth switch S5, the input end of the third current source Idac3 is connected to the power supply voltage, the output end is connected to the first end of the fifth switch S5, and the second end of the fifth switch S5 is connected to the first end of the capacitor to be measured Cs; the second charge extraction unit includes a fourth current source Idac4 and a sixth switch S6, the first end of the sixth switch S6 is connected to the first end of the capacitor to be measured Cs, the second end is connected to the input end of the fourth current source Idac4, and the output end of the fourth current source Idac4 is connected to the ground potential.

4. The pseudo differential capacitance detection circuit according to claim 3, characterized in that: The third current provided by the third current source Idac3 is n times the first current provided by the first current source Idac1 , and the fourth current provided by the fourth current source Idac4 is n times the second current provided by the second current source Idac2 , where n is a capacitance compensation multiple.

5. The pseudo differential capacitance detection circuit according to claim 1, characterized in that: The first conversion unit includes a first buffer, a seventh switch S7 and an eighth switch S8, wherein a first end of the seventh switch S7 is connected to a first end of a reference capacitor Cf, and a second end of the seventh switch S7 is connected to a first input end of the first buffer, and a second input end and an output end of the first buffer are respectively connected to a first end of the eighth switch S8; The second conversion unit includes a second buffer, a ninth switch S9 and a tenth switch S10, wherein a first end of the ninth switch S9 is connected to a first end of the capacitor Cs to be measured, and a second end is connected to a first input end of the second buffer, and a second input end and an output end of the second buffer are respectively connected to a first end of the tenth switch S10; The first end of the first storage capacitor Cm1 is connected to the second end of the eighth switch S8, and the second end is connected to the ground potential; A first end of the second storage capacitor Cm2 is connected to a second end of the tenth switch S10, and a second end of the second storage capacitor Cm2 is connected to the ground potential.

6. The pseudo differential capacitance detection circuit according to claim 1, characterized in that: The control unit includes an eleventh switch S11, a twelfth switch S12, a thirteenth switch S14 and a fourteenth switch S14; The first end of the eleventh switch S11 is connected to the first end of the first storage capacitor Cm1, and the second end is connected to the first end of the first modulation capacitor Cmod1; The first end of the twelfth switch S12 is connected to the first end of the first storage capacitor Cm1, and the second end is connected to the first end of the second modulation capacitor Cmod2; The first end of the thirteenth switch S13 is connected to the first end of the second storage capacitor Cm2, and the second end is connected to the first end of the first modulation capacitor Cmod1; The first end of the fourteenth switch S14 is connected to the first end of the second storage capacitor Cm2, and the second end is connected to the first end of the second modulation capacitor Cmod2; The second end of the first modulation capacitor Cmod1 and the second end of the second modulation capacitor Cmod2 are both connected to the ground potential.

7. The pseudo differential capacitance detection circuit according to claim 6, characterized in that: The circuit also includes a D flip-flop connected to a comparator, wherein a first input terminal of the comparator is connected to a first terminal of a first modulation capacitor Cmod1, a second input terminal is connected to a first terminal of a second modulation capacitor Cmod2, an output terminal of the comparator is connected to an input terminal D of the D flip-flop, and an output terminal Q of the D flip-flop is used to output a control signal to control the thirteenth switch S13 and / or the fourteenth switch S14.

8. The pseudo differential capacitance detection circuit according to claim 1, characterized in that: The first storage capacitor Cm1, the second storage capacitor Cm2, the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 are all on-chip capacitors, and the reference capacitor Cf is an on-chip capacitor or an off-chip capacitor.

9. The pseudo differential capacitance detection circuit according to claim 8, characterized in that: The first storage capacitor Cm1, the second storage capacitor Cm2, the first modulation capacitor Cmod1, the second modulation capacitor Cmod2, the reference capacitor Cf and the measured capacitor Cs satisfy: Cmod1<Cs, Cmod2<Cs; Cmod1 / Cm1≥100; Cmod2 / Cm2≥100; Cmod1 / (Cm1+Cf)=0.1~10; Cmod2 / (Cm2+Cs)=0.05~10; Cmod1 / (Cm2+Cs)=0.05~10; Cmod2 / (Cm1+Cf)=0.1~10.

10. The pseudo differential capacitance detection circuit according to claim 8, characterized in that: The sizes of the first storage capacitor Cm1, the second storage capacitor Cm2, the first modulation capacitor Cmod1, the second modulation capacitor Cmod2, the reference capacitor Cf and the measured capacitor Cs are respectively: Cs=0~200pF; Cf=5~50pF; Cm1=Cm2=10~1000fF; Cmod1=Cmod2=1~100pF.

11. The pseudo differential capacitance detection circuit according to claim 1, characterized in that: The size of the measured capacitance Cs is: Cs=Dutycycle(Q)*Cf*(n+1), wherein Dutycycle(Q) is the duty cycle of the control signal output by the comparator, and the capacitance compensation multiple n=Idac3 / Idac1=Idac4 / Idac2.

12. A pseudo differential capacitance detection method, characterized in that: The method comprises: The reference capacitor Cf and the capacitor to be measured Cs are charged respectively; Inject or extract charges into the reference capacitor Cf and the capacitor to be measured Cs respectively; Converting the charge signal on the reference capacitor Cf and the charge signal on the capacitor to be measured Cs into a first voltage signal and a second voltage signal respectively, and storing them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively; Transfer the charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 to the first modulation capacitor Cmod1 or the second modulation capacitor Cmod2, and modulate the first voltage signal and the second voltage signal respectively through the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2; Compare the voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to obtain a control signal Q; The size of the capacitance to be measured Cs is obtained according to the duty cycle of the control signal Q, the reference capacitance Cf, and the current ratio of injecting or extracting charges.

13. The pseudo differential capacitance detection method according to claim 12, characterized in that: The method comprises several quantization cycles, each of which comprises the following steps: The reference capacitor Cf and the capacitor to be measured Cs are charged respectively; Injecting charges into the reference capacitor Cf and the capacitor to be measured Cs respectively through the first current and the third current; Converting the charge signal on the reference capacitor Cf and the charge signal on the capacitor to be measured Cs into a first voltage signal and a second voltage signal respectively, and storing them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively; The charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 are transferred to the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2, the first voltage signal and the second voltage signal are modulated by the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2; Compare the voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 to obtain a control signal Q1; The reference capacitor Cf and the capacitor to be measured Cs are charged respectively; Extracting charges from the reference capacitor Cf and the capacitor to be measured Cs respectively through the second current and the fourth current; Converting the charge signal on the reference capacitor Cf and the charge signal on the capacitor to be measured Cs into a first voltage signal and a second voltage signal respectively, and storing them in the first storage capacitor Cm1 and the second storage capacitor Cm2 respectively; Transferring the charges in the first storage capacitor Cm1 and the second storage capacitor Cm2 to the second modulation capacitor Cmod2 and the first modulation capacitor Cmod1 respectively, and modulating the first voltage signal and the second voltage signal respectively through the second modulation capacitor Cmod2 and the first modulation capacitor Cmod1; The voltage signals in the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 are compared to obtain the control signal Q2.

14. The pseudo differential capacitance detection method according to claim 13, characterized in that: The method further comprises: If the control signal Q1 is at a high level, the first voltage signal and the second voltage signal are modulated by the first modulation capacitor Cmod1 and the second modulation capacitor Cmod2 respectively; if the control signal Q1 is at a low level, the first voltage signal is modulated by the first modulation capacitor Cmod1; and, If the control signal Q2 is at a high level, the first voltage signal and the second voltage signal are modulated respectively by the second modulation capacitor Cmod2 and the first modulation capacitor Cmod1; if the control signal Q2 is at a low level, the first voltage signal is modulated by the second modulation capacitor Cmod2.

15. The pseudo differential capacitance detection method according to claim 13, characterized in that: The size of the measured capacitor Cs is: Cs=Dutycycle(Q)*Cf*(n+1), wherein Dutycycle(Q) is the duty cycle of the control signal Q output by the comparator, the capacitance compensation multiple n=Idac3 / Idac1=Idac4 / Idac2, and Idac1, Idac2, Idac3, and Idac4 are the sizes of the first current, the second current, the third current, and the fourth current, respectively.

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