Filter and manufacturing method therefor, and electronic device

Abstract

The present invention relates to the technical field of passive devices, and provides a filter and a manufacturing method therefor, and an electronic device. The filter comprises a dielectric substrate, and at least one capacitor and at least one inductor integrated on the dielectric substrate; the filter further comprises a first buffer layer provided on the dielectric substrate; the material of the first buffer layer is an organic material; the first buffer layer is provided with a first accommodating portion and a second accommodating portion; a first electrode plate of the capacitor is located in the first accommodating portion; at least part of the structure of the inductor is located in the second accommodating portion; the surface of the first electrode plate of the capacitor facing away from the dielectric substrate and the surface, facing away from the dielectric substrate, of the structure of the inductor located in the second accommodating portion are both flush with the surface of the first buffer layer facing away from the dielectric substrate.

Description

Filter and preparation method thereof, and electronic equipment Technical Field

[0001] The present disclosure belongs to the technical field of passive devices, and particularly relates to a filter, a preparation method thereof, and an electronic device. Background Art

[0002] With the development of communication technology, the frequency used in mobile communications is getting higher and higher, from hundreds of megahertz in 2G technology to 3.5GHz and millimeter waves in 5G technology. The current market demand for the miniaturization of electronic products is getting higher and higher. At present, passive components such as capacitors, inductors, and resistors account for about 70% of the area on the printed circuit board (PCB). Integrated passive devices (IPD) technology can reduce the area of ​​passive devices by more than 80%, and the market prospects are broad. Based on the different integrated substrates, integrated passive device technology can be divided into silicon-based, low-temperature co-fired ceramic (LTCC)-based, glass-based and other technical routes. As the main energy-consuming component in electronic products, the RF front-end requires a significant reduction in device electromagnetic loss. Due to the advantages of glass-based materials in dielectric loss and cost, glass-based integrated passive devices have gradually become the mainstream route.

[0003] Glass-based IPDs directly stack single- or double-sided metal redistribution layers (RDLs) on the glass surface. The thermal expansion coefficients of metal RDLs and glass differ by 3 to 7 times, and their thermal conductivity by 10 to over 300 times. Metal RDLs are excellent conductors of heat, and their thermal expansion coefficients are much greater than that of glass. When these two materials are directly interconnected, and single or multiple layers of different materials (metal, organic, and inorganic) are stacked on top, thermal stresses are generated during fabrication, flip-chip soldering, and reliability testing, and transferred to the interconnects between the metal RDLs and the glass. This increases the risk of delamination and detachment between the metal RDLs and the glass interconnects, leading to device reliability and performance degradation or even failure. The risk of delamination, which can degrade device reliability and performance, or even lead to device failure, is particularly high when multiple layers of metal RDLs are stacked with organic materials.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a filter and a preparation method thereof, and an electronic device.

[0006] In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a filter, comprising a dielectric substrate, at least one capacitor and at least one inductor integrated on the dielectric substrate; the filter further comprises a first buffer layer provided on the dielectric substrate; the material of the first buffer layer is an organic material;

[0007] The first buffer layer has a first accommodating portion and a second accommodating portion. The first electrode plate of the capacitor is filled in the first accommodating portion, and at least a portion of the structure of the inductor is filled in the second accommodating portion. The first electrode plate of the capacitor faces away from the surface of the dielectric substrate, and the structure of the inductor filled in the second accommodating portion faces away from the surface of the dielectric substrate, and both are flush with the surface of the first buffer layer facing away from the dielectric substrate.

[0008] In some embodiments, the dielectric substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction, and a first connecting via extending through its thickness direction; the first buffer layer is disposed on the first surface;

[0009] The inductor includes a first conductive structure provided on the first surface, a second conductive structure provided on the second surface, and a first connecting electrode provided in the first connecting via; the second conductive structure is electrically connected to the first conductive structure through the first connecting electrode, thereby forming a coil structure of the inductor;

[0010] The second accommodation portion penetrates the entire thickness of the first buffer layer, and the second conductive structure is filled in the second accommodation portion.

[0011] In some embodiments, the filter further includes a second buffer layer disposed on the second surface; the material of the second buffer layer is an organic material;

[0012] The second buffer layer has a third accommodating portion, the third accommodating portion extends through the entire thickness of the second buffer layer, the first conductive structure is filled in the third accommodating portion, and a surface of the first conductive structure facing away from the dielectric substrate is flush with a surface of the second buffer layer facing away from the dielectric substrate.

[0013] In some embodiments, the first receiving portion penetrates a portion of the thickness of the first buffer layer.

[0014] In some embodiments, the dielectric substrate has a first slot partially penetrating along a thickness direction thereof, and the first slot defines the first receiving portion.

[0015] In some embodiments, the first accommodating portion and the second accommodating portion both penetrate a portion of the thickness of the first buffer layer; and the coil structure of the inductor is filled in the second accommodating portion.

[0016] In some embodiments, the dielectric substrate has a first slot and a second slot partially penetrating along the thickness direction of the dielectric substrate;

[0017] The first buffer layer covers the dielectric substrate, the first groove defines the first accommodating portion, and the second groove defines the second accommodating portion.

[0018] In some embodiments, the first buffer layer serves as the dielectric substrate.

[0019] In some embodiments, the organic material includes any one of polyimide, resin, and photoresist.

[0020] In a second aspect, an embodiment of the present disclosure further provides a method for manufacturing a filter, comprising: providing a dielectric substrate, forming at least one capacitor and at least one inductor on the dielectric substrate, and further comprising forming a first buffer layer on the dielectric substrate; the step of forming the first buffer layer comprising:

[0021] cleaning and drying the dielectric substrate;

[0022] forming a first film layer on the dielectric substrate; the first film layer covers the dielectric substrate;

[0023] The first film layer is patterned to form the first buffer layer; the first buffer layer has a first accommodating portion and a second accommodating portion, the first accommodating portion is configured to accommodate a first plate of a capacitor, and the second accommodating portion is configured to accommodate at least a partial structure of an inductor.

[0024] In some embodiments, the first receiving portion and the second receiving portion both penetrate a portion of the thickness of the first buffer layer, and the second receiving portion is configured to receive a coil structure of an inductor.

[0025] In some embodiments, the dielectric substrate has a first slot and a second slot partially penetrating along the thickness direction of the dielectric substrate;

[0026] The first buffer layer covers the dielectric substrate, the first groove defines the first accommodating portion, and the second groove defines the second accommodating portion.

[0027] In some embodiments, the first film layer includes a first sub-film layer and a second sub-film layer formed sequentially in a direction away from the dielectric substrate.

[0028] In some embodiments, the step of forming at least one capacitor and at least one inductor on the dielectric substrate includes:

[0029] forming a first conductive film layer on a side of the first buffer layer facing away from the dielectric substrate; the first conductive film layer covers the first buffer layer;

[0030] The first conductive film layer is polished by CMP to form a first electrode plate of the capacitor and a coil structure of the inductor; surfaces of the first electrode plate and the coil structure facing away from the dielectric substrate are both flush with a surface of the first buffer layer facing away from the dielectric substrate.

[0031] In some embodiments, the dielectric substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction, and a first connecting via extending through its thickness direction; the first buffer layer is disposed on the first surface;

[0032] The filter further includes a second buffer layer disposed on the second surface; the material of the second buffer layer is an organic material;

[0033] The second buffer layer has a third accommodating portion, the third accommodating portion extending through the entire thickness of the second buffer layer. The third accommodating portion is configured to accommodate a first conductive structure of an inductor, and a surface of the first conductive structure facing away from the dielectric substrate is flush with a surface of the second buffer layer facing away from the dielectric substrate.

[0034] The second receiving portion penetrates the entire thickness of the first buffer layer, and the second receiving portion is configured to receive a second conductive structure of the inductor.

[0035] In some embodiments, the first receiving portion penetrates a portion of the thickness of the first buffer layer.

[0036] In some embodiments, the dielectric substrate has a first slot partially penetrating along a thickness direction thereof, and the first slot defines the first receiving portion.

[0037] In some embodiments, the step of forming at least one capacitor and at least one inductor on the dielectric substrate includes:

[0038] forming a first connection electrode of the inductor in the first connection via hole;

[0039] forming a second conductive film layer on a side of the second buffer layer facing away from the dielectric substrate;

[0040] The second conductive film layer is polished flat by CMP to form a first conductive structure of the inductor; a surface of the first conductive structure facing away from the dielectric substrate is flush with a surface of the second buffer layer facing away from the dielectric substrate;

[0041] forming a third conductive film layer on a side of the first buffer layer facing away from the dielectric substrate;

[0042] The third conductive film layer is polished flat by CMP to form a first electrode plate of the capacitor and a second conductive structure of the inductor; surfaces of the first electrode plate and the second conductive structure facing away from the dielectric substrate are both flush with a surface of the first buffer layer facing away from the dielectric substrate.

[0043] In a third aspect, an embodiment of the present disclosure further provides an electronic device comprising the filter according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1 is a schematic diagram of the structure of an exemplary glass-based 3D IPD filter;

[0045] FIG2 is a schematic structural diagram of a filter provided in an embodiment of the present disclosure;

[0046] FIG3 is a schematic diagram of the structure of another filter provided in an embodiment of the present disclosure;

[0047] FIG4 is a schematic diagram of the structure of another filter provided in an embodiment of the present disclosure;

[0048] FIG5 is a schematic diagram of the structure of another filter provided in an embodiment of the present disclosure;

[0049] FIG6 is a schematic diagram of the structure of another filter provided in an embodiment of the present disclosure;

[0050] 7a to 7c are flow charts of a preparation process for forming a first buffer layer according to an embodiment of the present disclosure;

[0051] 8a to 8c are flow charts of another preparation process for forming a first buffer layer according to an embodiment of the present disclosure;

[0052] 9a to 9e are flow charts of another preparation process for forming a first buffer layer according to an embodiment of the present disclosure;

[0053] 10a to 10d are flow charts of another preparation process for forming a first buffer layer according to an embodiment of the present disclosure;

[0054] FIG11 is a cross-sectional view of a first buffer layer in an embodiment of the present disclosure;

[0055] 12a to 12d are flow charts of a filter manufacturing process according to an embodiment of the present disclosure;

[0056] 13a to 13d are flow charts of another filter manufacturing process provided by an embodiment of the present disclosure;

[0057] 14a to 14e are flow charts of another filter manufacturing process provided by an embodiment of the present disclosure;

[0058] 15a to 15f are flow charts of another filter manufacturing process provided by an embodiment of the present disclosure;

[0059] 16a to 16g are flow charts of a process for preparing another filter provided in an embodiment of the present disclosure.

[0060] The figures are marked as follows: 1. dielectric substrate; S1. first surface; S2. second surface; 21. first conductive structure; 22. second conductive structure; 23. first connecting electrode; 24. coil structure; 31. first electrode plate; 32. dielectric layer; 4. interlayer insulating layer; 5. protective layer; 6. first buffer layer; 61. first accommodating portion; 62. second accommodating portion; 7. second buffer layer; 71. third accommodating portion; 81. first slot; 82. second slot; 9. temporary carrier layer; 01. cutting path; 02. etching mask layer; 03. first film layer; 031. first sub-film layer; 032. second sub-film layer; 04. interface; 05. first conductive film layer; 06. second conductive film layer; 07. third conductive film layer. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0063] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0064] In the prior art, LC-type two-dimensional (2D) or three-dimensional (3D) IPD filters usually involve the stacking and overlapping of multiple layers of metal. The overlapping conditions of each layer of metal directly determine the performance and reliability of the device. Therefore, the more metal layers there are, the more difficult the process is and the greater the risk of failure. Glass-based IPD is to directly stack single-sided or double-sided metal RDL lines on a glass base, and then make other stacked layers. The metal RDL lines referred to in the embodiments of the present disclosure refer to metal layers formed on one or both sides of a glass base. Figure 1 is a schematic structural diagram of an exemplary glass-based 3D IPD filter. As shown in Figure 1, the filter includes a dielectric substrate 1, and at least one inductor and at least one capacitor integrated on the dielectric substrate 1. In the disclosed embodiment, the dielectric substrate 1 is a glass substrate and includes a first surface S1 and a second surface S2 disposed opposite each other along its thickness, and a first connection via extending through its thickness. The inductor includes a first conductive structure 21 disposed on the first surface S1, a second conductive structure 22 disposed on the second surface S2, and a first connection electrode 23 disposed within the first connection via. The second conductive structure 22 is electrically connected to the first conductive structure 21 via the first connection electrode 23 to form a coil structure 24 of the inductor. The capacitor includes a first electrode 31 disposed on the same layer as the second conductive structure 22, and a dielectric layer 32 disposed on a side of the first electrode 31 facing away from the dielectric substrate 1.

[0065] It should be noted that "same-layer arrangement" in the disclosed embodiments means that multiple structures are formed from the same material layer through a patterning process, so these structures are located in the same layer in terms of stacking relationship; however, this does not mean that the distances between these structures and the substrate are necessarily the same. In the disclosed embodiments, the "patterning process" refers to the steps of forming a structure with a specific pattern, which can be a photolithography process, which includes one or more steps such as forming a material layer, applying photoresist, exposing, developing, etching, and photoresist stripping. Of course, the "patterning process" can also be other processes such as imprinting and inkjet printing.

[0066] Specifically, as shown in FIG1 , the filter further includes an interlayer insulating layer 4 disposed on the side of the second conductive structure 22 and the dielectric layer 32 facing away from the dielectric substrate 1, and a protective layer 5 disposed on the side of the first conductive structure 21 facing away from the dielectric substrate 1, and the interlayer insulating layer 4 has an opening exposing the second conductive structure 22 and the dielectric layer 32. The material of the interlayer insulating layer 4 can be an inorganic insulating material. For example, an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon dioxide (SiO2), or a laminated composite film layer of several SiNx inorganic insulating layers and SiO2 inorganic insulating layers. The metal RDL circuit in the filter is the first conductive structure 21, the second conductive structure 22 and the first electrode 31.

[0067] The inventors discovered that the filter shown in FIG1 has the following problems:

[0068] 1) Poor reliability.

[0069] Due to the mismatch in thermal expansion coefficient and thermal conductivity between glass and metal materials, the combined effects of thermal shock and stress can easily lead to repeated expansion and contraction between the interconnect layer glass and the metal RDL lines, causing material fatigue and resulting in delamination, shedding, high impedance, etc., which in turn leads to performance degradation or failure of the IPD.

[0070] Specifically, as shown in FIG1 , the first conductive structure 21 and second conductive structure 22 of the inductor and the first plate 31 of the capacitor are directly connected to the glass substrate. The side of the second conductive structure 22 of the inductor and the first plate 31 of the capacitor facing away from the glass substrate will subsequently be stacked with single or multiple layers of different materials (metal, organic, and inorganic). Solder balls or copper pillar bumps are fabricated on the pads of the outermost metal RDL circuit. These layers undergo reflow soldering during subsequent flip-chip soldering on the PCB substrate and reliability testing. Due to the significant difference in thermal expansion coefficients and thermal conductivity between the metal RDL circuit and glass, the metal RDL circuit is a good conductor of heat and has a much larger thermal expansion coefficient than glass. When these two materials are directly interconnected, heat is transferred to the interconnect surface with the glass via the metal RDL circuit in a very short period of time, causing thermal shock to the interconnect layer. This can easily lead to repeated expansion and contraction between the interconnect layer glass and the metal RDL, causing material fatigue and potentially delamination or shedding of the interconnect layer, leading to performance degradation or failure of the IPD. Especially when multi-layer metal RDL lines and organic materials are stacked, the multi-layer structure will generate greater stress and transfer it to the metal layer and glass interconnect interface, making delamination more likely to occur, resulting in a higher risk of device reliability and performance degradation or failure.

[0071] 2) Device performance is unstable and has poor consistency.

[0072] The surface flatness and roughness of the layer where the second conductive structure 22 of the inductor and the first electrode 31 of the capacitor are located are difficult to control, which will lead to poor capacitance consistency, decreased and unstable device performance, and increased process manufacturing costs and control difficulties.

[0073] It should be noted that, in the embodiment of the present disclosure, only the first electrode 31 and the dielectric layer 32 of the capacitor are illustrated. In fact, the capacitor also includes a second electrode arranged on the side of the dielectric layer 32 away from the dielectric substrate 1. The capacitor is a flat capacitor structure, that is, a capacitor with an MIM (metal-insulator-metal) structure is formed by two parallel metal electrodes and an insulating dielectric layer 32 in the middle. The size of the capacitor is mainly determined by factors such as the overlapping area of ​​the metal electrodes, the flatness of the metal and the properties of the dielectric material. Although the capacitor structure is relatively simple, only by finely manufacturing each layer of material can the uniformity and accuracy of the integrated capacitor be effectively guaranteed. Specifically, the MIM structure capacitor is usually composed of three layers: an upper metal layer, a middle insulating layer and a lower metal layer. The upper metal layer and the lower metal layer are respectively connected to the external electrodes, and the current is conducted through the upper metal layer and the lower metal layer; the middle insulating layer separates the upper metal layer and the lower metal layer, that is, separates their potentials, thereby generating a capacitor circuit. As shown in Figure 1, the first plate 31 of the capacitor is the lower metal layer, and the second plate not shown is the upper metal layer. The capacitor also includes a dielectric layer 32 (middle insulating layer) located between the first plate 31 and the second plate, and the capacitor is connected to the outside through a connection structure.

[0074] The first pole plate 31 is used as the lower metal layer of the capacitor. When forming the first pole plate 31, it is necessary to prepare a thick copper layer. When thickened by electroplating copper, the copper surface flatness is poor and the roughness is large, which will lead to the poor flatness of the dielectric layer 32, making the capacitance uniformity deteriorate, and the device performance is reduced and unstable. To improve the capacitance uniformity, it is necessary to improve the flatness and roughness of the copper surface on the first pole plate 31. At present, chemical mechanical polishing (CMP) technology can be introduced to solve this problem. However, when using CMP, the electroplated thick copper layer on the first pole plate 31 does not have an effective CMP cut-off layer, which will cause CMP to be unable to control the grinding amount of copper, and then it is difficult to control the copper thickness after CMP, and making the corresponding cut-off layer separately will increase the complexity and production cost of the process. Therefore, it is difficult to improve the capacitance uniformity in the IPD filter as shown in Figure 1 by CMP.

[0075] In summary, the IPD filter shown in FIG1 has poor reliability, unstable device performance, and poor uniformity, while increasing the cost of process manufacturing and the difficulty of control.

[0076] In view of this, embodiments of the present disclosure provide a filter that substantially eliminates one or more of the problems caused by limitations and defects of the related art.

[0077] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a filter. FIG2 is a schematic structural diagram of a filter provided in an embodiment of the present disclosure. As shown in FIG2 , the filter in the embodiment of the present disclosure includes a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the filter also includes a first buffer layer 6 provided on the dielectric substrate 1; the material of the first buffer layer 6 is an organic material; the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62; the first electrode 31 of the capacitor is filled in the first accommodating portion 61, and at least part of the structure of the inductor is filled in the second accommodating portion 62, and the first electrode 31 of the capacitor faces away from the surface of the dielectric substrate 1, and the structure of the inductor filled in the second accommodating portion 62 faces away from the surface of the dielectric substrate 1, and both are flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0078] It should be noted that the current three-dimensional integration of digital circuits (such as dynamic random access memory (DRAM) and logic chips) generally uses silicon substrates and through-silicon via (TSV) technology. In recent years, as people's demand for communication capacity and speed continues to increase, communication frequencies have continued to rise. Due to high-frequency applications, the materials used for adapter plates or substrates must have low dielectric loss and low dielectric constant to reduce the substrate's RF power dissipation and increase the self-resonant frequency. Because silicon is a semiconductor material, carriers around TSVs can move freely under the influence of electric or magnetic fields, affecting adjacent circuits or signals and reducing the chip's high-frequency performance. Glass, on the other hand, has no freely moving charges, a tunable thermal expansion coefficient, and excellent dielectric properties. Replacing silicon substrates with glass substrates and replacing TSVs with through-glass via (TGV) technology can effectively avoid the high-frequency loss problem of TSVs. Furthermore, due to the semiconductor properties of silicon, TSV also requires the fabrication of electrical isolation layers, diffusion barriers, seed layers, and void-free copper fill within the vias. This not only complicates the process but also creates significant parasitic capacitance, often failing to meet the performance requirements of 3D integrated RF microsystems. TGV technology eliminates the need for copper-filled barrier layers and oxide capping films, reducing the capacitance between the copper plating and the substrate, and lowering electromagnetic interference between the active and passive circuits within the vias. It also significantly reduces process complexity and processing costs. Glass thinning and polishing processes are also relatively simple compared to silicon. Therefore, glass is a suitable material for the RF field, and TGV is an ideal solution for 3D integration.

[0079] Therefore, when describing the IPD filter in the embodiments of this disclosure, the dielectric substrate 1 is described in detail using a glass substrate as an example, and no further details are given below. The 2D and 3D structures in this disclosure refer to inductor structures, while the capacitors in the filter are 2D structures. The figures in the embodiments of this disclosure are for illustrative purposes only and are intended to facilitate understanding of the present invention. Their specific specifications and parameters need to be designed and adjusted based on specific product requirements.

[0080] Continuing with Figure 2, the filter in the disclosed embodiment, compared to filters in the prior art, adds a first buffer layer 6, and the material of the first buffer layer 6 is an organic material. The first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62. The first plate 31 of the capacitor is filled in the first accommodating portion 61, and at least part of the structure of the inductor is filled in the second accommodating portion 62. The surface of the first plate 31 of the capacitor facing away from the dielectric substrate 1, and the surface of the inductor filled in the second accommodating portion 62 facing away from the dielectric substrate 1, are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1. The metal RDL circuit in the disclosed embodiment is the first plate 31 of the capacitor filled in the first accommodating portion 61, and at least part of the structure of the inductor filled in the second accommodating portion 62. This arrangement allows the first buffer layer 6 to buffer heat and stress, effectively solving the risk of delamination at the interface between the metal RDL circuit and the glass substrate interconnect layer due to thermal and stress shocks, thereby avoiding degradation or failure of device reliability and performance. Furthermore, the first buffer layer 6 in the disclosed embodiment can also serve as a stop layer for CMP planarization of the metal RDL circuit, thereby simplifying the process scheme for CMP planarization of the metal RDL circuit, reducing process difficulty and cost, and improving quality and efficiency.

[0081] In some embodiments, as shown in FIG2 , the dielectric substrate 1 includes a first surface S1 and a second surface S2 oppositely disposed along its thickness direction, and a first connection via extending through its thickness direction; a first buffer layer 6 is disposed on the first surface S1; the inductor includes a first conductive structure 21 disposed on the first surface S1, a second conductive structure 22 disposed on the second surface S2, and a first connection electrode 23 disposed within the first connection via; the second conductive structure 22 is electrically connected to the first conductive structure 21 via the first connection electrode 23 to form the inductor; a second accommodating portion 62 extends through the entire thickness of the first buffer layer 6, and the second conductive structure 22 is filled within the second accommodating portion 62.

[0082] Specifically, as shown in Figure 2, the filter in the disclosed embodiment is a glass-based 3D IPD filter. The first plate 31 of the capacitor is filled in the first accommodating portion 61, and the second conductive structure 22 of the inductor is filled in the second accommodating portion 62. The second accommodating portion 62 extends through the entire thickness of the first buffer layer 6. Furthermore, the surface of the first plate 31 of the capacitor facing away from the dielectric substrate 1 and the surface of the second conductive structure 22 of the inductor facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1. The metal RDL circuit in the disclosed embodiment is the first plate 31 of the capacitor filled in the first accommodating portion 61 and the second conductive structure 22 of the inductor filled in the second accommodating portion 62. This arrangement allows the first buffer layer 6 to buffer heat and stress, effectively solving the risk of delamination at the interface between the metal RDL circuit and the glass substrate interconnect layer due to thermal and stress shocks, thereby avoiding degradation or failure of device reliability and performance. Furthermore, the first buffer layer 6 in the disclosed embodiment can also serve as a stop layer for CMP planarization of the metal RDL circuit, thereby simplifying the process scheme for CMP planarization of the metal RDL circuit, reducing process difficulty and cost, and improving quality and efficiency.

[0083] In some embodiments, as shown in FIG2 , the filter in the embodiment of the present disclosure includes not only a first buffer layer 6 but also a second buffer layer 7 disposed on the second surface S2; the material of the second buffer layer 7 is an organic material; the second buffer layer 7 has a third accommodating portion 71; the third accommodating portion 71 extends through the entire thickness of the second buffer layer 7, the first conductive structure 21 is filled in the third accommodating portion 71, and the surface of the first conductive structure 21 facing away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 facing away from the dielectric substrate 1.

[0084] Specifically, as shown in FIG2 , in the disclosed embodiment, the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62, and the second buffer layer 7 has a third accommodating portion 71. The first plate 31 of the capacitor is filled in the first accommodating portion 61, the second conductive structure 22 of the inductor is filled in the second accommodating portion 62, and the first conductive structure 21 of the inductor is filled in the third accommodating portion 71. The surface of the first plate 31 of the capacitor facing away from the dielectric substrate 1 and the surface of the second conductive structure 22 of the inductor facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1, and the surface of the first conductive structure 21 facing away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 facing away from the dielectric substrate 1. The metal RDL circuit in the disclosed embodiment comprises the first plate 31 of the capacitor filled in the first accommodating portion 61, the second conductive structure 22 of the inductor filled in the second accommodating portion 62, and the first conductive structure 21 filled in the third accommodating portion 71. Such a configuration allows the first buffer layer 6 and the second buffer layer 7 to buffer heat and stress, effectively solving the risk of delamination at the interface between the metal RDL circuit and the glass substrate interconnection layer due to thermal and stress shocks, thereby avoiding degradation or failure of device reliability and performance. At the same time, the first buffer layer 6 and the second buffer layer 7 in the disclosed embodiment can also serve as a stop layer for CMP planarization of the metal RDL circuit, thereby simplifying the process scheme for CMP planarization of the metal RDL circuit, reducing process difficulty and cost, and improving quality and efficiency.

[0085] In some embodiments, as shown in FIG2 , the first receiving portion 61 partially penetrates the thickness of the first buffer layer 6. The dielectric substrate 1 of the filter in the disclosed embodiment is a planar glass substrate, and the first receiving portion 61 partially penetrates the thickness of the first buffer layer 6 to accommodate the first plate 31 of the capacitor.

[0086] In some embodiments, Figure 3 is a structural schematic diagram of another filter provided in an embodiment of the present disclosure. As shown in Figure 3, the filter in the embodiment of the present disclosure is a glass-based 3D IPD filter, including a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the dielectric substrate 1 includes a first surface S1 and a second surface S2 arranged opposite to each other along its thickness direction, and a first connection via extending through its thickness direction; the inductor includes a first conductive structure 21 arranged on the first surface S1, a second conductive structure 22 arranged on the second surface S2, and a first connection electrode 23 arranged in the first connection via; the second conductive structure 22 is electrically connected to the first conductive structure 21 through the first connection electrode 23 to form a coil structure of the inductor. The filter further includes a first buffer layer 6 disposed on the first surface S1 of the dielectric substrate 1, and a second buffer layer 7 disposed on the second surface S2 of the dielectric substrate 1. Both the first buffer layer 6 and the second buffer layer 7 are made of organic materials. The first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62, and the second buffer layer 7 has a third accommodating portion 71. The second accommodating portion 62 extends through the entire thickness of the first buffer layer 6, and the third accommodating portion 71 extends through the entire thickness of the second buffer layer 7. The first plate 31 of the capacitor is filled within the first accommodating portion 61, the second conductive structure 22 of the inductor is filled within the second accommodating portion 62, and the first conductive structure 21 of the inductor is filled within the third accommodating portion 71. The surfaces of the first plate 31 of the capacitor facing away from the dielectric substrate 1 and the second conductive structure 22 of the inductor facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1, and the surface of the first conductive structure 21 of the inductor facing away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 facing away from the dielectric substrate 1. The dielectric substrate 1 has a first slot 81 extending partially through the dielectric substrate 1, and the first slot 81 defines the first accommodating portion 61.

[0087] The dielectric substrate 1 of the filter in the disclosed embodiment is a grooved glass substrate. The glass substrate is grooved to form a first groove 81 that partially penetrates along its thickness. When the first buffer layer 6 is formed on the glass substrate, the first groove 81 defines a first receiving portion 61. This arrangement eliminates the need to process the first buffer layer 6 to form the first receiving portion 61.

[0088] In some embodiments, Figure 4 is a structural schematic diagram of another filter provided in an embodiment of the present disclosure. As shown in Figure 4, the filter in the embodiment of the present disclosure is a glass-based 2D IPD filter, including a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the filter also includes a first buffer layer 6 arranged on the dielectric substrate 1, and the material of the first buffer layer 6 is an organic material; the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62, and the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6; the first electrode 31 of the capacitor is filled in the first accommodating portion 61, and the coil structure 24 of the inductor is filled in the second accommodating portion 62, and the surface of the first electrode 31 of the capacitor facing away from the dielectric substrate 1 and the surface of the coil structure 24 of the inductor facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0089] Specifically, as shown in Figure 4, the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6. The dielectric substrate 1 of the filter in the disclosed embodiment is a planar glass substrate, and the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6 to accommodate the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor.

[0090] In some embodiments, FIG5 is a schematic structural diagram of another filter provided in an embodiment of the present disclosure. As shown in FIG5 , the filter in the embodiment of the present disclosure is a glass-based 2D IPD filter, comprising a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the filter further comprises a first buffer layer 6 disposed on the dielectric substrate 1, the material of the first buffer layer 6 being an organic material; the first buffer layer 6 having a first accommodating portion 61 and a second accommodating portion 62; the dielectric substrate 1 having a first slot 81 and a second slot 82 partially penetrating along the thickness direction thereof; the first buffer layer 6 covers the dielectric substrate 1, and the first slot 81 defines the first accommodating portion 61, and the second slot 82 defines the second accommodating portion 62; the first plate 31 of the capacitor is filled in the first accommodating portion 61, and the coil structure 24 of the inductor is filled in the second accommodating portion 62, and the surface of the first plate 31 of the capacitor facing away from the dielectric substrate 1 and the surface of the coil structure 24 of the inductor facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0091] Specifically, as shown in FIG5 , the dielectric substrate 1 of the filter in the embodiment of the present disclosure is a grooved glass substrate. The glass substrate is grooved to form a first groove 81 and a second groove 82 that partially penetrate along its thickness. When the first buffer layer 6 is formed on the glass substrate, the first groove 81 defines a first accommodating portion 61, and the second groove 82 defines a second accommodating portion 62. This arrangement eliminates the need to process the first buffer layer 6 to form the first accommodating portion 61 and the second accommodating portion 62.

[0092] In some embodiments, Figure 6 is a structural schematic diagram of another filter provided in an embodiment of the present disclosure. As shown in Figure 6, the filter in the embodiment of the present disclosure is a flexible 2D IPD filter, including a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the filter also includes a first buffer layer 6 arranged on the dielectric substrate 1, and the material of the first buffer layer 6 is an organic material; the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62, and the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6; the first electrode 31 of the capacitor is filled in the first accommodating portion 61, and the coil structure 24 of the inductor is filled in the second accommodating portion 62, and the surface of the first electrode 31 of the capacitor facing away from the dielectric substrate 1 and the surface of the coil structure 24 of the inductor facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1; the first buffer layer 6 serves as the dielectric substrate 1.

[0093] Specifically, as shown in FIG6 , the first buffer layer 6 of the filter in the embodiment of the present disclosure is used as the dielectric substrate 1 to obtain a flexible 2D IPD filter.

[0094] In some embodiments, the organic material includes any one of polyimide, resin and photoresist. In the embodiment of the present disclosure, the organic material includes but is not limited to polyimide, resin and photoresist, as long as the first buffer layer 6 and the second buffer layer 7 formed in Figures 2 and 3, and the first buffer layer 6 in Figures 4, 5 and 6 can play a role in buffering heat and stress. For example, the organic material can be polyimide, and the first buffer layer 6 and the second buffer layer 7 formed in this way can not only play a role in buffering heat and stress, but also can alleviate the problems of delamination, shedding, high RDL impedance and so on caused by fatigue at the interface between the metal RDL circuit and the interconnection layer of the glass substrate, thereby improving the reliability of the IPD; in addition, the first buffer layer 6 and the second buffer layer 7 formed in this way can also serve as a cutoff layer for CMP planarization of the metal RDL circuit, which is beneficial to improving the capacitance uniformity and stability, thereby simplifying the process scheme of CMP planarization of the metal RDL circuit, reducing the process difficulty and large-scale production cost, and improving the device performance and quality.

[0095] In a second aspect, an embodiment of the present disclosure further provides a method for preparing a filter, comprising: providing a dielectric substrate 1, forming at least one capacitor and at least one inductor on the dielectric substrate 1, and also forming a first buffer layer 6 on the dielectric substrate 1.

[0096] For ease of description and understanding, the following specifically describes only the step of forming the first buffer layer 6 when preparing a glass-based 2D IPD filter.

[0097] FIG7a to FIG7c are flow charts of a preparation process for forming a first buffer layer 6 according to an embodiment of the present disclosure. As shown in FIG7a to FIG7c, the first buffer layer 6 prepared in this manner can be applied to the glass-based 2D IPD filter shown in FIG4. When forming the first buffer layer 6, the preparation method may include steps S11 to S13, as follows:

[0098] S11 , cleaning and drying the dielectric substrate 1 .

[0099] Specifically, as shown in Fig. 7a, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0100] Specifically, when cleaning the dielectric substrate 1 , it can be cleaned in sequence using deionized water (DI), a detergent, isopropyl alcohol, etc. Each cleaning time is no less than 10 minutes.

[0101] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0102] S12 , forming a first film layer 03 on the dielectric substrate 1 .

[0103] Specifically, as shown in FIG7 b , when the first film layer 03 is formed on the dielectric substrate 1 , the first film layer 03 covers the dielectric substrate 1 .

[0104] Specifically, an organic material can be coated on the dielectric substrate 1 to form the first film layer 03. Organic materials include, but are not limited to, polyimide, resin, and photoresist, as long as they can buffer heat and stress. For example, a spin coating process can be used to apply the organic material to a target thickness of 2 to 20 μm on the cleaned dielectric substrate 1.

[0105] S13 , patterning the first film layer 03 to form a first buffer layer 6 .

[0106] Specifically, as shown in FIG4 and FIG7 c , the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62 . The first accommodating portion 61 is configured to accommodate the first electrode 31 of the capacitor, and the second accommodating portion 62 is configured to accommodate the coil structure 24 of the inductor.

[0107] Specifically, the first film layer 03 is patterned to form a first buffer layer 6 corresponding to the metal RDL circuit (i.e., the first plate 31 of the capacitor and the coil structure 24 of the inductor). Both the first and second accommodating portions 61 and 62 extend through a portion of the thickness of the first buffer layer 6. The first and second accommodating portions 61 and 62 extend perpendicularly to the dielectric substrate 1, with a thickness ranging from 1 to 15 μm. This leaves 1 to 15 μm of organic material. Finally, the layer is cured and formed to produce the desired first buffer layer 6 with the first and second accommodating portions 61 and 62.

[0108] 7c, the patterning of the first film layer 03 can be performed using Halftone lithography to remove the organic material within the scribe line 01 and expose the dielectric substrate 1. Removing the organic material within the scribe line 01 is to separate adjacent devices and increase the warpage stress of the product.

[0109] It should be noted that whether to remove the organic material in the cutting street 01 depends on the product's ability to resist the stress of the entire first buffer layer 6. For example, if the product has a strong ability to resist the stress of the entire first buffer layer 6, then there is no need to remove the organic material in the cutting street 01.

[0110] Figures 8a to 8c are flow charts of another process for forming a first buffer layer 6 according to an embodiment of the present disclosure. As shown in Figures 8a to 8c, the first buffer layer 6 prepared in this manner can be applied to the glass-based 2D IPD filter shown in Figure 5. When forming the first buffer layer 6, the preparation method may include steps S21 to S23, as follows:

[0111] S21 , cleaning and drying the dielectric substrate 1 .

[0112] Specifically, as shown in Figure 8a, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a grooved glass substrate. The dielectric substrate 1 has a first groove 81 and a second groove 82 extending partially through the substrate along its thickness. The shape of the first groove 81 corresponds to the first plate 31 of the capacitor, and the shape of the second groove 82 corresponds to the coil structure 24 of the inductor. The thickness of the glass substrate ranges from 0.1 to 0.4 mm, and the depth of the first groove 81 and the second groove 82 ranges from 3 to 30 μm.

[0113] Specifically, when cleaning the dielectric substrate 1 , it can be cleaned in sequence using DI, detergent, isopropyl alcohol, etc. Each cleaning time is no less than 10 minutes.

[0114] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0115] S22 , forming a first film layer 03 on the dielectric substrate 1 .

[0116] Specifically, as shown in FIG8 b , when the first film layer 03 is formed on the dielectric substrate 1 , the first film layer 03 covers the dielectric substrate 1 .

[0117] Specifically, an organic material can be coated on the dielectric substrate 1 to form the first film layer 03. Organic materials include, but are not limited to, polyimide, resin, and photoresist, as long as they can buffer heat and stress. For example, the organic material can be spray-coated to a target thickness of 1 to 25 μm on the cleaned dielectric substrate 1.

[0118] S23 , patterning the first film layer 03 to form a first buffer layer 6 .

[0119] Specifically, as shown in Figures 5 and 8c, the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62. The first accommodating portion 61 is configured to accommodate the first plate 31 of the capacitor, and the second accommodating portion 62 is configured to accommodate the coil structure 24 of the inductor. The first buffer layer 6 covers the dielectric substrate 1, and the first slot 81 defines the first accommodating portion 61, and the second slot 82 defines the second accommodating portion 62.

[0120] Specifically, the first film layer 03 is patterned to form a first buffer layer 6 corresponding to the metal RDL circuit (i.e., the first plate 31 of the capacitor and the coil structure 24 of the inductor). The first and second accommodating portions 61, 62 are perpendicular to the dielectric substrate 1, with a thickness ranging from 1 to 20 μm from the dielectric substrate 1, leaving 1 to 20 μm of organic material. Finally, the first buffer layer 6 is cured and formed, producing the desired first and second accommodating portions 61, 62.

[0121] 8c, the patterning of the first film layer 03 can be performed using Halftone lithography to remove the organic material within the scribe line 01 and expose the dielectric substrate 1. Removing the organic material within the scribe line 01 is to separate adjacent devices and increase the warpage stress of the product.

[0122] It should be noted that whether to remove the organic material in the cutting street 01 depends on the product's ability to resist the stress of the entire first buffer layer 6. For example, if the product has a strong ability to resist the stress of the entire first buffer layer 6, then there is no need to remove the organic material in the cutting street 01.

[0123] Figures 9a to 9e are flow charts of another process for forming a first buffer layer 6 according to an embodiment of the present disclosure. As shown in Figures 9a to 9e, the first buffer layer 6 prepared in this manner can be applied to the glass-based 2D IPD filter shown in Figure 4. When forming the first buffer layer 6, the preparation method may include steps S31 to S33, as follows:

[0124] S31 , cleaning and drying the dielectric substrate 1 .

[0125] Specifically, as shown in Fig. 9a, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0126] Specifically, when cleaning the dielectric substrate 1 , it can be cleaned in sequence using DI, detergent, isopropyl alcohol, etc. Each cleaning time is no less than 10 minutes.

[0127] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0128] S32 , forming a first film layer 03 on the dielectric substrate 1 .

[0129] Specifically, as shown in FIG9 b , when the first film layer 03 is formed on the dielectric substrate 1 , the first film layer 03 covers the dielectric substrate 1 .

[0130] Specifically, an organic material can be coated on the dielectric substrate 1 to form the first film layer 03. Organic materials include, but are not limited to, polyimide, resin, and photoresist, as long as they can buffer heat and stress. For example, a spin coating process can be used to apply the organic material to a target thickness of 2 to 20 μm on the cleaned dielectric substrate 1.

[0131] S33 , patterning the first film layer 03 to form a first buffer layer 6 .

[0132] Specifically, as shown in FIG4 and FIG9c-9e, the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62. The first accommodating portion 61 is configured to accommodate the first electrode 31 of the capacitor, and the second accommodating portion 62 is configured to accommodate the coil structure 24 of the inductor.

[0133] Furthermore, as shown in Figure 9c, the first film layer 03 can be patterned using Halftone lithography to remove the organic material within the scribe lines 01, exposing the dielectric substrate 1. Finally, the film is cured to produce a first film layer 03 with a thickness ranging from 1 to 15 μm. Removing the organic material within the scribe lines 01 is done to separate adjacent devices and improve the product's warpage stress.

[0134] It should be noted that whether to remove the organic material in the cutting street 01 depends on the product's ability to resist the stress of the entire first buffer layer 6. For example, if the product has a strong ability to resist the stress of the entire first buffer layer 6, then there is no need to remove the organic material in the cutting street 01.

[0135] Specifically, as shown in Figure 9d, an etching mask layer 02 is formed for the first film layer 03. A layer of photoresist with a thickness of 10 to 30 μm is applied on the first film layer 03 by spin coating, and then photolithography is performed to expose the first film layer 03 corresponding to the metal RDL circuit that needs to be etched and thinned.

[0136] Specifically, as shown in FIG9e , the first film layer 03 is patterned to form a first buffer layer 6 corresponding to the metal RDL circuit (i.e., the first plate 31 of the capacitor and the coil structure 24 of the inductor). A plasma stripper can be used to remove the exposed first film layer 03 after curing to a target groove depth of 2 to 10 μm, and then remove the photoresist (i.e., etch the mask layer 02), thereby forming a first buffer layer 6 having a first accommodating portion 61 and a second accommodating portion 62.

[0137] The first accommodation portion 61 and the second accommodation portion 62 both penetrate part of the thickness of the first buffer layer 6 . The first accommodation portion 61 and the second accommodation portion 62 are 2 to 10 μm away from the dielectric substrate 1 in a direction perpendicular to the dielectric substrate 1 .

[0138] Figures 10a to 10d are another process flow chart for forming a first buffer layer 6 according to an embodiment of the present disclosure. As shown in Figures 10a to 10d, the first buffer layer 6 prepared in this manner can be applied to the glass-based 2D IPD filter shown in Figure 4. When forming the first buffer layer 6, the preparation method may include steps S41 to S43, as follows:

[0139] S41 , cleaning and drying the dielectric substrate 1 .

[0140] Specifically, as shown in Fig. 10a, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0141] Specifically, when cleaning the dielectric substrate 1 , it can be cleaned in sequence using DI, detergent, isopropyl alcohol, etc. Each cleaning time is no less than 10 minutes.

[0142] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0143] S42 , forming a first film layer 03 on the dielectric substrate 1 ; the first film layer 03 includes a first sub-film layer 031 and a second sub-film layer 032 formed in sequence along a direction away from the dielectric substrate 1 .

[0144] Specifically, as shown in FIG10 b , when the first sub-film layer 031 is formed on the dielectric substrate 1 , the first sub-film layer 031 covers the dielectric substrate 1 .

[0145] Specifically, an organic material can be coated on the dielectric substrate 1 to form the first sub-film layer 031. Organic materials include, but are not limited to, polyimide, resin, and photoresist, as long as they can buffer heat and stress. For example, a spin coating process can be used to apply the organic material to a target thickness of 2 to 10 μm on the cleaned dielectric substrate 1.

[0146] Furthermore, as shown in FIG10b, the patterning process of the first sub-film layer 031 can use Halftone lithography technology to remove the organic material in the cutting line 01 and expose the dielectric substrate 1. Here, the organic material in the cutting line 01 is removed to separate adjacent devices and increase the warpage stress of the product.

[0147] It should be noted that whether to remove the organic material in the cutting street 01 depends on the product's ability to resist the stress of the entire first buffer layer 6. For example, if the product has a strong ability to resist the stress of the entire first buffer layer 6, then there is no need to remove the organic material in the cutting street 01.

[0148] S43 , patterning the first film layer 03 to form a first buffer layer 6 .

[0149] Specifically, as shown in Figures 4, 10c, and 10d, a second sub-film layer 032 is formed on the side of the first sub-film layer 031 facing away from the dielectric substrate 1. The second sub-film layer 032 is patterned to form a first buffer layer 6 corresponding to the metal RDL circuit (i.e., the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor). Photolithography (exposure and development) can be used to remove the organic material in the area corresponding to the metal RDL circuit and the cutting path 01, and then solidify and shape it, ultimately producing the required first buffer layer 6 having the first accommodating portion 61 and the second accommodating portion 62.

[0150] Specifically, the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6 . In a direction perpendicular to the dielectric substrate 1 , the first accommodating portion 61 and the second accommodating portion 62 are 2 to 10 μm away from the dielectric substrate 1 , that is, 2 to 10 μm of organic material is retained.

[0151] In the embodiment of the present disclosure, the first buffer layer 6 is produced by a two-step coating process, i.e., the thickness of the first sub-film layer 031 is actually equal to the depth of the first accommodating portion 61 and the second accommodating portion 62. FIG11 is a cross-sectional view of the first buffer layer 6 in the embodiment of the present disclosure. As shown in FIG11 , the first buffer layer 6 is sliced ​​to produce its cross-sectional view. The scanning electron microscope (SEM) cross-sectional view of the first buffer layer 6 shows that an interface 04 exists between the two-step coating buffer layers, i.e., an interface 04 exists between the first sub-film layer 031 and the second sub-film layer 032.

[0152] It should be noted that the two-step coating method for the first buffer layer 6 can simplify the steps of forming the first accommodating portion 61 and the second accommodating portion 62, but the bonding strength is weaker than the one-step coating method. Whether to use a one-step coating or a two-step coating method to prepare the first buffer layer 6 can be determined according to the actual product requirements and is not limited in this disclosure.

[0153] It should be noted that when it is necessary to prepare the first buffer layer 6 of a glass-based 3D IPD filter, the steps are similar to the method for preparing the first buffer layer 6 of a glass-based 2D IPD filter disclosed above. The main difference is that the second accommodating portion 62 runs through the entire thickness of the first buffer layer 6, which will not be repeated here in this disclosure.

[0154] FIG12a to FIG12d are flow charts of a process for preparing a filter provided by an embodiment of the present disclosure. As shown in FIG12a to FIG12d , when preparing the glass-based 2D IPD filter shown in FIG4 , the preparation method may include steps S51 to S54, which are specifically as follows:

[0155] S51 , cleaning and drying the dielectric substrate 1 .

[0156] Specifically, as shown in Fig. 12a, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0157] Specifically, when cleaning the dielectric substrate 1 , it can be cleaned in sequence using DI, detergent, isopropyl alcohol, etc. Each cleaning time is no less than 10 minutes.

[0158] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0159] S52 , forming a first buffer layer 6 .

[0160] Specifically, as shown in FIG12 b , the step of forming the first buffer layer 6 on the dielectric substrate 1 may include any one of steps S11 to S13 , steps S31 to S33 , and steps S41 to S43 , which is not limited in the present disclosure.

[0161] S53 , forming a first conductive film layer 05 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0162] Specifically, as shown in FIG12 c , a first conductive film layer 05 is formed on a side of the first buffer layer 6 facing away from the dielectric substrate 1 , and the first conductive film layer 05 covers the first buffer layer 6 .

[0163] Specifically, the first conductive film layer 05 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer facing away from the dielectric substrate 1. The thickness of Ti ranges from 20 to 200 nm, and the thickness of Cu ranges from 100 to 1000 nm. The thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness ranging from 2 to 10 μm.

[0164] S54 , polishing the first conductive film layer 05 by CMP to form the first electrode 31 of the capacitor and the coil structure 24 of the inductor.

[0165] Specifically, as shown in FIG12d, the first conductive film layer 05 is polished flat by CMP to form the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor. The surfaces of the first electrode plate 31 and the coil structure 24 facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0166] It should be noted that since the first electrode 31 of the capacitor and the coil structure 24 of the inductor are located in a layer that is very critical in the entire device, high flatness requirements are required. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0167] Specifically, when the first conductive film layer 05 is smoothed by CMP, the metal Ti layer of the first conductive film layer 05 in contact with the first buffer layer 6 can serve as a cutoff layer for the metal Cu layer. This arrangement allows the metal Ti layer to be removed after removing the metal Cu layer on the side of the first buffer layer 6 facing away from the dielectric substrate 1, so that the surfaces of the first electrode plate 31 and the coil structure 24 facing away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0168] FIG13a to FIG13d are flow charts of another filter manufacturing process provided by an embodiment of the present disclosure. As shown in FIG13a to FIG13d, when manufacturing the glass-based 2D IPD filter shown in FIG5, the manufacturing method may include steps S61 to S64, which are specifically as follows:

[0169] S61 , cleaning and drying the dielectric substrate 1 .

[0170] Specifically, as shown in Figure 13a, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a grooved glass substrate. The dielectric substrate 1 has a first groove 81 and a second groove 82 extending partially through the dielectric substrate 1 along its thickness. The shape of the first groove 81 corresponds to the first plate 31 of the capacitor, and the shape of the second groove 82 corresponds to the coil structure 24 of the inductor. The thickness of the glass substrate ranges from 0.1 to 0.4 mm, and the depth of the first groove 81 and the second groove 82 ranges from 3 to 30 μm.

[0171] Specifically, when cleaning the dielectric substrate 1 , it can be cleaned in sequence using DI, detergent, isopropyl alcohol, etc. Each cleaning time is no less than 10 minutes.

[0172] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0173] S62 , forming a first buffer layer 6 .

[0174] Specifically, as shown in FIG13 b , the step of forming the first buffer layer 6 on the dielectric substrate 1 may include steps S21 to S23 , which will not be described in detail herein.

[0175] S63 , forming a first conductive film layer 05 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0176] Specifically, as shown in FIG13 c , a first conductive film layer 05 is formed on a side of the first buffer layer 6 facing away from the dielectric substrate 1 , and the first conductive film layer 05 covers the first buffer layer 6 .

[0177] Specifically, the first conductive film layer 05 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer facing away from the dielectric substrate 1. The thickness of Ti ranges from 20 to 200 nm, and the thickness of Cu ranges from 100 to 1000 nm. The thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness ranging from 2 to 10 μm.

[0178] S64 , polishing the first conductive film layer 05 by CMP to form the first electrode 31 of the capacitor and the coil structure 24 of the inductor.

[0179] Specifically, as shown in FIG13d, the first conductive film layer 05 is polished flat by CMP to form the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor. The surfaces of the first electrode plate 31 and the coil structure 24 facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0180] It should be noted that since the first electrode 31 of the capacitor and the coil structure 24 of the inductor are located in a layer that is very critical in the entire device, high flatness requirements are required. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0181] Specifically, when the first conductive film layer 05 is smoothed by CMP, the metal Ti layer of the first conductive film layer 05 in contact with the first buffer layer 6 can serve as a cutoff layer for the metal Cu layer. This arrangement allows the metal Ti layer to be removed after removing the metal Cu layer on the side of the first buffer layer 6 facing away from the dielectric substrate 1, so that the surfaces of the first electrode plate 31 and the coil structure 24 facing away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0182] FIG14a to FIG14e are flow charts of another filter manufacturing process provided by an embodiment of the present disclosure. As shown in FIG14a to FIG14e , when manufacturing the flexible 2D IPD filter shown in FIG6 , the manufacturing method may include steps S71 to S75, as follows:

[0183] S71 , cleaning and drying the dielectric substrate 1 , and forming a temporary carrier layer 9 .

[0184] Specifically, as shown in Fig. 14a, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0185] Specifically, when cleaning the dielectric substrate 1 , it can be cleaned in sequence using DI, detergent, isopropyl alcohol, etc. Each cleaning time is no less than 10 minutes.

[0186] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0187] Specifically, a temporary carrier material is coated on the dielectric substrate 1 to form a temporary carrier layer 9. The thickness of the temporary carrier layer 9 is in the range of 5 to 20 μm.

[0188] S72 , forming a first buffer layer 6 .

[0189] Specifically, as shown in FIG14 b , the step of forming the first buffer layer 6 on the dielectric substrate 1 may include any one of steps S11 to S13 , steps S31 to S33 , and steps S41 to S43 , which is not limited in the present disclosure.

[0190] S73 , forming a first conductive film layer 05 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0191] Specifically, as shown in FIG14 c , a first conductive film layer 05 is formed on a side of the first buffer layer 6 facing away from the dielectric substrate 1 , and the first conductive film layer 05 covers the first buffer layer 6 .

[0192] Specifically, the first conductive film layer 05 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer facing away from the dielectric substrate 1. The thickness of Ti ranges from 20 to 200 nm, and the thickness of Cu ranges from 100 to 1000 nm. The thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness ranging from 2 to 10 μm.

[0193] S74 , polishing the first conductive film layer 05 by CMP to form the first electrode 31 of the capacitor and the coil structure 24 of the inductor.

[0194] Specifically, as shown in FIG14d, the first conductive film layer 05 is smoothed by CMP to form the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor. The surfaces of the first electrode plate 31 and the coil structure 24 facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0195] It should be noted that since the first electrode 31 of the capacitor and the coil structure 24 of the inductor are located in a layer that is very critical in the entire device, high flatness requirements are required. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0196] Specifically, when the first conductive film layer 05 is smoothed by CMP, the metal Ti layer of the first conductive film layer 05 in contact with the first buffer layer 6 can serve as a cutoff layer for the metal Cu layer. This arrangement allows the metal Ti layer to be removed after removing the metal Cu layer on the side of the first buffer layer 6 facing away from the dielectric substrate 1. This allows the surfaces of the first electrode plate 31 and the coil structure 24 facing away from the dielectric substrate 1 to be flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0197] S75 , removing the dielectric substrate 1 .

[0198] Specifically, as shown in Figure 14e, the dielectric substrate 1 is removed to obtain a flexible 2D IPD filter. After step S74, single or multiple layers of different materials (metal, organic, and inorganic) are stacked, depending on device requirements, to complete device fabrication. Finally, the dielectric substrate 1, after cutting the device, is removed by destroying the temporary carrier layer 9 to obtain a flexible 2D IPD filter.

[0199] FIG15a to FIG15f are flow charts of another filter manufacturing process provided by an embodiment of the present disclosure. As shown in FIG15a to FIG15f , when manufacturing the glass-based 3D IPD filter shown in FIG2 , the manufacturing method may include steps S81 to S86, which are specifically as follows:

[0200] S81 , cleaning and drying the dielectric substrate 1 , and forming a partial structure of the inductor and a second buffer layer 7 .

[0201] Specifically, as shown in FIG15 a , the dielectric substrate 1 is cleaned. The dielectric substrate 1 includes a first surface S1 and a second surface S2 disposed opposite to each other along its thickness direction, and a first connecting via extending through its thickness direction. The dielectric substrate 1 is a glass substrate having a thickness ranging from 0.1 to 0.4 mm.

[0202] When cleaning the dielectric substrate 1, DI, detergent, isopropyl alcohol, etc. may be used in sequence for cleaning, wherein each cleaning time is not less than 10 minutes.

[0203] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0204] Specifically, in the embodiment of the present disclosure, a laser-induced etching method can be used to produce the first connection via of the TGV, and the diameter of the first connection via can range from 50um to 80μm. The cross-sectional shape of the first connection via varies depending on the process technology used. For example, the cross-sectional shape of the first connection via can be cylindrical, hourglass-shaped, etc. Metallization filling is performed in the first connection via, and the metallization filling in the through-hole is completed by sputtering and electroplating to form a first connection electrode 23 for connecting the upper and lower conductive structures of the inductor.

[0205] Specifically, a second buffer layer 7 is formed on the first surface S1 of the dielectric substrate 1. The second buffer layer 7 is made of an organic material and has a third accommodating portion 71 thereon. The third accommodating portion 71 extends through the entire thickness of the second buffer layer 7 and is configured to accommodate the first conductive structure 21 of the inductor. The steps for forming the second buffer layer 7 on the first surface S1 of the dielectric substrate 1 can refer to steps S11 to S13, steps S31 to S33, and steps S41 to S43. Since the filter in the embodiment of the present disclosure is a 3D IPD filter, the main difference in preparing the second buffer layer 7 compared to preparing a 2DIPD filter is that the third accommodating portion 71 extends through the entire thickness of the second buffer layer 7.

[0206] S82 , forming a second conductive film layer 06 on a side of the second buffer layer 7 facing away from the dielectric substrate 1 .

[0207] Specifically, as shown in FIG15 b , a second conductive film layer 06 is formed on a side of the second buffer layer 7 facing away from the dielectric substrate 1 , and the second conductive film layer 06 covers the second buffer layer 7 .

[0208] Specifically, the second conductive film layer 06 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer facing away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, and the thickness of Cu is in the range of 100 to 1000 nm. The thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness in the range of 2 to 10 μm.

[0209] S83 , polishing the second conductive film layer 06 by CMP to form the first conductive structure 21 of the inductor.

[0210] 15c, the second conductive film layer 06 is polished flat by CMP to form the first conductive structure 21 of the inductor.

[0211] Specifically, when the second conductive film layer 06 is smoothed by CMP, the metal Ti layer of the second conductive film layer 06 in contact with the second buffer layer 7 can serve as a cutoff layer for the metal Cu layer. With this arrangement, after removing the metal Cu layer on the side of the second buffer layer 7 facing away from the dielectric substrate 1, the metal Ti layer can be removed, so that the surface of the first conductive structure 21 facing away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 facing away from the dielectric substrate 1.

[0212] S84 , forming a first buffer layer 6 .

[0213] Specifically, as shown in Figure 15d, the steps of forming the first buffer layer 6 on the second surface S2 of the dielectric substrate 1 can refer to steps S11-S13, steps S31-S33, and steps S41-S43. Since the filter in the embodiment of the present disclosure is a 3D IPD filter, the main difference in preparing the first buffer layer 6 compared to preparing a 2D IPD filter is that the second accommodating portion 62 extends through the entire thickness of the first buffer layer 6. The second accommodating portion 62 is configured to accommodate the second conductive structure 22 of the inductor. Whether it is a 3D IPD filter or a 2D IPD filter, when the dielectric substrate 1 does not have a slot, the first accommodating portion 61 extends through part of the thickness of the first buffer layer 6.

[0214] S85 , forming a third conductive film layer 07 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0215] Specifically, as shown in FIG15 e , a third conductive film layer 07 is formed on a side of the first buffer layer 6 facing away from the dielectric substrate 1 , and the third conductive film layer 07 covers the first buffer layer 6 .

[0216] Specifically, the third conductive film layer 07 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer facing away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, and the thickness of Cu is in the range of 100 to 1000 nm. The thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness in the range of 2 to 10 μm.

[0217] S86 , polishing the third conductive film layer 07 by CMP to form the first electrode 31 of the capacitor and the second conductive structure 22 of the inductor.

[0218] Specifically, as shown in FIG15f, the third conductive film layer 07 is polished flat by CMP to form the first electrode plate 31 of the capacitor and the second conductive structure 22 of the inductor. The surfaces of the first electrode plate 31 and the second conductive structure 22 facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0219] It should be noted that since the layers of the first plate 31 of the capacitor and the second conductive structure 22 of the inductor are very critical in the entire device, high flatness requirements are required. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0220] Specifically, when the third conductive film layer 07 is smoothed by CMP, the metal Ti layer of the third conductive film layer 07 in contact with the first buffer layer 6 can serve as a cutoff layer for the metal Cu layer. This arrangement allows the metal Ti layer to be removed after removing the metal Cu layer on the side of the first buffer layer 6 facing away from the dielectric substrate 1, so that the surfaces of the first electrode 31 and the second conductive structure 22 facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0221] FIG16a to FIG16g are flow charts of another filter manufacturing process provided by an embodiment of the present disclosure. As shown in FIG16a to FIG16g, when manufacturing the glass-based 3D IPD filter shown in FIG3, the manufacturing method may include steps S91 to S97, which are specifically as follows:

[0222] S91 , cleaning and drying the dielectric substrate 1 , and forming a partial structure of the inductor.

[0223] Specifically, as shown in Figure 16a, the dielectric substrate 1 is cleaned. The dielectric substrate 1 includes a first surface S1 and a second surface S2 disposed opposite each other along its thickness, a first connecting via extending through its thickness, and a first slot 81 extending partially through its thickness. The dielectric substrate 1 is a glass substrate having a thickness ranging from 0.1 to 0.4 mm.

[0224] When cleaning the dielectric substrate 1, DI, detergent, isopropyl alcohol, etc. may be used in sequence for cleaning, wherein each cleaning time is not less than 10 minutes.

[0225] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0226] Specifically, in the embodiment of the present disclosure, a laser-induced etching method can be used to produce the first connection via of the TGV, and the diameter of the first connection via can range from 50um to 80μm. The cross-sectional shape of the first connection via varies depending on the process technology used. For example, the cross-sectional shape of the first connection via can be cylindrical, hourglass-shaped, etc. Metallization filling is performed in the first connection via, and the metallization filling in the through-hole is completed by sputtering and electroplating to form a first connection electrode 23 for connecting the upper and lower conductive structures of the inductor.

[0227] S92 , forming a second buffer layer 7 .

[0228] Specifically, as shown in FIG16b , a second buffer layer 7 is formed on the first surface S1 of the dielectric substrate 1. The second buffer layer 7 is made of an organic material and has a third accommodating portion 71 thereon. The third accommodating portion 71 extends through the entire thickness of the second buffer layer 7 and is configured to accommodate the first conductive structure 21 of the inductor. The steps for forming the second buffer layer 7 on the first surface S1 of the dielectric substrate 1 can refer to steps S11 to S13, steps S31 to S33, and steps S41 to S43. Since the filter in the embodiment of the present disclosure is a 3D IPD filter, the main difference in preparing the second buffer layer 7 compared to preparing a 2D IPD filter is that the third accommodating portion 71 extends through the entire thickness of the second buffer layer 7.

[0229] S93 , forming a second conductive film layer 06 on a side of the second buffer layer 7 facing away from the dielectric substrate 1 .

[0230] Specifically, as shown in FIG16 c , a second conductive film layer 06 is formed on a side of the second buffer layer 7 facing away from the dielectric substrate 1 , and the second conductive film layer 06 covers the second buffer layer 7 .

[0231] Specifically, the second conductive film layer 06 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer facing away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, and the thickness of Cu is in the range of 100 to 1000 nm. The thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness in the range of 2 to 10 μm.

[0232] S94 , polishing the second conductive film layer 06 by CMP to form the first conductive structure 21 of the inductor.

[0233] 16c, the second conductive film layer 06 is polished flat by CMP to form the first conductive structure 21 of the inductor.

[0234] Specifically, when the second conductive film layer 06 is smoothed by CMP, the metal Ti layer of the second conductive film layer 06 in contact with the second buffer layer 7 can serve as a cutoff layer for the metal Cu layer. With this arrangement, after removing the metal Cu layer on the side of the second buffer layer 7 facing away from the dielectric substrate 1, the metal Ti layer can be removed, so that the surface of the first conductive structure 21 facing away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 facing away from the dielectric substrate 1.

[0235] S95 , forming a first buffer layer 6 .

[0236] Specifically, as shown in Figure 16e, the steps of forming the first buffer layer 6 on the second surface S2 of the dielectric substrate 1 can be referred to as steps S21 to S23. Since the filter in the disclosed embodiment is a 3D IPD filter, the main difference in the preparation of the first buffer layer 6 compared to the preparation of a 2D IPD filter is that the second accommodating portion 62 extends through the entire thickness of the first buffer layer 6 and is configured to accommodate the second conductive structure 22 of the inductor. Furthermore, in the disclosed embodiment, the dielectric substrate 1 has a slot, and the first slot 81 defines the first accommodating portion 61.

[0237] S96 , forming a third conductive film layer 07 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0238] Specifically, as shown in FIG16 f , a third conductive film layer 07 is formed on the side of the first buffer layer 6 facing away from the dielectric substrate 1 , and the third conductive film layer 07 covers the first buffer layer 6 .

[0239] Specifically, the third conductive film layer 07 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer facing away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, and the thickness of Cu is in the range of 100 to 1000 nm. The thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness in the range of 2 to 10 μm.

[0240] S97 , polishing the third conductive film layer 07 by CMP to form the first electrode 31 of the capacitor and the second conductive structure 22 of the inductor.

[0241] Specifically, as shown in FIG16g , the third conductive film layer 07 is smoothed by CMP to form the first electrode plate 31 of the capacitor and the second conductive structure 22 of the inductor. The surfaces of the first electrode plate 31 and the second conductive structure 22 facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0242] It should be noted that since the layers of the first plate 31 of the capacitor and the second conductive structure 22 of the inductor are very critical in the entire device, high flatness requirements are required. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0243] Specifically, when the third conductive film layer 07 is smoothed by CMP, the metal Ti layer of the third conductive film layer 07 in contact with the first buffer layer 6 can serve as a cutoff layer for the metal Cu layer. This arrangement allows the metal Ti layer to be removed after removing the metal Cu layer on the side of the first buffer layer 6 facing away from the dielectric substrate 1, so that the surfaces of the first electrode 31 and the second conductive structure 22 facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0244] In a third aspect, an embodiment of the present disclosure further provides an electronic device comprising the filter of any one of the above embodiments.

[0245] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A filter comprising a dielectric substrate, at least one capacitor and at least one inductor integrated on the dielectric substrate; characterized in that: The filter further comprises a first buffer layer disposed on the dielectric substrate; the material of the first buffer layer is an organic material; The first buffer layer has a first accommodating portion and a second accommodating portion; the first electrode plate of the capacitor is filled in the first accommodating portion, and at least a part of the structure of the inductor is filled in the second accommodating portion, and the first electrode plate of the capacitor is away from the surface of the dielectric substrate, and the structure of the inductor filled in the second accommodating portion is away from the surface of the dielectric substrate, and both are flush with the surface of the first buffer layer away from the dielectric substrate.

2. The filter according to claim 1, characterized in that The dielectric substrate comprises a first surface and a second surface which are arranged opposite to each other along the thickness direction thereof, and a first connecting via which penetrates along the thickness direction thereof; the first buffer layer is arranged on the first surface; The inductor comprises a first conductive structure arranged on the first surface, a second conductive structure arranged on the second surface, and a first connecting electrode arranged in the first connecting via; the second conductive structure is electrically connected to the first conductive structure through the first connecting electrode to form a coil structure of the inductor; The second accommodation portion penetrates the entire thickness of the first buffer layer, and the second conductive structure is filled in the second accommodation portion.

3. The filter according to claim 2, characterized in that It also includes a second buffer layer disposed on the second surface; the material of the second buffer layer is an organic material; The second buffer layer has a third accommodating portion, the third accommodating portion runs through the entire thickness of the second buffer layer, the first conductive structure is filled in the third accommodating portion, and a surface of the first conductive structure away from the dielectric substrate is flush with a surface of the second buffer layer away from the dielectric substrate.

4. The filter according to claim 3, characterized in that The first receiving portion penetrates a portion of the thickness of the first buffer layer.

5. The filter according to claim 3, characterized in that The dielectric substrate has a first slot partially penetrating along the thickness direction thereof, and the first slot defines the first accommodation portion.

6. The filter according to claim 1, characterized in that The first accommodating portion and the second accommodating portion both penetrate a portion of the thickness of the first buffer layer; and the coil structure of the inductor is filled in the second accommodating portion.

7. The filter according to claim 1, characterized in that The dielectric substrate has a first slot and a second slot partially penetrating along the thickness direction thereof; The first buffer layer covers the dielectric substrate, and the first groove defines the first accommodating portion, and the second groove defines the second accommodating portion.

8. The filter according to claim 6, characterized in that The first buffer layer serves as the dielectric substrate.

9. The filter according to any one of claims 1 to 8, characterized in that: The organic material includes any one of polyimide, resin and photoresist.

10. A method for preparing a filter, characterized in that: include: Providing a dielectric substrate, forming at least one capacitor and at least one inductor on the dielectric substrate, and further comprising the step of forming a first buffer layer on the dielectric substrate; The step of forming the first buffer layer comprises: Cleaning and drying the dielectric substrate; forming a first film layer on the dielectric substrate; the first film layer covers the dielectric substrate; The first film layer is patterned to form the first buffer layer; the first buffer layer has a first accommodating portion and a second accommodating portion, the first accommodating portion is configured to accommodate a first plate of a capacitor, and the second accommodating portion is configured to accommodate at least a partial structure of an inductor.

11. The method for preparing a filter according to claim 10, characterized in that: The first accommodation portion and the second accommodation portion both penetrate a portion of the thickness of the first buffer layer, and the second accommodation portion is configured to accommodate a coil structure of an inductor.

12. The method for preparing a filter according to claim 10, characterized in that: The dielectric substrate has a first slot and a second slot partially penetrating along the thickness direction thereof; The first buffer layer covers the dielectric substrate, and the first groove defines the first accommodating portion, and the second groove defines the second accommodating portion.

13. The method for preparing a filter according to claim 10, characterized in that: The first film layer includes a first sub-film layer and a second sub-film layer which are sequentially formed in a direction away from the dielectric substrate.

14. The method for preparing a filter according to claim 11 or 12, characterized in that: The step of forming at least one capacitor and at least one inductor on the dielectric substrate comprises: forming a first conductive film layer on a side of the first buffer layer away from the dielectric substrate; the first conductive film layer covers the first buffer layer; The first conductive film layer is polished by CMP to form a first electrode plate of the capacitor and a coil structure of the inductor; surfaces of the first electrode plate and the coil structure facing away from the dielectric substrate are flush with a surface of the first buffer layer facing away from the dielectric substrate.

15. The method for preparing a filter according to claim 10, characterized in that: The dielectric substrate comprises a first surface and a second surface which are arranged opposite to each other along the thickness direction thereof, and a first connecting via which penetrates along the thickness direction thereof; the first buffer layer is arranged on the first surface; The filter further comprises a second buffer layer disposed on the second surface; the material of the second buffer layer is an organic material; The second buffer layer has a third accommodating portion, the third accommodating portion runs through the entire thickness of the second buffer layer, the third accommodating portion is configured to accommodate a first conductive structure of an inductor, and a surface of the first conductive structure facing away from the dielectric substrate is flush with a surface of the second buffer layer facing away from the dielectric substrate; The second receiving portion penetrates the entire thickness of the first buffer layer, and the second receiving portion is configured to receive a second conductive structure of an inductor.

16. The method for preparing a filter according to claim 15, characterized in that: The first receiving portion penetrates a portion of the thickness of the first buffer layer.

17. The method for preparing a filter according to claim 15, characterized in that: The dielectric substrate has a first slot partially penetrating along the thickness direction thereof, and the first slot defines the first accommodation portion.

18. The method for preparing a filter according to claim 16 or 17, characterized in that: The step of forming at least one capacitor and at least one inductor on the dielectric substrate comprises: forming a first connection electrode of the inductor in the first connection via hole; forming a second conductive film layer on a side of the second buffer layer away from the dielectric substrate; The second conductive film layer is polished flat by CMP to form a first conductive structure of the inductor; a surface of the first conductive structure facing away from the dielectric substrate is flush with a surface of the second buffer layer facing away from the dielectric substrate; forming a third conductive film layer on a side of the first buffer layer away from the dielectric substrate; The third conductive film layer is polished by CMP to form a first electrode plate of the capacitor and a second conductive structure of the inductor; surfaces of the first electrode plate and the second conductive structure facing away from the dielectric substrate are both flush with a surface of the first buffer layer facing away from the dielectric substrate.

19. An electronic device, characterized in that: The filter comprises the filter according to any one of claims 1 to 9.

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