Fault-tolerant synchronous clock transmission system

Abstract

Disclosed in the present invention is a fault-tolerant synchronous clock transmission system, comprising a first transmission terminal, a second transmission terminal and a first transmission channel, the first transmission terminal being connected to the second transmission terminal by means of the first transmission channel, the first transmission terminal sending first transmission frames at a preset time interval to the second transmission terminal by means of the first transmission channel, each first transmission frame comprising a first synchronization header, the second transmission terminal using a received first synchronization header position to perform clock recovery to generate a local clock, the first synchronization header consisting of n1 start symbols, and n1≥3. The start symbols are encoded by means of line codes, and the second transmission terminal uses the received start symbols to determine the position of the first synchronization header. When at most two start symbols among the n1 start symbols have error, the second transmission terminal can still use the received start symbols to determine the position of the first synchronization header where the start symbols are located.

Description

A fault-tolerant synchronous clock transmission system Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a fault-tolerant synchronous clock transmission system. Background Art

[0002] In serial data transmission systems, to conserve wires, communication lines often lack dedicated clock lines for transmitting clock signals. To ensure accurate data reception at the receiving end, data is typically encoded with a line code before transmission. This line coding increases the transitions between transmitted data bits. At the receiving end, a clock and data recovery circuit then recovers the clock for data sampling. This method is used in transmission protocols such as PCIe, USB 3.0, and DisplayPort. This method requires continuous data transmission without interruptions, as otherwise the clock recovery process would be interrupted, leading to received data errors.

[0003] In another type of time-sharing transmission system based on time slices, such as the common in-vehicle audio transmission system, time-sharing transmission is often used to transmit audio data. Each time slice transmits one or more audio sampling points, and the system does not transmit data between time slices. In other words, the clock recovery circuit cannot rely on the continuous transmission of data.

[0004] To perform clock recovery, the transmitter can add a special character as a synchronization header before the data of a time slice. After receiving the synchronization header, the receiver can use the synchronization header position to perform clock recovery and generate a local clock. The synchronization header position is the time after the receiver receives the last bit of the synchronization header. The receiver uses the generated local clock to sample the data, thereby achieving the purpose of correctly receiving data.

[0005] In an in-vehicle serial data transmission system, due to possible noise interference in the in-vehicle environment, the synchronization header may have bit errors. If the synchronization header is missed due to bit errors, it may cause clock recovery errors.

[0006] Currently, there is a lack of a method that can recover the clock through the received synchronization header position and detect the synchronization header position without being affected by synchronization header errors.

[0007] Summary of the Invention

[0008] The technical problem to be solved by the present invention is how to recover the clock through the received synchronization head position while making the synchronization head position detection not affected by the synchronization head error.

[0009] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0010] As a fault-tolerant synchronous clock transmission system of the present invention, it includes a first transmission terminal, a second transmission terminal, and a first transmission channel. The first transmission terminal is connected to the second transmission terminal through the first transmission channel. The first transmission terminal sends a first transmission frame to the second transmission terminal through the first transmission channel at a preset time interval. The first transmission frame includes a first synchronization header. The second transmission terminal uses the received first synchronization header position to perform clock recovery and generate a local clock. The first synchronization header is composed of n1 start symbols, n1≥3, and the start symbols are encoded by a line code. The second transmission terminal uses the received start symbol to determine the position of the first synchronization header. Among the n1 start symbols, when at most two start symbols are erroneous, the second transmission terminal can still use the received start symbol to determine the position of the first synchronization header where it is located.

[0011] Preferably, the n1 start characters include at least 3 unique K codes.

[0012] Preferably, the three unique K codes are K1, K2, and K3, and the three K codes are different from each other.

[0013] Preferably, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n1 is ≥ 4. In addition to the three unique K codes, the n1 start symbols also include a D code D1, and D1 is not the first or last start symbol in the first synchronization header.

[0014] Preferably, the three unique K codes are K1, K1, and K2, two K1s are the same, K1 and K2 are different, and n1≥4. In addition to the three unique K codes, the n1 start symbols also include a D code D1.

[0015] Preferably, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n1 is ≥ 5. In addition to the three unique K codes, the n1 start characters also include D codes D1 and D2, and D1 is different from D2.

[0016] Preferably, the first transmission frame further includes a first data field for transmitting data.

[0017] Preferably, the synchronous clock transmission system further includes a second transmission channel and a third transmission terminal, the second transmission channel is connected to the second transmission terminal, the second transmission terminal sends a second transmission frame to the third transmission terminal through the second transmission channel, the second transmission frame includes a second synchronization header, the second synchronization header is synchronized with the first synchronization header, the third transmission terminal uses the received second synchronization header position to perform clock recovery to generate a local clock, the second synchronization header is composed of n2 start symbols, n2≥3, the start symbol is encoded by the line code, the third transmission terminal uses the received start symbol to determine the position of the second synchronization head, among the n2 start symbols, when at most two start symbols are erroneous, the third transmission terminal can still use the received start symbol to determine the position of the second synchronization head where it is located.

[0018] Preferably, the n2 start characters include at least 3 unique K codes.

[0019] Preferably, the three unique K codes are K1, K2, and K3, and the three K codes are different from each other.

[0020] Preferably, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n1 is ≥ 4. In addition to the three unique K codes, the n1 start symbols also include a D code D1, and D1 is not the first or last start symbol in the first synchronization header.

[0021] Preferably, the three unique K codes are K1, K1, and K2, two K1s are the same, K1 and K2 are different, and n1≥4. In addition to the three unique K codes, the n1 start symbols also include a D code D1.

[0022] Preferably, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n1 is ≥ 5. In addition to the three unique K codes, the n1 start characters also include D codes D1 and D2, and D1 is different from D2.

[0023] Preferably, the second transmission frame further includes a second data field for transmitting data.

[0024] Preferably, the second transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, and then uses the generated local clock to send the second transmission frame.

[0025] Preferably, the line code is 8b / 10b code.

[0026] Preferably, the line code is 9b / 10b code.

[0027] As a transmission terminal of the present invention, it is connected to a first transmission channel, and receives a first transmission frame transmitted at a preset time interval from the first transmission channel. The first transmission frame includes a first synchronization header. The transmission terminal uses the received first synchronization header position to perform clock recovery and generate a local clock. The first synchronization header is composed of n1 start symbols, n1≥3, and the start symbols are encoded by a line code. The transmission terminal uses the received start symbols to determine the position of the first synchronization header. Among the n1 start symbols, when at most two start symbols are erroneous, the transmission terminal can still use the received start symbols to determine the position of the first synchronization header where it is located.

[0028] Preferably, the n2 start characters include at least 3 unique K codes.

[0029] Preferably, the three unique K codes are K1, K2, and K3, and the three K codes are different from each other.

[0030] Preferably, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n2 is ≥ 4. In addition to the three unique K codes, the n2 start symbols also include the D code D1, and D1 is not the first or last start symbol in the first synchronization header.

[0031] Preferably, the three unique K codes are K1, K1, and K2, two K1s are the same, K1 and K2 are different, and n2≥4. In addition to the three unique K codes, the n2 start characters also include a D code D1.

[0032] Preferably, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n2 is ≥ 5. In addition to the three unique K codes, the n2 start characters also include D codes D1 and D2, and D1 is different from D2.

[0033] Preferably, the first transmission frame further includes a first data field for transmitting data.

[0034] Preferably, the transmission terminal is further connected to a second transmission channel, and the transmission terminal sends a second transmission frame through the second transmission channel, wherein the second transmission frame includes a second synchronization header, and the second synchronization header is composed of n2 start symbols, where n2≥3.

[0035] Preferably, the start symbol is encoded through the line code, the second synchronization head is synchronized with the first synchronization head, the terminal receiving the second synchronization head uses the received second synchronization head position to perform clock recovery to generate a local clock, and the terminal receiving the second synchronization head uses the received start symbol to determine the position of the second synchronization head. Among the n2 start symbols of the second synchronization head, when at most two start symbols are erroneous, the terminal receiving the second synchronization head can still use the received start symbol to determine the position of the second synchronization head where it is located.

[0036] Preferably, the n2 start characters include at least 3 unique K codes.

[0037] Preferably, the three unique K codes are K1, K2, and K3, and the three K codes are different from each other.

[0038] Preferably, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n1 is ≥ 4. In addition to the three unique K codes, the n1 start symbols also include a D code D1, and D1 is not the first or last start symbol in the first synchronization header.

[0039] Preferably, the three unique K codes are K1, K1, and K2, two K1s are the same, K1 and K2 are different, and n1≥4. In addition to the three unique K codes, the n1 start symbols also include a D code D1.

[0040] Preferably, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n1 is ≥ 5. In addition to the three unique K codes, the n1 start characters also include D codes D1 and D2, and D1 is different from D2.

[0041] Preferably, the second transmission frame further includes a second data field for transmitting data.

[0042] Preferably, the transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, and then uses the generated local clock to send the second transmission frame.

[0043] Preferably, the line code is 8b / 10b code.

[0044] Preferably, the line code is 9b / 10b code. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] FIG1 is a block diagram of a fault-tolerant synchronous clock transmission system according to the present invention;

[0046] 2 is a schematic diagram of a first transmission terminal sending a first transmission frame in a fault-tolerant synchronous clock transmission system of the present invention;

[0047] 3 is a schematic diagram of the structure of a first transmission frame and the position of a first synchronization header in a fault-tolerant synchronous clock transmission system of the present invention;

[0048] FIG4 is a schematic diagram of a type of synchronization header in a fault-tolerant synchronous clock transmission system of the present invention;

[0049] FIG5 is a schematic diagram of another type of synchronization header in a fault-tolerant synchronous clock transmission system of the present invention;

[0050] FIG6 is a schematic diagram of another type of synchronization header in a fault-tolerant synchronous clock transmission system of the present invention;

[0051] 7 is a schematic diagram of another type of synchronization header in a fault-tolerant synchronous clock transmission system of the present invention;

[0052] FIG8 is a block diagram of another fault-tolerant synchronous clock transmission system of the present invention.

[0053] 9 is a schematic diagram of another fault-tolerant synchronous clock transmission system of the present invention, in which a first transmission terminal sends a first transmission frame and a second transmission terminal sends a second transmission frame;

[0054] FIG10 is a block diagram of another fault-tolerant synchronous clock transmission system of the present invention.

[0055] Where: 1 First transmission terminal 2 Second transmission terminal 3 First transmission channel 4 Third transmission terminal 5 Second transmission channel DETAILED DESCRIPTION

[0056] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings. It should be understood that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0057] As shown in Figure 1, in an application embodiment of the present invention, as a fault-tolerant synchronous clock transmission system of the present invention, it is used to transmit synchronous clock. The transmission system includes a first transmission terminal 1, a second transmission terminal 2, and a first transmission channel 3. The first transmission terminal 1 is connected to the second transmission terminal 2 through the first transmission channel 3.

[0058] As shown in FIG2 , in this embodiment, the first transmission terminal 1 sends a first transmission frame to the second transmission terminal 2 through the first transmission channel 3 at a preset time interval T1 , where A0 , A1 , A2 , . . . are all first transmission frames.

[0059] As shown in Figure 3, in this embodiment, the first transmission frame includes a first synchronization header, and the second transmission terminal 2 uses the received first synchronization header position to perform clock recovery to generate a local clock. The first synchronization header position is the time when the second transmission terminal 2 receives and recognizes the first synchronization header. After receiving and recognizing the synchronization header, the synchronization header position information is generated, and this information is sent to the phase-locked loop circuit to generate a clock signal with the same frequency as the synchronization header.

[0060] The present invention does not limit the implementation method of the synchronization header receiving circuit, nor does it limit how the synchronization header position information is used to recover the clock. A variety of methods can be used to receive the synchronization header, such as an oversampling receiving circuit. The oversampling clock is much higher than the transmission rate (at least three times). After the synchronization header is recognized, the synchronization header position information is generated. This information is then fed into a phase-locked loop circuit to generate a clock signal with the same frequency as the synchronization header.

[0061] The first synchronization header consists of n1 start symbols, where n1 ≥ 3. These start symbols are encoded with a line code and then sent to the first transmission channel 3. Common line codes include 4b / 5b, 8b / 10b, and 9b / 10b. Using line codes to encode the start symbols ensures sufficient "0" and "1" transitions in the synchronization header, reducing or eliminating the DC component of the signal during synchronization header transmission. This simplifies receiver circuit design and lowers the bit error rate, facilitating clock recovery at the receiver. Line codes consist of K codes and D codes. K codes are typically used to encode control characters, while D codes are used to encode data. A K code is considered unique if its binary sequence appears only within the control characters it encodes and not within any D code or combination of D codes. For example, in the 8b / 10b encoding standard, which is widely used in protocols such as SATA, PCIE, RapidIO, and USB 3.0, K28.1, K28.5, and K28.7 are unique K codes. Using a unique K code as a start character can prevent false detection of synchronization headers in the data field. In this embodiment, the line code uses 8b / 10b, but the present invention does not limit the line code used. A symbol before 8b / 10b encoding is 8 bits, and a symbol after 8b / 10b encoding is 10 bits.

[0062] As shown in FIG3 , in this embodiment, the first transmission frame further includes a first data field, and the first data field is used to transmit data. In other embodiments, the first transmission frame may not include the first data field.

[0063] In this embodiment, the second transmission terminal 2 uses the received start symbol to determine the location of the first synchronization header. In the international standard ISO 7637-2 fast pulse interference test, each fast pulse can interfere with the signal on the transmission line for up to 50 nanoseconds. Taking a 100 Mbps data rate as an example, five consecutive bit errors will occur on the transmission channel. When these five bits belong to two start symbols, two start symbols may be erroneous. Among the n1 start symbols of the first synchronization header, if at most two start symbols are erroneous, the second transmission terminal can still use the received start symbol to determine its location in the first synchronization header. To achieve this, the n1 start symbols must contain at least three unique K codes.

[0064] As shown in Figure 4(a), n1 = 3. The first synchronization header consists of three unique K codes, K1, K2, and K3. Figures 4(b) through 4(d) illustrate three scenarios when two start symbols in the first synchronization header are erroneous (the shaded areas represent erroneous start symbols), namely, the detection of "K1," "K2," and "K3," respectively. These three scenarios are independent and can be distinguished by the second transmission terminal 2. For example, in Figure 4(b), where K2 and K3 are erroneous, the first synchronization header ends 20 bits after the second transmission terminal 2 detects "K1" (an 8b / 10b-encoded start symbol is 10 bits).

[0065] As shown in Figure 5(a), n1 = 4. The first synchronization header consists of three identical, unique K codes: K1, K1, K1, and D code D1. D1 is not the first or last start symbol in the first synchronization header. Figures 5(b) through 5(g) illustrate six scenarios when two start symbols in the first synchronization header are erroneous (the shaded area indicates an erroneous start symbol, and "X" indicates an erroneous start symbol after 8b / 10b encoding). These scenarios are "K1D1," "K1XK1," "K1XXK1," "D1K1," "D1XK1," and "K1K1," respectively. These six scenarios are independent and can be distinguished by the second transmission terminal 2. For example, in Figure 5(c), where D1 and the third K1 are erroneous, the first synchronization header ends 10 bits after the second transmission terminal 2 detects "K1XK1."

[0066] As shown in Figure 6(a), n1 = 4. The first synchronization header consists of three unique K codes, K1, K1, and K2, and a D code, D1. The two K1s are identical, but K1 and K2 are different. Figures 6(b) through 6(g) illustrate six scenarios when two start symbols in the first synchronization header are erroneous (the shaded area represents an erroneous start symbol, and "X" represents an erroneous start symbol after 8b / 10b encoding). These scenarios are "K1K1," "K1XK2," "K1XXD1," "K1K2," "K1XD1," and "K2D1," respectively. These six scenarios are independent and can be distinguished by the second transmission terminal 2. For example, in the case of errors in K2 and D1 shown in Figure 6(b), the first synchronization header ends 20 bits after the second transmission terminal 2 detects "K1K1."

[0067] As shown in Figure 7(a), n1 = 5. The first synchronization header consists of three identical unique K codes, K1, K1, and K1, and two different D codes, D1 and D2. Figures 7(b) to 7(k) show 10 scenarios when two start symbols in the first synchronization header are erroneous (the shaded area indicates an erroneous start symbol, and "X" indicates an erroneous start symbol after 8b / 10b encoding). These scenarios are respectively "K1K1K1," "K1K1XD1," "K1K1XXD2," "K1XK1D1," "K1XK1XD2," "K1XXD1D2," "K1K1D1," "K1K1XD2," "K1XD1D2," and "K1D1D2." These 10 scenarios are independent and can be distinguished by the second transmission terminal 2. For example, in the case of errors in D1 and D2 shown in Figure 7(b), the first synchronization header ends 20 bits after the second transmission terminal 2 detects "K1K1K1."

[0068] The embodiments shown in FIG. 4 to FIG. 7 are merely preferred embodiments of the first synchronization head in the present invention, and the protection scope of the present invention is not limited to these embodiments.

[0069] In this embodiment, either one or both of the first transmission terminal 1 and the second transmission terminal 2 may be in the form of an integrated circuit chip.

[0070] In another application embodiment of the present invention as shown in Figure 8, as a fault-tolerant synchronous clock transmission system of the present invention, it is used to transmit synchronous clock. Compared with the embodiment shown in Figure 1, the transmission system not only includes a first transmission terminal 1, a second transmission terminal 2, and a first transmission channel 3, but also includes a third transmission terminal 4 and a second transmission channel 5. The first transmission terminal 1 is connected to the second transmission terminal 2 through the first transmission channel 3, and the second transmission terminal 2 is connected to the third transmission terminal 4 through the second transmission channel 5.

[0071] As shown in Figure 9, in this embodiment, the first transmission terminal 1 sends a first transmission frame to the second transmission terminal 2 through the first transmission channel 3 at a preset time interval T1. A0, A1, A2,... are all first transmission frames. After receiving the first transmission frame, the second transmission terminal 2 uses the generated local clock to send a second transmission frame at a preset time interval T2. B0, B1, B2,... are all second transmission frames.

[0072] In this embodiment, the structure of the first transmission frame is shown in Figure 3. Similar to the structure of the first transmission frame shown in Figure 3, the second transmission frame includes a second synchronization header. The third transmission terminal 4 uses the received second synchronization header position to perform clock recovery and generate a local clock. The second synchronization header position represents the time when the third transmission terminal 4 received the second synchronization header. The second synchronization header consists of n2 start symbols, where n2 ≥ 3. The start symbols are encoded with a line code and then transmitted to the third transmission terminal 4. In this embodiment, the second transmission frame also includes a second data field, which is used to transmit data. In other embodiments, the second transmission frame may not include the second data field.

[0073] In this embodiment, the third transmission terminal 4 uses the received start symbols to determine the location of the second synchronization header. Even if at most two of the n2 start symbols in the second synchronization header contain errors, the third transmission terminal 4 can still use the received start symbols to determine the location of the second synchronization header. To achieve this, the n2 start symbols must contain at least three unique K codes. For an embodiment of how the third transmission terminal 4 can still use the received start symbols to determine the location of the second synchronization header even if two of the n2 start symbols contain errors, see Figures 4 to 7.

[0074] As shown in Figure 9, in this embodiment, in order to enable the third transmission terminal 4 to correctly perform clock recovery and generate a local clock, the second synchronization header is synchronized with the first synchronization header, that is, the time interval T1 for the first transmission terminal 1 to send the first synchronization header is the same as the time interval T2 for the second transmission terminal 2 to send the second synchronization header, T1 = T2.

[0075] In this embodiment, any one or more of the first transmission terminal 1 , the second transmission terminal 2 , and the third transmission terminal 4 may be in the form of an integrated circuit chip.

[0076] In another application embodiment of the present invention as shown in Figure 10, as a fault-tolerant synchronous clock transmission system of the present invention, it includes more transmission terminals and shows a more complex topology. In this embodiment, each transmission terminal has at most one upstream transmission terminal, but can have multiple downstream transmission terminals. Each transmission terminal receives a synchronization header from its upstream transmission terminal (except transmission terminal 11) and sends a synchronization header to its downstream transmission terminal (except transmission terminals 41, 42, and 43). The synchronization header sent to the downstream transmission terminal is synchronized with the synchronization header received from the upstream transmission terminal.

[0077] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A fault-tolerant synchronous clock transmission system, comprising a first transmission terminal, a second transmission terminal, and a first transmission channel, wherein the first transmission terminal is connected to the second transmission terminal via the first transmission channel, Features: The first transmission terminal sends a first transmission frame to the second transmission terminal through the first transmission channel at a preset time interval, The first transmission frame comprises a first synchronization header, The second transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, The first synchronization header is composed of n1 start symbols, n1≥3, The start symbol is encoded by line code. The second transmission terminal determines the position of the first synchronization header using the received start symbol, When errors occur in at most two of the n1 start symbols, the second transmission terminal can still determine the position of the first synchronization header where it is located by using the received start symbols.

2. A fault-tolerant synchronous clock transmission system according to claim 1, characterized in that: The n1 start symbols contain at least 3 unique K codes.

3. A fault-tolerant synchronous clock transmission system according to claim 2, characterized in that: The three unique K codes are K1, K2, and K3, and the three K codes are different from each other.

4. A fault-tolerant synchronous clock transmission system according to claim 2, characterized in that: The three unique K codes are K1, K1, K1, and the three K codes are the same. The n1≥4, in addition to the three unique K codes, the n1 start symbols also include a D code D1, and D1 is not the first or last start symbol in the first synchronization header.

5. A fault-tolerant synchronous clock transmission system according to claim 2, characterized in that: The three unique K codes are K1, K1, and K2, the two K1s are the same, and K1 and K2 are different. The n1≥4, in addition to the 3 unique K codes, the n1 start symbols also include a D code D1.

6. A fault-tolerant synchronous clock transmission system according to claim 2, characterized in that: The three unique K codes are K1, K1, K1, and the three K codes are the same. The n1≥5, in addition to the three unique K codes, the n1 start symbols also include D codes D1 and D2, and D1 is different from D2.

7. A fault-tolerant synchronous clock transmission system according to claim 1, characterized in that: The first transmission frame also includes a first data field for transmitting data.

8. The fault-tolerant synchronous clock transmission system according to claim 1, characterized in that: The synchronous clock transmission system further comprises a second transmission channel and a third transmission terminal. The second transmission channel is connected to the second transmission terminal, and the second transmission terminal sends a second transmission frame to the third transmission terminal through the second transmission channel. The second transmission frame comprises a second synchronization header, The second synchronization header is synchronized with the first synchronization header, The third transmission terminal uses the received second synchronization header position to perform clock recovery to generate a local clock, The second synchronization header is composed of n2 start symbols, n2≥3, The start symbol is encoded by line code. The third transmission terminal determines the position of the second synchronization header using the received start symbol, When errors occur in at most two of the n2 start symbols, the third transmission terminal can still determine the position of the second synchronization header where it is located by using the received start symbols.

9. A fault-tolerant synchronous clock transmission system according to claim 8, characterized in that: The n2 start characters include at least 3 unique K codes.

10. A fault-tolerant synchronous clock transmission system according to claim 9, characterized in that: The three unique K codes are K1, K2, and K3, and the three K codes are different from each other.

11. A fault-tolerant synchronous clock transmission system according to claim 9, characterized in that: The three unique K codes are K1, K1, K1, and the three K codes are the same. The n1≥4, in addition to the three unique K codes, the n1 start symbols also include a D code D1, and D1 is not the first or last start symbol in the first synchronization header.

12. A fault-tolerant synchronous clock transmission system according to claim 9, characterized in that: The three unique K codes are K1, K1, and K2, the two K1s are the same, and K1 and K2 are different. The n1≥4, in addition to the 3 unique K codes, the n1 start symbols also include a D code D1.

13. The fault-tolerant synchronous clock transmission system according to claim 9, characterized in that: The three unique K codes are K1, K1, K1, and the three K codes are the same. The n1≥5, in addition to the three unique K codes, the n1 start symbols also include D codes D1 and D2, and D1 is different from D2.

14. A fault-tolerant synchronous clock transmission system according to claim 8, characterized in that: The second transmission frame further includes a second data field for transmitting data.

15. The fault-tolerant synchronous clock transmission system according to claim 8, characterized in that: The second transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, and then uses the generated local clock to send a second transmission frame.

16. A fault-tolerant synchronous clock transmission system according to claim 1 or 8, characterized in that: The line code is 8b / 10b code.

17. A fault-tolerant synchronous clock transmission system according to claim 1 or 8, characterized in that: The line code is 9b / 10b code.

18. A transmission terminal connected to a first transmission channel, characterized in that: The transmission terminal receives a first transmission frame transmitted at a preset time interval from the first transmission channel, The first transmission frame comprises a first synchronization header, The transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, The first synchronization header is composed of n1 start symbols, n1≥3, The start symbol is encoded by line code. The transmission terminal determines the position of the first synchronization header using the received start symbol, When errors occur in at most two of the n1 start symbols, the transmission terminal can still use the received start symbols to determine the position of the first synchronization header where it is located.

19. A fault-tolerant synchronous clock transmission system according to claim 18, characterized in that: The n2 start characters include at least 3 unique K codes.

20. A fault-tolerant synchronous clock transmission system according to claim 19, characterized in that: The three unique K codes are K1, K2, and K3, and the three K codes are different from each other.

21. The fault-tolerant synchronous clock transmission system according to claim 19, characterized in that: The three unique K codes are K1, K1, K1, and the three K codes are the same. The n2≥4, in addition to the three unique K codes, the n2 start symbols also include a D code D1, and D1 is not the first or last start symbol in the first synchronization header.

22. A fault-tolerant synchronous clock transmission system according to claim 19, characterized in that: The three unique K codes are K1, K1, and K2, the two K1s are the same, and K1 and K2 are different. The n2≥4, in addition to the 3 unique K codes, the n2 start symbols also include the D code D1.

23. A fault-tolerant synchronous clock transmission system according to claim 19, characterized in that: The three unique K codes are K1, K1, K1, and the three K codes are the same. The n2≥5, in addition to the 3 unique K codes, the n2 start codes also include the D code D1 and D2, D1 is different from D2.

24. A fault-tolerant synchronous clock transmission system according to claim 18, characterized in that: The first transmission frame also includes a first data field for transmitting data.

25. A transmission terminal according to claim 18, characterized in that: The transmission terminal is also connected to a second transmission channel, and the transmission terminal sends a second transmission frame through the second transmission channel. The second transmission frame includes a second synchronization header, and the second synchronization header is composed of n2 start symbols, where n2≥3. The start symbol is encoded by line code. The second synchronization header is synchronized with the first synchronization header, The terminal receiving the second synchronization header uses the received second synchronization header position to perform clock recovery to generate a local clock. The terminal receiving the second synchronization header determines the position of the second synchronization header using the received start symbol, When at most two of the n2 start symbols in the second synchronization header are erroneous, the terminal receiving the second synchronization header can still determine the position of the second synchronization header by using the received start symbols.

26. A fault-tolerant synchronous clock transmission system according to claim 25, characterized in that: The n2 start characters include at least 3 unique K codes.

27. A fault-tolerant synchronous clock transmission system according to claim 26, characterized in that: The three unique K codes are K1, K2, and K3, and the three K codes are different from each other.

28. A fault-tolerant synchronous clock transmission system according to claim 26, characterized in that: The three unique K codes are K1, K1, K1, and the three K codes are the same. The n1≥4, in addition to the three unique K codes, the n1 start symbols also include a D code D1, and D1 is not the first or last start symbol in the first synchronization header.

29. A fault-tolerant synchronous clock transmission system according to claim 26, characterized in that: The three unique K codes are K1, K1, and K2, the two K1s are the same, and K1 and K2 are different. The n1≥4, in addition to the 3 unique K codes, the n1 start symbols also include a D code D1.

30. A fault-tolerant synchronous clock transmission system according to claim 26, characterized in that: The three unique K codes are K1, K1, K1, and the three K codes are the same. The n1≥5, in addition to the three unique K codes, the n1 start symbols also include D codes D1 and D2, and D1 is different from D2.

31. A fault-tolerant synchronous clock transmission system according to claim 25, characterized in that: The second transmission frame further includes a second data field for transmitting data.

32. A transmission terminal according to claim 25, characterized in that: The transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, and then uses the generated local clock to send a second transmission frame.

33. A fault-tolerant synchronous clock transmission system according to claim 18 or 25, characterized in that: The line code is 8b / 10b code.

34. A fault-tolerant synchronous clock transmission system according to claim 18 or 25, characterized in that: The line code is 9b / 10b code.

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