Array substrate, display panel and display apparatus

Abstract

Provided in at least one embodiment of the present disclosure are an array substrate, a display panel and a display apparatus. The array substrate comprises: a semiconductor layer and a light shielding layer which are stacked on a base substrate. The semiconductor layer comprises a first branch portion and a second branch portion which are oppositely arranged, and a connecting portion connecting the first branch portion and the second branch portion. The first branch portion comprises a first channel area, and the second branch portion comprises a second channel area. A first via hole structure is provided on the side of the first branch portion away from the base substrate, the orthographic projection of the first via hole structure on the base substrate being located within the orthographic projection of an end portion of the first branch portion away from the connecting portion on the base substrate. The orthographic projection of the light shielding layer on the base substrate at least covers the orthographic projections of the first channel area and the first via hole structure on the base substrate. The array substrate can reduce the current leakage phenomenon by adjusting the design of the light shielding layer, thereby improving the retention capability of pixel capacitors, relieving the problem of low-frequency flickering and furthermore ensuring the aperture ratio of display panels.

Description

Array substrate, display panel, and display device

[0001] This application claims priority to Chinese patent application No. 202310796827.7 filed on June 30, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to an array substrate, a display panel, and a display device. Background Art

[0003] Low-Temperature Polycrystalline Silicon Thin Film Transistor (LTPS TFT) technology has matured. Compared to amorphous silicon TFTs and metal oxide TFTs, LTPS TFTs have higher carrier mobility, which can enhance the driving capability of display devices using them and reduce power consumption. Current LTPS TFTs have a top-gate structure. When using LTPS TFTs in liquid crystal display panels, a light-shielding layer must be designed to completely cover the channel region; otherwise, light leakage will occur in the LTPS channel.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides an array substrate, a display panel, and a display device. In the array substrate, the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projection of the first channel region and the first via structure on the base substrate. By adjusting the design of the light-shielding layer, the array substrate can reduce the leakage current of the subsequently formed display panel to enhance the retention capacity of the pixel capacitance, thereby improving the problem of flickering at low frequencies and ensuring the aperture ratio of the subsequently formed display panel.

[0006] At least one embodiment of the present disclosure provides an array substrate, which includes a base substrate and a semiconductor layer and a light-shielding layer stacked on the base substrate, the semiconductor layer including a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion including a first channel region, the second branch portion including a second channel region, a first via structure being provided on a side of the first branch portion away from the base substrate, and the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the end of the first branch portion away from the connecting portion on the base substrate; the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projection of the first channel region and the first via structure on the base substrate.

[0007] For example, in the array substrate provided in at least one embodiment of the present disclosure, the side of the second branch portion away from the base substrate has a second via structure, and the orthographic projection of the second via structure on the base substrate is located within the orthographic projection of the end of the second branch portion away from the connecting portion on the base substrate, and the minimum distance between the second via structure and the connecting portion is greater than or equal to the minimum distance between the first via structure and the connecting portion.

[0008] For example, in the array substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the light shielding layer on the base substrate.

[0009] For example, in the array substrate provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the base substrate, the portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and the portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure.

[0010] For example, in the array substrate provided in at least one embodiment of the present disclosure, the first branch portion and the second branch portion both extend along a first direction, the connecting portion extends along a second direction intersecting the first direction, the first branch portion, the second branch portion and the connecting portion are arranged to form an opening area, and the light-shielding layer covers at least part of the opening area.

[0011] For example, the array substrate provided by at least one embodiment of the present disclosure also includes a first metal layer arranged on a side of the semiconductor layer away from the base substrate, the first metal layer includes a gate line extending in the second direction, the gate line includes a first gate and a second gate, the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel region on the base substrate.

[0012] For example, in the array substrate provided in at least one embodiment of the present disclosure, there is a gap between the light shielding layer and the connecting portion in the first direction.

[0013] For example, in the array substrate provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the base substrate, the portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, the portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are respectively the first sub-light-shielding portion and the second sub-light-shielding portion, and the first sub-light-shielding portion and the second sub-light-shielding portion are spaced apart from each other.

[0014] For example, in the array substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light-shielding portion on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the second sub-light-shielding portion on the base substrate.

[0015] At least one embodiment of the present disclosure also provides a display panel, which includes a first substrate and a second substrate arranged opposite to each other, wherein the first substrate includes a base substrate and a semiconductor layer and a light-shielding layer stacked on the base substrate; the second substrate includes a black matrix; the semiconductor layer includes a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion includes a first channel region, the second branch portion includes a second channel region, and a first via structure is provided on the side of the first branch portion away from the base substrate, and the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the end of the first branch portion away from the connecting portion on the base substrate; the orthographic projection of the light-shielding layer on the base substrate is located within the orthographic projection of the black matrix on the base substrate, and at least covers the orthographic projection of the first channel region and the first via structure on the base substrate.

[0016] For example, in the display panel provided in at least one embodiment of the present disclosure, the end of the second branch portion away from the connecting portion corresponds to a second via structure, and the second via structure is farther away from the connecting portion than the first via structure.

[0017] For example, in the display panel provided in at least one embodiment of the present disclosure, the material of the light-shielding layer includes a conductive metal, the orthographic projection of the black matrix on the base substrate covers the orthographic projection of the second via structure on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the light-shielding layer on the base substrate.

[0018] For example, in the display panel provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the first substrate, the portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and the portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure.

[0019] For example, in the display panel provided in at least one embodiment of the present disclosure, the first branch portion and the second branch portion both extend along a first direction, the connecting portion extends along a second direction intersecting the first direction, the first branch portion, the second branch portion and the connecting portion are arranged to form an opening area, and the light-shielding layer covers at least part of the opening area.

[0020] For example, in the display panel provided by at least one embodiment of the present disclosure, the first substrate further includes a first metal layer arranged on a side of the semiconductor layer away from the base substrate, the first metal layer includes a gate line extending in the second direction, the gate line includes a first gate and a second gate, the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel region on the base substrate.

[0021] For example, in the display panel provided in at least one embodiment of the present disclosure, the orthographic projection of the first gate on the base substrate is within the orthographic projection of the black matrix on the base substrate, and the orthographic projection of the second gate on the base substrate is within the orthographic projection of the black matrix on the base substrate.

[0022] For example, in the display panel provided in at least one embodiment of the present disclosure, a gap is provided between the light shielding layer and the connecting portion in the first direction.

[0023] For example, in the display panel provided in at least one embodiment of the present disclosure, the orthographic projection of the edge of the portion of the light-shielding layer corresponding to the first branch portion close to the connecting portion on the base substrate overlaps with the orthographic projection of the edge of the portion of the black matrix corresponding to the first branch portion close to the connecting portion on the base substrate.

[0024] For example, in the display panel provided in at least one embodiment of the present disclosure, the orthographic projection of the edge of the portion of the light-shielding layer corresponding to the first branch portion farthest from the connecting portion on the base substrate and the orthographic projection of the edge of the portion of the black matrix corresponding to the first branch portion farthest from the connecting portion on the base substrate overlap.

[0025] For example, in the display panel provided in at least one embodiment of the present disclosure, the orthographic projection of the edge of the light-shielding layer away from the connecting portion on the base substrate includes a first part located on the side of the first via structure away from the connecting portion and a second part located on the side of the second via structure away from the connecting portion, and the orthographic projection of the second part on the base substrate is located within the orthographic projection of the edge of the black matrix farthest from the second via structure on the base substrate.

[0026] For example, in the display panel provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the first substrate, the portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, the portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are respectively the first sub-light-shielding portion and the second sub-light-shielding portion, and the first sub-light-shielding portion and the second sub-light-shielding portion are spaced apart from each other.

[0027] For example, in the display panel provided in at least one embodiment of the present disclosure, the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light-shielding portion on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the second sub-light-shielding portion on the base substrate.

[0028] For example, in the display panel provided in at least one embodiment of the present disclosure, the end of the second branch portion away from the connecting portion corresponds to a second via structure, and the maximum distance between the second via structure and the connecting portion is equal to the maximum distance between the first via structure and the connecting portion.

[0029] For example, in the display panel provided in at least one embodiment of the present disclosure, the material of the light-shielding layer includes a non-conductive light-shielding material, and the orthographic projection of the black matrix on the base substrate and the orthographic projection of the light-shielding layer on the base substrate both cover the orthographic projection of the second via structure on the base substrate.

[0030] For example, in the display panel provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure or a structure spaced apart from each other.

[0031] At least one embodiment of the present disclosure further provides a display device, which includes the array substrate described in any of the above embodiments, or the display panel described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0033] FIG1 is a schematic diagram of a planar structure of a thin film transistor;

[0034] FIG2 is a schematic diagram of a cross-sectional structure of an array substrate;

[0035] FIG3 is a schematic diagram of a cross-sectional structure of the thin film transistor in FIG1 ;

[0036] FIG4 is a schematic planar structural diagram of an array substrate and a black matrix provided by at least one embodiment of the present disclosure;

[0037] FIG5 is a schematic diagram of a stacked structure of an array substrate provided by at least one embodiment of the present disclosure;

[0038] FIG6 is a schematic diagram of a stacked structure of another array substrate provided by at least one embodiment of the present disclosure;

[0039] FIG7 is a schematic diagram of a stacked structure of another array substrate provided by at least one embodiment of the present disclosure;

[0040] FIG8 is a schematic diagram of the cross-sectional structure of the array substrate in FIG7 ;

[0041] FIG9 is a schematic diagram of a planar structure of another array substrate provided by at least one embodiment of the present disclosure;

[0042] FIG10 is a schematic diagram of the cross-sectional structure of the array substrate shown in FIG9 ;

[0043] FIG11 is a schematic diagram of a planar structure of another array substrate provided by at least one embodiment of the present disclosure;

[0044] FIG12 is a schematic diagram of the cross-sectional structure of the array substrate shown in FIG11 ;

[0045] FIG13 is a schematic diagram of a planar structure of another array substrate provided by at least one embodiment of the present disclosure;

[0046] FIG14 is a schematic diagram of the cross-sectional structure of the array substrate shown in FIG13;

[0047] FIG15 is a schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure;

[0048] FIG16 is a schematic diagram of a stacked structure of another array substrate provided by at least one embodiment of the present disclosure;

[0049] FIG17 is a schematic diagram of a stacked structure of another array substrate provided by at least one embodiment of the present disclosure;

[0050] FIG18 is a schematic diagram of a cross-sectional structure of a display panel provided by at least one embodiment of the present disclosure;

[0051] FIG19 is a schematic diagram of a planar structure of a display panel provided by at least one embodiment of the present disclosure;

[0052] FIG20 is a schematic cross-sectional view of a first substrate provided in at least one embodiment of the present disclosure;

[0053] FIG21 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure;

[0054] FIG22 is a schematic diagram of the cross-sectional structure of the first substrate in FIG21;

[0055] FIG23 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure;

[0056] FIG24 is a schematic diagram of the cross-sectional structure of the first substrate in FIG23;

[0057] FIG25 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure;

[0058] FIG26 is a schematic diagram of the cross-sectional structure of the first substrate in FIG25 ;

[0059] FIG27 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure;

[0060] FIG28 is a schematic diagram of the cross-sectional structure of the first substrate in FIG27;

[0061] FIG29 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure;

[0062] FIG30 is a schematic diagram of the cross-sectional structure of the first substrate shown in FIG29;

[0063] FIG31 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure;

[0064] FIG32 is a schematic diagram of the cross-sectional structure of the first substrate shown in FIG31;

[0065] FIG33 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure;

[0066] FIG34 is a schematic diagram of a stacked structure of another display panel provided by at least one embodiment of the present disclosure;

[0067] FIG35 is a block diagram of a display panel provided by at least one embodiment of the present disclosure; and

[0068] FIG36 is a block diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0069] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0070] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0071] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present invention include the situations of "parallel", "perpendicular", "same" in a strict sense, as well as the situations of "approximately parallel", "approximately perpendicular", "approximately the same" and the like that contain a certain error. For example, the above-mentioned "approximately" may mean that the difference between the compared objects is 10% of the average value of the compared objects, or within 5%. When the number of a component or element is not specifically indicated below in the embodiments of the present invention, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer setting" in the embodiments of the present invention refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0072] Currently, mobile devices such as mobile phones, tablet computers, and laptops have increasingly higher requirements for low power consumption. Reducing the refresh rate of display panels has become a major method to reduce the power consumption of display panels. When the display panel has a low refresh rate, the retention time of the pixel capacitor is prolonged. When the leakage current of the thin film transistor (abbreviated as I off ) is large, the retention capacity of the pixel capacitor decreases, and the voltage difference between the pixel electrode and the common electrode decreases, which will cause the brightness of the display panel to decay, and then lead to the aggravation of the pixel flicker problem. At the same time, the optical effects such as afterimage will also deteriorate due to the aggravation of the leakage current problem.

[0073] For example, Figure 1 is a schematic diagram of a planar structure of a thin film transistor, and Figure 2 is a schematic diagram of a cross-sectional structure of an array substrate. In combination with Figures 1 and 2, an interlayer insulating layer 13 is provided between the pixel electrode 11 and the first source and drain electrode 12 of the thin film transistor, and a first via structure 14 is provided in the interlayer insulating layer 13. In order to prevent the first via structure 14 from leaking light, a black matrix 15 (not shown in Figure 2) needs to be set to block the first via structure 14. In this way, in the first direction X, in the right part of the black matrix 15 corresponding to the first via structure 14, the length L1 of the black matrix 15 blocking the upper side of the channel region 16 (the upper side of the gate line 17 coverage area) is greater than the length L2 of the black matrix 15 blocking the lower side of the channel region 16 (the lower side of the gate line 17 coverage area). Therefore, the blocking range of the black matrix 15 on both sides of the channel region 16 in the first direction X is inconsistent, and the black matrix 15 blocks the upper part of the channel region 16 more than the lower part of the channel region 16. Backlight is incident from the side where the low-temperature polysilicon thin film transistor is located. Under certain lighting conditions, photogenerated carriers will be excited in the channel region 16, resulting in a leakage current (I off ) increases, that is, the light intensity and the leakage current Ioff is positively correlated. A light shielding layer 18 is provided on the side of the channel region 16 close to the base substrate 10. The light shielding layer 18 can reduce the light received by the channel region 16, thereby reducing the leakage current under light conditions. A first insulating layer 22 is provided between the light shielding layer 18 and the channel region 16, and a passivation layer 23 is provided between the first insulating layer 22 and the first source-drain electrode 12. The second source-drain electrode 21 and the first source-drain electrode 12 are arranged relative to each other, and a gate and a gate insulating layer 20 are formed in the gap between the second source-drain electrode 21 and the first source-drain electrode 12. The display panel displays by line scanning. The pixel is charged for only a few microseconds in one frame, and the rest of the time is in the voltage holding stage. Under ideal conditions, the pixel voltage always maintains the set voltage, but due to the presence of leakage current in the thin film transistor, there will be voltage attenuation in the voltage holding stage. The degree of voltage attenuation is related to the leakage current I of the thin film transistor. off And the voltage holding time is positively correlated, and the formula for leakage current voltage drop is △V=I off *T hold / Cst. When the display panel is performing low-frequency display, the frame time is lengthened (when the refresh rate is 60Hz, the frame time is 16.7ms; when the refresh rate is 15Hz, the frame time is 66.7ms), the pixel voltage holding time is lengthened, and under the premise that the leakage current speed remains the same, the voltage attenuation caused by the leakage current at low refresh frequency will increase, and the pixel brightness attenuation will also increase, thereby aggravating the flicker problem.

[0074] For example, FIG3 is a schematic diagram of the cross-sectional structure of the thin film transistor in FIG1 . As shown in FIG3 , two spaced-apart light-shielding layers 18 respectively shield the two channel regions 16 , each light-shielding layer 18 shields the entire corresponding channel region 16 , and the two adjacent light-shielding layers 18 are symmetrically designed. For example, as shown in FIG1 , in one example, in the first direction X, the shielding length L3 of the light-shielding layer 18 on the upper side of the gate line 17 is 2.05 microns, and the shielding length L4 on the lower side of the gate line 17 is also 2.05 microns. In this way, a portion of the light-shielding layer 18 on the lower side of the gate line 17 has exceeded the shielding range of the black matrix 15 and entered the opening area, which will cause the aperture ratio of the pixels of the display panel formed subsequently to be reduced. For example, compared with the case where the light-shielding layer 18 does not enter the opening area, the aperture ratio of the pixel will decrease by 0.8%. The light shielding layer 18 also shields the two gate electrodes of the dual-gate thin film transistor separately, so that the light shielding layer 18 does not shield the space between the two channel regions 16. For each channel region 16, the distance L5 of the space outside the channel region 16 shielded by the light shielding layer 18 in the second direction Y perpendicular to the first direction X is small. For example, in one example, the distance L5 is only 1.5 microns. The length L3 of the space above the gate line 17 shielded by the light shielding layer 18 in the first direction X is 2.05 microns. The length L3 is also small, resulting in a leakage current (I off ) is large, which has a greater impact on light effects such as flickering at low refresh rates.

[0075] It should be noted that, in the cross-sectional structure shown in FIG. 3 , the third direction Z is perpendicular to the plane where the first direction X and the second direction Y are located, that is, the third direction Z is a direction perpendicular to the main surface of the base substrate 10 .

[0076] The inventors of the present disclosure noticed that the channel regions corresponding to the two gates of the thin film transistor can be blocked by a whole light-shielding layer or a light-shielding layer with a larger area and spaced apart, and the blocking area of ​​the light-shielding layer on the side of the first source and drain electrode connected to the pixel electrode can be increased, that is, the first via structure in the above-mentioned interlayer insulating layer is blocked by a light-shielding layer, which can reduce the leakage current phenomenon of the display panel formed subsequently.

[0077] At least one embodiment of the present disclosure provides an array substrate, which includes a base substrate and a semiconductor layer and a light-shielding layer stacked on the base substrate, the semiconductor layer including a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion including a first channel region, the second branch portion including a second channel region, a first via structure being provided on a side of the first branch portion away from the base substrate, and the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the end of the first branch portion away from the connecting portion on the base substrate; the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projection of the first channel region and the first via structure on the base substrate, and the array substrate can reduce the leakage current of a subsequently formed display panel by adjusting the design of the light-shielding layer to enhance the retention capability of the pixel capacitance, thereby improving the problem of flickering at low frequency, and also ensuring the aperture ratio of the subsequently formed display panel.

[0078] For example, FIG4 is a schematic diagram of a planar structure of an array substrate and a black matrix provided in at least one embodiment of the present disclosure. As shown in FIG4, the array substrate 21 includes a base substrate 211 and a semiconductor layer 212 and a light shielding layer 213 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122. The first branch portion 2121 includes a first channel region 2124, and the second branch portion 2122 includes a second channel region 2125. On the side of the first branch portion 2121 away from the base substrate 211, It has a first via structure 2126, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211; the orthographic projection of the light-shielding layer 213 on the base substrate 211 at least covers the first channel region 2124 and the orthographic projection of the first via structure 2126 on the base substrate 211. By adjusting the design of the light-shielding layer 213, the array substrate 21 can reduce the leakage current of the subsequently formed display panel to enhance the retention capacity of the pixel capacitance, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the subsequently formed display panel.

[0079] It should be noted that the semiconductor layer is in a state during the process of manufacturing the array substrate. There are other subsequent processes to conduct part of the semiconductor area, that is, after forming the gate and gate line mentioned later, there is a heavy doping step to turn the part of the semiconductor layer outside the area covered by the gate into a conductor, so that the gate can block the channel area. Therefore, the channel area corresponding to the semiconductor layer is located below the gate line, and the conductorized part corresponds to the first source-drain electrode and the second source-drain electrode.

[0080] For example, as shown in FIG4 , two channel regions, a first channel region 2124 and a second channel region 2125, are shown in the array substrate 21. The end portion (first source-drain electrode) of the first branch portion 2121 corresponding to the first via structure 2126 is electrically connected to the pixel electrode 222 through the first via structure 2126. The end portion (second source-drain electrode) of the second branch portion 2122 is connected to the data line 221. The data line 221 intersects with the gate line 2128 to define a pixel region, in which the pixel electrode 222 is disposed.

[0081] It should be noted that in order to reflect the positional relationship between the light-shielding layer and semiconductor layer on the array substrate and the black matrix, a black matrix 223 is also shown in Figure 4. The orthographic projection of the black matrix 223 on the base substrate 211 covers the orthographic projection of the data line 221, the gate line 2128, the light-shielding layer 213, the first branch portion 2121, the second branch portion 2122 and the lower right corner of the connecting portion 2123 on the base substrate 211, but the black matrix 223 is not mentioned when describing the array substrate.

[0082] For example, as shown in Figure 4, the array substrate 21 also includes a touch signal line 224, which includes a first part 224a and a second part 224b arranged parallel to the data line 221, and the orthographic projection of the black matrix 223 on the base substrate 211 also covers the orthographic projection of the touch signal line 224 on the base substrate 211.

[0083] For example, FIG5 is a schematic diagram of a stacked structure of an array substrate provided by at least one embodiment of the present disclosure. As shown in FIG5 , the array substrate 21 includes a base substrate 211 and a semiconductor layer 212 and a light shielding layer 213 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122. The first branch portion 2121 includes a first channel region 2124, and the second branch portion 2122 includes a second channel region 2125. A first via structure 2126 is provided on a side of the first branch portion 2121 away from the base substrate 211, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211. The light shielding layer 213 The orthographic projection on the base substrate 211 at least covers the orthographic projection of the first channel region 2124 and the first via structure 2126 on the base substrate 211. The array substrate 21 can reduce the leakage current of the subsequently formed display panel by adjusting the design of the light-shielding layer 213 to enhance the retention capability of the pixel capacitance, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the subsequently formed display panel.

[0084] For example, as shown in FIG5 , a second via structure 2127 is provided on a side of the second branch portion 2122 away from the base substrate 211, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the end of the second branch portion 2122 away from the connecting portion 2123 on the base substrate 211. The minimum distance between the second via structure 2127 and the connecting portion 2123 is greater than the minimum distance between the first via structure 2126 and the connecting portion 2123, that is, the second via structure 2127 is further away from the connecting portion 2123 than the first via structure 2126. In other examples, the minimum distance between the second via structure 2127 and the connecting portion 2123 may be equal to the minimum distance between the first via structure 2126 and the connecting portion 2123.

[0085] For example, as shown in FIG. 5 , the orthographic projection of the second via structure 2127 on the base substrate 211 is outside the orthographic projection of the light shielding layer 213 on the base substrate 211 , that is, the light shielding layer 213 does not cover the second via structure 2127 .

[0086] For example, in one example, a plurality of thin film transistors are arranged on the base substrate 211, and the portions of the light-shielding layer 213 corresponding to different thin film transistors are spaced apart from each other, and the portions of the light-shielding layer 213 corresponding to the first channel region 2124 and the second channel region 2125 of the same thin film transistor are an integral structure, that is, in addition to covering the first channel region 2124 and the second channel region 2125, the light-shielding layer 213 also covers the portion between the first channel region 2124 and the second channel region 2125.

[0087] For example, as shown in Figure 5, the first branch portion 2121 and the second branch portion 2122 both extend along the first direction X, and the connecting portion 2123 extends along the second direction Y that intersects the first direction X. The first branch portion 2121, the second branch portion 2122 and the connecting portion 2123 are arranged to form an opening area, and the shading layer 213 covers at least part of the opening area.

[0088] For example, in one example, the first direction X and the second direction Y are perpendicular.

[0089] For example, as shown in Figure 5, the array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211, and the first metal layer 214 includes a gate line 2128 extending in the second direction Y, and the orthographic projection of the gate line 2128 on the base substrate 211 and the orthographic projection of the first channel region 2124 on the base substrate 211 and the orthographic projection of the second channel region 2125 on the base substrate 211 all overlap.

[0090] For example, as shown in FIG. 5 , there is a gap between the light shielding layer 213 and the connecting portion 2123 in the first direction X, that is, the lower edge of the light shielding layer 213 is located above the upper edge of the connecting portion 2123 .

[0091] For example, FIG6 is a schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure. In one example, a plurality of thin film transistors are provided on the base substrate 211. The portions of the light shielding layer 213 corresponding to different thin film transistors are spaced apart from each other. The portions of the light shielding layer 213 corresponding to the first channel region 2124 and the second channel region 2125 of the same thin film transistor are respectively the first sub-light shielding portion 213a and the second sub-light shielding portion 213b. The first sub-light shielding portion 213a and the second sub-light shielding portion 213b are spaced apart from each other. As can be seen from FIG6, the distance between the edge of the second sub-light shielding portion 213b farthest from the connection portion 2123 and the connection portion 2123 is greater than the distance between the edge of the first sub-light shielding portion 213a farthest from the connection portion 2123 and the connection portion 2123.

[0092] For example, as shown in Figure 6, the end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, and the second via structure 2127 is farther away from the connecting portion 2123 than the first via structure 2126. That is, in the plan view shown in Figure 6, the first branch portion 2121 and the second branch portion 2122 are both long strips and extend in the first direction X. Moreover, the length of the second branch portion 2122 in the first direction X is greater than the length of the first branch portion 2121 in the first direction X. That is, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is greater than the distance between the first via structure 2126 and the connecting portion 2123, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2126 corresponding to the end of the first branch portion 2121 are not flush.

[0093] For example, as shown in FIG6 , the first sub-light-shielding portion 213a covers the orthographic projections of the first channel region 2124 and the first via structure 2126 on the base substrate 211, and the second sub-light-shielding portion 213b covers the orthographic projection of the second channel region 2125 on the base substrate 211, but does not cover the orthographic projection of the second via structure 2127 on the base substrate 211. By designing the first sub-light-shielding portion 213a to cover the orthographic projections of the first channel region 2124 and the first via structure 2126 on the base substrate 211, and designing the second sub-light-shielding portion 213b to cover the orthographic projection of the second channel region 2125 on the base substrate 211, the array substrate 21 can reduce leakage current, improve the pixel capacitance retention capability, thereby improving the flicker problem at low frequencies, and also ensure the aperture ratio of the subsequently formed display panel.

[0094] For example, as shown in Figure 6, the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the first sub-light-shielding portion 213a on the base substrate 211, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located outside the orthographic projection of the second sub-light-shielding portion 213b on the base substrate 211.

[0095] For example, Figure 7 is a schematic diagram of the stacked structure of another array substrate provided in at least one embodiment of the present disclosure, and Figure 8 is a schematic diagram of the cross-sectional structure of the array substrate in Figure 7. For example, combining Figures 7 and 8, the array substrate 21 includes a base substrate 211 and a light-shielding layer 213 and a semiconductor layer 212 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 that are arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122. The first branch portion 2121 includes a first channel region 2124, and the second branch portion 2122 includes a second channel region 2125. The end of the first branch portion 2121 away from the connecting portion 2123 corresponds to the first via structure 2126, that is, the side of the first branch portion 2121 away from the base substrate 211 has the first via structure 2126, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211. The end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, that is, the side of the second branch portion 2122 away from the base substrate 211 has the second via structure 2127, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the end of the second branch portion 2122 away from the connecting portion 2123 on the base substrate 211. The orthographic projection of the light-shielding layer 213 on the base substrate 211 covers the orthographic projections of the first channel region 2124, the second channel region 2125, the first via structure 2126 and the second via structure 2127 on the base substrate 211. By setting the light-shielding layer 213 to cover the entire area of ​​the first channel region 2124, the second channel region 2125, the first via structure 2126 and the second via structure 2127, the array substrate 21 can reduce leakage current and improve the retention capacity of the pixel capacitance, thereby improving the problem of flickering at low frequency and ensuring the aperture ratio of the display panel formed subsequently.

[0096] For example, in combination with Figure 7, in the first direction X, the second via structure 2127 is farther away from the connecting portion 2123 relative to the first via structure 2126, that is, in the plan view shown in Figure 7, the first branch portion 2121 and the second branch portion 2122 are both long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is greater than the length of the first branch portion 2121 in the first direction X, that is, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is greater than the distance between the first via structure 2126 and the connecting portion 2123, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2126 corresponding to the end of the first branch portion 2121 are not flush.

[0097] For example, in combination with Figures 7 and 8, the array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211, the first metal layer 214 includes a gate line 2128 extending in the second direction Y, the gate line 2128 is in a long strip shape, the gate line 2128 includes a first gate 2128a and a second gate 2128b, the orthographic projection of the first gate 2128a on the base substrate 211 overlaps with the orthographic projection of the first channel region 2124 on the base substrate 211, and the orthographic projection of the second gate 2128b on the base substrate 211 overlaps with the orthographic projection of the second channel region 2125 on the base substrate 211.

[0098] For example, the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure, the first gate 2128a and the second gate 2128b are part of the gate line 2128, the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124, and the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.

[0099] For example, as shown in Figure 8, a first insulating layer 219 is provided between the light-shielding layer 213 and the semiconductor layer 212, a gate insulating layer 217 is provided between the first insulating layer 219 and the first metal layer 214, and an interlayer insulating layer 218 is provided on the side of the first metal layer 214 away from the base substrate 211.

[0100] For example, as shown in Figures 7 and 8, the orthographic projection of the edge of the light shielding layer 213 away from the connection portion 2123 on the base substrate 211 includes a first portion 213c located on the side of the first via structure 2124 away from the connection portion 2123 and a second portion 213d located on the side of the second via structure 2127 away from the connection portion 2123. The upper edge of the first portion 213c and the upper edge of the second portion 213d are not on the same straight line, that is, the planar shape of the light shielding layer 213 is stepped. In the first direction X, the distance between the first portion 213c and the connection portion 2123 is greater than the distance between the second portion 213d and the connection portion 2123. The orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the light shielding layer 213 on the base substrate 211. It should be noted that, in this example, the material of the light-shielding layer 213 is a non-conductive light-shielding material. When the material of the light-shielding layer 213 is a non-conductive light-shielding material, even if the interlayer insulating layer 218 is etched to over-etch the light-shielding layer 213, the problem of short circuit between the first source-drain electrode and the second source-drain electrode of the thin-film transistor will not occur.

[0101] For example, Figure 9 is a schematic diagram of the planar structure of another array substrate provided in at least one embodiment of the present disclosure, and Figure 10 is a schematic diagram of the cross-sectional structure of the array substrate shown in Figure 9. For example, combining Figures 9 and 10, the array substrate 21 includes a base substrate 211 and a light-shielding layer 213 and a semiconductor layer 212 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 that are arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122. The first branch portion 2121 includes a first channel region 2124, and the second branch portion 2122 includes a second channel region 2125. The end of the first branch portion 2121 away from the connecting portion 2123 corresponds to the first via structure 2126, that is, the side of the first branch portion 2121 away from the base substrate 211 has the first via structure 2126, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211. The end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, that is, the side of the second branch portion 2122 away from the base substrate 211 has the second via structure 2127, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the end of the second branch portion 2122 away from the connecting portion 2123 on the base substrate 211. The orthographic projection of the light-shielding layer 213 on the base substrate 211 covers the orthographic projections of the first channel region 2124, the second channel region 2125, the first via structure 2126 and the second via structure 2127 on the base substrate 211. By setting the light-shielding layer 213 to cover the entire area of ​​the first channel region 2124, the second channel region 2125, the first via structure 2126 and the second via structure 2127, the array substrate 21 can reduce leakage current and improve the retention capacity of the pixel capacitance, thereby improving the problem of flickering at low frequency and ensuring the aperture ratio of the display panel formed subsequently.

[0102] For example, in combination with Figure 9, the end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127. In the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is equal to the distance between the first via structure 2124 and the connecting portion 2123. That is, in the plan view shown in Figure 9, the first branch portion 2121 and the second branch portion 2122 are both long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is equal to the length of the first branch portion 2121 in the first direction X, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2124 corresponding to the end of the first branch portion 2121 are flush.

[0103] For example, in combination with Figures 9 and 10, the array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211, the first metal layer 214 includes a gate line 2128 extending in the second direction Y, the gate line 2128 is in a long strip shape, the gate line 2128 includes a first gate 2128a and a second gate 2128b, the orthographic projection of the first gate 2128a on the base substrate 211 overlaps with the orthographic projection of the first channel region 2124 on the base substrate 211, and the orthographic projection of the second gate 2128b on the base substrate 211 overlaps with the orthographic projection of the second channel region 2125 on the base substrate 211. For example, the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure, the first gate 2128a and the second gate 2128b are part of the gate line 2128, the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124, and the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.

[0104] For example, as shown in Figure 10, a first insulating layer 219 is provided between the light-shielding layer 213 and the semiconductor layer 212, a gate insulating layer 217 is provided between the first insulating layer 219 and the first metal layer 214, and an interlayer insulating layer 218 is provided on the side of the first metal layer 214 away from the base substrate 211.

[0105] For example, in combination with Figures 9 and 10, in one example, the material of the light-shielding layer 213 includes a non-conductive light-shielding material, and the orthographic projections of the first via structure 2126 and the second via structure 2127 on the base substrate 211 are both located within the orthographic projection of the light-shielding layer 213 on the base substrate 211.

[0106] For example, in combination with Figures 9 and 10, the light-shielding layer 213 is an integral structure, and the orthographic projection of the light-shielding layer 213 on the base substrate 211 covers the orthographic projection of the first channel region 2124 on the base substrate 211, the orthographic projection of the second channel region 2125 on the base substrate 211, the orthographic projection of the first via structure 2126 on the base substrate 211, and the orthographic projection of the second via structure 2127 on the base substrate 211, as well as covers the gap between the first channel region 2124 and the second channel region 2125, and covers the gap between the first via structure 2126 and the second via structure 2127.

[0107] For example, Figure 11 is a schematic diagram of the planar structure of another array substrate provided in at least one embodiment of the present disclosure, and Figure 12 is a schematic diagram of the cross-sectional structure of the array substrate shown in Figure 11. For example, combining Figures 11 and 12, the array substrate 21 includes a base substrate 211 and a light-shielding layer 213 and a semiconductor layer 212 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 that are arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122. The first branch portion 2121 includes a first channel region 2124, and the second branch portion 2122 includes a second channel region 2125. The end of the first branch portion 2121 away from the connecting portion 2123 corresponds to the first via structure 2126, that is, the side of the first branch portion 2121 away from the base substrate 211 has the first via structure 2126, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211. The portions of the light-shielding layer 213 corresponding to different thin-film transistors are spaced apart from each other. The portions of the light-shielding layer 213 corresponding to the first channel region 2124 and the second channel region 2125 of the same thin-film transistor are respectively a first sub-light-shielding portion 213a and a second sub-light-shielding portion 213b, and the first sub-light-shielding portion 213a and the second sub-light-shielding portion 213b are spaced apart from each other. The first sub-light-shielding portion 213a covers the orthographic projections of the first channel region 2124 and the first via structure 2126 on the base substrate 211, and the second sub-light-shielding portion 213b covers the orthographic projections of the second channel region 2125 and the second via structure 2127 on the base substrate 211. The array substrate 21 is designed such that the first sub-light-shielding portion 213a is designed such that the orthographic projection of the first sub-light-shielding portion 213a on the base substrate 211 covers the orthographic projection of the first channel region 2124 and the first via structure 2126 on the base substrate 211, and the second sub-light-shielding portion 213b is designed such that the orthographic projection of the second sub-light-shielding portion 213b on the base substrate 211 covers the orthographic projection of the second channel region 2125 and the second via structure 2127 on the base substrate 211. This design can reduce leakage current and enhance the retention capacity of pixel capacitance, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel subsequently formed.

[0108] For example, in combination with Figure 11, the end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, and the second via structure 2127 is farther away from the connecting portion 2123 than the first via structure 2126, that is, in the plan view shown in Figure 11, the first branch portion 2121 and the second branch portion 2122 are both long strips and extend in the first direction X. The length of the second branch portion 2122 in the first direction X is equal to the length of the first branch portion 2121 in the first direction X, that is, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is equal to the distance between the first via structure 2126 and the connecting portion 2123, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2126 corresponding to the end of the first branch portion 2121 are flush.

[0109] For example, in combination with Figures 11 and 12, the array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211, the first metal layer 214 includes a gate line 2128 extending in the second direction Y, the gate line 2128 is in a long strip shape, the gate line 2128 includes a first gate 2128a and a second gate 2128b, the orthographic projection of the first gate 2128a on the base substrate 211 overlaps with the orthographic projection of the first channel region 2124 on the base substrate 211, and the orthographic projection of the second gate 2128b on the base substrate 211 overlaps with the orthographic projection of the second channel region 2125 on the base substrate 211.

[0110] For example, the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure, the first gate 2128a and the second gate 2128b are part of the gate line 2128, the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124, and the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.

[0111] For example, as shown in Figure 12, a first insulating layer 219 is provided between the light-shielding layer 213 and the semiconductor layer 212, a gate insulating layer 217 is provided between the first insulating layer 219 and the first metal layer 214, and an interlayer insulating layer 218 is provided on the side of the first metal layer 214 away from the base substrate 211.

[0112] For example, as shown in Figures 11 and 12 , the orthographic projection of the edge of the first sub-light-shielding portion 213a, distal to the connection portion 2123, on the substrate 211 includes a first portion 213c located on the side of the first via structure 2126 distal to the connection portion 2123. The orthographic projection of the edge of the second sub-light-shielding portion 213b, distal to the connection portion 2123, on the substrate 211 includes a second portion 213d located on the side of the second via structure 2127 distal to the connection portion 2123. In other words, both the first sub-light-shielding portion 213a and the second sub-light-shielding portion 213b have a long strip shape in plan view, and the length of the first sub-light-shielding portion 213a is equal to the length of the second sub-light-shielding portion 213b. In the first direction X, the distance between the first portion 213c and the connection portion 2123 is equal to the distance between the second portion 213d and the connection portion 2123. The orthographic projection of the second via structure 2127 on the substrate 211 is located within the orthographic projection of the light-shielding layer 213 on the substrate 211. It should be noted that in this example, the material of the light-shielding layer 213 is a non-conductive light-shielding material. Even if the interlayer insulating layer 218 is etched to over-etch the light-shielding layer 213, the first source-drain electrode and the second source-drain electrode of the thin film transistor will not be short-circuited.

[0113] For example, a plurality of thin film transistors are provided on the array substrate 21, and the portions of the light-shielding layer 213 corresponding to different thin film transistors are spaced apart from each other. In combination with Figures 11 and 12, the portions of the light-shielding layer 213 corresponding to the first channel region 2124 and the second channel region 2125 of the same thin film transistor are respectively the first sub-light-shielding portion 213a and the second sub-light-shielding portion 213b, and the first sub-light-shielding portion 213a and the second sub-light-shielding portion 213b are spaced apart from each other, and the orthographic projection of the first channel region 2124 on the base substrate 211 is completely located within the orthographic projection of the first sub-light-shielding portion 213a on the base substrate 211, and the orthographic projection of the second channel region 2125 on the base substrate 211 is completely located within the orthographic projection of the second sub-light-shielding portion 213b on the base substrate 211. The orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the first sub-light-shielding portion 213a on the base substrate 211, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the second sub-light-shielding portion 213b on the base substrate 211.

[0114] For example, Figure 13 is a schematic diagram of the planar structure of another array substrate provided in at least one embodiment of the present disclosure, and Figure 14 is a schematic diagram of the cross-sectional structure of the array substrate shown in Figure 13. As shown in Figure 13, the array substrate 21 includes a base substrate 211 and a light-shielding layer 213 and a semiconductor layer 212 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 that are arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122. The first branch portion 2121 includes a first channel region 2124, and the second branch portion 2122 includes a second channel region 2125. The end of the first branch portion 2121 away from the connecting portion 2123 corresponds to the first via structure 2126, that is, the side of the first branch portion 2121 away from the base substrate 211 has the first via structure 2126, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211. The end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127. That is, the second via structure 2127 is provided on the side of the second branch portion 2122 away from the base substrate 211, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the end of the second branch portion 2122 away from the connecting portion 2123 on the base substrate 211. The orthographic projection of the light shielding layer 213 on the base substrate 211 covers the orthographic projections of the first channel region 2124, the second channel region 2125, and the first via structure 2126 on the base substrate 311. By providing the light shielding layer 213 to cover the entire area of ​​the first channel region 2124, the second channel region 2125, and the first via structure 2126, the array substrate 21 can reduce leakage current and improve the pixel capacitance retention capability, thereby improving flicker at low frequencies and ensuring the aperture ratio of the subsequently formed display panel.

[0115] For example, as shown in Figure 13, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is equal to the distance between the first via structure 2124 and the connecting portion 2123, that is, in the plan view shown in Figure 13, the first branch portion 2121 and the second branch portion 2122 are both long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is equal to the length of the first branch portion 2121 in the first direction X, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2124 corresponding to the end of the first branch portion 2121 are flush.

[0116] For example, as shown in Figure 13, the array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211. The first metal layer 214 includes a gate line 2128 extending in the second direction Y. The gate line 2128 is in a long strip shape. The gate line 2128 includes a first gate 2128a and a second gate 2128b. The orthographic projection of the first gate 2128a on the base substrate 211 overlaps with the orthographic projection of the first channel region 2124 on the base substrate 211, and the orthographic projection of the second gate 2128b on the base substrate 211 overlaps with the orthographic projection of the second channel region 2125 on the base substrate 211.

[0117] For example, the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure, the first gate 2128a and the second gate 2128b are part of the gate line 2128, the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124, and the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.

[0118] For example, as shown in Figure 14, a first insulating layer 219 is provided between the light-shielding layer 213 and the semiconductor layer 212, a gate insulating layer 217 is provided between the first insulating layer 219 and the first metal layer 214, and an interlayer insulating layer 218 is provided on the side of the first metal layer 214 away from the base substrate 211.

[0119] For example, in combination with Figures 13 and 14, in one example, the material of the light-shielding layer 213 includes a non-conductive light-shielding material or a conductive light-shielding material, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the light-shielding layer 213 on the base substrate 211.

[0120] For example, in combination with Figures 13 and 14, the light-shielding layer 213 is an integral structure, and the orthographic projection of the light-shielding layer 213 on the base substrate 211 covers the orthographic projection of the first channel region 2124 on the base substrate 211, the orthographic projection of the second channel region 2125 on the base substrate 211, and the orthographic projection of the first via structure 2126 on the base substrate 211, as well as covers the gap between the first channel region 2124 and the second channel region 2125. The planar shape of the light-shielding layer 213 is stepped.

[0121] For example, Figure 15 is a schematic diagram of the stacked structure of another array substrate provided by at least one embodiment of the present disclosure. In one example, a plurality of thin film transistors are arranged on the base substrate 211, and the portions of the light-shielding layer 213 corresponding to different thin film transistors are spaced apart from each other, and the light-shielding layer 213 only corresponds to the first channel region 2124 of the same thin film transistor, that is, the orthographic projection of the light-shielding layer 213 on the base substrate 211 only covers the orthographic projection of the first channel region 2124 on the base substrate 211, and does not cover the orthographic projection of the second channel region 2125 on the base substrate 211.

[0122] For example, as shown in Figure 15, the end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, and the second via structure 2127 is farther away from the connecting portion 2123 than the first via structure 2126. That is, in the plan view shown in Figure 15, the first branch portion 2121 and the second branch portion 2122 are both long strips and extend in the first direction X. Moreover, the length of the second branch portion 2122 in the first direction X is greater than the length of the first branch portion 2121 in the first direction X. That is, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is greater than the distance between the first via structure 2126 and the connecting portion 2123, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2126 corresponding to the end of the first branch portion 2121 are not flush.

[0123] For example, as shown in FIG15 , the array substrate 21 can reduce leakage current and enhance the pixel capacitance retention capability by designing the light-shielding layer 213 to cover the positive projection of the first channel region 2124 and the first via structure 2126 on the base substrate 211, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel subsequently formed.

[0124] For example, FIG16 is a schematic diagram of the stacked structure of another array substrate provided in at least one embodiment of the present disclosure. The array substrate shown in FIG16 differs from the array substrate shown in FIG5 only in that a touch signal line 220 extending along a first direction X is provided between a first branch portion 2121 and a second branch portion 2122. This design saves space for wiring placement and makes the array substrate thinner and lighter. The structure of the array substrate shown in FIG16 can be found in the description of the array substrate shown in FIG5 and will not be repeated here.

[0125] For example, FIG17 is a schematic diagram of the stacked structure of another array substrate provided in at least one embodiment of the present disclosure. The array substrate shown in FIG17 differs from the array substrate shown in FIG11 only in that a touch signal line 220 extending along a first direction X is provided between a first branch portion 2121 and a second branch portion 2122. This design saves space for wiring placement, making the array substrate thinner and lighter. The structure of the array substrate shown in FIG17 can be found in the description of the array substrate shown in FIG11 and will not be repeated here.

[0126] For example, for a display panel, a black matrix can be provided on an opposing substrate arranged opposite to the array substrate, and the length of the light-shielding layer that blocks the spacing area on the lower side of the gate line in the first direction X can be reduced, so that the edges of the light-shielding layer are all shrunk into the area covered by the black matrix, which can further improve the aperture ratio of the display panel.

[0127] At least one embodiment of the present disclosure provides a display panel comprising a first substrate and a second substrate disposed oppositely, wherein the first substrate comprises a base substrate and a semiconductor layer and a light shielding layer stacked on the base substrate; the second substrate comprises a black matrix; the semiconductor layer comprises a first branch portion and a second branch portion disposed oppositely, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion comprising a first channel region, the second branch portion comprising a second channel region, a first via structure being provided on a side of the first branch portion away from the base substrate, and an orthographic projection of the first via structure on the base substrate being located within an orthographic projection of an end of the first branch portion away from the connecting portion on the base substrate; and an orthographic projection of the light shielding layer on the base substrate being located within an orthographic projection of the black matrix on the base substrate and covering at least the first channel region and the orthographic projection of the first via structure on the base substrate. By adjusting the design of the light shielding layer, the display panel can reduce leakage current of a subsequently formed display panel, thereby improving the pixel capacitance retention capability, thereby improving flicker at low frequencies, and ensuring the aperture ratio of the subsequently formed display panel. Furthermore, the edges of the light shielding layer are retracted to within the area covered by the black matrix, thereby further improving the aperture ratio of the display panel.

[0128] For example, Figure 18 is a schematic diagram of the cross-sectional structure of a display panel provided by at least one embodiment of the present disclosure, Figure 19 is a schematic diagram of the planar structure of a display panel provided by at least one embodiment of the present disclosure, and Figure 20 is a schematic diagram of the cross-sectional structure of a first substrate provided by at least one embodiment of the present disclosure. As shown in Figures 18, 19 and 20, the display panel 30 includes a first substrate 31 and a second substrate 32 arranged relatively to each other, and the first substrate 31 includes a base substrate 311 and a light-shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122. The first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a. The end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first branch portion 3121 has the first via structure 314 on the side away from the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311 is located at the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311. 11, the orthographic projection of the light-shielding layer 313 on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311, and at least covers the orthographic projections of the first channel region 3121a, the second channel region 3122a and the first via structure 314 on the base substrate 311. The display panel 30 sets the black matrix 321 to cover the entire area of ​​the light-shielding layer 313, and sets the light-shielding layer 313 to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a and the first via structure 314. This can reduce the leakage current phenomenon of the display panel formed subsequently, enhance the retention ability of the pixel capacitance, thereby improving the flicker problem at low frequency, and can also ensure the aperture ratio of the display panel.

[0129] It should be noted that the semiconductor layer is in a state during the process of manufacturing the display panel. There are other subsequent processes to conduct part of the semiconductor area. That is, after forming the gate and gate line mentioned later, there is a heavy doping step to turn the part of the semiconductor layer outside the area covered by the gate into a conductor, so that the gate can block the channel area. Therefore, the channel area corresponding to the semiconductor layer is located below the gate.

[0130] It should also be noted that, although the light shielding layer 313 covers the second channel region 3122a in the embodiment shown in FIG. 19 , in other examples, the light shielding layer 313 may not cover the second channel region 3122a.

[0131] For example, in one embodiment, the first substrate 31 is an array substrate, and the second substrate 32 is an opposing substrate disposed opposite the array substrate, such as a color filter substrate. Other structures on the color filter substrate can refer to conventional designs and are not described here in detail.

[0132] For example, in combination with Figure 19, the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and the second via structure 315 is farther away from the connecting portion 3123 than the first via structure 314, that is, in the plan view shown in Figure 19, the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is greater than the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the minimum distance between the second via structure 315 and the connecting portion 3123 is greater than the minimum distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are not flush.

[0133] For example, in combination with Figures 19 and 20, the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, and the first metal layer 316 includes a gate line 3161 extending in the second direction Y. The gate line 3161 is in a long strip shape, and the gate line 3161 includes a first gate 3161a and a second gate 3161b. The orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311.

[0134] For example, in conjunction with FIG19 and FIG20 , the orthographic projection of the first gate 3161a on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311, so that the black matrix 321 completely covers the first gate 3161a and the second gate 3161b. In addition, the black matrix 321 covers the entire gate line 3161.

[0135] It should be noted that in the embodiment shown in FIG19 , the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Moreover, although the data lines are not shown in FIG19 , in actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0136] For example, as shown in Figure 20, a first insulating layer 319 is provided between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is provided on the side of the first metal layer 316 away from the base substrate 311.

[0137] For example, in combination with Figures 19 and 20, in one example, the material of the light-shielding layer 313 includes a conductive metal with light-shielding properties, the orthographic projection of the black matrix 321 on the base substrate 311 and the orthographic projection of the light-shielding layer 313 on the base substrate 311 both cover the orthographic projection of the first via structure 314 on the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located outside the orthographic projection of the light-shielding layer 313 on the base substrate 311.

[0138] It should be noted that if the light-shielding layer 313 is used to block the second via structure 315, the black matrix 321 is needed to block the light-shielding layer 313 again. Taking into account the presence of alignment fluctuations in the process, when the light-shielding layer 313 is added here, the alignment fluctuations of the multi-layer structure will lead to the need to design a wider black matrix, thereby sacrificing the pixel aperture ratio of the subsequently formed display panel. Based on the yield of the display panel, there is a risk of over-etching the light-shielding layer 313 when etching the interlayer insulating layer 318. Moreover, when the material of the light-shielding layer 313 is a conductive metal with light-shielding properties, over-etching the interlayer insulating layer 318 will cause a short circuit between the first source-drain electrode and the second source-drain electrode of the thin-film transistor, thereby causing the thin-film transistor to lose its switching function.

[0139] It should also be noted that when the material of the light-shielding layer 313 is not a conductive material with light-shielding properties, that is, when the material of the light-shielding layer 313 is an insulating material with light-shielding properties, the light-shielding layer 313 can also cover the second via structure 315. In this way, even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, there will be no short circuit problem between the first source-drain electrode and the second source-drain electrode of the thin-film transistor.

[0140] For example, in one example of the present disclosure, in conjunction with FIG. 19 and FIG. 20 , the light shielding layer 313 covers the first via structure 314 to reduce the leakage current I of the thin film transistor. off The effect is quite significant. When the shielding area of ​​the light shielding layer 313 on the first channel region 3121a changes, the corresponding leakage current I off The data are as follows: Taking the conventional design as the benchmark (100%), the data obtained from the experimental item is compared with the data obtained from the conventional design. It can be concluded that when the shielding area of ​​the light shielding layer 313 to the first channel region 3121a is increased, the leakage current I off The improvement effect is obvious, but the adjustment of the blocking area of ​​the second channel region 3122a by the light-shielding layer 313 has little effect on the characteristics of the thin film transistor. Therefore, under the premise of not affecting the aperture ratio of the display panel formed subsequently, the blocking area of ​​the first channel region 3121a by the light-shielding layer 313 is increased as much as possible, and the light-shielding layer 313 blocks the first via structure 314, and reduces the blocking area of ​​the second channel region 3122a by the light-shielding layer 313, which can reduce the impact on the aperture ratio of the display panel formed subsequently.

[0141] For example, in one example of the present disclosure, in order to ensure that the first via structure 314 does not leak light, the black matrix 321 needs to completely block the first via structure 314, and make the distance between the first via structure 314 and the edge of the black matrix 321 adjacent to the first via structure 314 in the first direction X be 1.15 microns. Therefore, in order to ensure that the light-shielding layer 313 does not affect the aperture ratio of the display panel formed subsequently, in the first direction X, the upper edge of the right side portion of the light-shielding layer 313 corresponding to the first via structure is flush with the upper edge of the first via structure 314.

[0142] For example, as shown in FIG19 , in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 6.15 microns. The light shielding layer 313 completely blocks the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314. On the upper side of the gate line 3161, the light shielding layer 313 blocks a length of 6.15 microns from the first branch portion 3121. On the lower side of the gate line 3161 in the first direction X, the length of the portion of the black matrix 321 corresponding to the first branch portion 3121 is 1.4 microns. To ensure the aperture ratio of the subsequently formed display panel is not affected, the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 in the first direction X. The distance between the lower edge of the light shielding layer 313 corresponding to the first branch portion 3121 and the gate line 3161 is 1.4 microns. In the second direction Y, the light shielding layer 313 is longer, with the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 being 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 being 2.0 microns. Furthermore, the light shielding layer 313 is designed as a single piece, completely shielding the gap between the first branch portion 3121 and the second branch portion 3122, effectively shielding the portion above the gate line 3161. For example, when the display panel is designed based on the above numerical values, under the condition of 6500 nit illumination, the light transmittance is 34%; under the condition of 20000 nit illumination, the light transmittance is 31%.

[0143] For example, when the display panel is designed based on the numerical values ​​in the embodiments shown in Figures 19 and 20 above, 10 sets of experimental data on low-frequency flicker are obtained, which are: -35.82, -33.53, -36.55, -36.45, -35.78, -38.12, -36.21, -36.45, -35.72 and -37.41, so that the average flicker value can be obtained to be -36.204. Correspondingly, when the display panel is designed based on the numerical values ​​of the conventional design in Figure 1, 10 sets of experimental data on low-frequency flicker are obtained, which are: -28.12, -26.58, -26.09, -28.22, -27.35, -29.2, -27.63, -28.54, -27.86 and -29.51, so that the average flicker value can be obtained to be -27.91. It can be concluded from the above experimental data that by optimizing the design of the light shielding layer 313 , the flicker level of the display image of the display panel can be effectively improved to meet the control standards for the display panel.

[0144] For example, in another example, in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 5.5 microns. The light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314. On the upper side of the gate line 3161, the light shielding layer 313 shields the first branch portion 3121 by 5.5 microns. In the first direction X, on the lower side of the gate line 3161, the length of the portion of the black matrix 321 corresponding to the side of the first branch portion 3121 is 1.4 microns. To ensure the aperture ratio of the subsequently formed display panel is not affected, the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 in the first direction X. The distance between the lower edge of the light shielding layer 313 corresponding to the first branch portion 3121 and the gate line 3161 is 1.4 microns. In the second direction Y, the light shielding layer 313 is longer, with the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 being 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 being 2.0 microns. Furthermore, the light shielding layer 313 is designed as a single piece, completely shielding the gap between the first branch portion 3121 and the second branch portion 3122, effectively shielding the gap above the gate line 3161. For example, when the display panel is designed based on the above numerical values, under the condition of 6500 nit illumination, the light transmittance is 49%; under the condition of 20000 nit illumination, the light transmittance is 41%.

[0145] For example, in another embodiment, in the first direction X, the distance between the upper edge of the first via structure 314 and the gate line 3161 is 5 microns. The light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314. Above the gate line 3161, the light shielding layer 313 shields the first branch portion 3121 by 5 microns. Below the gate line 3161, in the first direction X, the length of the portion of the black matrix 321 corresponding to the first branch portion 3121 is 1.4 microns. To ensure that the aperture ratio of the display panel is not affected, in the first direction X, the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121, and the distance between the lower edge of the light shielding layer 313 and the gate line 3161 is 1.4 microns. In the second direction Y, the length of the light-shielding layer 313 is relatively long. The minimum distance between the right edge of the light-shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light-shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns. In addition, the light-shielding layer 313 is designed as a single block, completely blocking the gap between the first branch portion 3121 and the second branch portion 3122. In other words, the light-shielding layer 313 fully blocks the gap above the gate line 3161. For example, when designing a display panel based on the above numerical values, the light transmittance is 57% under 6500 nit illumination and 48% under 20,000 nit illumination.

[0146] For example, in another embodiment, in the first direction X, the distance between the upper edge of the first via structure 314 and the gate line 3161 is 4.5 microns. The light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314. Therefore, on the upper side of the gate line 3161, the length of the first branch portion 3121 blocked by the light shielding layer 313 is 4.5 microns. On the lower side of the gate line 3161 in the first direction X, the length of the portion of the black matrix 321 corresponding to the first branch portion 3121 is 1.4 microns. To ensure that the aperture ratio of the display panel is not affected, in the first direction X, the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the black matrix 321, and the distance between the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 and the gate line 3161 is 1.4 microns. In the second direction Y, the length of the light-shielding layer 313 is relatively long. The minimum distance between the right edge of the light-shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light-shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns. In addition, the light-shielding layer 313 is designed as a whole block, and the light-shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122. In other words, the light-shielding layer 313 fully blocks the gap above the gate line 3161. For example, when designing a display panel based on the above numerical values, under 6500 nit illumination, the light transmittance is 64%; under 20,000 nit illumination, the light transmittance is 61%.

[0147] For example, in another example, in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 6.15 microns. The light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314. On the upper side of the gate line 3161, the light shielding layer 313 shields the first branch portion 3121 by 6.15 microns. In the first direction X, on the lower side of the gate line 3161, the length of the portion of the black matrix 321 corresponding to the side of the first branch portion 3121 is 0.7 microns. To minimize the impact on the display panel's aperture ratio, the lower edge of the portion of the light-shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 in the first direction X. The distance between the lower edge of the light-shielding layer 313 corresponding to the first branch portion 3121 and the gate line 3161 is 0.7 microns. In the second direction Y, the light-shielding layer 313 is longer, with the minimum distance between the right edge of the light-shielding layer 313 and the right edge of the first branch portion 3121 being 2.0 microns, and the minimum distance between the left edge of the light-shielding layer 313 and the left edge of the second branch portion 3122 being 2.0 microns. Furthermore, the light-shielding layer 313 is designed as a single piece, completely shielding the gap between the first branch portion 3121 and the second branch portion 3122, effectively shielding the portion above the gate line 3161. For example, when the display panel is designed based on the above numerical values, under the condition of 6500 nit illumination, the light transmittance is 36%; under the condition of 20000 nit illumination, the light transmittance is 35%.

[0148] For example, in another example, in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 6.15 microns. The light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314. On the upper side of the gate line 3161, the light shielding layer 313 shields the first branch portion 3121 by 6.15 microns. In the first direction X, on the lower side of the gate line 3161, the length of the portion of the black matrix 321 corresponding to the side of the first branch portion 3121 is 0 microns. To minimize the impact on the display panel's aperture ratio, the lower edge of the portion of the light-shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 in the first direction X. The distance between the lower edge of the light-shielding layer 313 corresponding to the first branch portion 3121 and the gate line 3161 is 0 microns. In the second direction Y, the light-shielding layer 313 is longer, with a minimum distance of 2.0 microns between the right edge of the light-shielding layer 313 and the right edge of the first branch portion 3121, and a minimum distance of 2.0 microns between the left edge of the light-shielding layer 313 and the left edge of the second branch portion 3122. Furthermore, the light-shielding layer 313 is designed as a single piece, completely shielding the gap between the first branch portion 3121 and the second branch portion 3122, effectively shielding the portion above the gate line 3161. For example, when the display panel is designed based on the above numerical values, under the condition of 6500 nit illumination, the light transmittance is 39%; under the condition of 20000 nit illumination, the light transmittance is 32%.

[0149] Based on the analysis of the above experimental data, it can be concluded that the channel regions corresponding to the two gates of the thin film transistor are blocked by a whole light-shielding layer or a light-shielding layer with a larger area and spaced apart, and the light-shielding layer increases the blocking area on the side of the first source and drain electrode connected to the pixel electrode, that is, when the first via structure in the above-mentioned interlayer insulating layer is blocked, the leakage current of the thin film transistor included in the display panel can be reduced, and the length of the light-shielding layer on the lower side of the gate line in the first direction X that blocks the spacing area is reduced, so that the edges of the light-shielding layer are all shrunk into the area covered by the black matrix, which can further improve the aperture ratio of the display panel.

[0150] For example, multiple thin-film transistors can be provided on the first substrate 31, and the portions of the light-shielding layer 313 corresponding to different thin-film transistors are spaced apart from each other. For example, as shown in FIG19 , the portions of the light-shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin-film transistor form a single integral structure. The design of the light-shielding layer 313 as a single integral structure increases the area covered by the light-shielding layer 313 on one side of the first via structure 314, thereby reducing leakage current of the thin-film transistor.

[0151] For example, as shown in Figure 19, the first branch portion 3121 and the second branch portion 3122 both extend along the first direction X, and the connecting portion 3123 extends along the second direction Y intersecting the first direction X. The first branch portion 3121, the second branch portion 3122 and the connecting portion 3123 are arranged to form an opening area, and the shading layer 313 covers at least part of the opening area, so that the shading layer 313 can be set to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a and the first via structure 314, so as to reduce the leakage current of the thin film transistor, and enhance the retention ability of the pixel capacitance, improve the problem of flickering at low frequency, and in addition, ensure the aperture ratio of the display panel.

[0152] For example, in one example, the first direction X and the second direction Y are perpendicular.

[0153] For example, as shown in Figure 19, the orthographic projections of the two side edges of the gate line 3161 in the second direction Y on the substrate 311 and the orthographic projections of the corresponding two side edges of the black matrix 321 in the second direction Y on the substrate 311 overlap respectively, that is, the orthographic projections of the edge lines on both sides of the gate line 3161 in the second direction Y on the substrate 311 and the orthographic projections of the edge lines on both sides of the black matrix 321 in the second direction Y on the substrate 311 coincide with each other, so that the gate line 3161 can be shrunk into the area covered by the black matrix 321, thereby further improving the aperture ratio of the display panel.

[0154] For example, as shown in FIG19 , in one example, in the first direction X, there is a gap between the light shielding layer 313 and the connecting portion 3123 , that is, there is a gap between the black matrix 321 and the connecting portion 3123 . In this way, while reducing the leakage current of the thin film transistor included in the display panel, the flicker problem of the display panel at low frequency can be improved, and the aperture ratio of the display panel can be increased.

[0155] For example, as shown in FIG19 , in one example, the orthographic projection of the edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 close to the connection portion 3123 on the substrate substrate 311 overlaps with the orthographic projection of the edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 close to the connection portion 3123 on the substrate substrate 311, that is, the orthographic projection of the edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 close to the connection portion 3123 on the substrate substrate 311 overlaps with the orthographic projection of the edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 close to the connection portion 3123 on the substrate substrate 311. 1 close to the connection portion 3123 on the base substrate 311. That is, the orthographic projection of the edge of the portion of the light-shielding layer 313 corresponding to the first branch portion 3121 close to the connection portion 3123 on the base substrate 311 coincides with the orthographic projection of the edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 close to the connection portion 3123 on the base substrate 311. This ensures that the edge of the light-shielding layer 313 can be completely retracted into the area covered by the black matrix 321 to ensure the aperture ratio of the display panel.

[0156] For example, in other examples, in the second direction Y, the leftmost edge of the light-shielding layer 313 may also coincide with the leftmost edge of the black matrix 321 or be located within the orthographic projection of the leftmost edge of the black matrix 321 on the base substrate 311; the rightmost edge of the light-shielding layer 313 may also coincide with the leftmost edge of the black matrix 321 or be located within the orthographic projection of the rightmost edge of the black matrix 321 on the base substrate 311.

[0157] For example, as shown in Figure 19, the bottom edge of the partial light-shielding layer 313 corresponding to the first branch portion 3121 located on the lower side of the gate line 3161 in the first direction X and the edge of the partial black matrix 321 corresponding to the first branch portion 3121 located on the lower side of the gate line 3161 in the first direction X, which is closest to the connecting portion 3123, overlap in their orthographic projections on the base substrate 311, that is, at least part of the black matrix 321 is also flush with the edge of the light-shielding layer 313.

[0158] For example, FIG21 is a schematic diagram of the planar structure of another display panel provided by at least one embodiment of the present disclosure, and FIG22 is a schematic diagram of the cross-sectional structure of the first substrate in FIG21. For example, in combination with FIG18, FIG21 and FIG22, the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122. The first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a. The end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first The side of the branch portion 3121 away from the base substrate 311 has a first via structure 314, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311. The end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, that is, the side of the second branch portion 3122 away from the base substrate 311 has the second via structure 315, and The orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the end of the second branch portion 3122 away from the connecting portion 3123 on the base substrate 311, the orthographic projection of the light-shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311, and the orthographic projection of the light-shielding layer 313 on the base substrate 311 covers the orthographic projections of the first channel region 3121a, the second channel region 3122a, the first via structure 314, and the second via structure 315 on the base substrate 311. The display panel 30 can reduce leakage current and enhance the pixel capacitance retention capability by setting the black matrix 321 to cover the entire area of ​​the light-shielding layer 313, and setting the light-shielding layer 313 to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a, the first via structure 314, and the second via structure 315, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel.

[0159] For example, in combination with Figure 21, in the first direction X, the second via structure 315 is farther away from the connecting portion 3123 relative to the first via structure 314, that is, in the plan view shown in Figure 21, the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is greater than the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is greater than the distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are not flush.

[0160] For example, in combination with Figures 21 and 22, the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311. The first metal layer 316 includes a gate line 3161 extending in the second direction Y. The gate line 3161 is in a long strip shape. The gate line 3161 includes a first gate 3161a and a second gate 3161b. The orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311. The orthographic projections of the first gate 3161a and the second gate 3161b on the base substrate 311 are within the orthographic projection of the black matrix 321 on the base substrate 311.

[0161] It should be noted that in the embodiment shown in FIG21 , the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Moreover, although the data lines are not shown in FIG19 , in actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0162] For example, as shown in Figure 22, a first insulating layer 319 is provided between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is provided on the side of the first metal layer 316 away from the base substrate 311.

[0163] For example, as shown in Figures 21 and 22, the orthographic projection of the edge of the light shielding layer 313 away from the connection portion 3123 on the substrate 311 includes a first portion 313c located on the side of the first via structure 314 away from the connection portion 3123 and a second portion 313d located on the side of the second via structure 315 away from the connection portion 3123. The upper edge of the first portion 313c and the upper edge of the second portion 313d are not on the same straight line, that is, the planar shape of the light shielding layer 313 is stepped, and the planar shape of the black matrix 321 is grid-like. Although the planar shape of the black matrix 321 shown in Figure 21 is rectangular, the planar shape of the light shielding layer 313 corresponding to the black matrix 321 is also stepped, and in the first direction X, the distance between the first portion 313c and the connection portion 3123 is less than the distance between the second portion 313d and the connection portion 3123. The second portion 313d overlaps with the orthographic projection of the edge of the black matrix 321 located above the second via structure 315 on the substrate 311. That is, the second portion 313d coincides with the orthographic projection of the upper edge of the portion of the black matrix 321 on the left side corresponding to the second via structure 315 on the substrate 311. The first portion 313c is spaced apart from the orthographic projection of the edge of the black matrix 321 located above the first via structure 314 on the substrate 311. The orthographic projection of the black matrix 321 on the substrate 311 and the orthographic projection of the light-shielding layer 313 on the substrate 311 both cover the orthographic projection of the second via structure 315 on the substrate 311. That is, the orthographic projection of the second via structure 315 on the substrate 311 is located within the orthographic projection of the light-shielding layer 313 on the substrate 311. It should be noted that, in this example, the material of the light-shielding layer 313 is a non-conductive light-shielding material. When the material of the light-shielding layer 313 is a non-conductive light-shielding material, even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, the problem of short circuit between the first source-drain electrode and the second source-drain electrode of the thin-film transistor will not occur.

[0164] For example, FIG23 is a schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure, and FIG24 is a schematic diagram of a cross-sectional structure of the first substrate in FIG23. For example, in conjunction with FIG18, FIG23, and FIG24, the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321. The semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 disposed opposite each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122. The first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a. The end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314. The orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311. The portions of the light-shielding layer 313 corresponding to different thin-film transistors are spaced apart from each other. The portions of the light-shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin-film transistor are respectively a first sub-light-shielding portion 313a and a second sub-light-shielding portion 313b, and the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b are spaced apart from each other. The first sub-light-shielding portion 313a covers the orthographic projection of the first channel region 3121a and the first via structure 314 on the base substrate 311, and the second sub-light-shielding portion 313b covers the orthographic projection of the second channel region 3122a on the base substrate 311, but does not cover the orthographic projection of the second via structure 315 on the base substrate 311. The display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the black matrix 321 to cover the entire area of ​​the light-shielding layer 313 and the area between the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, and designing the first sub-light-shielding portion 313a to cover the orthographic projection of the first channel region 3121a and the first via structure 314 on the base substrate 311, and designing the second sub-light-shielding portion 313b to cover the orthographic projection of the second channel region 3122a on the base substrate 311, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel.

[0165] For example, in combination with Figure 23, the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and the second via structure 315 is farther away from the connecting portion 3123 than the first via structure 314, that is, in the plan view shown in Figure 23, the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is greater than the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is greater than the distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are not flush.

[0166] For example, in combination with Figures 23 and 24, the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate 3161 extending in the second direction Y, the gate 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311, and the orthographic projections of the first gate 3161a and the second gate 3161b on the base substrate 311 are within the orthographic projection of the black matrix 321 on the base substrate 311.

[0167] It should be noted that in the embodiment shown in FIG23 , the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Moreover, although the data lines are not shown in FIG19 , in actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0168] For example, as shown in Figure 23, a first insulating layer 319 is provided between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is provided on the side of the first metal layer 316 away from the base substrate 311.

[0169] For example, as shown in Figures 23 and 24 , the orthographic projection of the edge of the first sub-light-shielding portion 313a away from the connecting portion 3123 on the substrate 311 includes a first portion 313c located on the side of the first via structure 314 away from the connecting portion 3123, and the orthographic projection of the edge of the second sub-light-shielding portion 313b away from the connecting portion 3123 on the substrate 311 includes a second portion 313d located on the side of the second via structure 315 away from the connecting portion 3123. In other words, both the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b have a long strip shape in plan view, and the length of the first sub-light-shielding portion 313a is shorter than the length of the second sub-light-shielding portion 313b. In the first direction X, the distance between the first portion 313c and the connecting portion 3123 is shorter than the distance between the second portion 313d and the connecting portion 3123. The orthographic projections of the second portion 313d and the edge of the black matrix 321 located above the second via structure 315 on the substrate 311 overlap, that is, the orthographic projections of the second portion 313d and the edge of the black matrix 321 located above the second via structure 315 on the substrate 311 coincide with each other, and the orthographic projections of the first portion 313c and the edge of the black matrix 321 located above the first via structure 314 on the substrate 311 are spaced apart. The orthographic projection of the black matrix 321 on the substrate 311 covers the orthographic projection of the second via structure 315 on the substrate 311, while the orthographic projection of the light shielding layer 313 on the substrate 311 does not cover the orthographic projection of the second via structure 315 on the substrate 311, that is, the orthographic projection of the second via structure 315 on the substrate 311 is outside the orthographic projection of the light shielding layer 313 on the substrate 311. It should be noted that, in this example, the material of the light-shielding layer 313 is a non-conductive light-shielding material or a light-shielding conductive material. Even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, there will be no short circuit problem between the first source-drain electrode and the second source-drain electrode of the thin film transistor.

[0170] For example, a plurality of thin film transistors are provided on the first substrate 31, and the portions of the light-shielding layer 313 corresponding to different thin film transistors are spaced apart from each other. In combination with Figures 23 and 24, the portions of the light-shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, and the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b are spaced apart from each other, and the orthographic projection of the first channel region 3121a on the base substrate 311 is completely located within the orthographic projection of the first sub-light-shielding portion 313a on the base substrate 311, and the orthographic projection of the second channel region 3122a on the base substrate 311 is completely located within the orthographic projection of the second sub-light-shielding portion 313b on the base substrate 311. The orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the first sub-light-shielding portion 313a on the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located outside the orthographic projection of the second sub-light-shielding portion 313b on the base substrate 311.

[0171] For example, as shown in Figures 23 and 24, the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and the maximum distance between the second via structure 315 and the connecting portion 3123 is greater than the maximum distance between the first via structure 314 and the connecting portion 3123.

[0172] For example, FIG25 is a schematic diagram of the planar structure of another display panel provided in at least one embodiment of the present disclosure, and FIG26 is a schematic diagram of the cross-sectional structure of the first substrate in FIG25. For example, in combination with FIG18, FIG25, and FIG26, the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 disposed opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122. The first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a. The end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, and the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315. The orthographic projection of the light-shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311, and covers the orthographic projections of the first channel region 3121a, the second channel region 3122a, the first via structure 314 and the second via structure 315 on the base substrate 311. The display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the black matrix 321 to cover the entire area of ​​the light-shielding layer 313 and setting the light-shielding layer 313 to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a, the first via structure 314 and the second via structure 315, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel.

[0173] For example, in the planar structure schematic diagram shown in Figure 25, the orthographic projection of the light-shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311, and the orthographic projection area of ​​the light-shielding layer 313 on the base substrate 311 is smaller than the orthographic projection area of ​​the black matrix 321 on the base substrate 311. Of course, the embodiments of the present disclosure are not limited to this. Without considering the part of the black matrix covering the lower left corner of the connecting portion 3123, the planar shape of the light-shielding layer 313 and the planar shape of the part of the black matrix 321 corresponding to the light-shielding layer can also be the same.

[0174] For example, in combination with Figure 25, the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is equal to the distance between the first via structure 314 and the connecting portion 3123, that is, in the plan view shown in Figure 25, the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is equal to the length of the first branch portion 3121 in the first direction X, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are flush.

[0175] For example, in combination with Figures 25 and 26, the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate 3161 extending in the second direction Y, the gate 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311, and the orthographic projections of the first gate 3161a and the second gate 3161b on the base substrate 311 are within the orthographic projection of the black matrix 321 on the base substrate 311.

[0176] It should be noted that in the embodiment shown in FIG25 , the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Moreover, although the data lines are not shown in FIG19 , in actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0177] For example, as shown in Figure 26, a first insulating layer 319 is provided between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is provided on the side of the first metal layer 316 away from the base substrate 311.

[0178] For example, in combination with Figures 25 and 26, in one example, the material of the light-shielding layer 313 includes a non-conductive light-shielding material, the orthographic projection of the black matrix 321 on the base substrate 311 covers the orthographic projections of the first via structure 314 and the second via structure 315 on the base substrate 311, and the orthographic projections of the first via structure 314 and the second via structure 315 on the base substrate 311 are both located within the orthographic projection of the light-shielding layer 313 on the base substrate 311.

[0179] For example, in combination with Figures 25 and 26, the light-shielding layer 313 is an integral structure, and the orthographic projection of the light-shielding layer 313 on the substrate substrate 311 covers the orthographic projection of the first channel region 3121a on the substrate substrate 311, the orthographic projection of the second channel region 3122a on the substrate substrate 311, the orthographic projection of the first via structure 314 on the substrate substrate 311, and the orthographic projection of the second via structure 315 on the substrate substrate 311, as well as covers the gap between the first channel region 3121a and the second channel region 3122a, and covers the gap between the first via structure 314 and the second via structure 315.

[0180] For example, Figure 27 is a schematic diagram of the planar structure of another display panel provided by at least one embodiment of the present disclosure, and Figure 28 is a schematic diagram of the cross-sectional structure of the first substrate in Figure 27. For example, in combination with Figures 18, 27 and 28, the first substrate 31 includes a base substrate 311 and a light-shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122, the first branch portion 3121 includes a first channel region 3121a, the second branch portion 3122 includes a second channel region 3122a, the end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first via structure 314 is provided on the side of the first branch portion 3121 away from the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311, and the orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311. Portions of the light-shielding layer 313 corresponding to different thin-film transistors are spaced apart from each other. Portions of the light-shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin-film transistor are respectively formed as a first sub-light-shielding portion 313a and a second sub-light-shielding portion 313b, and the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b are spaced apart from each other. The first sub-light-shielding portion 313a covers the orthographic projections of the first channel region 3121a and the first via structure 314 on the base substrate 311, and the second sub-light-shielding portion 313b covers the orthographic projections of the second channel region 3122a and the second via structure 315 on the base substrate 311. The display panel 30 sets the black matrix 321 to cover the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, but does not cover the area between the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, and designs the first sub-light-shielding portion 313a so that the orthographic projection of the first sub-light-shielding portion 313a on the substrate 311 covers the first channel area 3121a and the orthographic projection of the first via structure 314 on the substrate 311, and designs the second sub-light-shielding portion 313b so that the orthographic projection of the second sub-light-shielding portion 313b on the substrate 311 covers the orthographic projection of the second channel area 3122a and the second via structure 315 on the substrate 311. This design can reduce leakage current and improve the retention capacity of pixel capacitance, thereby improving the problem of flickering at low frequency and ensuring the aperture ratio of the display panel.

[0181] For example, in combination with Figure 27, the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and the minimum distance between the second via structure 315 and the connecting portion 3123 is equal to the minimum distance between the first via structure 314 and the connecting portion 3123, that is, in the plan view shown in Figure 27, the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X. The length of the second branch portion 3122 in the first direction X is equal to the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is equal to the distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are flush.

[0182] For example, in conjunction with Figures 27 and 28, the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311. The first metal layer 316 includes a gate 3161 extending in the second direction Y. The gate 3161 is in a long strip shape. The gate line 3161 includes a first gate 3161a and a second gate 3161b. The orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311. The orthographic projection of the gate line 3161 on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311, that is, the gate line 3161 is also contracted to within the range defined by the black matrix 321, thereby not reducing the aperture ratio of the display panel.

[0183] It should be noted that in the embodiment shown in FIG27 , the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Moreover, although the data lines are not shown in FIG19 , in actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0184] For example, as shown in Figure 28, a first insulating layer 319 is provided between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is provided on the side of the first metal layer 316 away from the base substrate 311.

[0185] For example, as shown in Figures 27 and 28 , the orthographic projection of the side of the first sub-light-shielding portion 313a away from the connecting portion 3123 on the substrate 311 includes a first portion 313c located on the side of the first via structure 314 away from the connecting portion 3123, and the orthographic projection of the side of the second sub-light-shielding portion 313b away from the connecting portion 3123 on the substrate 311 includes a second portion 313d located on the side of the second via structure 315 away from the connecting portion 3123. The upper edge of the first portion 313c and the upper edge of the second portion 313d are collinear. That is, the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b are both elongated in plan view, and the length of the first sub-light-shielding portion 313a in the first direction X is equal to the length of the second sub-light-shielding portion 313b in the first direction X. In the first direction X, the distance between the first portion 313c and the connecting portion 3123 is equal to the distance between the second portion 313d and the connecting portion 3123. The second portion 313d overlaps with the orthographic projection of the upper edge of the black matrix 321 located above the second via structure 315 on the substrate 311. That is, the second portion 313d coincides with the orthographic projection of the upper edge of the black matrix 321 located above the second via structure 315 on the substrate 311. The first portion 313c coincides with the orthographic projection of the upper edge of the black matrix 321 located above the first via structure 314 on the substrate 311. The orthographic projection of the black matrix 321 on the substrate 311 and the orthographic projection of the light-shielding layer 313 on the substrate 311 both cover the orthographic projection of the second via structure 315 on the substrate 311. That is, the orthographic projection of the second via structure 315 on the substrate 311 is located within the orthographic projection of the light-shielding layer 313 on the substrate 311. It should be noted that in this example, the material of the light-shielding layer 313 is a non-conductive light-shielding material. Even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, the first source-drain electrode and the second source-drain electrode of the thin film transistor will not be short-circuited.

[0186] For example, a plurality of thin film transistors are provided on the first substrate 31, and the portions of the light-shielding layer 313 corresponding to different thin film transistors are spaced apart from each other. In combination with Figures 27 and 28, the portions of the light-shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, and the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b are spaced apart from each other, and the orthographic projection of the first channel region 3121a on the base substrate 311 is completely located within the orthographic projection of the first sub-light-shielding portion 313a on the base substrate 311, and the orthographic projection of the second channel region 3122a on the base substrate 311 is completely located within the orthographic projection of the second sub-light-shielding portion 313b on the base substrate 311. The orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the first sub-light-shielding portion 313a on the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the second sub-light-shielding portion 313b on the base substrate 311.

[0187] For example, FIG29 is a schematic diagram of the planar structure of another display panel provided by at least one embodiment of the present disclosure, and FIG30 is a schematic diagram of the cross-sectional structure of the first substrate shown in FIG29. As shown in conjunction with FIG18, FIG29, and FIG30, the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 disposed opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122. The first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a. The end of the first branch portion 3121 away from the connection portion 3123 corresponds to the first via structure 314. Specifically, the first via structure 314 is located on the side of the first branch portion 3121 away from the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connection portion 3123 on the base substrate 311. The end of the second branch portion 3122 away from the connection portion 3123 corresponds to the second via structure 315. Specifically, the second via structure 315 is located on the side of the second branch portion 3122 away from the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the end of the second branch portion 3122 away from the connection portion 3123 on the base substrate 311. The orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311. The orthographic projection of the light-shielding layer 313 on the base substrate 311 covers the orthographic projections of the first channel region 3121a, the second channel region 3122a and the first via structure 2126 on the base substrate 311. The display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the light-shielding layer 213 to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a and the first via structure 314, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel formed subsequently.

[0188] For example, as shown in Figure 29, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is equal to the distance between the first via structure 314 and the connecting portion 3123, that is, in the plan view shown in Figure 29, the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is equal to the length of the first branch portion 3121 in the first direction X, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 2124 corresponding to the end of the first branch portion 3121 are flush.

[0189] For example, as shown in Figures 29 and 30, the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311. The first metal layer 316 includes a gate line 3161 extending in the second direction Y. The gate line 3161 is in a long strip shape. The gate line 3161 includes a first gate 3161a and a second gate 3161b. The orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311.

[0190] For example, the first gate 3161a, the second gate 3161b and the gate line 3161 are an integrated linear structure, the first gate 3161a and the second gate 3161b are part of the gate line 3161, the first gate 3161a is the part of the gate line 3161 corresponding to the first channel region 3121a, and the second gate 3161b is the part of the gate line 3161 corresponding to the second channel region 3122a.

[0191] It should be noted that in the embodiment shown in FIG29 , the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Moreover, although the data lines are not shown in FIG19 , in actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0192] For example, as shown in Figure 30, a first insulating layer 319 is provided between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is provided on the side of the first metal layer 316 away from the base substrate 311.

[0193] For example, in combination with Figures 29 and 30, in one example, the material of the shading layer 313 includes a non-conductive shading material or a conductive shading material, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the shading layer 313 on the base substrate 311.

[0194] For example, in combination with Figures 29 and 30, the light-shielding layer 313 is an integral structure, and the orthographic projection of the light-shielding layer 313 on the substrate substrate 311 covers the orthographic projection of the first channel region 3121a on the substrate substrate 311, the orthographic projection of the second channel region 3122a on the substrate substrate 311, and the orthographic projection of the first via structure 314 on the substrate substrate 311, as well as covers the gap between the first channel region 3121a and the second channel region 3122a. The planar shape of the light-shielding layer 313 is stepped.

[0195] For example, FIG31 is a schematic diagram of the planar structure of another display panel provided in at least one embodiment of the present disclosure, and FIG32 is a schematic diagram of the cross-sectional structure of the first substrate shown in FIG31. As shown in conjunction with FIG18, FIG31, and FIG32, the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 disposed opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122. The first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a. The end of the first branch portion 3121 away from the connection portion 3123 corresponds to the first via structure 314. Specifically, the first via structure 314 is located on the side of the first branch portion 3121 away from the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connection portion 3123 on the base substrate 311. The end of the second branch portion 3122 away from the connection portion 3123 corresponds to the second via structure 315. Specifically, the second via structure 315 is located on the side of the second branch portion 3122 away from the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the end of the second branch portion 3122 away from the connection portion 3123 on the base substrate 311. The orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311. The orthographic projection of the light-shielding layer 313 on the base substrate 311 covers the orthographic projection of the first channel region 3121a and the first via structure 2126 on the base substrate 311. The display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the light-shielding layer 213 to cover the entire area of ​​the first channel region 3121a and the first via structure 314, but not covering the orthographic projection of the second channel region 3122a on the base substrate 311, thereby improving the problem of flickering at low frequency and ensuring the aperture ratio of the display panel formed subsequently.

[0196] For example, as shown in FIG. 31 , in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is greater than the distance between the first via structure 314 and the connecting portion 3123 .

[0197] For example, as shown in Figures 31 and 32, the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311. The first metal layer 316 includes a gate line 3161 extending in the second direction Y. The gate line 3161 is in a long strip shape. The gate line 3161 includes a first gate 3161a and a second gate 3161b. The orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311.

[0198] It should be noted that in the embodiment shown in FIG31 , the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 on one side corresponding to the second branch portion 3122, resulting in two raised portions on the left side of the black matrix. Moreover, although the data lines are not shown in FIG19 , in actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0199] For example, as shown in Figure 32, a first insulating layer 319 is provided between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is provided on the side of the first metal layer 316 away from the base substrate 311.

[0200] For example, in combination with Figures 31 and 32, in one example, the material of the shading layer 313 includes a non-conductive shading material or a conductive shading material, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the shading layer 313 on the base substrate 311.

[0201] For example, FIG33 is a schematic diagram of the planar structure of another display panel provided in at least one embodiment of the present disclosure. The display panel shown in FIG33 differs from the display panel shown in FIG19 only in that a touch signal line 320 extending along the first direction X is provided between the first branch portion 3121 and the second branch portion 3122. This saves space for wiring placement and makes the display panel thinner and lighter. The structure of the display panel shown in FIG33 can be found in the description of the display panel shown in FIG19 and will not be repeated here.

[0202] For example, in the structure shown in FIG. 33 , the black matrix 321 also covers the touch signal line 320 .

[0203] For example, FIG34 is a schematic diagram of the laminated structure of another display panel provided in at least one embodiment of the present disclosure. The display panel shown in FIG34 differs from the display panel shown in FIG27 only in that a touch signal line 320 extending along the first direction X is provided between the first branch portion 3121 and the second branch portion 3122. This saves space for wiring placement and makes the display panel thinner and lighter. The structure of the display panel shown in FIG34 can be found in the description of the display panel shown in FIG27 and will not be repeated here.

[0204] For example, in the structure shown in FIG. 34 , the black matrix 321 also covers the touch signal line 320 .

[0205] For example, FIG35 is a block diagram of a display panel provided in at least one embodiment of the present disclosure. As shown in FIG35 , the display panel 30 includes the array substrate 21 in any of the above embodiments, that is, a first substrate 31. In one example, the display panel 30 further includes a liquid crystal layer sandwiched between the first substrate 31 and a second substrate 32. Other circuit structures included in the display panel can refer to conventional designs and are not limited in the embodiments of the present disclosure.

[0206] At least one embodiment of the present disclosure further provides a display device. For example, FIG36 is a block diagram of a display device provided by at least one embodiment of the present disclosure. As shown in FIG36 , the display device 500 includes the display panel 30 described in any one of the above items, and the display panel 30 includes the array substrate provided by any one of the above embodiments.

[0207] For example, the display device 500 may be a display device having a display function. For example, the display device 500 may be a monitor, an OLED display panel, an OLED TV, a liquid crystal display panel, a liquid crystal display TV, a QLED display panel, a QLED TV, an electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigation system, or any other product or component having a display function and a touch function.

[0208] At least one embodiment of the present disclosure provides an array substrate, a display panel, and a display device, which have at least one of the following beneficial technical effects:

[0209] (1) The array substrate provided in at least one embodiment of the present disclosure can reduce the leakage current of the display panel by adjusting the design of the light-shielding layer, thereby designing the light-shielding layer to block the first via structure, thereby improving the retention capacity of the pixel capacitance, thereby improving the problem of flickering at low frequencies, and also ensuring the aperture ratio of the display panel.

[0210] (2) In the display panel provided by at least one embodiment of the present disclosure, the light-shielding layer is designed as a whole block, and the light-shielding layer completely blocks the gap portion between the first branch portion and the second branch portion, that is, the light-shielding layer fully blocks the gap portion above the gate line, which can reduce the leakage current of the thin film transistor without affecting the aperture ratio.

[0211] (3) In the display panel provided by at least one embodiment of the present disclosure, the edges of the light-shielding layer are shrunk into the area covered by the black matrix, which can further improve the aperture ratio of the display panel.

[0212] There are a few points to note:

[0213] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0214] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale.

[0215] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0216] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An array substrate, comprising a base substrate and a semiconductor layer and a light-shielding layer stacked on the base substrate, the semiconductor layer comprising a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion comprising a first channel region, the second branch portion comprising a second channel region, a first via structure being provided on a side of the first branch portion away from the base substrate, and an orthographic projection of the first via structure on the base substrate is located within an orthographic projection of an end of the first branch portion away from the connecting portion on the base substrate; the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projection of the first channel region and the first via structure on the base substrate.

2. The array substrate according to claim 1, wherein: The second branch portion has a second via structure on the side away from the base substrate, and the orthographic projection of the second via structure on the base substrate is located within the orthographic projection of the end of the second branch portion away from the connecting portion on the base substrate, and the minimum distance between the second via structure and the connecting portion is greater than or equal to the minimum distance between the first via structure and the connecting portion.

3. The array substrate according to claim 2, wherein: The orthographic projection of the second via structure on the base substrate is outside the orthographic projection of the light shielding layer on the base substrate.

4. The array substrate according to any one of claims 1 to 3, wherein: A plurality of thin film transistors are arranged on the base substrate, portions of the light shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure.

5. The array substrate according to claim 4, wherein: The first branch portion and the second branch portion both extend along a first direction, the connecting portion extends along a second direction intersecting the first direction, the first branch portion, the second branch portion and the connecting portion are arranged to form an opening area, and the shading layer covers at least a portion of the opening area.

6. The array substrate according to any one of claims 1 to 5, further comprising a first metal layer arranged on a side of the semiconductor layer away from the base substrate, the first metal layer comprising a gate line extending in the second direction, the gate line comprising a first gate and a second gate, the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel region on the base substrate.

7. The array substrate according to claim 5, wherein: There is a gap between the light shielding layer and the connecting portion in the first direction.

8. The array substrate according to any one of claims 1 to 3, wherein: A plurality of thin film transistors are arranged on the base substrate, and portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other. Portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are respectively a first sub-light-shielding portion and a second sub-light-shielding portion, and the first sub-light-shielding portion and the second sub-light-shielding portion are spaced apart from each other.

9. The array substrate according to claim 8, wherein: The orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light shielding portion on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the second sub-light shielding portion on the base substrate.

10. A display panel, comprising a first substrate and a second substrate arranged opposite to each other, wherein: The first substrate includes a base substrate and a semiconductor layer and a light shielding layer stacked on the base substrate; The second substrate includes a black matrix; The semiconductor layer includes a first branch portion and a second branch portion that are arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion includes a first channel region, the second branch portion includes a second channel region, a first via structure is provided on a side of the first branch portion that is away from the substrate, and an orthographic projection of the first via structure on the substrate is located within an orthographic projection of an end of the first branch portion that is away from the connecting portion on the substrate; The orthographic projection of the light shielding layer on the base substrate is located within the orthographic projection of the black matrix on the base substrate, and at least covers the orthographic projections of the first channel region and the first via structure on the base substrate.

11. The display panel according to claim 10, wherein: An end of the second branch portion away from the connecting portion corresponds to a second via structure, and the second via structure is further away from the connecting portion than the first via structure.

12. The display panel according to claim 11, wherein: The material of the light-shielding layer includes a conductive metal, the orthographic projection of the black matrix on the base substrate covers the orthographic projection of the second via structure on the base substrate, and the orthographic projection of the second via structure on the base substrate is outside the orthographic projection of the light-shielding layer on the base substrate.

13. The display panel according to any one of claims 10 to 12, wherein: A plurality of thin film transistors are arranged on the first substrate, portions of the light shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure.

14. The display panel according to claim 13, wherein: The first branch portion and the second branch portion both extend along a first direction, the connecting portion extends along a second direction intersecting the first direction, the first branch portion, the second branch portion and the connecting portion are arranged to form an opening area, and the shading layer covers at least a portion of the opening area.

15. The display panel according to any one of claims 10 to 14, wherein: The first substrate also includes a first metal layer arranged on a side of the semiconductor layer away from the base substrate, the first metal layer includes a gate line extending in the second direction, the gate line includes a first gate and a second gate, the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel region on the base substrate.

16. The display panel according to claim 15, wherein: The orthographic projection of the first gate on the base substrate is within the orthographic projection of the black matrix on the base substrate, and the orthographic projection of the second gate on the base substrate is within the orthographic projection of the black matrix on the base substrate.

17. The display panel according to claim 16, wherein: There is a gap between the light shielding layer and the connecting portion in the first direction.

18. The display panel according to any one of claims 14 to 17, wherein: The orthographic projection of the edge of the portion of the light-shielding layer corresponding to the first branch portion close to the connecting portion on the base substrate overlaps with the orthographic projection of the edge of the portion of the black matrix corresponding to the first branch portion close to the connecting portion on the base substrate.

19. The display panel according to claim 11, wherein: The orthographic projection of the edge of the portion of the light-shielding layer corresponding to the first branch portion farthest from the connecting portion on the base substrate overlaps with the orthographic projection of the edge of the portion of the black matrix corresponding to the first branch portion farthest from the connecting portion on the base substrate.

20. The display panel according to claim 19, wherein: The orthographic projection of the edge of the light-shielding layer away from the connecting portion on the base substrate includes a first part located on the side of the first via structure away from the connecting portion and a second part located on the side of the second via structure away from the connecting portion, and the orthographic projection of the second part on the base substrate is located within the orthographic projection of the edge of the black matrix farthest from the second via structure on the base substrate.

21. The display panel according to claim 19 or 20, wherein: A plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are respectively the first sub-light-shielding portion and the second sub-light-shielding portion, and the first sub-light-shielding portion and the second sub-light-shielding portion are spaced apart from each other.

22. The display panel according to claim 21, wherein: The orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light shielding portion on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the second sub-light shielding portion on the base substrate.

23. The display panel according to claim 10, wherein: An end of the second branch portion away from the connecting portion corresponds to a second via structure, and a maximum distance between the second via structure and the connecting portion is equal to a maximum distance between the first via structure and the connecting portion.

24. The display panel according to claim 23, wherein: The material of the light shielding layer includes a non-conductive light shielding material, and the orthographic projection of the black matrix on the base substrate and the orthographic projection of the light shielding layer on the base substrate both cover the orthographic projection of the second via structure on the base substrate.

25. The display panel according to claim 23 or 24, wherein: A plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure or a structure spaced apart from each other.

26. A display device, comprising the array substrate according to any one of claims 1 to 9, or the display panel according to any one of claims 10 to 25.

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