Visual programming implementation method and apparatus for programmable logic device

Abstract

The present application relates to a visual programming implementation method and apparatus for a programmable logic device, a computer device, a storage medium, and a computer program product. The method comprises: obtaining logic association configuration data and data path configuration data of a programmable logic device; and on the basis of the data path configuration data and the logic association configuration data, establishing mapping between a physical layer and a logic layer of the programmable logic device, wherein the logic layer comprises a plurality of instantiated logic blocks, and the data path configuration data is obtained by transforming, by a connected embedded platform, initial data path configuration data generated by a visual development platform. By using this method, decoupling and configurability of the physical layer and the logic layer can be achieved, improving the data updating efficiency; moreover, the method can be applied to engineering sites having complex and changeable function requirements, and has greater flexibility and versatility.

Description

Visual programming implementation method and device for programmable logic device

[0001] Cross-references

[0002] This application refers to Chinese Patent Application No. 2023107732527, filed on June 27, 2023, entitled “Visual Programming Implementation Method and Device for Programmable Logic Devices,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to the technical field of digital circuit design, and in particular to a method, apparatus, computer equipment, storage medium, and computer program product for implementing visual programming of a programmable logic device. Background Art

[0004] With the development of embedded programmable logic device technology, the control link delay in DC grid flexible control systems can now achieve a performance level of 100 microseconds. This is mainly due to the use of programmable logic devices in the system to run strong real-time application functions.

[0005] Currently, in the field of DC power, application functions are usually implemented in FPGAs (Field-Programmable Gate Arrays). Current mainstream manufacturers all use function-oriented design for FPGAs.

[0006] However, in general, the FPGA programs in the control systems used on engineering project sites are usually customized. When faced with diverse functional requirements, a large number of data modifications and updates are required. As a result, computer equipment needs to perform multiple data processing operations, which makes on-site data updates inefficient.

[0007] Summary of the Invention

[0008] Based on this, it is necessary to provide an efficient visual programming implementation method, device, computer equipment, computer-readable storage medium and computer program product for programmable logic devices that can meet various engineering needs in order to address the above technical problems.

[0009] In a first aspect, the present application provides a method for implementing visual programming of a programmable logic device. The method comprises:

[0010] Acquiring logic association configuration data and data path configuration data of a programmable logic device;

[0011] Establishing a mapping between a physical layer and a logical layer of a programmable logic device according to the data path configuration data and the logic association configuration data;

[0012] The logic layer includes a plurality of instantiated logic blocks, and the data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

[0013] The technical solution of the embodiment of the present application is different from the traditional method of converting the language of the written logic code through a synthesis tool to obtain the connection relationship configuration data of the programmable logic device. Instead, the data path configuration data obtained by converting the initial data path configuration data by the embedded platform is directly obtained without the need for language conversion. In addition, by pre-building instantiated logic blocks, a mapping of the physical layer and the logical layer can be established based on the logical association configuration data and the data path configuration data, separating the underlying hardware devices from the upper-level application programs, and realizing the decoupling and configurability of the physical layer and the logical layer. When the functional requirements change, the application function can be changed by modifying the configuration items of the logic block, thereby improving the data update efficiency and being applicable to engineering sites with complex and changing functional requirements, with greater flexibility and versatility.

[0014] In some embodiments, establishing a mapping between a physical layer and a logical layer of a programmable logic device according to the data path configuration data and the logic association configuration data includes:

[0015] According to the data path configuration data and the logical association configuration data, the mapping between the physical mapping layer, the communication interface layer and the data exchange interface layer and the logical layer is established; the physical layer includes the physical mapping layer, the communication interface layer and the data exchange interface layer.

[0016] In the technical solution of the embodiment of the present application, by dividing the physical layer into a physical mapping layer, a communication interface layer and a data exchange interface layer, and establishing a mapping between the physical mapping layer, the communication interface layer and the data exchange interface layer and the logical layer, the coupling degree between the modules can be reduced, making the modules more reusable and achieving higher resource utilization.

[0017] In some embodiments, the instantiated logic block includes a communication logic block, and the logic-associated configuration data includes input and output parameters and a parameter model of the communication logic block, and protocol parameters and protocol channel data of a communication interface layer;

[0018] Establishing a mapping between the communication interface layer and the logic layer based on the data path configuration data and the logic association configuration data includes:

[0019] According to the data path configuration data, the input and output parameters and parameter model of the communication logic block are associated with the protocol parameters and protocol channel parameters of the communication interface layer, and a mapping between the communication interface layer and the communication logic block is established, wherein the parameter model is associated with the logic association configuration data.

[0020] In the technical solution of the embodiment of the present application, by associating the input and output parameters and parameter model of the communication logic block with the protocol parameters and protocol channel parameters of the communication interface layer, a mapping between the communication interface layer and the communication logic block is established, which can facilitate the modification, expansion and reconstruction of the communication logic block and the communication interface layer, and achieve better compatibility between different platforms or systems.

[0021] In some embodiments, the instantiated logic block includes a functional logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the functional logic block, as well as signal data and data lines of a data exchange interface layer;

[0022] Establishing a mapping between the data exchange interface layer and the logic layer based on the data path configuration data and the logic association configuration data includes:

[0023] Associate the input and output parameters of the functional logic block with the data transceiver channel of the communication logic block, and associate the input and output parameters and parameter model of the functional logic block with the signal data and data lines of the data exchange interface layer to establish a mapping between the data exchange interface layer and the logic layer.

[0024] In the technical solution of the embodiment of the present application, data transmission and processing functions are realized by establishing a mapping between the data exchange interface layer and the communication function logic block, so that each component has a high cohesion, reduces the coupling degree of the system, and thus improves the maintainability of the system.

[0025] In some embodiments, the physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block, and an application function data block;

[0026] Establishing a mapping between the physical mapping layer and the logical layer based on the data path configuration data and the logical association configuration data includes:

[0027] According to the logical function resource configuration data and data path configuration data of each data block in the logical association configuration data, the mapping relationship between the configuration data block, monitoring data block, sampling data block, control command data block and application function data block and the logical layer is established respectively.

[0028] In the technical solution of the embodiment of the present application, by establishing a mapping relationship between the configuration data block, the monitoring data block, the sampling data block, the control command data block and the application function data block and the logical layer, the design and implementation complexity of the system can be simplified, the development efficiency can be improved, and it can also be flexibly configured and adjusted for different application scenarios.

[0029] In some embodiments, the configuration data block performs data read and write operations through RAM (Random Access Memory).

[0030] In the technical solution of the embodiments of the present application, by caching the data of the configuration data block in RAM, the number of data exchanges with external devices can be reduced, achieving high-speed, low-latency data transmission and processing. In addition, the RAM size, read and write speed and other parameters can be configured as needed to meet the needs of different application scenarios.

[0031] In some embodiments, the monitoring data block, the sampling data block, the control command data block, and the application function data block perform data reading and writing operations through FIFO (First-In-First-Out).

[0032] In the technical solution of the embodiment of the present application, data reading and writing operations are performed in a FIFO manner, which can better control and synchronize data flow, and can also dynamically adjust the storage capacity and data transmission rate according to the needs of the application, thereby enhancing flexibility.

[0033] In some embodiments, the method further comprises:

[0034] Obtaining hierarchical partitioning data of programmable logic devices;

[0035] According to the hierarchical division of data, the interface layer of the programmable logic device is divided into a physical layer, a logical association layer and a logical layer.

[0036] In the technical solution of the embodiment of the present application, the programmable logic device is divided into a physical layer, a logical association layer and a logical layer by hierarchical division data, and the logical association layer is used as a bridge to achieve mapping and decoupling of the physical layer and the logical association layer.

[0037] In a second aspect, the present application also provides a device for implementing visual programming of a programmable logic device. The device comprises:

[0038] A data acquisition module, used to acquire logic association configuration data and data path configuration data of a programmable logic device;

[0039] A data mapping module, configured to establish a mapping between the physical layer and the logical layer of the programmable logic device according to the data path configuration data and the logic association configuration data;

[0040] The logic layer includes a plurality of instantiated logic blocks, and the data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

[0041] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned method for implementing visual programming of a programmable logic device when executing the computer program.

[0042] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-mentioned method for implementing visual programming of a programmable logic device.

[0043] In a fifth aspect, the present application further provides a computer program product, comprising a computer program that, when executed by a processor, implements the steps of the above-mentioned method for implementing visual programming of a programmable logic device.

[0044] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on the drawings without inventive work. In the drawings:

[0046] FIG1 is a diagram illustrating an application environment of a method for implementing visual programming of a programmable logic device in some embodiments of the present application;

[0047] FIG2 is a flow chart of a method for implementing visual programming of a programmable logic device in some embodiments of the present application;

[0048] FIG3 is a flowchart illustrating steps for establishing mapping between the physical layer and the logical layer in some other embodiments of the present application;

[0049] FIG4 is a detailed schematic diagram of a method for implementing visual programming of a programmable logic device in some other embodiments of the present application;

[0050] FIG5 is a schematic diagram of establishing a mapping between a communication function logic block, a function logic block, and a logic layer in some embodiments of the present application;

[0051] FIG6 is a diagram illustrating a visual implementation framework of FPGA abstraction layering in some embodiments of the present application;

[0052] FIG7 is a detailed flowchart of a method for implementing visual programming of a programmable logic device in other embodiments of the present application;

[0053] FIG8 is a structural block diagram of a device for implementing visual programming of a programmable logic device in some embodiments of the present application;

[0054] FIG9 is a structural block diagram of a device for implementing visual programming of a programmable logic device in some other embodiments of the present application;

[0055] FIG10 is a diagram showing the internal structure of a computer device in some embodiments of the present application. DETAILED DESCRIPTION

[0056] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0058] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0059] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0060] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0061] With the development of embedded programmable logic device technology, the control link delay in DC grid flexible control systems has been able to achieve a performance level of 100 microseconds. This is mainly due to the use of programmable logic devices (PLDs) in the system to run strong real-time application functions.

[0062] Taking FPGAs as an example, circuit designs written in hardware description languages ​​like Verilog HDL (Hardware Description Language) or VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) can be quickly downloaded and tested onto an FPGA after simple synthesis and layout. Programmable components can be used to implement basic logic gates (such as AND, OR, XOR, and NOT) or more complex combinational functions like decoders or mathematical equations.

[0063] Currently, in the field of DC power, application functions are typically implemented in FPGAs, with mainstream manufacturers adopting a function-oriented FPGA design approach. There are two main implementation approaches: the traditional development method based on Hardware Description Language (HDL), and the visual implementation method based on graphical design tools. The traditional development approach adopts a hierarchical and modular design approach, describing processing by writing HDL code and calling IP (Intellectual Property) cores. This design approach requires extensive code writing, is labor-intensive, and requires long debugging times, extending the development cycle. Visual programming, on the other hand, takes a visual development approach, using familiar icons to represent design content and lines to represent the interactions between subsystems. Developers can build processing algorithms through intuitive visual operations. Compared to traditional development methods, visual programming is simple and direct, requires less programming skills, and can significantly improve development efficiency. Consequently, it is gaining increasing popularity.

[0064] However, in the application of FPGA visual programming, project site requirements often change, often requiring on-site adjustments and modifications to FPGA software application functions. This requires numerous data modifications and updates, requiring computer equipment to perform multiple data processing operations, resulting in inefficient on-site data updates. Furthermore, FPGA programs are often customized, with each project site having different functional versions and interface definitions. This makes it difficult to simply use a single programming solution to meet the needs of all on-site projects.

[0065] Based on the above problems, the present application proposes a method for implementing visual programming of a programmable logic device. Specifically, the logic block of the programmable logic device is instantiated in advance according to functional requirements, and then data path configuration data and logic association configuration data are obtained. The data path configuration data is obtained by converting the initial data path configuration data generated by the visual development platform by the connected embedded platform. Then, based on the data path configuration data and the logic association configuration data, a mapping between the physical layer and the logical layer of the programmable logic device is established, and the underlying hardware device is separated from the upper-level application program, thereby realizing the decoupling and configurability of the physical layer and the logical layer. When the functional requirements change, the application function can be changed by modifying the configuration items of the logic block, thereby improving the data update efficiency. The method is applicable to engineering sites with complex and changing functional requirements, and has greater flexibility and versatility.

[0066] The visual programming implementation method of the programmable logic device provided in the embodiment of the present application can be applied to the application environment as shown in Figure 1. Among them, the programmable logic device takes an FPGA chip as an example, and the programmable logic device design platform takes an FPGA design platform as an example. The visual development platform 100 communicates with the embedded platform 102 through a network, and the embedded platform 102 communicates with the FPGA design platform 104 through a serial port. Specifically, the developer can perform FPGA visual design on the visual development platform 100 according to the functional requirements of the visual engineering project. The visual development platform 100 generates initial data path configuration data corresponding to the visual engineering project and sends the initial data path configuration data to the embedded platform 102. The embedded platform 102 receives the initial data path configuration data and converts the initial data path configuration data into data path configuration data that can be recognized by the FPGA design platform 104. The embedded platform sends the data path configuration data to the FPGA design platform 104, and the FPGA design platform 104 receives and stores the recognizable data path configuration data.

[0067] When the FPGA design platform 104 receives the visual design instruction, it obtains the logic association configuration data and data path configuration data of the programmable logic device, and establishes a mapping between the physical layer and the logical layer of the programmable logic device based on the data path configuration data and the logic association configuration data, thereby realizing the decoupling of the physical layer and the logical layer.

[0068] The visual development platform 100 can be, but is not limited to, various personal computers, laptops, smartphones, tablet computers, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, smart car devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0069] In some embodiments, as shown in FIG2 , a method for implementing visual programming of a programmable logic device is provided. The method is applied to the FPGA design platform 102 (hereinafter referred to as the platform) in FIG1 . The programmable logic device is described using an FPGA as an example. The method includes the following steps:

[0070] S200: Acquire logic association configuration data and data path configuration data of a programmable logic device.

[0071] A programmable logic device (PLD) is a general-purpose programmable digital logic circuit with a high degree of integration that can meet the needs of general digital system design. Commonly used programmable logic devices include, but are not limited to, programmable array logic (PAL), programmable logic array (PLA), complex programmable logic device (CPLD), and FPGA. Logical association configuration data refers to the configuration data in the logical association layer of a programmable logic device, specifically including relevant configuration data for implementing the mapping between the physical layer and the logical layer, and configuration data for describing the connection relationship between the programmable logic unit and the programmable interconnection resources of the physical layer, such as the input and output parameters and parameter model data of each functional logic block, as well as communication protocol and communication channel data. In this embodiment, the logical association configuration data can be pre-stored data.

[0072] Datapath configuration data refers to configuration data used to characterize the connection relationships between various resources within a programmable logic device (PLD), and can be understood as logic netlist data. Taking FPGAs as an example, the connections between different resources within an FPGA chip are often referred to as the "FPGA internal data path," or simply "data path" or "internal connections." Specifically, datapath configuration data includes configuration data such as signal transmission paths, interconnections between logic elements, clock distribution, and data storage, and is key to implementing various computing and control functions within the FPGA chip. Datapath configuration data can instruct a programmable logic device to connect a specific input pin to the input port of a specific logic unit, and to connect the output port of that logic unit to a specific output pin. In this embodiment, datapath configuration data refers to datapath configuration data that can be directly recognized by the programmable logic device. Specifically, the datapath configuration data can be obtained by converting initial datapath configuration data by an embedded platform. The initial datapath configuration data is generated by a visual development platform based on a designed engineering project. The initial datapath configuration data is data described in a software programming language (such as C, C++, etc.).

[0073] In a specific implementation, the visualization development host computer can generate initial data path configuration data based on a designed engineering project suitable for the DC control and protection field, and send this initial data path configuration data to the embedded platform. The embedded platform receives the initial data path configuration data from the visualization development platform and converts it into data path configuration data, such as binary data path configuration data. The embedded platform then sends the converted data path configuration data to the FPGA design platform. The FPGA design platform stores the data path configuration data. When the FPGA design platform receives the visualization implementation instruction, it retrieves the stored FPGA logic-related configuration data and data path configuration data.

[0074] S400 , establishing a mapping between the physical layer and the logical layer of a programmable logic device according to the data path configuration data and the logic association configuration data.

[0075] The physical layer of an FPGA generally refers to the underlying hardware structure and circuit design of the FPGA chip. It interfaces with external systems and carries functions such as input and output signals and power supply. Specifically, it includes hardware-related components such as the silicon chip, pins, device packaging, and circuit boards. The physical layer involves mapping logic circuits to the physical resources of the FPGA chip, including how to rationally utilize available logic units, registers, and wiring resources to achieve the designed functions and performance requirements. The logic layer of an FPGA refers to the logic circuits formed by connecting basic logic units such as LUTs (Look-Up Tables) and registers according to a specific netlist. It is the core of the FPGA's implementation of specific functions. Programming the logic layer can implement various digital circuit functions, such as counters, multiplexers, and state machines. In this embodiment, the logic layer includes multiple logic blocks that have been pre-implemented through FPGA code based on functional requirements. These logic blocks have already implemented the corresponding logic circuits. Specifically, the logic blocks may include communication logic blocks, functional logic blocks, and sampling processing logic blocks.

[0076] In specific implementation, after the platform obtains the logical association configuration data and data path configuration data, it can connect the FPGA based on the data path configuration data and the logical association configuration data, realize the connection between resources such as programmable logic units and programmable input units / output units in the FPGA, establish the mapping of the physical layer and the logical layer of the FPGA, and realize the decoupling of the physical layer and the logical layer.

[0077] The above-mentioned visual programming implementation method for programmable logic devices is different from the method of converting the language of the written logic code through a synthesis tool to obtain the connection relationship configuration data of the programmable logic device. Instead, the data path configuration data obtained by converting the initial data path configuration data by the embedded platform is directly obtained without the need for language conversion. In addition, by pre-building instantiated logic blocks, a mapping of the physical layer and the logical layer can be established based on the logical association configuration data and the data path configuration data, separating the underlying hardware devices from the upper-level application programs, and realizing the decoupling and configurability of the physical layer and the logical layer. When the functional requirements change, the application function can be changed by modifying the configuration items of the logic block, thereby improving the efficiency of data updating. It is also applicable to engineering sites with complex and changing functional requirements and has greater flexibility and versatility.

[0078] As shown in FIG3 , in some embodiments, the method further includes: S100 , obtaining hierarchical division data of the programmable logic device, and dividing the interface layer of the programmable logic device into a physical layer, a logical association layer, and a logical layer according to the hierarchical division data.

[0079] Hierarchical partitioning data refers to data used to divide programmable logic devices into different levels. In this embodiment, in the visual implementation framework of FPGA layer extraction and stratification, the FPGA chip can be divided into a physical layer, a logical association layer, and a logical layer based on the hierarchical partitioning data. Among them, the logical association layer serves as a bridge between the physical layer and the logical layer, providing a configuration for converting the logic design into the underlying physical resources, thereby realizing the mapping of the logic design with the actual hardware resources on the FPGA chip. Through the logical association layer, developers can connect logic elements (such as logic gates, registers, etc.), registers, and timing information (such as clock signals) with the underlying physical resources (such as lookup tables, triggers, connection resources, etc.). Through this connection, designers can design and program on the logical layer, and then map these designs to the physical resources of the FPGA chip to realize the required functions and logic.

[0080] In the technical solution of the embodiment of the present application, the programmable logic device is divided into a physical layer, a logical association layer and a logical layer by hierarchical division data, and the logical association layer is used as a bridge to achieve mapping and decoupling of the physical layer and the logical association layer.

[0081] As shown in FIG3 , in some embodiments, S400 includes:

[0082] S420, establishing mapping between the physical mapping layer, the communication interface layer, the data exchange interface layer and the logical layer according to the data path configuration data and the logical association configuration data; the physical layer includes the physical mapping layer, the communication interface layer and the data exchange interface layer.

[0083] In this embodiment, the physical layer is designed based on the functional requirements of the DC control and protection field, primarily encompassing control functions, protection functions, and internal and external communication. Specifically, it comprises a physical mapping layer, a communication interface layer, and a data exchange interface layer. The physical mapping layer converts the logic design into hardware circuits. Its primary function is to map the user-provided logic design onto programmable logic units and other hardware resources, generating physical circuits corresponding to the logic design. The communication interface layer handles communication and data exchange with external devices. Specifically, the communication interface layer converts data from various devices into a format that the FPGA can internally recognize and process, while also converting data within the FPGA into the format required by external devices. Furthermore, the communication interface layer typically includes a buffer area to implement flow control during data transmission, ensuring smooth and reliable data transmission. The data exchange interface layer provides a standard data transmission interface for communication between different internal modules. Specifically, the data exchange interface layer provides functions such as data conversion, data buffering, and data verification.

[0084] During specific implementation, the logical association configuration data includes the association configuration data between the physical mapping layer, the communication interface layer, and the data exchange interface layer and the logical layer. Through the data path configuration data and the logical association configuration data, the mapping between the logical layer and the physical mapping layer, the communication interface layer, and the data exchange interface layer can be established respectively. In practical applications, it is possible to pre-define the physical mapping definition layer, build general basic function blocks such as adders, multipliers, etc., build general input and output and parameter model interfaces, and build a general model resource pool. Pre-define the logic blocks in the logic layer and instantiate the logic blocks. Then, map the circuit elements (such as gates, triggers, etc.) on the logic layer to the physical elements on the FPGA chip, and perform layout and routing to establish a mapping between the physical mapping layer and the logic layer. Considering the efficiency and bandwidth limitations of data transmission, establish an interface from the logic layer to the physical layer to realize communication between the elements of the logic layer and the elements of the physical layer. Considering the relationship between data processing speed and data, an interface is established for data exchange between the logical layer and the physical layer, including input and output ports and intermediate variables, to establish a mapping between the data exchange interface layer and the logical layer. Commonly used data exchange interfaces include FIFO and DMA (Direct Memory Access).

[0085] In the technical solution of the embodiment of the present application, by dividing the physical layer into a physical mapping layer, a communication interface layer and a data exchange interface layer, and establishing a mapping between the physical mapping layer, the communication interface layer and the data exchange interface layer and the logical layer, the coupling degree between the modules can be reduced, making the modules more reusable and achieving higher resource utilization.

[0086] In some embodiments, the instantiated logic block includes a communication logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the communication logic block, as well as protocol parameters and protocol channel data of the communication interface layer.

[0087] As shown in Figure 4, S420 includes: S422, according to the data path configuration data, the input and output parameters and parameter model of the communication logic block are associated with the protocol parameters and protocol channel parameters of the communication interface layer, and a mapping between the communication interface layer and the communication logic block is established, wherein the parameter model is associated with the logic association configuration data.

[0088] The logic blocks of the logic layer include communication logic blocks, which are logic blocks used to implement data communication and can be multiple. Specifically, the communication logic block can be a communication protocol CBB (Common Building Blocks) group composed of multiple communication protocol function blocks. The logical association configuration data includes the input and output parameters and parameter model of the communication logic block, as well as the protocol parameters and protocol channel data of the communication interface layer. Among them, the parameter model is a parameter model determined based on factors such as the type of data transmitted, the transmission rate, and the transmission method. In this embodiment, the parameter model is associated with the communication-related logical association configuration data in the logical association layer. The protocol parameters include information such as data format, transmission rate, and checksum, and the protocol channel refers to the physical connection between the communication function module and other modules.

[0089] In specific implementations, establishing a mapping between the communication interface layer and the logic layer can involve associating the input and output parameters and parameter models of the communication logic block with the protocol parameters and protocol channel parameters of the communication interface layer based on the data path configuration data. This association process can be considered a matching and coordination process, enabling access to communication functions. The parameter models of the communication logic block are associated with the logical association configuration data to ensure smooth data exchange. As shown in Figure 5, based on the data path configuration data, the logical association layer can be used to establish a mapping between the input and output parameters and parameter models of the communication protocol CBB and the transmit and receive channels and communication parameters of the communication interface layer.

[0090] In the technical solution of the embodiment of the present application, by associating the input and output parameters and parameter model of the communication logic block with the protocol parameters and protocol channel parameters of the communication interface layer, a mapping between the communication interface layer and the communication logic block is established, which can facilitate the modification, expansion and reconstruction of the communication logic block and the communication interface layer, and achieve better compatibility between different platforms or systems.

[0091] In some embodiments, the instantiated logic block includes a functional logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the functional logic block, as well as signal data and data lines of a data exchange interface layer.

[0092] As shown in Figure 4, S420 includes: S424, associating the input and output parameters of the functional logic block with the data transceiver channel of the communication logic block, and associating the input and output parameters and parameter model of the functional logic block with the signal data and data lines of the data exchange interface layer, and establishing a mapping between the data exchange interface layer and the logic layer.

[0093] A functional logic block refers to a functional block used to implement logical control. In this embodiment, the functional logic block includes a functional logic CBB group and an algorithm strategy CBB group. Logical association configuration data includes the input and output parameters and parameter models of the functional logic block, as well as signal data and data lines at the data exchange interface layer. The input and output parameters of the functional logic block include the data width of the input signal and the data width of the output signal. The data width of the input signal includes the number of input ports and the bit width of each input port, while the data width of the output signal includes the number of output ports and the bit width of each output port. The parameter model of the functional logic block includes internal states such as the initial value of registers or counters, timing information such as clock frequency, power consumption delay, and other characteristics. Signal data at the data exchange interface layer includes synchronization signals, timing signals, and check signals. In the data exchange interface layer, signals are transmitted through the physical layer, and the data link layer uses these signals to identify the start and end positions of data frames and detect errors. Data lines include unidirectional, bidirectional, and multidirectional lines, and are designed based on different transmission rate, distance, and cost requirements.

[0094] During specific implementation, the mapping between the functional logic block and the data exchange interface layer can be established by associating the input and output parameters of the functional logic block with the data transceiver channel of the communication logic block. Specifically, the input port of the functional logic block can be connected to the data sending channel of the communication logic block, and the output port of the functional logic block can be connected to the data receiving channel of the communication logic block. In addition, the input and output parameters and parameter models of the functional logic block can be associated with the signal data and data lines of the data exchange interface layer, that is, the input parameters of the functional logic block are mapped to the corresponding data lines, and the reading of the output parameters is mapped to the corresponding data lines. In this way, the mapping between the data exchange interface layer and the communication logic block is established to realize the FPGA visualization data transmission and processing function.

[0095] In the technical solution of the embodiment of the present application, data transmission and processing functions are realized by establishing a mapping between the data exchange interface layer and the communication function logic block, so that each component has a high cohesion, reduces the coupling degree of the system, and thus improves the maintainability of the system.

[0096] In some embodiments, the physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block, and an application function data block.

[0097] As shown in Figure 4, S420 includes: S426, establishing the mapping relationship between the configuration data block, monitoring data block, sampling data block, control command data block and application function data block and the logical layer according to the logical function resource configuration data and data path configuration data of each data block in the logical association configuration data.

[0098] Logical function resource configuration data refers to the configuration data of logical function resources such as computer programs, algorithms, code libraries, and logic gates. The interface block of the physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block, and an application function data block. Among them, the configuration data block can also be called a configuration interface block. The configuration data block is a group of registers or memory units used to store the configuration information of the FPGA chip. In this embodiment, the configuration interface block includes a general configuration interface block and a dedicated configuration interface block, among which the general configuration interface block refers to a block for storing configuration data unrelated to business needs, and the dedicated configuration interface block refers to a block for storing configuration data related to business needs.

[0099] The monitoring data block is used to monitor the working status and performance parameters of the FPGA chip. It can provide data such as the temperature, voltage, clock frequency, power consumption, and various error and warning information of the FPGA chip.

[0100] The sampling data block is used to capture the output signal or internal state of the FPGA chip. Specifically, it can capture the input and output waveforms, counter values, state machine states, register contents and other data of the FPGA chip, and store them in the internal buffer for subsequent processing.

[0101] The control command data block is used to send control commands to the FPGA chip, such as control commands for starting / stopping operations, setting clock frequencies, resetting state machines, etc. It can be implemented through special registers or memory units.

[0102] The application function data block is the main logic portion of the FPGA chip, used to implement various application functions. It can contain multiple modules, such as the processor core, DMA controller, and graphics processor. In the physical mapping layer, the application function data block is typically split into multiple logical areas and mapped to different physical resources on the FPGA chip.

[0103] In practical applications, a corresponding general configuration interface block can be generated based on the number of external and internal communication links of the FPGA; a corresponding dedicated configuration interface block can be generated based on configuration parameters such as the algorithm of the FPGA control and protection application function; a general monitoring information data block can be generated based on the monitoring information requirements sent by the FPGA general function to the embedded software; a general sampling information data block can be generated based on the sampling information requirements sent by the FPGA control and protection application function to the embedded software; a corresponding control command data block can be generated based on the control command parameters received from the embedded software by the FPGA control and protection application function; and a corresponding application function data block can be generated based on the application data information sent to the embedded software by the FPGA control and protection application function. Then, based on the logical function resource configuration data and data path configuration data of each data block in the logical association configuration data, a mapping relationship between the configuration data block, the monitoring data block, the sampling data block, the control command data block, and the application function data block and the logical layer can be established. It is understandable that in order to ensure data interaction between the embedded platform and the FPGA design platform, the embedded platform also needs to be defined according to the FPGA's monitoring data block, acquisition data block, control command data block and application function data block, and generate model definition files such as input, output, and parameters of the above data blocks. The generated input, output, parameter and other model definition files are then sent to the host computer visualization development platform to instantiate the FPGA's function blocks.

[0104] Specifically, it is possible to predefine logic function configuration resources based on the number of general configuration interface blocks and special configuration interface blocks, and establish an association relationship between logic data output and general configuration interface blocks and special configuration interface blocks through wiring layout; predefine corresponding logic data resources based on the configuration capacity of general monitoring data blocks, sampling data blocks, and application function data blocks, and establish an association relationship between logic data output and general monitoring data blocks, sampling data blocks, and application function data blocks; predefine corresponding logic data resources based on the configuration capacity of control command data, and establish an association relationship between control command data input and logic data; predefine logical data resource channels for sending and receiving based on the configuration capacity of the communication interface layer, and establish an association between the receiving channel and logic data, as well as an association between logic data and the sending channel; and predefine logical data resource channels for sending and receiving based on the interface requirements of internal data exchange, and establish an association between the receiving channel and logic data, as well as an association between logic data and the sending channel. The above-mentioned predefined logic function configuration resources refer to allocating logic resources to different applications or tasks to provide the required functions for specific applications.

[0105] In the technical solution of the embodiment of the present application, by establishing a mapping relationship between the configuration data block, the monitoring data block, the sampling data block, the control command data block and the application function data block and the logical layer, the design and implementation complexity of the system can be simplified, the development efficiency can be improved, and it can also be flexibly configured and adjusted for different application scenarios.

[0106] In some embodiments, the configuration data block performs data read and write operations via RAM.

[0107] RAM memory generally refers to random access memory, which can be used for reading and writing data. In this embodiment, the configuration data block performs data reading and writing operations through RAM, which means that the data of the general configuration data block and the dedicated configuration data block are written to RAM, and when the data needs to be used, the data is read from RAM. In this way, data can be easily transferred between different devices without the need for chip-level hardware support. Furthermore, the storage capacity and data transmission rate can be dynamically adjusted according to the needs of the application, thereby enhancing flexibility. It is understandable that in other implementations, the configuration data block can also perform data reading and writing through memories other than RAM, including but not limited to RAM.

[0108] In the technical solution of the embodiments of the present application, by caching the data of the configuration data block in RAM, the number of data exchanges with external devices can be reduced, achieving high-speed, low-latency data transmission and processing. In addition, the RAM size, read and write speed and other parameters can be configured as needed to meet the needs of different application scenarios.

[0109] In some embodiments, the monitoring data block, the sampling data block, the control command data block, and the application function data block perform data reading and writing operations through the FIFO.

[0110] FIFO memory is a first-in-first-out data storage device for storing and reading data in the order in which data is input, and the data that first enters the memory is read out first. In the present embodiment, the monitoring data block, the sampling data block, the control command data block and the application function data block can be set to perform data read and write operations through the FIFO, that is, when the data in the monitoring data block, the sampling data block, the control command data block and the application function data block are generated, they are first written into the FIFO. When these data are needed, the data can be read from the FIFO, and after processing, the state of the corresponding position in the FIFO is marked as idle state so that the next data can be written. Specifically, the appropriate FIFO depth and width can be selected according to the actual application scenario and system requirements. FIFO can also be used for data flow control and synchronization, and can buffer input data to ensure the continuity and stability of the output data flow.

[0111] In the technical solution of the embodiment of the present application, data reading and writing operations are performed in a FIFO manner, which can better control and synchronize data flow, and can also dynamically adjust the storage capacity and data transmission rate according to the needs of the application, thereby enhancing flexibility.

[0112] In order to more clearly illustrate the visual programming implementation method of the programmable logic device provided by the present application, the following is described with reference to Figures 6 and 7 and a specific embodiment, which includes the following steps:

[0113] S100 , obtaining hierarchical division data of a programmable logic device, and dividing the interface layer of the programmable logic device into a physical layer, a logical association layer, and a logical layer according to the hierarchical division data.

[0114] As shown in Figure 7, the FPGA visual framework diagram includes the physical layer, the logical association layer, and the logical layer. The physical layer includes the physical mapping layer, the communication interface layer, and the data exchange interface layer. The physical mapping layer includes multiple general configuration data blocks (also called general configuration interface blocks), dedicated configuration data blocks (also called dedicated configuration interface blocks), monitoring data blocks, sampling data blocks, control command data blocks, and application function data blocks. The logical layer includes multiple instantiated logic blocks and IP function cores, such as the communication protocol CBB group, the functional logic CBB group, the algorithm strategy CBB group, and the sampling and processing CBB group. The communication protocol CBB group belongs to the communication logic block, while the functional logic CBB group and the algorithm strategy CBB group belong to the functional logic block.

[0115] S200: Acquire logic association configuration data and data path configuration data of a programmable logic device.

[0116] The logical association configuration data includes the input and output parameters and parameter models of the communication function logic block, the input and output parameters and parameter models of the functional logic block, the communication protocol and communication channel data of the communication interface layer, and the signal data and data line data of the data exchange interface layer.

[0117] S422, according to the data path configuration data, associate the input and output parameters and parameter model of the communication logic block with the protocol parameters and protocol channel parameters of the communication interface layer, and establish a mapping between the communication interface layer and the communication logic block, wherein the parameter model is associated with the logic association configuration data.

[0118] S424, associate the input and output parameters of the functional logic block with the data transceiver channel of the communication logic block, and associate the input and output parameters and parameter model of the functional logic block with the signal data and data lines of the data exchange interface layer, and establish a mapping between the data exchange interface layer and the logic layer.

[0119] S426, establishing mapping relationships between configuration data blocks, monitoring data blocks, sampling data blocks, control command data blocks, and application function data blocks and the logical layer based on the logical function resource configuration data and data path configuration data of each data block in the logical association configuration data.

[0120] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0121] Based on the same inventive concept, embodiments of the present application also provide a visual programming implementation device for a programmable logic device for implementing the aforementioned visual programming implementation method for a programmable logic device. The implementation solution provided by this device is similar to the implementation solution described in the aforementioned method. Therefore, the specific limitations of the embodiments of the visual programming implementation device for one or more programmable logic devices provided below can be found in the limitations of the visual programming implementation method for a programmable logic device described above and will not be repeated here.

[0122] In some embodiments, as shown in FIG8 , a visual programming implementation apparatus 800 for a programmable logic device is provided, including: a data acquisition module 810 and a data mapping module 820 , wherein:

[0123] The data acquisition module 810 is used to acquire the logic association configuration data and data path configuration data of the programmable logic device.

[0124] The data mapping module 820 is used to establish a mapping between the physical layer and the logical layer of the programmable logic device according to the data path configuration data and the logic association configuration data.

[0125] The logic layer includes a plurality of instantiated logic blocks, and the data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

[0126] The above-mentioned visual programming implementation device for programmable logic devices is different from the traditional method of converting the language of the written logic code through a synthesis tool to obtain the connection relationship configuration data of the programmable logic device. Instead, the data path configuration data obtained by converting the initial data path configuration data by the embedded platform is directly obtained without language conversion. In addition, by pre-building instantiated logic blocks, a mapping of the physical layer and the logical layer can be established based on the logical association configuration data and the data path configuration data, separating the underlying hardware devices from the upper-level application programs, realizing the decoupling and configurability of the physical layer and the logical layer. When the functional requirements change, the application function can be changed by modifying the configuration items of the logic block, thereby improving the data update efficiency. It is also applicable to engineering sites with complex and changing functional requirements, and has greater flexibility and versatility.

[0127] In some embodiments, the data mapping module 820 is also used to establish a mapping between the physical mapping layer, the communication interface layer, and the data exchange interface layer and the logical layer based on the data path configuration data and the logical association configuration data; the physical layer includes the physical mapping layer, the communication interface layer, and the data exchange interface layer.

[0128] In some embodiments, the instantiated logic block includes a communication logic block, and the logic-associated configuration data includes input and output parameters and a parameter model of the communication logic block, and protocol parameters and protocol channel data of a communication interface layer;

[0129] The data mapping module 820 is also used to associate the input and output parameters and parameter model of the communication logic block with the protocol parameters and protocol channel parameters of the communication interface layer according to the data path configuration data, and establish a mapping between the communication interface layer and the communication logic block, wherein the parameter model is associated with the logic association configuration data.

[0130] In some embodiments, the instantiated logic block includes a functional logic block, and the logic-associated configuration data includes input and output parameters and parameter models of the functional logic block, as well as signal data and data lines of a data exchange interface layer;

[0131] The data mapping module 820 is also used to associate the input and output parameters of the functional logic block with the data transceiver channel of the communication logic block, and to associate the input and output parameters and parameter model of the functional logic block with the signal data and data lines of the data exchange interface layer, so as to establish a mapping between the data exchange interface layer and the logic layer.

[0132] In some embodiments, the physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block, and an application function data block;

[0133] The data mapping module 820 is also used to establish mapping relationships between configuration data blocks, monitoring data blocks, sampling data blocks, control command data blocks and application function data blocks and logical layers according to the logical function resource configuration data and data path configuration data of each data block in the logical association configuration data.

[0134] As shown in FIG9 , in some embodiments, the apparatus further includes a hierarchical division module 802 for acquiring hierarchical division data of the programmable logic device, and dividing the interface layer of the programmable logic device into a physical layer, a logical association layer, and a logical layer according to the hierarchical division data.

[0135] Each module in the visual programming implementation apparatus for a programmable logic device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0136] In some embodiments, a computer device is provided, which may be a terminal. A diagram of its internal structure may be shown in FIG10 . The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external terminals via wired or wireless communication, where the wireless communication may be achieved via Wi-Fi, a mobile cellular network, NFC (near-field communication), or other technologies. When executed by the processor, the computer program implements a method for visual programming of a programmable logic device. The display unit of the computer device is configured to produce a visually visible image and may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse.

[0137] Those skilled in the art will understand that the structure shown in FIG10 is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0138] In some embodiments, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of the above-mentioned method for implementing visual programming of a programmable logic device are implemented.

[0139] In some embodiments, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned visual programming implementation method of the programmable logic device are implemented.

[0140] In some embodiments, a computer program product is provided, including a computer program, which implements the steps in the above-mentioned method for implementing visual programming of a programmable logic device when executed by a processor.

[0141] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions.

[0142] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in the various embodiments provided herein may be, but are not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, and the like.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A method for implementing visual programming of a programmable logic device, the method comprising: Acquiring logic association configuration data and data path configuration data of a programmable logic device; Establishing a mapping between a physical layer and a logical layer of the programmable logic device according to the data path configuration data and the logic association configuration data; The logic layer includes a plurality of instantiated logic blocks, and the data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

2. The method according to claim 1, wherein: The step of establishing a mapping between a physical layer and a logical layer of the programmable logic device according to the data path configuration data and the logic association configuration data comprises: According to the data path configuration data and the logic association configuration data, a mapping between the physical mapping layer, the communication interface layer and the data exchange interface layer and the logic layer is established; the physical layer includes the physical mapping layer, the communication interface layer and the data exchange interface layer.

3. The method according to claim 2, wherein: The instantiated logic block includes a communication logic block, and the logic association configuration data includes input and output parameters and parameter models of the communication logic block, and protocol parameters and protocol channel data of the communication interface layer; Establishing a mapping between a communication interface layer and the logic layer according to the data path configuration data and the logic association configuration data includes: According to the data path configuration data, the input and output parameters and parameter model of the communication logic block are associated with the protocol parameters and protocol channel parameters of the communication interface layer, and a mapping between the communication interface layer and the communication logic block is established, wherein the parameter model is associated with the logic association configuration data.

4. The method according to claim 3, wherein: The instantiated logic block includes a functional logic block, and the logic association configuration data includes input and output parameters and parameter models of the functional logic block, and signal data and data lines of the data exchange interface layer; Establishing a mapping between a data exchange interface layer and the logic layer according to the data path configuration data and the logic association configuration data includes: The input and output parameters of the functional logic block are associated with the data transceiver channel of the communication logic block, and the input and output parameters and parameter model of the functional logic block are associated with the signal data and data lines of the data exchange interface layer to establish a mapping between the data exchange interface layer and the logic layer.

5. The method according to claim 2, wherein: The physical mapping layer includes a configuration data block, a monitoring data block, a sampling data block, a control command data block and an application function data block; Establishing the mapping between the physical mapping layer and the logical layer according to the data path configuration data and the logical association configuration data includes: According to the logical function resource configuration data of each data block in the logical association configuration data and the data path configuration data, a mapping relationship between the configuration data block, the monitoring data block, the sampling data block, the control command data block and the application function data block and the logical layer is established respectively.

6. The method according to claim 5, wherein: The configuration data block performs data reading and writing operations through the RAM.

7. The method according to claim 5, wherein: The monitoring data block, the sampling data block, the control command data block and the application function data block perform data reading and writing operations through FIFO.

8. The method according to any one of claims 1 to 7, further comprising: Obtaining hierarchical partitioning data of programmable logic devices; According to the hierarchical division data, the interface layer of the programmable logic device is divided into a physical layer, a logic association layer and a logic layer.

9. A visual programming implementation device for a programmable logic device, the device comprising: A data acquisition module, used to acquire logic association configuration data and data path configuration data of a programmable logic device; A data mapping module, used to establish a mapping between the physical layer and the logical layer of the programmable logic device according to the data path configuration data and the logic association configuration data; The logic layer includes a plurality of instantiated logic blocks, and the data path configuration data is obtained by converting the initial data path configuration data generated by the visualization development platform by the connected embedded platform.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method according to any one of claims 1 to 8 when executing the computer program.

11. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 8.

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