Semiconductor device manufacturing method

Abstract

The present application relates to the technical field of semiconductors, and particularly discloses a semiconductor device manufacturing method, comprising: forming, on a substrate, a first stack structure and a second stack structure which are spaced from each other, wherein the first stack structure and the second stack structure each comprise first semiconductor layers and second semiconductor layers which are alternately stacked; providing an isolation wall and sacrificial layers between the first stack structure and the second stack structure, wherein the sacrificial layers are located on two sides of the isolation wall so as to respectively isolate the partition wall from the first stack structure and the second stack structure, and the sacrificial layers have high etching selectivity relative to the first semiconductor layers or the second semiconductor layers; removing either the first semiconductor layers or the second semiconductor layers, and the sacrificial layers; and forming a gate structure around the other of the first semiconductor layers and the second semiconductor layers. According to the present application, an isolation wall and sacrificial layers are formed in the isolation trench, and the sacrificial layers are removed by means of a subsequent etching process, so as to form a gate structure surrounding the entire channel area, achieving less DIBL, achieving better control on leakage current of semiconductor devices.

Description

Method for manufacturing semiconductor device Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a method for manufacturing a semiconductor device. Background Art

[0002] In order to meet the challenges of shrinking critical dimensions and increasing device density of semiconductor devices, a forksheet transistor structure has been proposed. This structure introduces an isolation wall structure between two transistors to further shorten the distance between the two transistors.

[0003] However, in a conventional forksheet structure, the channel regions of the two transistors are attached to both sides of the isolation wall. When a gate structure is subsequently formed outside the channel region, the gate structure can only surround three sides of the channel region. In the 3nm and finer semiconductor manufacturing processes, it is difficult to achieve a smaller drain-induced barrier lowering (DIBL).

[0004] Summary of the Invention

[0005] The embodiment of the present application discloses a method for manufacturing a semiconductor device to solve the problem of large DIBL of semiconductor devices in related technologies.

[0006] In order to solve the above technical problems, the present invention discloses a method for manufacturing a semiconductor device, comprising:

[0007] forming a first stacked structure and a second stacked structure spaced apart from each other on a substrate, wherein the first stacked structure and the second stacked structure respectively include first semiconductor layers and second semiconductor layers that are alternately stacked;

[0008] Filling an isolation wall and a sacrificial layer between the first stacked structure and the second stacked structure, the sacrificial layer being located on both sides of the isolation wall to separate the isolation wall from the first stacked structure and the second stacked structure, respectively, and the sacrificial layer having a high etching selectivity with respect to the first semiconductor layer or the second semiconductor layer;

[0009] removing one of the first semiconductor layer and the second semiconductor layer and the sacrificial layer;

[0010] A gate structure is formed around the other of the first semiconductor layer and the second semiconductor layer.

[0011] As some optional implementation manners, forming a first stacked structure and a second stacked structure spaced apart from each other on a substrate includes:

[0012] forming the first semiconductor layers and the second semiconductor layers alternately stacked on the substrate;

[0013] The alternately stacked first semiconductor layers and the second semiconductor layers are etched to form isolation trenches, which separate the alternately stacked first semiconductor layers and the second semiconductor layers into the first stacked structure and the second stacked structure. The first stacked structure is used to form a first semiconductor device, and the second stacked structure is used to form a second semiconductor device.

[0014] As some optional implementation manners, filling an isolation wall and a sacrificial layer between the first stacked structure and the second stacked structure includes:

[0015] forming a liner layer covering the sidewalls and bottom surface of the isolation trench;

[0016] forming the isolation wall on the liner layer to fill the isolation trench;

[0017] removing at least a portion of the liner layer located on a sidewall of the isolation trench to form a cavity;

[0018] The cavity is filled with the sacrificial layer.

[0019] As some optional implementations, removing at least a portion of the liner layer located on the sidewall of the isolation trench to form a cavity includes:

[0020] removing at least a portion of the liner layer between the isolation wall and the first stacked structure to form a first cavity; and

[0021] removing at least a portion of the liner layer between the isolation wall and the second stacked structure to form a second cavity;

[0022] Filling the cavity with the sacrificial layer comprises:

[0023] filling the first cavity with a first sub-sacrificial layer, the first sub-sacrificial layer having a high etching selectivity with respect to one of the first semiconductor layer and the second semiconductor layer; and

[0024] The second cavity is filled with a second sacrificial sub-layer having a high etching selectivity ratio with respect to the other of the first semiconductor layer and the second semiconductor layer.

[0025] As some optional implementations, the sacrificial layer includes a first sub-sacrificial layer and a second sub-sacrificial layer;

[0026] The first sub-sacrificial layer is located between the isolation wall and the first stacked structure to separate the isolation wall from the first stacked structure, and the first sub-sacrificial layer has a high etching selectivity with respect to one of the first semiconductor layer and the second semiconductor layer;

[0027] The second sub-sacrificial layer is located between the isolation wall and the second stacked structure to separate the isolation wall and the second stacked structure, and the second sub-sacrificial layer has a high etching selectivity relative to the other of the first semiconductor layer and the second semiconductor layer.

[0028] As some optional embodiments, the material of the first sub-sacrificial layer is the same as that of one of the first semiconductor layer and the second semiconductor layer;

[0029] A material of the second sacrificial sub-layer is the same as that of the other of the first semiconductor layer and the second semiconductor layer.

[0030] As some optional embodiments, the first semiconductor layer is Si, and the second semiconductor layer is SiGe;

[0031] The first sub-sacrificial layer is one of polycrystalline Si and polycrystalline SiGe;

[0032] The second sacrificial sub-layer is the other of poly-Si and poly-SiGe.

[0033] As some optional embodiments, the first semiconductor layer has a high etching selectivity with respect to the second semiconductor layer; or

[0034] The second semiconductor layer has a high etching selectivity ratio with respect to the first semiconductor layer.

[0035] As some optional embodiments, the material of the sacrificial layer is the same as that of the first semiconductor layer or the second semiconductor layer;

[0036] When the material of the sacrificial layer is the same as that of the first semiconductor layer, the sacrificial layer and the first semiconductor layer have a high etching selectivity with respect to the second semiconductor layer, and the removing of one of the first semiconductor layer and the second semiconductor layer and the sacrificial layer comprises: removing the first semiconductor layer and the sacrificial layer;

[0037] When the material of the sacrificial layer is the same as that of the second semiconductor layer, the sacrificial layer and the second semiconductor layer have a high etching selectivity relative to the first semiconductor layer, and the removal of one of the first semiconductor layer and the second semiconductor layer and the sacrificial layer includes: removing the second semiconductor layer and the sacrificial layer.

[0038] As some optional embodiments, the first semiconductor layer is Si, and the second semiconductor layer is SiGe;

[0039] The sacrificial layer is polycrystalline Si or polycrystalline SiGe.

[0040] As some optional implementations, at least a portion of the liner layer located on the sidewall of the isolation trench is removed by a dry or wet etching process;

[0041] There is a high etching selectivity between the liner layer and the isolation wall; and

[0042] The sacrificial layer and the isolation wall have a high etching selectivity ratio.

[0043] As some optional implementation manners, before removing one of the first semiconductor layer and the second semiconductor layer and the sacrificial layer, the method further includes:

[0044] A source region and a drain region are formed on both sides of the first stacked structure and the second stacked structure along a second direction, the second direction being perpendicular to the first direction, and the first direction being the arrangement direction of the first stacked structure and the second stacked structure.

[0045] As some optional implementation manners, forming a source region and a drain region on both sides of the first stacked structure and the second stacked structure along the second direction includes:

[0046] removing one of the first semiconductor layer and the second semiconductor layer by a predetermined thickness along the second direction;

[0047] filling the removed one of the first semiconductor layer and the second semiconductor layer with an insulating layer;

[0048] Epitaxial growth is performed on the surface of the other of the first semiconductor layer and the second semiconductor layer to form the source region and the drain region.

[0049] In the manufacturing method of the semiconductor device of the embodiment of the present application, by forming an isolation wall and a sacrificial layer in the isolation trench and removing the sacrificial layer through a subsequent etching process, a gate structure surrounding the entire channel region can be formed, which can achieve a smaller DIBL and better control the leakage current of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0051] FIG2 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0052] FIG3 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0053] FIG4 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0054] FIG5 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0055] FIG6 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0056] FIG7 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0057] FIG8 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0058] 9 to 12 are schematic diagrams respectively showing one of the various stages of a method for manufacturing a semiconductor device according to another embodiment of the present application;

[0059] FIG13 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0060] FIG14 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0061] 15A and 15B are schematic diagrams showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0062] 16A and 16B are schematic diagrams showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0063] 17A and 17B are schematic diagrams showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0064] 18A and 18B are schematic diagrams showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0065] 19A and 19B are schematic diagrams showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0066] FIG. 20 is a schematic diagram showing one of the various stages of the method for manufacturing a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0067] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0068] It should be understood by those skilled in the art that the embodiments of the present application are merely illustrations of the structures and methods for which the present application may be implemented in various forms. In addition, each example provided in conjunction with the various embodiments is intended to be illustrative, not restrictive. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show the details of specific components. Therefore, the specific structural and functional details in the embodiments of the present application should not be interpreted as restrictive, but merely as a representative basis for teaching those skilled in the art to adopt the methods and structures of the embodiments of the present application in different ways. It should also be noted that identical and corresponding elements are represented by the same reference numerals.

[0069] In the following description, many specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it should be understood by those skilled in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0070] For the purposes of the following description, the terms "upper," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall relate to the orientation of the structures and methods disclosed in the drawings of the specification. It will be understood that when an element as a layer, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements between the two. It will also be understood that when an element is referred to as being "under" another element, the element can be directly under the other element or intervening elements may be present. Conversely, when an element is referred to as being "directly under" another element, there are no intervening elements between the two.

[0071] The technical solutions disclosed in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0072] An embodiment of the present application provides a method for manufacturing a semiconductor device, as shown in FIG1 , which may include the following steps.

[0073] S110. Form a first stacked structure and a second stacked structure spaced apart from each other on a substrate.

[0074] As shown in FIG3 , a first stacked structure 200A and a second stacked structure 200B are formed on a substrate 100. The first stacked structure 200A and the second stacked structure 200B respectively include alternating first semiconductor layers 110 and second semiconductor layers 120. In some optional embodiments, the first stacked structure 200A and the second stacked structure 200B may be separated by, for example, an isolation trench 130.

[0075] The substrate 100 includes a single crystal semiconductor layer on at least a portion of its surface. The substrate 100 may include a single crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some optional embodiments, the substrate 100 may be made of crystalline Si. The substrate 100 may include one or more buffer layers (not shown) in its surface region. The buffer layer may be used to gradually change the lattice constant from that of the substrate to that of the source / drain region. The buffer layer may be formed of an epitaxially grown single crystal semiconductor material, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In some optional embodiments, the substrate 100 may include a silicon germanium (SiGe) buffer layer epitaxially grown on a silicon substrate. Substrate 100 may also include various regions that have been appropriately doped with impurities (eg, p-type or n-type conductivity).

[0076] The first semiconductor layer 110 and the second semiconductor layer 120 can be made of materials with different lattice constants and can include one or more layers of Si, Ge, SiGe, GeSn, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In some optional embodiments, the first semiconductor layer 110 and the second semiconductor layer 120 are made of Si, Si compounds, SiGe, Ge or Ge compounds. In some optional embodiments, the first semiconductor layer 110 is Si and the second semiconductor layer 120 is SiGe. In other optional embodiments, the first semiconductor layer 110 can also be SiGe, and the Ge content of the first semiconductor layer 110 and the second semiconductor layer 120 is different. For the sake of simplicity, this document describes the embodiments of the present application in detail by taking the first semiconductor layer 110 as Si and the second semiconductor layer 120 as SiGe as an example.

[0077] It should be noted that, in the subsequent etching process, the first semiconductor layer 110 has a high etching selectivity relative to the second semiconductor layer 120, or the second semiconductor layer 120 has a high etching selectivity relative to the first semiconductor layer 110, so that the first semiconductor layer 110 or the second semiconductor layer 120 can be selectively removed. Here, high etching selectivity refers to an etching selectivity greater than 10, preferably greater than 50, and more preferably greater than 100, so that the selective etching process can be accurately performed, and while removing one of the first semiconductor layer 110 and the second semiconductor layer 120, damage to the other of the first semiconductor layer 110 and the second semiconductor layer 120 is minimized.

[0078] In this embodiment, the first stacked structure 200A is used to form a first semiconductor device, and the second stacked structure 200B is used to form a second semiconductor device. The first and second semiconductor devices may be, for example, field-effect transistors. For example, in which the first semiconductor layer 110 is Si and the second semiconductor layer 120 is SiGe, when the first semiconductor layer 110 is removed from the semiconductor device to be formed and the second semiconductor layer 120 remains, the semiconductor device can function as a P-type semiconductor device. When the second semiconductor layer 120 is removed from the semiconductor device to be formed and the first semiconductor layer 110 remains, the semiconductor device can function as an N-type semiconductor device.

[0079] In the example of FIG3 , the first semiconductor layer 110 and the second semiconductor layer 120 in the first stacked structure 200A and the second stacked structure 200B are arranged in the same layer. In some optional implementations of the embodiment of the present application, the first semiconductor layer 110 and the second semiconductor layer 120 in the first stacked structure 200A and the second stacked structure 200B may be arranged in staggered layers, that is, the first semiconductor layer 110 in the first stacked structure 200A and the second semiconductor layer 120 in the second stacked structure 200B are located at the same horizontal plane, and the second semiconductor layer 120 in the first stacked structure 200A and the first semiconductor layer 110 in the second stacked structure 200B are located at the same horizontal plane.

[0080] In some optional implementations of the embodiments of the present application, the above step S110 may include:

[0081] S111. Forming a first semiconductor layer and a second semiconductor layer alternately stacked on a substrate.

[0082] As shown in FIG. 2 , first semiconductor layers 110 and second semiconductor layers 120 are alternately stacked and formed on a substrate 100 .

[0083] S112 . Etch the alternately stacked first semiconductor layers and second semiconductor layers to form isolation trenches.

[0084] As shown in FIG3 , an isolation trench 130 is formed in the alternating stack of the first semiconductor layer 110 and the second semiconductor layer 120 by an etching process, and the isolation trench 130 separates the first stacked structure 200A for forming the first semiconductor device and the second stacked structure 200B for forming the second semiconductor device. As some optional implementations of the embodiments of the present application, the first semiconductor device and the second semiconductor device can be of the same conductivity type, for example, both are N-type semiconductor devices or P-type semiconductor devices. In other optional implementations, the first semiconductor device and the second semiconductor device can also be of different conductivity types, for example, the first semiconductor device is an N-type semiconductor device and the second semiconductor device is a P-type semiconductor device. In some optional implementations of the embodiments of the present application, the isolation trench 130 can extend deep into the substrate 100, as shown in FIG3 , so that it can serve as a shallow trench isolation (STI) structure to isolate the two semiconductor devices.

[0085] S120. Filling an isolation wall and a sacrificial layer between the first stacked structure and the second stacked structure.

[0086] As shown in FIG7 , an isolation wall 132 and a sacrificial layer 134 are formed between the first stacked structure 200A and the second stacked structure 200B, filling the space between the first stacked structure 200A and the second stacked structure 200B. The sacrificial layer 134 is located on both sides of the isolation wall 132 to separate the isolation wall 132 from the first stacked structure 200A and the second stacked structure 200B, respectively. In other words, both sides of the isolation wall 132 are separated from the first stacked structure 200A and the second stacked structure 200B by the sacrificial layer 134. To ensure that the sacrificial layer 134 is removed along with the first semiconductor layer 110 or the second semiconductor layer 120 in a subsequent etching process, the sacrificial layer 134 needs to have a high etching selectivity relative to the first semiconductor layer 110 or the second semiconductor layer 120.

[0087] In some optional implementations of the embodiment of the present application, the above step S120 may include:

[0088] S121. Form a liner layer covering the sidewalls and bottom surface of the isolation trench.

[0089] 4 , a liner layer 131 may be formed by CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes to cover the top, bottom, and sidewalls of the isolation trench 130. In some alternative embodiments, the liner layer 131 may be silicon oxide, such as formed by an ALD process.

[0090] S122. Form an isolation wall on the liner layer to fill the isolation trench.

[0091] As shown in FIG5 , an isolation wall 132 is formed on the liner layer 131, thereby filling the isolation trench 130. In this step, the isolation wall 132 can be formed, for example, by a process such as ALD or CVD. The isolation wall 132 can be made of silicon nitride, aluminum oxide, hafnium oxide (HfO2), or other high-k dielectric materials. Although not shown in the figure, those skilled in the art will understand that after the isolation wall 132 is formed to fill the isolation trench 130, the liner layer 131 and the isolation wall 132 outside the isolation trench 130 can be removed by a process such as etching or chemical mechanical polishing (CMP), thereby obtaining the semiconductor structure shown in FIG5 .

[0092] S123. Remove at least a portion of the liner layer located on the sidewalls of the isolation trench to form a cavity.

[0093] As shown in FIG6 , at least a portion of the liner layer 131 on the sidewalls of the isolation trench 130 is removed to form a cavity 133. In the example of FIG6 , a portion of the liner layer 131 on the sidewalls of the isolation trench 130 is removed, and the cavity 133 extends below the surface of the substrate 100. Of course, the entire liner layer 131 on the sidewalls of the isolation trench 130 can also be removed.

[0094] In some optional implementations of the present invention, since it is necessary to avoid damage to the isolation wall 132 when etching the liner layer 131, a high etching selectivity ratio is achieved between the liner layer 131 and the isolation wall 132. Therefore, a dry etching process can be used to perform step S123. For example, a lower chamber pressure can be used to increase the free path of the etching plasma, thereby extending the cavity 133 below the surface of the substrate 100. In other optional implementations of the present invention, a wet etching process can be used to perform step S123.

[0095] S124. Fill the cavity with a sacrificial layer.

[0096] 7 , the cavity 133 is filled with the sacrificial layer 134. In this step, a lower chamber pressure may be used to increase the free path of the deposition plasma so that the cavity 133 can be fully filled.

[0097] In some optional implementations of the embodiments of the present application, a high etching selectivity ratio is achieved between the sacrificial layer 134 and the isolation wall 132. To this end, the sacrificial layer 134 can be made of the same material as the first semiconductor layer 110 or the second semiconductor layer 120. Specifically, when the material of the sacrificial layer 134 is the same as that of the first semiconductor layer 110, the sacrificial layer 134 and the first semiconductor layer 110 have a high etching selectivity ratio relative to the second semiconductor layer 120, so that in a subsequent etching process, the sacrificial layer 134 is removed together with the first semiconductor layer 110. When the material of the sacrificial layer 134 is the same as that of the second semiconductor layer 120, the sacrificial layer 134 and the second semiconductor layer 120 have a high etching selectivity ratio relative to the first semiconductor layer 110, so that in a subsequent etching process, the sacrificial layer 134 and the second semiconductor layer 120 are removed together. Furthermore, while removing the sacrificial layer 134 and the first semiconductor layer 110 or the second semiconductor layer 120, it is necessary to prevent the isolation wall 132 from being etched. Based on the above considerations, in this embodiment, the material of a portion of the liner layer 131 is replaced with the material of the sacrificial layer 134 , so as to achieve subsequent selective etching.

[0098] In some more specific optional implementations of the embodiments of the present application, the first semiconductor layer 110 is Si, the second semiconductor layer 120 is SiGe, and the sacrificial layer 134 is polycrystalline Si or polycrystalline SiGe. When the sacrificial layer 134 is polycrystalline Si, the sacrificial layer 134 is removed together with the first semiconductor layer 110 in the subsequent etching process; when the sacrificial layer 134 is polycrystalline SiGe, the sacrificial layer 134 is removed together with the second semiconductor layer 110 in the subsequent etching process. Specifically, the step of filling the cavity 133 with the sacrificial layer 134 may include: filling the cavity 133 with amorphous Si or amorphous SiGe; and annealing the amorphous Si or amorphous SiGe to form polycrystalline Si or polycrystalline SiGe. For example, the cavity 133 may be filled with amorphous Si or amorphous SiGe using an LPCVD process, and then the filled amorphous Si or amorphous SiGe is subjected to a high-temperature annealing process to recrystallize the amorphous Si or amorphous SiGe into polycrystalline Si or polycrystalline SiGe.

[0099] S130. Form source regions and drain regions of the first semiconductor device and the second semiconductor device. To avoid blurring the main concept of the present application, this step will be described in detail below.

[0100] S140 . Remove one of the first semiconductor layer and the second semiconductor layer and the sacrificial layer.

[0101] In the example of FIG8 , the second semiconductor layer 120 and the sacrificial layer 134 in the first stacked structure 200A and the second stacked structure 200B are removed, leaving only the first semiconductor layer 110. As described above, the first semiconductor layer 110 may be, for example, Si, the second semiconductor layer 120 may be, for example, SiGe, and the sacrificial layer 134 may be, for example, polycrystalline SiGe. In the etching process of this step, by achieving a high etching selectivity between SiGe and Si, the second semiconductor layer 120 and the sacrificial layer 134 are removed, leaving only the first semiconductor layer 110, thereby forming two N-type semiconductor devices through subsequent processes. However, the present application is not limited to this. In some optional embodiments, the first semiconductor layer 110 may be, for example, Si, the second semiconductor layer 120 may be, for example, SiGe, and the sacrificial layer 134 may be, for example, polycrystalline Si. In this case, by achieving a high etching selectivity between Si and SiGe in the etching process, the first semiconductor layer 110 and the sacrificial layer 134 are removed, leaving only the second semiconductor layer 120, thereby forming two P-type semiconductor devices through subsequent processes. At the same time, since it is also necessary to avoid damaging the isolation wall 132 when removing the sacrificial layer 134 , a high etching selectivity ratio is required between the sacrificial layer 134 and the isolation wall 132 .

[0102] In some alternative embodiments of the present application, as shown in FIG9 to FIG12 , the sacrificial layers on both sides of the isolation wall 132 may be different. The sacrificial layer 134 may include a first sub-sacrificial layer 134a and a second sub-sacrificial layer 134b. The first sub-sacrificial layer 134a is located between the isolation wall 132 and the first stacked structure 200A to separate the isolation wall 132 from the first stacked structure 200A. The second sub-sacrificial layer 134b is located between the isolation wall 132 and the second stacked structure 200B to separate the isolation wall 132 from the second stacked structure 200B. The first sub-sacrificial layer 134a has a high etching selectivity with respect to one of the first semiconductor layer 110 and the second semiconductor layer 120, and the second sub-sacrificial layer 134b has a high etching selectivity with respect to the other of the first semiconductor layer 110 and the second semiconductor layer 120. For example, the first sub-sacrificial layer 134a has a high etching selectivity with respect to the first semiconductor layer 110, and the second sub-sacrificial layer 134b has a high etching selectivity with respect to the second semiconductor layer 120. Thus, in the subsequent etching process of the first stacked structure 200A, the first sub-sacrificial layer 134a is removed together with the second semiconductor layer 120, and only the first semiconductor layer 110 is retained in the first stacked structure 200A; in the subsequent etching process of the second stacked structure 200B, the second sub-sacrificial layer 134b is removed together with the first semiconductor layer 110, and only the first semiconductor layer 120 is retained in the second stacked structure 200B, so that an N-type semiconductor device and a P-type semiconductor device can be formed through subsequent processes.

[0103] Specifically, the material of the first sub-sacrificial layer 134a is the same as that of one of the first semiconductor layer 110 and the second semiconductor layer 120, and the material of the second sub-sacrificial layer 134b is the same as that of the other of the first semiconductor layer 110 and the second semiconductor layer 120. For example, the material of the first sub-sacrificial layer 134a is the same as that of the second semiconductor layer 120, and the material of the second sub-sacrificial layer 134b is the same as that of the first semiconductor layer 110. More specifically, the first semiconductor layer 110 is Si, the second semiconductor layer 120 is SiGe, the first sub-sacrificial layer 134a is one of polycrystalline Si and polycrystalline SiGe, and the second sub-sacrificial layer 134b is the other of polycrystalline Si and polycrystalline SiGe. For example, the first sub-sacrificial layer 134a is polycrystalline SiGe, and the second sub-sacrificial layer 134b is polycrystalline Si.

[0104] Specifically, the method of forming the first sacrificial sub-layer 134a and the second sacrificial sub-layer 134b may include the following steps:

[0105] S123a. Remove at least part of the liner layer between the isolation wall and the first stacked structure to form a first cavity.

[0106] As shown in FIG9 , a mask layer is required to form the liner layer 131b between the protective isolation wall 132 and the second stacked structure 200B. The mask layer may, for example, cover the isolation wall 132, the liner layer 131b and the second stacked structure 200B, so that at least a portion of the liner layer 131 between the exposed isolation wall 132 and the first stacked structure 200A may be etched to form a first cavity 133a.

[0107] S124a. Fill the first cavity with a first sacrificial sub-layer.

[0108] As shown in Figure 10, the first cavity 133a shown in Figure 9 is filled with a first sub-sacrificial layer 134a, and the first sub-sacrificial layer 134a has a high etching selectivity with respect to one of the first semiconductor layer 110 and the second semiconductor layer 120. In an alternative embodiment, the first semiconductor layer 110 is Si, the second semiconductor layer 120 is SiGe, and the first sub-sacrificial layer 134a is polycrystalline SiGe.

[0109] S123b. Remove at least part of the liner layer between the isolation wall and the second stacked structure to form a second cavity.

[0110] As shown in FIG11 , the mask layer formed in the above step S123a is removed, and a mask layer is formed to protect the first sub-sacrificial layer 134a between the isolation wall 132 and the first stacked structure 200A. The mask layer can, for example, cover the isolation wall 132, the first sub-sacrificial layer 134a and the first stacked structure 200A, so that at least a portion of the liner layer 131b between the exposed isolation wall 132 and the second stacked structure 200B can be etched to form a second cavity 133b.

[0111] S124b. Fill the second cavity with a second sacrificial sub-layer.

[0112] As shown in FIG. 12 , the second sub-sacrificial layer 134 b is filled into the second cavity 133 b shown in FIG. 11 , and the mask layer formed in step S123 b is removed, thereby obtaining the semiconductor structure shown in FIG. 12 .

[0113] Through the above steps S123a, S124a, S123b and S124b, the first sub-sacrificial layer 134a and the second sub-sacrificial layer 134b can be respectively formed on both sides of the isolation wall 132, so that through subsequent processes, an N-type semiconductor device and a P-type semiconductor device can be respectively formed on both sides of the isolation wall 132.

[0114] S150 . Form a gate structure around the other of the first semiconductor layer and the second semiconductor layer.

[0115] The gate structure may include a gate dielectric layer 141 and a gate electrode layer 142 disposed around the other of the first and second semiconductor layers (ie, the one of the first and second semiconductor layers remaining after step S140 is completed).

[0116] In the example of FIG13 , since the second semiconductor layer 120 is removed, only the first semiconductor layer 110 remains, and since the sacrificial layer 134 is removed, a gap exists between the first semiconductor layer 110 and the isolation wall 132, so that a gate dielectric layer 141 can be formed around the entire first semiconductor layer 110. The first semiconductor layer 110 surrounded by the gate dielectric layer 141 forms a channel region of the semiconductor device. In some optional embodiments, the gate dielectric layer 141 may include one or more layers of a dielectric material (such as silicon oxide, silicon nitride, or a high-k dielectric material), other suitable dielectric materials, and / or combinations thereof. The high-k dielectric material may include, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, an interfacial layer may be formed between the channel region (i.e., the first semiconductor layer 110) and the gate dielectric layer 141. The gate dielectric layer 141 may be formed by CVD, ALD, or any other suitable method. In an alternative embodiment, the thickness of the gate dielectric layer 141 is in a range from about 1 nm to about 6 nm.

[0117] As shown in FIG14 , a gate electrode layer 142 is filled outside the gate dielectric layer 141, thereby forming a gate electrode layer 142 disposed around the first semiconductor layer 110. In some optional embodiments, the gate electrode layer 142 may include one or more layers of a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, alloys thereof, other suitable materials, and / or combinations thereof. The gate electrode layer 142 may be formed by CVD, ALD, electroplating, or other suitable methods.

[0118] Unlike the conventional forksheet structure in which the gate structure can only surround three sides of the channel, in the manufacturing method of the semiconductor device of the embodiment of the present application, by forming an isolation wall and a sacrificial layer in the isolation trench and removing the sacrificial layer through a subsequent etching process, a gate structure surrounding the entire channel area can be formed, which can achieve a smaller DIBL and better control the leakage current of the semiconductor device.

[0119] Step S130 will be described in detail below. More specifically, source and drain regions 160 need to be formed on both sides of the first stacked structure 200A and the second stacked structure 200B along a second direction, wherein the second direction is perpendicular to the first direction, and the first direction is the arrangement direction of the first stacked structure 200A and the second stacked structure 200B. The above-mentioned step S130 may specifically include:

[0120] S131 . Form a dummy gate structure 140 covering the first stacked structure 200A, the second stacked structure 200B, the isolation wall 132 and the sacrificial layer 134 , as shown in FIG. 15A and FIG. 15B .

[0121] S132 . Remove one of the first semiconductor layer 110 and the second semiconductor layer 120 by a predetermined thickness along the second direction.

[0122] In the example of FIG. 16A and FIG. 16B , the second semiconductor layer 120 is removed by a predetermined thickness, which is approximately 3 nm to 10 nm, more preferably approximately 5 nm.

[0123] S133 . Fill one of the removed first semiconductor layer 110 and the second semiconductor layer 120 with the insulating layer 150 (ie, the one of the first semiconductor layer 110 and the second semiconductor layer 120 removed by a predetermined thickness after completing step S132 ).

[0124] In the examples of Figures 17A and 17B , the removed second semiconductor layer 120 is filled with an insulating layer 150. The insulating layer 150 may be, for example, silicon nitride and may be formed on the sidewalls of the first semiconductor layer 110 and the second semiconductor layer 120 using an ALD process, and then the insulating layer 150 on the first semiconductor layer 110 may be removed using an etching process. The insulating layer 150 is used to prevent a subsequently formed gate structure from being electrically conductive to the source region or the drain region.

[0125] S134 . Perform epitaxial growth on the surface of the other of the first semiconductor layer 110 and the second semiconductor layer 120 to form source and drain regions 160 .

[0126] 18A and 18B , a source region and a drain region 160 are grown on the surface of the first semiconductor layer 110 by epitaxial growth. The dummy gate structure is then removed, thereby obtaining the semiconductor structure shown in FIG18A and FIG18B .

[0127] In some embodiments, after completing step S134, the following steps may also be included:

[0128] S135 . Form an insulating structure 161 on the source and drain regions 160 , as shown in FIG. 19A and FIG. 19B .

[0129] Thus, the source and drain structures of the semiconductor device of the embodiment of the present application are manufactured through the above steps S131 to S135. In the subsequent process, the gate structure of the semiconductor device is manufactured through the above steps S140 and S150.

[0130] In order to more clearly illustrate the semiconductor structure after step S140, FIG20 shows a cross-sectional axial view of the semiconductor structure after step S140. As shown in FIG20 , the channel region (i.e., the first semiconductor layer 110) is connected to the source region and the drain region 160 at both ends along the second direction, respectively, so that it is shown as a suspended arrangement in the cross-sectional view in the first direction shown in FIG8 . An insulating layer 150 is formed between the source region and the drain region 160 and the gate structure to be formed to prevent the gate structure from being conductive with the source region and the drain region 160. In the manufacturing method of the semiconductor device of the embodiment of the present application, by forming an isolation wall and a sacrificial layer in the isolation trench and removing the sacrificial layer through a subsequent etching process, a gate structure surrounding the entire channel region can be formed, which can achieve a smaller DIBL and better control of the leakage current of the semiconductor device.

[0131] The above embodiments of this application focus on the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. Considering the simplicity of the text, they will not be repeated here.

[0132] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a first stacked structure and a second stacked structure spaced apart from each other on a substrate, wherein the first stacked structure and the second stacked structure respectively include first semiconductor layers and second semiconductor layers that are alternately stacked; Filling an isolation wall and a sacrificial layer between the first stacked structure and the second stacked structure, wherein the sacrificial layer is located on both sides of the isolation wall to separate the isolation wall from the first stacked structure and the second stacked structure respectively, and the sacrificial layer has a high etching selectivity ratio relative to the first semiconductor layer or the second semiconductor layer; removing one of the first semiconductor layer and the second semiconductor layer and the sacrificial layer; A gate structure is formed around the other of the first semiconductor layer and the second semiconductor layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method of forming a first stacked structure and a second stacked structure spaced apart from each other on a substrate comprises: forming the first semiconductor layers and the second semiconductor layers alternately stacked on the substrate; The alternately stacked first semiconductor layers and the second semiconductor layers are etched to form isolation trenches, and the isolation trenches separate the alternately stacked first semiconductor layers and the second semiconductor layers into the first stacked structure and the second stacked structure, wherein the first stacked structure is used to form a first semiconductor device, and the second stacked structure is used to form a second semiconductor device.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The step of filling an isolation wall and a sacrificial layer between the first stacked structure and the second stacked structure comprises: forming a liner layer covering the sidewalls and bottom surface of the isolation trench; forming the isolation wall on the liner layer to fill the isolation trench; removing at least a portion of the liner layer located on the sidewall of the isolation trench to form a cavity; The cavity is filled with the sacrificial layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The removing at least a portion of the liner layer located on the sidewall of the isolation trench to form a cavity comprises: removing at least a portion of the liner layer between the isolation wall and the first stacked structure to form a first cavity; and removing at least a portion of the liner layer between the isolation wall and the second stacked structure to form a second cavity; The step of filling the cavity with the sacrificial layer comprises: filling the first cavity with a first sub-sacrificial layer, the first sub-sacrificial layer having a high etching selectivity ratio with respect to one of the first semiconductor layer and the second semiconductor layer; and The second cavity is filled with a second sacrificial sub-layer having a high etching selectivity ratio with respect to the other of the first semiconductor layer and the second semiconductor layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The sacrificial layer includes a first sub-sacrificial layer and a second sub-sacrificial layer; The first sub-sacrificial layer is located between the isolation wall and the first stacked structure to separate the isolation wall from the first stacked structure, and the first sub-sacrificial layer has a high etching selectivity relative to one of the first semiconductor layer and the second semiconductor layer; The second sub-sacrificial layer is located between the isolation wall and the second stacked structure to separate the isolation wall from the second stacked structure, and the second sub-sacrificial layer has a high etching selectivity relative to the other of the first semiconductor layer and the second semiconductor layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The material of the first sacrificial sub-layer is the same as that of one of the first semiconductor layer and the second semiconductor layer; The material of the second sacrificial sub-layer is different from that of the first semiconductor layer and the second semiconductor layer. The other is the same.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The first semiconductor layer is Si, and the second semiconductor layer is SiGe; The first sub-sacrificial layer is one of poly-Si and poly-SiGe; The second sacrificial sub-layer is the other of poly-Si and poly-SiGe.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The first semiconductor layer has a high etching selectivity with respect to the second semiconductor layer; or The second semiconductor layer has a high etching selectivity ratio with respect to the first semiconductor layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The material of the sacrificial layer is the same as that of the first semiconductor layer or the second semiconductor layer; When the material of the sacrificial layer is the same as that of the first semiconductor layer, the sacrificial layer and the first semiconductor layer have a high etching selectivity relative to the second semiconductor layer, and the removing of one of the first semiconductor layer and the second semiconductor layer and the sacrificial layer comprises: removing the first semiconductor layer and the sacrificial layer; When the material of the sacrificial layer is the same as that of the second semiconductor layer, the sacrificial layer and the second semiconductor layer have a high etching selectivity relative to the first semiconductor layer, and the removing of one of the first semiconductor layer and the second semiconductor layer and the sacrificial layer includes: removing the second semiconductor layer and the sacrificial layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The first semiconductor layer is Si, and the second semiconductor layer is SiGe; The sacrificial layer is polycrystalline Si or polycrystalline SiGe.

11. The method for manufacturing a semiconductor device according to claim 3, wherein: Removing at least a portion of the liner layer located on the sidewall of the isolation trench by using a dry or wet etching process; The liner layer and the isolation wall have a high etching selectivity ratio; and The sacrificial layer and the isolation wall have a high etching selectivity ratio.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11, characterized in that: Before removing one of the first semiconductor layer and the second semiconductor layer and the sacrificial layer, the method further includes: A source region and a drain region are formed on both sides of the first stacked structure and the second stacked structure along a second direction, the second direction is perpendicular to the first direction, and the first direction is the arrangement direction of the first stacked structure and the second stacked structure.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The forming of a source region and a drain region on both sides of the first stacked structure and the second stacked structure along the second direction comprises: removing one of the first semiconductor layer and the second semiconductor layer by a predetermined thickness along the second direction; filling the removed one of the first semiconductor layer and the second semiconductor layer with an insulating layer; Epitaxial growth is performed on the surface of the other of the first semiconductor layer and the second semiconductor layer to form the source region and the drain region.

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