Semiconductor device

Abstract

Provided is a highly reliable semiconductor device. A storage circuit including an OS transistor is combined with a latch circuit including an Si transistor. The storage circuit including the OS transistor is less likely to cause a software error. A logic value of the latch circuit is compared with a logic value of the storage circuit including the OS transistor, and data equal to a logic value of the storage circuit including the OS transistor is supplied to the latch circuit including the Si transistor in accordance with the comparison result.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, with the increase in the amount of data handled, there has been a demand for storage devices with larger storage capacities. There has also been a demand for storage devices that are less susceptible to data loss due to soft errors and are more reliable. A soft error is a defect in which part of the data stored in a storage device is unintentionally inverted (bit inversion) due to radiation. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays. In particular, radiation that is thought to have come from outer space is also called "cosmic rays." Soft errors caused by radiation are also called SEUs (single event upsets).

[0004] A defect in which a single-bit soft error occurs in one word (a block of data) is called an SBU (Single Bit Upset), and a defect in which multiple-bit soft errors occur in one word is called an MBU (Multi Bit Upset).

[0005] Soft errors are easy to recover from because they do not involve physical destruction. For example, ECC (Error Check and Correct) memory is known, which detects errors and corrects data in the SBU. ECC memory is used in electronic devices that cannot tolerate data errors, such as computers used in scientific and technical calculations or financial institutions.

[0006] On the other hand, it is difficult to correct data in the MBU in ECC memory. Memory scrubbing, which corrects data at the SBU stage, is known as a countermeasure against MBUs. Patent Document 1 also discloses an ECC memory that implements a countermeasure against MBUs by dividing a single stored word into multiple parts and assigning a correction code (also called "check data" or "check bits") to each part.

[0007] Special table Hei 5-508042

[0008] Conventional ECC memories calculate check bits corresponding to one word of data, combine the data with the check bits to generate and store a new word of data. This increases the amount of data stored in the physical memory, reducing the actual available storage capacity. Furthermore, in conventional ECC memories, when the aforementioned memory scrubbing is performed, correcting one bit of data requires rewriting one word containing the corresponding error bit, or rewriting all data stored in other memory cells connected to the same word line as the memory cell storing the data to be corrected, which increases power consumption. Increasing the frequency of memory scrubbing to address MBU issues also increases power consumption.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device capable of correcting data in an MBU.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0010] It should be noted that the problems associated with one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. It should be noted that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. One embodiment of the present invention solves at least one of the problems listed above and other problems.

[0011] (1) One embodiment of the present invention is a semiconductor device including: a first memory circuit including a transistor containing silicon (also referred to as an "Si transistor") in a channel formation region and having a function of storing first data; a second memory circuit including a transistor containing an oxide semiconductor (also referred to as an "OS transistor") in a channel formation region and having a function of storing second data; a function of making a logical value of the first data equal to a logical value of the second data by writing data to the first memory circuit and the second memory circuit; a function of outputting a first signal and making the first signal active when the logical value of the first data is "1" and the logical value of the second data is "0"; a function of outputting a second signal and making the second signal active when the logical value of the first data is "0" and the logical value of the second data is "1"; and a function of supplying third data, the logical value of which is equal to the logical value of the second data, to the first memory circuit when one of the first signal or the second signal is active.

[0012] That is, when there is a possibility that an error (logical value is inverted) occurs in the logical value of first data stored in a first memory circuit having a Si transistor, the semiconductor device detects the error by comparing the first data with second data input to a second memory circuit having an OS transistor, and inputs correct third data (the same logical value as the second data) to the first memory circuit.

[0013] In (1), a latch circuit can be used as the first memory circuit. For example, a latch circuit having a first inverter circuit and a second inverter circuit, in which the output of the first inverter circuit is electrically connected to the input of the second inverter circuit, and the output of the second inverter circuit is electrically connected to the input of the first inverter circuit, can be used.

[0014] (2) Another embodiment of the present invention includes a first memory circuit and a second memory circuit. The first memory circuit includes a first inverter circuit, a second inverter circuit, a first transistor, and a second transistor. An output of the first inverter circuit is electrically connected to an input of the second inverter circuit. An output of the second inverter circuit is electrically connected to the input of the first inverter circuit. The output of the first inverter circuit is electrically connected to a first wiring via a source and a drain of the first transistor. An output of the second inverter circuit is electrically connected to a second wiring via a source and a drain of the second transistor. The second memory circuit includes third to eighth transistors and a capacitor. One of a source or a drain of the third transistor is electrically connected to the output of the first inverter circuit, the input of the second inverter circuit, and one of a source or a drain of the fourth transistor. The other of the source or the drain of the third transistor is connected to one terminal of the capacitor and a gate of the fourth transistor. the other of the source or drain of the sixth transistor is electrically connected to the output of the second inverter circuit, the input of the first inverter circuit, and one of the source or drain of the seventh transistor; the other of the source or drain of the sixth transistor is electrically connected to the other terminal of the capacitance element and the gate of the seventh transistor; the other of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor; the other of the source or drain of the eighth transistor is electrically connected to the fourth wiring; the gate of the third transistor is electrically connected to the gate of the sixth transistor; and the gates of the fifth transistor and the eighth transistor are electrically connected to the fifth wiring.

[0015] In (2), each of the first inverter circuit and the second inverter circuit preferably includes a transistor containing silicon in a channel formation region, and each of the third transistor and the sixth transistor preferably includes an oxide semiconductor in a channel formation region. Furthermore, each of the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor preferably includes an oxide semiconductor in a channel formation region.

[0016] The semiconductor device shown in (2) has a function of supplying a potential L to the third wiring when the potential of the output of the first inverter circuit is a potential L and the potential of the gate of the fourth transistor is a potential H. Also, it has a function of supplying a potential L to the fourth wiring when the potential of the output of the second inverter circuit is a potential L and the potential of the gate of the seventh transistor is a potential H.

[0017] In (1) and (2), the first memory circuit and the second memory circuit preferably have an overlapping region, which can reduce the area occupied by the semiconductor device.

[0018] According to one embodiment of the present invention, error correction can be performed without adding check bits to one word of data. Alternatively, according to one embodiment of the present invention, error correction can be achieved without increasing the amount of data stored in a physical memory. Alternatively, a reduction in the substantially usable storage capacity of a semiconductor device such as a physical memory can be prevented.

[0019] According to one embodiment of the present invention, a semiconductor device capable of correcting data in an MBU can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0020] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above. Note that the other effects are effects not mentioned in this section, which will be described below. Those skilled in the art can derive the other effects from the description in the specification or drawings, and can extract them as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects.

[0021] FIG. 1 is a diagram illustrating a semiconductor device. FIG. 2 is a diagram illustrating a semiconductor device. FIG. 3 is a diagram illustrating a semiconductor device. FIGS. 4A and 4B are diagrams illustrating a semiconductor device. FIGS. 5A and 5B are diagrams illustrating a semiconductor device. FIGS. 6A to 6D are diagrams illustrating an XOR circuit. FIG. 7 is a timing chart illustrating the operation of the semiconductor device. FIG. 8 is a diagram illustrating the operation of the semiconductor device. FIG. 9 is a diagram illustrating the operation of the semiconductor device. FIG. 10 is a diagram illustrating the operation of the semiconductor device. FIG. 11 is a diagram illustrating the operation of the semiconductor device. FIG. 12 is a diagram illustrating the operation of the semiconductor device. FIG. 13 is a diagram illustrating the operation of the semiconductor device. FIG. 14 is a diagram illustrating the operation of the semiconductor device. FIG. 15 is a diagram illustrating the operation of the semiconductor device. FIG. 16 is a diagram illustrating the operation of the semiconductor device. FIG. 17 is a diagram illustrating the operation of the semiconductor device. FIGS. 18A and 18B are diagrams illustrating the operation of the semiconductor device. FIG. 19 is a diagram illustrating the semiconductor device. FIGS. 20A to 20D are diagrams illustrating the semiconductor device. FIG. 21 is a diagram illustrating the semiconductor device. FIG. 22A is a flowchart illustrating the operation of the semiconductor device. FIG. 22B is a diagram illustrating the operation of the semiconductor device. FIG. 23A is a flowchart illustrating the operation of the semiconductor device. FIG. 23B is a diagram illustrating the operation of the semiconductor device. FIG. 24 is a flowchart illustrating the operation of the semiconductor device. FIGS. 25A and 25B are diagrams illustrating the operation of the semiconductor device. FIG. 26 is a flowchart illustrating the operation of the semiconductor device. FIG. 27 is a diagram illustrating an example of a planar configuration of the semiconductor device. FIGS. 28A and 28B are diagrams illustrating an example of a cross-sectional configuration of the semiconductor device. FIGS. 29A to 29E are diagrams illustrating an example of a configuration of a transistor. FIGS. 30A and 30B are diagrams illustrating an example of a configuration of a transistor. FIG. 31 is a diagram illustrating an example of a configuration of a transistor. FIGS. 32A to 32C are diagrams illustrating an example of a configuration of a transistor. FIG. 33 is a diagram illustrating an example of a configuration of a semiconductor device. FIGS. 34A to 34C are diagrams illustrating an example of a configuration of a transistor. FIGS. 35A to 35C are diagrams illustrating an example of a configuration of a transistor.36A to 36J are diagrams illustrating an example of an electronic device, 37A to 37C are diagrams illustrating an example of an electronic device, and FIG. 38 is a diagram illustrating an example of an electronic device.

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0023] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0024] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited. The drawings are schematic illustrations of ideal examples, and the shapes or values ​​shown in the drawings are not limited.

[0025] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, plan views, etc.

[0026] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment, in the claims, etc. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment, in the claims, etc.

[0027] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0028] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0029] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0030] In this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0031] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" can be replaced with other terms without using them. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor." Or, the term "conductor" can be changed to the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" can be changed to the term "insulator." Or, the term "insulator" can be changed to the term "insulating layer" or "insulating film."

[0032] Note that voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a certain point. However, generally, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is simply called potential or voltage, and potential and voltage are often used synonymously. For this reason, in this specification and elsewhere, potential may be read as voltage, and voltage may be read as potential, unless otherwise specified.

[0033] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0034] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0035] In this specification, when it is explicitly stated that X and Y are connected, this includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, this is not limited to a specific connection relationship, for example, a connection relationship shown in a diagram or text, but also includes connection relationships other than those shown in a diagram or text.

[0036] As an example of the case where X and Y are electrically connected, one or more elements (e.g., switches, transistors, inductors, resistive elements, etc.) that enable the electrical connection between X and Y can be connected between X and Y.

[0037] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or amount of current, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0038] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0039] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, unless otherwise specified, and include an error of plus or minus 20%.

[0040] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0041] In this specification and the like, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the reference numeral. For example, the semiconductor layer 163 may be referred to as the semiconductor layer 163[1] or the semiconductor layer 163[2].

[0042] Embodiment 1 A memory cell 100 according to one embodiment of the present invention will be described. FIG. 1 illustrates a configuration example of a memory cell 100, which is a type of semiconductor device. The memory cell 100 includes a first memory circuit 110 and a second memory circuit 120. Each of the first memory circuit 110 and the second memory circuit 120 has a function of holding 1-bit data. The memory cell 100 also has a function of outputting a first signal and a second signal using data held in the first memory circuit 110 (also referred to as "first data") and data held in the second memory circuit 120 (also referred to as "second data").

[0043] The first memory circuit 110 is electrically connected to the wirings 101, 102, and 103. The second memory circuit 120 is electrically connected to the wirings 104, 105, 106, and 108. The wirings 101, 102, 106, and 108 are electrically connected to the correction circuit 130. Thus, the memory cell 100 is electrically connected to the correction circuit 130. The correction circuit 130 is also electrically connected to the wiring 107.

[0044] 2 and 3 show circuit configuration examples of a memory cell 100, which is a type of semiconductor device. As an example of the memory cell 100, Fig. 2 shows a circuit configuration example of a memory cell 100a. The memory cell 100a includes a first memory circuit 110 and a second memory circuit 120a.

[0045] The first memory circuit 110 includes an inverter circuit INV1, an inverter circuit INV2, a transistor Tr11, and a transistor Tr12. The output of the inverter circuit INV1 is connected to the input of the inverter circuit INV2, and the output of the inverter circuit INV2 is connected to the input of the inverter circuit INV1.

[0046] One of the source or drain of transistor Tr11 is connected to a wiring 101, and the other of the source or drain is connected to the output of inverter circuit INV1 and the input of inverter circuit INV2. One of the source or drain of transistor Tr12 is connected to the output of inverter circuit INV2 and the input of inverter circuit INV1. The other of the source or drain of transistor Tr12 is connected to a wiring 102. The gate of transistor Tr11 and the gate of transistor Tr11 are connected to a wiring 103. The first memory circuit 110 functions as a latch circuit. Therefore, the memory cell 100a also functions as a latch circuit.

[0047] In this specification and the like, the region where the output of the inverter circuit INV1, the input of the inverter circuit INV2, and the other of the source or drain of the transistor Tr11 are connected is referred to as "node Q." Also, in this specification and the like, the region where the output of the inverter circuit INV2, the input of the inverter circuit INV1, and the other of the source or drain of the transistor Tr12 are connected is referred to as "node QB."

[0048] The second memory circuit 120a includes transistors Tr21 to Tr26 and a capacitor Cs. One of the source and the drain of the transistor Tr21 is connected to the output of the inverter circuit INV1, the input of the inverter circuit INV2, the other of the source and the drain of the transistor Tr11, and one of the source and the drain of the transistor Tr22. The other of the source and the drain of the transistor Tr21 is connected to the gate of the transistor Tr22 and one terminal of the capacitor Cs.

[0049] One of the source or drain of transistor Tr23 is connected to the output of inverter circuit INV2, the input of inverter circuit INV1, one of the source or drain of transistor Tr12, and one of the source or drain of transistor Tr24. The other of the source or drain of transistor Tr23 is connected to the gate of transistor Tr24 and the other terminal of capacitance element Cs. The gates of transistors Tr21 and Tr23 are connected to wiring 104.

[0050] The other of the source or the drain of transistor Tr22 is connected to one of the source or the drain of transistor Tr25. The other of the source or the drain of transistor Tr25 is connected to wiring 106, and the gate is connected to wiring 105. The other of the source or the drain of transistor Tr24 is connected to one of the source or the drain of transistor Tr26. The other of the source or the drain of transistor Tr26 is connected to wiring 108, and the gate is connected to wiring 105. The second memory circuit 120a functions as an error detection circuit. Therefore, the memory cell 100a functions as a latch circuit with an error detection function.

[0051] In this specification, etc., the region where the other of the source or drain of transistor Tr21, one terminal of capacitance element Cs, and the gate of transistor Tr22 are connected is referred to as "node SN." Also, in this specification, etc., the region where the other of the source or drain of transistor Tr23, the other terminal of capacitance element Cs, and the gate of transistor Tr24 are connected is referred to as "node SNB."

[0052] A signal BL is supplied to the wiring 101, a signal BLB is supplied to the wiring 102, and a signal WL is supplied to the wiring 103. A signal SET is supplied to the wiring 104, and a signal CHK is supplied to the wiring 105.

[0053] A single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like is used alone or in combination as a semiconductor layer in which a channel of a transistor included in the first memory circuit 110 is formed. Examples of the semiconductor material include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, and gallium arsenide may also be used.

[0054] The inverter circuit INV1, the inverter circuit INV2, the transistor Tr11, and the transistor Tr12 included in the first memory circuit 110 are, for example, transistors (Si transistors) containing silicon in a region where a semiconductor channel is formed (also referred to as a "channel formation region"). In particular, it is preferable to use a Si transistor using a single crystal semiconductor or a polycrystalline semiconductor as the semiconductor where the channel is formed. Si transistors using a single crystal semiconductor or a polycrystalline semiconductor have high operating speeds and are relatively easy to manufacture, resulting in high productivity. On the other hand, memory circuits or memory elements (also referred to as "Si memories") using Si transistors have high data read and write speeds but are prone to soft errors.

[0055] An n-channel transistor can pass a higher on-current than a p-channel transistor. Using n-channel transistors as the transistors Tr11 and Tr12 can increase the operating speed of the first memory circuit 110. Therefore, the operating speed of the memory cell 100a can be increased.

[0056] It is easier to realize a normally-off transistor with a p-channel transistor than with an n-channel transistor. Using p-channel transistors as the transistors Tr11 and Tr12 can reduce the leakage current between the node Q and the wiring 101 and the leakage current between the node QB and the wiring 102. This reduces the power consumption of the first memory circuit 110. This reduces the power consumption of the memory cell 100a. Furthermore, the memory cell 100a is less susceptible to the influence of the leakage current of other memory cells 100a connected to the same wiring 101 and the same wiring 102, which stabilizes the operation of the memory cell 100a and improves its reliability. This stabilizes the operation of the memory cell 100a and improves its reliability.

[0057] Among the transistors Tr21 to Tr26 included in the second memory circuit 120a, at least the transistors Tr21 and Tr23 are transistors containing silicon in their semiconductor channel formation regions (OS transistors). Although the operating speed of OS transistors is slower than that of Si transistors, their off-state current is significantly lower than that of Si transistors because their band gap is 2 eV or more. Therefore, data written to the nodes SN and SNB of the second memory circuit 120 can be held for a long period of time.

[0058] Furthermore, when either or both of the transistors Tr22 and Tr25 are OS transistors, leakage current between the node Q and the wiring 106 is reduced, thereby reducing the power consumption of the memory cell 100. Similarly, when either or both of the transistors Tr22 and Tr25 are OS transistors, leakage current between the node QB and the wiring 108 is reduced, thereby reducing the power consumption of the memory cell 100.

[0059] Furthermore, by using Si transistors for the transistors Tr22, Tr24, Tr25, and Tr26, the operating speed of the second memory circuit 120a can be increased.

[0060] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in their characteristics. For example, their off-state current hardly increases even in high-temperature environments. Specifically, their off-state current hardly increases even in temperatures ranging from room temperature to 200° C. Furthermore, their on-state current is unlikely to decrease even in high-temperature environments. Therefore, a memory circuit or memory element (also referred to as an "OS memory") using an OS transistor operates stably and has high reliability even in high-temperature environments.

[0061] The electrical characteristics of the OS memory are less susceptible to fluctuations due to radiation such as cosmic rays, which means that soft errors caused by radiation are less likely to occur, thereby improving the reliability of the memory cell 100a.

[0062] The memory cell 100a is a memory element including a Si memory and an OS memory. By combining the Si memory, which has a high operating speed, with the OS memory, which has a high reliability, a memory cell with a high operating speed and high reliability can be realized. Therefore, a storage device with a high operating speed and high reliability can be realized.

[0063] 3 shows an example of the circuit configuration of a memory cell 100b, which is another example of the memory cell 100. The memory cell 100b is a modified version of the memory cell 100a. To avoid repetition, differences between the memory cell 100b and the memory cell 100a will be mainly described.

[0064] The memory cell 100b includes a first memory circuit 110 and a second memory circuit 120b. The second memory circuit 120b includes a memory element CsB in addition to the memory element Cs. One terminal of the memory element CsB is connected to the other of the source and drain of the transistor Tr23. In the second memory circuit 120a, the region where the other of the source and drain of the transistor Tr23, one terminal of the memory element CsB, and the gate of the transistor Tr24 are connected is referred to as a "node SNB."

[0065] In the second memory circuit 120b, a power supply potential or a fixed potential is supplied to the other terminal of the capacitance element Cs and the other terminal of the capacitance element CsB. The second memory circuit 120b has an additional circuit element, the capacitance element CsB, compared to the second memory circuit 120a. However, since it is possible to supply a power supply potential or a fixed potential to the other terminal of the capacitance element Cs and the other terminal of the capacitance element CsB, the potentials of the nodes SN and SNB are more stable than in the second memory circuit 120a. This improves the reliability of the memory cell 100b.

[0066] Furthermore, the memory cell 100 (memory cell 100a or memory cell 100b) may be provided with the first memory circuit 110 and the second memory circuit 120 (second memory circuit 120a or second memory circuit 120b) overlapping each other. By providing the first memory circuit 110 and the second memory circuit 120 overlapping each other, the area occupied by the memory cell 100 can be reduced. FIG. 4A shows a conceptual perspective view of the memory cell 100. FIG. 4B is a conceptual perspective view for explaining the configuration of the memory cell 100 in more detail.

[0067] The layer 10 includes a first memory circuit 110. The layer 20 includes a second memory circuit 120. For example, a single-crystal silicon substrate may be used as the layer 10, and the first memory circuit 110 may be formed on the silicon substrate. By forming the channel formation region of the Si transistor included in the first memory circuit 110 on the silicon substrate, a single-crystal Si transistor having a single-crystal semiconductor in the channel formation region and operating at a high speed can be formed.

[0068] Alternatively, for example, an SOI (Silicon on Insulator) substrate may be used as the layer 10. Examples of the SOI substrate include a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that occur in the surface layer, a Smart Cut method in which a semiconductor substrate is cleaved by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment, and an ELTRAN method (registered trademark: Epitaxial Layer Transfer). A Si transistor fabricated using an SOI substrate has reduced parasitic capacitance and can achieve high-speed operation.

[0069] Furthermore, because an OS transistor is a thin film transistor, it can easily be provided as the layer 20 overlapping the layer 10. In addition, as described above, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. Therefore, even if the second memory circuit 120 including an OS transistor is provided overlapping the first memory circuit 110 including a Si transistor, the second memory circuit 120 is less susceptible to heat generation from the first memory circuit 110, and high reliability can be achieved.

[0070] <Correction Circuit 130> Figures 5A and 5B show examples of the circuit configuration of a correction circuit 130, which is a type of semiconductor device. As an example of the correction circuit 130, Figure 5A shows an example of the circuit configuration of a correction circuit 130a. The correction circuit 130a has inverter circuits INV3 and INV4, transistors Tr90 to Tr93, and a first circuit 132. Figure 5A shows the circuit symbol of a two-input, one-output XOR (exclusive OR) circuit as the first circuit 132.

[0071] One of the source and the drain of the transistor Tr90 is connected to the wiring 106 and the input of the inverter circuit INV3. The other of the source and the drain of the transistor Tr90 is connected to one of the source and the drain of the transistor Tr91. The other of the source and the drain of the transistor Tr91 is connected to the wiring 108 and the input of the inverter circuit INV4. A potential H is supplied to the other of the source and the drain of the transistor Tr90 and to the one of the source and the drain of the transistor Tr91. In FIG. 2, the potential H is supplied via the wiring 137.

[0072] The output of the inverter circuit INV3 is connected to one input of the first circuit 132 and one of the source or drain of the transistor Tr92. The other of the source or drain of the transistor Tr92 is connected to the wiring 101. The output of the inverter circuit INV4 is connected to the other input of the first circuit 132 and one of the source or drain of the transistor Tr93. The other of the source or drain of the transistor Tr93 is connected to the wiring 102. The output of the first circuit 132 is connected to the gate of the transistor Tr92 and the gate of the transistor Tr93. Furthermore, in this specification and the like, the region where the output of the first circuit 132, the gate of the transistor Tr92, and the gate of the transistor Tr93 are connected is referred to as "node ZN."

[0073] The operation speed of the correction circuit 130 can be increased by using Si transistors for at least part of the inverter circuits INV3 and INV4, the transistors Tr90 to Tr93, and the first circuit 132. Si transistors have high operation speed and a high charge supply capability. For example, using Si transistors for the transistors Tr92 and Tr93 can increase the charge supply capability to the wirings 101 and 102. Note that elements functioning as switches can be used as the transistors Tr90 to Tr93. For example, n-channel transistors or p-channel transistors can be used as the transistors Tr90 to Tr93.

[0074] Furthermore, by using OS transistors for at least part of the inverter circuits INV3 and INV4, the transistors Tr90 to Tr93, and the first circuit 132, the power consumption of the correction circuit 130a can be reduced. Furthermore, by using OS transistors, the operation can be stabilized even in a high-temperature environment, and the reliability of the correction circuit 130a can be improved. For example, by using OS transistors for the transistors Tr90 and Tr91, the leakage current between the wiring 106 and the wiring 108 when the transistors Tr90 and Tr91 are off can be significantly reduced.

[0075] When the correction circuit 130a is formed using Si transistors, the correction circuit 130a can be provided in the layer 10. When the correction circuit 130a is formed using OS transistors, the correction circuit 130a can be provided in the layer 20. When the correction circuit 130a is formed using Si transistors and OS transistors, part of the correction circuit 130a can be provided in the layer 10 and the other part can be provided in the layer 20.

[0076] 5B shows an example of the circuit configuration of a correction circuit 130b as another example of the correction circuit 130. The correction circuit 130b is a modified version of the correction circuit 130a. To reduce repetition in the explanation, the differences between the correction circuit 130b and the correction circuit 130a will be mainly described.

[0077] The correction circuit 130b has a circuit configuration in which the first circuit 132 is removed from the correction circuit 130a. Furthermore, the connections of the transistors Tr92 and Tr93 differ from those of the correction circuit 130a. In the correction circuit 130b, one of the source and the drain of the transistor Tr92 is connected to the wiring 102. A potential L is supplied to the other of the source and the drain of the transistor Tr92. In FIG. 5B , the potential L is supplied to the other of the source and the drain of the transistor Tr92 via the wiring 138.

[0078] In the correction circuit 130b, one of the source and the drain of the transistor Tr93 is connected to the wiring 101. The other of the source and the drain of the transistor Tr93 is supplied with a potential L. In FIG. 5B , the potential L is supplied to the other of the source and the drain of the transistor Tr93 via a wiring 139.

[0079] <First Circuit 132> The XOR circuit used as the first circuit 132 will now be described. Fig. 6A shows the circuit symbol of a two-input, one-output XOR circuit. Table 1 shows the truth table of the XOR circuit.

[0080]

[0081] An XOR circuit outputs Z of "1" when one of inputs A and B is "0" and the other is "1." Furthermore, output Z is "0" when both inputs A and B are "0" and when both inputs A and B are "1." If "1" is the potential H and "0" is the potential L, output Z will be at potential H when one of inputs A and B is at potential L and the other is at potential H. Furthermore, output Z will be at potential L when both inputs A and B are at potential L and when both inputs A and B are at potential H. Because it operates in this way, an XOR circuit is also called a "discrepancy circuit."

[0082] An XOR circuit can also be realized by combining various logic circuits. Fig. 6B shows an XOR circuit composed of four NAND circuits. Fig. 6C shows an XOR circuit composed of three NAND circuits and two inverter circuits (NOT circuits). Fig. 6D shows an XOR circuit composed of one OR circuit, two AND circuits, and two NOT circuits.

[0083] <<Circuit Operation Example>> An example of the operation of the memory cell 100 and the correction circuit 130 will be described. First, an example of the operation of the memory cell 100a and the correction circuit 130a will be described. Figure 7 is a timing chart illustrating the operation of the memory cell 100a and the correction circuit 130a. Figures 8 to 17 are circuit diagrams illustrating the operating states of the memory cell 100a and the correction circuit 130a.

[0084] In this specification and the like, a potential that can turn an n-channel transistor into an off state is referred to as potential L. A potential that can turn a p-channel transistor into an on state is referred to as potential L. For example, a low power supply potential VSS can be used as potential L, but this does not mean a specific potential. In this specification and the like, a potential that can turn an n-channel transistor into an on state is referred to as potential H. A potential that can turn a p-channel transistor into an off state is referred to as potential H. For example, a high power supply potential VDD can be used as potential H, but this does not mean a specific potential. Note that the high power supply potential VDD is a potential higher than the low power supply potential VSS.

[0085] For example, if it is stated that "a potential L is supplied" to each of two wires, the potentials L supplied to the two wires do not have to be equal to each other. Similarly, if it is stated that "a potential H is supplied" to each of two wires, the potentials H supplied to the two wires do not have to be equal to each other.

[0086] In drawings, symbols indicating potential such as "H" or "L" (also called "potential symbols") may be written adjacent to terminals, wiring, etc. Arrows may also be written to indicate the direction and path of current flow. To make it easier to understand potential changes in terminals, wiring, etc., potential symbols attached to terminals, wiring, etc. where potential changes have occurred may be written in boxes. An "x" symbol may also be placed over a transistor in an off state.

[0087] [Data Write Operation] The operation of writing data to the memory cell 100a will be described.

[0088] In this specification and the like, when the potential of node Q is potential H and the potential of node QB is potential L, it is considered that data of logical value "1" is written or held in the first memory circuit 110. In other words, when the potential of the output of inverter circuit INV1 is potential H and the potential of the output of inverter circuit INV2 is potential L, it is considered that data of logical value "1" is written or held in the first memory circuit 110 as first data.

[0089] Furthermore, when the potential of the node Q is the potential L and the potential of the node QB is the potential H, it is assumed that data of the logical value "0" is written or held in the first memory circuit 110. That is, when the potential of the output of the inverter circuit INV1 is the potential L and the potential of the output of the inverter circuit INV2 is the potential H, it is assumed that data of the logical value "0" is written or held in the first memory circuit 110 as the first data.

[0090] Furthermore, in this specification and the like, when the potential of node SN is potential H and the potential of node SNB is potential L, it is considered that data of logical value "1" is written or held in the second memory circuit 120. In other words, when the potential of the gate of transistor Tr22 is potential H, it is considered that data of logical value "1" is written or held in the second memory circuit 120 as second data.

[0091] Furthermore, in this specification and the like, when the potential of node SN is potential L and the potential of node SNB is potential H, it is considered that data of logical value "0" is written or held in the second memory circuit 120. In other words, when the potential of the gate of transistor Tr22 is potential L, it is considered that data of logical value "0" is written or held in the second memory circuit 120 as second data.

[0092] Also, immediately before the data write operation starts, the signal BL, node QB, node SNB, the output of inverter circuit INV3, and the output of inverter circuit INV4 are all at potential H. The outputs of signal BLB, signal WL, node Q, signal SET, node SN, signal CHK, and signal PRE are all at potential L. Since the outputs of inverter circuit INV3 and inverter circuit INV4 are all at potential H, the output of the first circuit 132 becomes potential L. Therefore, the potential of node ZN is potential L.

[0093] In a period T51, the signals WL and SET are set to potential H (see FIGS. 7 and 8). When the signal WL is set to potential H, the transistors Tr11 and Tr12 are turned on, the potential of the node Q is set to potential H, and the potential of the node QB is set to potential L.

[0094] In this specification and the like, when the potential of the signal WL is a potential that turns on the transistors Tr11 and Tr12, it is said that "the signal WL is active." By making the signal WL active, data is written to the first memory circuit 110 or data is read from the first memory circuit 110.

[0095] Furthermore, when the signal SET goes to the H potential, the transistors Tr21 and Tr23 are turned on, the potential of the node SN goes to the H potential, and the potential of the node SNB goes to the L potential.

[0096] In this specification and the like, when the potential of the signal SET is a potential that turns on the transistors Tr21 and Tr23, it is said that "the signal SET is active." By making the signal SET active, data is written to the second memory circuit 120.

[0097] When the potential of the node SN becomes the potential H, the transistor Tr22 is turned on. When the potential of the node SNB becomes the potential L, the transistor Tr24 is turned off.

[0098] In a period T52, the signals WL and SET are set to potential L (see FIGS. 7 and 9). When the signal WL is set to potential L, the transistors Tr11 and Tr12 are turned off. When the signal SET is set to potential L, the transistors Tr21 and Tr23 are turned off.

[0099] When transistors Tr11 and Tr12 are turned off, the potential of node Q is fixed at potential H, and the potential of node QB is fixed at potential L. When transistors Tr21 and Tr23 are turned off, nodes SN and SNB are brought into a floating state (electrically floating state), and the potentials written to nodes SN and SNB during period T51 are held. In this way, data "1" is held in both the first memory circuit 110 and the second memory circuit 120.

[0100] [Data Read Operation] Next, the operation of reading data stored in the memory cell 100a will be described. Here, it is assumed that data with a logical value of "1" is written to the memory cell 100a. Also, immediately before the start of the read operation (immediately before the period T53), the signals WL, SET, CHK, and PRE are at potential L, and the potentials of the wirings 106 and 108 are also at potential L. Also, it is assumed that the wiring 101 is at potential L and in a floating state. Also, it is assumed that the wiring 102 is at potential H and in a floating state.

[0101] In a period T53, the signal WL is set to a potential H (see FIGS. 7 and 10). When the signal WL is set to the potential H, the transistors Tr11 and Tr12 are turned on. When the transistor Tr11 is turned on, the output potential of the inverter circuit INV1 is supplied to the wiring 101. When the transistor Tr12 is turned on, the output potential of the inverter circuit INV2 is supplied to the wiring 102. By detecting the potentials of the wirings 101 and 102, data held in the memory cell 100 can be read. In this embodiment, the potential of the wiring 101 is set to a potential H, and the potential of the wiring 102 is set to a potential L.

[0102] [Data Error Checking Operation] Next, a check and correction operation for the presence or absence of a data error (also referred to as an "error checking operation") will be described. Immediately before the error checking operation starts (immediately before the period T54), the signal WL, the signal SET, the signal CHK, and the signal PRE are at potential L, and the potentials of the wirings 106 and 108 are also at potential L. The wiring 101 is at potential L, and the wiring 102 is at potential H.

[0103] [When No Soft Error Occurs] First, a case where no soft error occurs in the memory cell 100a will be described. In this embodiment, it is assumed that both the first data and the second data have a logical value of "1".

[0104] In a period T54, the signal PRE is set to a potential H (see FIGS. 7 and 11). When the signal PRE is set to the potential H, the transistors Tr90 and Tr91 are turned on, and the potential H is supplied to the wirings 106 and 108. That is, the potentials of the wirings 106 and 108 are set to the potential H. When the potential of the wiring 106 is set to the potential H, the output potential of the inverter circuit INV3 is set to the potential L. When the potential of the wiring 108 is set to the potential H, the output potential of the inverter circuit INV4 is set to the potential L.

[0105] In this specification and the like, when the potential of the signal PRE is a potential that turns on the transistors Tr90 and Tr91, it is said that "the signal PRE is active." By making the signal PRE active, a potential H is supplied to the wiring 106 and the wiring 108.

[0106] Next, in a period T55, the signal PRE is made inactive (in this embodiment, the signal PRE is set to potential L), and the signal CHK is set to potential H (see FIGS. 7 and 12). When the signal PRE is made inactive, the transistors Tr90 and Tr91 are turned off, and the wirings 106 and 108 are brought into a floating state.

[0107] When the signal CHK becomes a potential H, the transistors Tr25 and Tr26 are turned on. In this specification and the like, when the potential of the signal CHK is a potential that turns on the transistors Tr25 and Tr26, it is said that "the signal CHK is active."

[0108] In the period T55, the potential of the node SN is at the potential H, so the transistor Tr22 is in the on state. Also, the potential of the node SNB is at the potential L, so the transistor Tr24 is in the off state. Therefore, when the signal CHK becomes active, the output potential of the inverter circuit INV1 (here, the same as the potential of the node Q) is supplied to the wiring 106 via the transistors Tr22 and Tr25.

[0109] In this specification and the like, the potential supplied from the second memory circuit 120a to the wiring 106 is referred to as a "first signal." When a potential L is supplied from the second memory circuit 120a to the wiring 106, it is referred to as a "first signal being active." When the potential supplied from the second memory circuit 120a to the wiring 106 is a potential H, or when no potential is supplied from the second memory circuit 120a to the wiring 106, it is referred to as a "first signal being inactive." When the potential supplied from the second memory circuit 120a to the wiring 108 is referred to as a "second signal," it is referred to as a "second signal." When a potential L is supplied from the second memory circuit 120a to the wiring 108, it is referred to as a "second signal being active." When the potential supplied from the second memory circuit 120a to the wiring 108 is a potential H, or when no potential is supplied from the second memory circuit 120a to the wiring 108, it is referred to as a "second signal being inactive." When the first signal becomes active, the output of the inverter circuit INV3 becomes the potential H. When the second signal becomes active, the output of the inverter circuit INV4 becomes the potential H.

[0110] During period T55, the output potential of the inverter circuit INV1 is at potential H, and therefore the first signal is inactive. Therefore, the potential of the wiring 106 remains at potential H, and the output of the inverter circuit INV3 also remains at potential L. Furthermore, because the transistor Tr24 is in the off state, even if the transistor Tr26 is turned on, the second signal is inactive. Therefore, the potential of the wiring 108 remains at potential H, and the output of the inverter circuit INV4 also remains at potential L.

[0111] In this embodiment, the error checking operation when data "1" is held in both the first memory circuit 110 and the second memory circuit 120 has been described, but even in the error checking operation when data "0" is held in both the first memory circuit 110 and the second memory circuit 120a, the potentials of the wiring 106 and the wiring 108 become the potential H. Therefore, the outputs of the inverter circuits INV3 and INV4 remain at the potential L.

[0112] In this way, when the logical value of the first data and the logical value of the second data are equal, both the first signal and the second signal are inactive. Therefore, potential L is input to both of the two inputs of the first circuit 132, and the output of the first circuit 132 becomes potential L. When the output of the first circuit 132 is potential L, the transistors Tr92 and Tr93 are in the off state.

[0113] Furthermore, in the configuration of the memory cell 100a shown in this embodiment, neither the first signal nor the second signal becomes active. Even if both the first signal and the second signal are active, the output of the first circuit 132 is at potential L, so the transistors Tr92 and Tr93 are in an off state. Furthermore, if both the first signal and the second signal become active, there is a possibility that an abnormal state, such as damage, has occurred in the memory cell 100a. By monitoring the first signal and the second signal, it is possible to detect an abnormal state of the memory cell 100a and stop use of the memory cell 100a. Furthermore, if a certain number or more of the memory cells 100a become abnormal, measures such as stopping the system can be taken as necessary.

[0114] Note that when high-speed transistors such as Si transistors are used as the transistors Tr22, Tr24, Tr25, and Tr26, the precharge operation described above does not need to be performed. Even when low-speed transistors such as OS transistors are used as the transistors Tr22, Tr24, Tr25, and Tr26, the precharge operation described above does not need to be performed as long as it is possible to read data over a long period of time. When the precharge operation is not performed, the wiring 107 and the transistors Tr90 and Tr91 do not need to be provided.

[0115] Next, in a period T56, the signal WL is set to a potential H (see FIGS. 7 and 13). When a soft error does not occur, the output of the first circuit 132 is at a potential L, the transistors Tr92 and Tr93 are off, and the wirings 101 and 102 are floating.

[0116] When the signal WL has a potential H, the transistors Tr11 and Tr12 are turned on. At this time, the wiring 101 is in a floating state, so the output of the inverter circuit INV1 is supplied to the wiring 101. In addition, the wiring 102 is also in a floating state, so the output of the inverter circuit INV2 is supplied to the wiring 102.

[0117] The period T56 is also a period for writing correct data back to the first storage circuit 110 if a soft error occurs. If no soft error occurs, data is not rewritten to the first storage circuit 110. Therefore, if both the first signal and the second signal are inactive, the period T56 does not need to be performed. By not performing the period T56, unnecessary operations are reduced, and power consumption is reduced.

[0118] [When a Soft Error Occurs] Next, a read operation when a soft error occurs in the memory cell 100a will be described.

[0119] First, assume that a soft error occurs during period T57 (see FIGS. 7 and 14). For example, assume that radiation 999 enters memory cell 100a, causing a bit inversion in first memory circuit 110, which is composed of Si transistors. That is, in this embodiment, the logical value of the first data changes from "1" to "0." Specifically, the potential of node Q becomes potential L, and the potential of node QB becomes potential H.

[0120] Since the second memory circuit 120 configured with OS transistors is less susceptible to soft errors, bit inversion does not occur in the second memory circuit 120. The logical value of the second data remains "1." Therefore, in the memory cell 100a in which the soft error occurred, the logical values ​​of the first data and the second data are different from each other.

[0121] The error checking operation when a soft error occurs will be described using the periods T58 to T60. Immediately before the error checking operation starts (immediately before the period T58), the signal WL is at the potential L, and the potentials of the wirings 106 and 108 are also at the potential L. Also, the wirings 101 and 102 are in a floating state.

[0122] In a period T58, the signal PRE is set to the potential H (see FIGS. 7 and 15). As in the period T54, when the potential of the signal PRE becomes the potential H, the transistors Tr90 and Tr91 are turned on, and the potentials of the wirings 106 and 108 become the potential H. In addition, the output potentials of the inverter circuits INV3 and INV4 become the potential L.

[0123] Next, in a period T59, the signal PRE is set to a potential L, and the signal CHK is set to a potential H (see FIGS. 7 and 16). As in the period T55, when the signal PRE is set to a potential L, the transistors Tr90 and Tr91 are turned off, and the wiring 106 and the wiring 108 are set to a floating state. When the signal CHK is set to a potential H, the transistors Tr25 and Tr26 are turned on. At this time, the potential of the node SN is at a potential H, so the transistor Tr22 is on. Furthermore, the potential of the node SNB is at a potential L, so the transistor Tr24 is off. Therefore, the output potential of the inverter circuit INV1 is supplied to the wiring 106 via the transistors Tr22 and Tr25.

[0124] In period T59, the output potential of the inverter circuit INV1 (the potential of the node Q) is the potential L, and therefore the potential L is supplied from the second memory circuit 120a to the wiring 106. That is, the first signal becomes active, the potential of the wiring 106 becomes the potential L, and the output of the inverter circuit INV3 becomes the potential H. On the other hand, the second signal is inactive. Note that when the logical value of the first data is "1" and the logical value of the second data is "0," the first signal is inactive and the second signal is active. Therefore, the output of the inverter circuit INV3 becomes the potential L, and the output of the inverter circuit INV4 becomes the potential H.

[0125] In this embodiment, when the logical value of the first data is "0" and the logical value of the second data is "1," the first signal becomes active, and when the logical value of the first data is "1" and the logical value of the second data is "0," the second signal becomes active. In this way, when the logical value of the first data and the logical value of the second data are different, only one of the first signal and the second signal becomes active. Therefore, when the logical value of the first data and the logical value of the second data are different, a potential H is input to one input of the first circuit 132 and a potential L is input to the other input, and the output of the first circuit 132 becomes a potential H.

[0126] When the output of the first circuit 132 becomes a potential H, the transistors Tr92 and Tr93 are turned on. Then, the output of the inverter circuit INV3 is supplied to the wiring 101 via the channel formation region of the transistor Tr92. Also, the output of the inverter circuit INV4 is supplied to the wiring 102 via the channel formation region of the transistor Tr92. In this embodiment, the potential H is supplied to the wiring 101, and the potential L is supplied to the wiring 102.

[0127] For example, when a high power supply potential VDD is used as the potential H and the potential H is output via a circuit element, the potential of the output potential H may be lower than the high power supply potential VDD. Also, when a low power supply potential VSS is used as the potential L and the potential L is output via a circuit element, the potential of the output potential L may be higher than the low power supply potential VSS. Outputting the potential H as the high power supply potential VDD and outputting the potential L as the low power supply potential VSS are called "full swing output."

[0128] To more reliably write the correction data to the first memory circuit 110, the potentials H and L supplied to the wirings 101 and 102 are preferably full-swing output potentials H and L. To transmit the output of the first circuit 132 to the wiring 101 as a full-swing output, the transistor Tr92 may be replaced with an analog switch. To transmit the output of the first circuit 132 to the wiring 102 as a full-swing output, the transistor Tr93 may be replaced with an analog switch.

[0129] Next, in a period T60, the signal WL is set to a potential H (see FIGS. 7 and 17). When a soft error occurs, the wiring 101 and the wiring 102 are not in a floating state. In this embodiment, the potential H is supplied to the wiring 101, and the potential L is supplied to the wiring 102.

[0130] When the signal WL becomes the potential H, the transistors Tr11 and Tr12 are turned on. Then, the output of the inverter circuit INV3 is supplied to the node Q. Also, the output of the inverter circuit INV4 is supplied to the node QB. In this embodiment, the potential of the node Q changes from the potential L to the potential H, and the potential of the node QB changes from the potential H to the potential L. That is, data with a logical value of "1" is supplied from the correction circuit 130a to the first memory circuit 110.

[0131] In this specification and the like, the data supplied from the correction circuit 130a to the first memory circuit 110 is also referred to as "third data." The third data is data for correcting the first data in which bit inversion has occurred due to a soft error. In this embodiment, when data with a logical value of "0" is supplied as the third data to the first memory circuit 110, a potential L is supplied to the wiring 101 and a potential H is supplied to the wiring 102.

[0132] In this manner, the first data in which a bit inversion has occurred can be corrected. The logical value of the third data for correcting the first data is determined by the first signal and the second signal, which are the comparison results between the first data and the second data. The logical value of the third data is equal to the logical value of the second data. The third data is also data for correcting the first data. Therefore, the third data generated in period T59 has a logical value different from the logical value of the first data in period T59.

[0133] Furthermore, the memory cell 100b functions in the same manner as the memory cell 100a, and therefore the operation of the memory cell 100b can be understood with reference to the operation of the memory cell 100a.

[0134] <Correction Circuit 130b> Next, an example of the operation of the correction circuit 130b will be described. The correction circuit 130b can also generate the third data in the same way as the correction circuit 130a. In this embodiment, differences between the operation of the correction circuit 130b and the operation of the correction circuit 130a will be mainly described.

[0135] [When No Soft Error Occurs] First, the operation of the correction circuit 130b when no soft error occurs in the memory cell 100 (memory cell 100a or memory cell 100b) will be described (see FIG. 18A). In this embodiment, it is assumed that both the first data and the second data have a logical value of "1." As in period T55 (see FIGS. 7 and 12), both the first signal and the second signal are inactive, so both the transistors Tr92 and Tr93 are in the off state. Therefore, both the wiring 101 and the wiring 102 are in the floating state, and no data is written to the first memory circuit 110 even if period T56 is executed thereafter.

[0136] [When a Soft Error Occurs] Next, a read operation when a soft error occurs in the memory cell 100 will be described (see FIG. 18B). In this embodiment, it is assumed that the logical value of the first data is "0" and the logical value of the second data is "1". As in period T59 (see FIGS. 7 and 16), the first signal of the second memory circuit 120 becomes active and the second signal becomes inactive.

[0137] In the configuration of the correction circuit 130b, when the first signal becomes active, the output of the inverter circuit INV3 becomes a potential H, and the transistor Tr92 is turned on. When the transistor Tr92 is turned on, the potential of the wiring 102 becomes a potential L. Furthermore, because the second signal is inactive, the output of the inverter circuit INV4 is a potential L, and the transistor Tr93 is turned off. Therefore, the wiring 101 is in a floating state.

[0138] Subsequently, similarly to the period T60 (see FIGS. 7 and 17), the signal WL is set to the potential H. When a soft error occurs, one of the wiring 101 and the wiring 102 is set to a floating state, and the potential L is supplied to the other. In this embodiment, the wiring 101 is set to a floating state, and the potential L is supplied to the wiring 102. When the potential L is supplied to the wiring 102, the potential of the node QB changes from the potential H to the potential L. When the potential of the node QB becomes the potential L, the output of the inverter circuit INV1 (node ​​Q) changes from the potential L to the potential H.

[0139] In this manner, the first data in which a bit inversion has occurred can be corrected. The logical value of the third data for correcting the first data is determined by the first signal and the second signal, which are the results of comparing the first data and the second data.

[0140] In the configuration of the correction circuit 130b, when the first signal becomes active, a potential L is supplied to the wiring 102. This corresponds to the correction circuit 130b outputting third data having a logical value of "1". In the configuration of the correction circuit 130b, when the second signal becomes active, a potential L is supplied to the wiring 101. This corresponds to the correction circuit 130b outputting third data having a logical value of "0".

[0141] In the correction circuit 130b, when third data is written to the first memory circuit 110 and the first data in which bit inversion has occurred is corrected, one of the wiring 101 and the wiring 102 is brought into a floating state. As a result, the operation speed of the correction circuit 130b is slower than that of the correction circuit 130a. On the other hand, because the correction circuit 130b does not have the first circuit 132, the number of circuit elements is smaller than that of the correction circuit 130a, and the occupied area can be reduced.

[0142] In this way, the memory cell 100 according to one embodiment of the present invention can check for the presence or absence of a data error for each bit (for each memory cell 100). Furthermore, by using the memory cell 100 according to one embodiment of the present invention and the correction circuit 130, error correction for each bit becomes possible. A storage device including the memory cell 100 according to one embodiment of the present invention facilitates correction of soft errors in the MBU. A storage device including the memory cell 100 according to one embodiment of the present invention does not require the addition of check bits for data correction, and therefore can achieve a highly reliable storage device without reducing the usable storage capacity. A storage device including the memory cell 100 according to one embodiment of the present invention can detect the presence or absence of a data error and correct the error in hardware, and functions as an ECC memory that does not require check bits.

[0143] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0144] Embodiment 2 In this embodiment, a memory cell array 200 including a memory cell 100 (memory cell 100a or memory cell 100b) according to one embodiment of the present invention and a memory device 300 including the memory cell array 200 will be described.

[0145] 19 shows an example of the configuration of a memory cell array 200 including a plurality of memory cells 100 arranged in a matrix of m rows and n columns (m and n are each an integer of 1 or greater). By arranging a plurality of memory cells 100 in a matrix, a memory device with a large storage capacity can be realized.

[0146] In Figure 19, the memory cell 100 in the first row and first column is shown as memory cell 100[1,1], the memory cell 100 in the mth row and nth column is shown as memory cell 100[m,n], the memory cell 100 in the ith row and first column (i is an integer greater than or equal to 1 and less than or equal to m indicating an arbitrary row) is shown as memory cell 100[i,1], the memory cell 100 in the mth row and first column is shown as memory cell 100[m,1], the memory cell 100 in the first row and nth column is shown as memory cell 100[1,n], and the memory cell 100 in the ith row and nth column is shown as memory cell 100[i,n].

[0147] In this specification and the like, the memory cell 100 in the i-th row and j-th column (j is an integer of 1 to n indicating an arbitrary column) may be referred to as memory cell 100[i,j]. In this specification and the like, the correction circuit 130 in the j-th column may be referred to as correction circuit 130[j].

[0148] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction (direction along the X axis) is referred to as a "row" and the Y direction (direction along the Y axis) is referred to as a "column," but the X direction may be referred to as a "column" and the Y direction may be referred to as a "row."

[0149] In this specification and the like, any memory cell 100 among the multiple memory cells 100 arranged in a matrix may be referred to as a "memory cell 100" or a "memory cell 100[i, j]".

[0150] The first memory circuit 110 and the second memory circuit 120 included in each of the plurality of memory cells 100 arranged in a matrix are also indicated in the same manner as the memory cell 100. For example, the first memory circuit 110 and the second memory circuit 120 included in the memory cell 100[1,1] are indicated as the first memory circuit 110[1,1] and the second memory circuit 120[1,1], respectively. Furthermore, for example, the first memory circuit 110 and the second memory circuit 120 included in the memory cell 100[m,n] are indicated as the first memory circuit 110[m,n] and the second memory circuit 120[m,n], respectively.

[0151] 19, the wirings 103, 104, and 105 connected to the memory cells 100 arranged in the first row are denoted by wiring 103[1], wiring 104[1], and wiring 105[1], respectively. The wirings 103, 104, and 105 connected to the memory cells 100 arranged in the i-th row are denoted by wiring 103[i], wiring 104[i], and wiring 105[i], respectively. The wirings 103, 104, and 105 connected to the memory cells 100 arranged in the m-th row are denoted by wiring 103[m], wiring 104[m], and wiring 105[m], respectively.

[0152] 19, the signal WL supplied to the wiring 103[1] is denoted as the signal WL[1], the signal SET supplied to the wiring 104[1] is denoted as the signal SET[1], and the signal CHK supplied to the wiring 105[1] is denoted as the signal CHK[1]. The wirings and signals in the mth row and the wirings and signals in the i-th row are also denoted in the same manner.

[0153] 19, the wiring 101 connected to the memory cells 100 arranged in the first column is indicated as wiring 101[1], and the wiring 101 connected to the memory cells 100 arranged in the nth column is indicated as wiring 101[n]. The wiring 102 connected to the memory cells 100 arranged in the first column is indicated as wiring 102[1], and the wiring 102 connected to the memory cells 100 arranged in the nth column is indicated as wiring 102[n]. The wiring 106 connected to the memory cells 100 arranged in the first column is indicated as wiring 106[1], and the wiring 106 connected to the memory cells 100 arranged in the nth column is indicated as wiring 106[n]. The wiring 108 connected to the memory cells 100 arranged in the first column is indicated as wiring 108[1], and the wiring 108 connected to the memory cells 100 arranged in the nth column is indicated as wiring 108[n].

[0154] Furthermore, the memory cells 100 are connected to one correction circuit 130 (correction circuit 130a or correction circuit 130b) for each column. In FIG. 19, the correction circuit 130 (correction circuit 130a or correction circuit 130b) connected to the memory cells 100 arranged in the first column is shown as correction circuit 130[1]. Furthermore, the correction circuit 130 connected to the memory cells 100 arranged in the nth column is shown as correction circuit 130[n].

[0155] 19, the signal BL supplied to the wiring 101[1] is denoted as a signal BL[1], and the signal BLB supplied to the wiring 102[1] is denoted as a signal BLB[1]. Note that the wirings and signals in the n-th column are also denoted in the same manner.

[0156] 20A is a block diagram illustrating a configuration example of a memory device 300 including the memory cell 100 of one embodiment of the present invention. The memory device 300 illustrated in FIG. 20A includes a driver circuit 21, a memory cell array 200, and a correction circuit 130.

[0157] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0158] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0159] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0160] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0161] The voltage generating circuit 33 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when a signal of potential H is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a voltage.

[0162] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 100. The peripheral circuit 41 includes a row decoder , a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit .

[0163] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to be accessed, and the column decoder 44 is a circuit for specifying the column to be accessed. The row driver 43 has the function of selecting the wiring specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 100, the function of reading data from the memory cell 100, the function of holding the read data, etc.

[0164] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 100. The data (Dout) read from the memory cell 100 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0165] The PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. The PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply potential of the memory device 300 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to potential H, and is higher than VDD. The on / off of the PSW22 is controlled by a signal PON1, and the on / off of the PSW23 is controlled by a signal PON2. In FIG. 20A, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0166] 20B , a first memory circuit 110 and a driving circuit 21 may be provided in the layer 10. By providing the first memory circuit 110 and the driving circuit 21 in the layer 10, the first memory circuit 110 and the driving circuit 21 can be formed simultaneously, thereby improving the productivity of the memory device 300.

[0167] 20C , the driving circuit 21 may be provided on the layer 50, and the layers 10 and 20 may be provided on top of the layer 50. Like the layer 10, the layer 50 may be a single-crystal semiconductor substrate or an SOI substrate. The layers 50 and 10 may be connected using a through-electrode technique such as a through silicon via (TSV) or a bonding technique such as Cu-Cu direct bonding. By separately forming the layer 50 and the layer 10, which include the driving circuit 21, the operation of the driving circuit 21 included in the layer 50 can be confirmed before connecting the layer 50 and the layer 10. Therefore, only non-defective layers 50 can be connected to the layer 10, thereby improving the manufacturing yield of the memory device 300.

[0168] 20D , layers 10 and 20 constituting memory cell array 200 may be repeatedly stacked on layer 50 including driver circuit 21. FIG. 20D shows an example in which k layers (k is an integer of 2 or more) of layers 10 and k layers 20 are stacked on layer 50. Layers 10 and 20 provided as the first layers on layer 50 are denoted as layer 10[1] and layer 20[1], respectively, and layers 10 and 20 provided as the kth layers are denoted as layer 10[k] and layer 20[k], respectively.

[0169] By overlapping the layer 50 including the drive circuit 21 with the layers 10 and 20 that make up the memory cell array 200, the signal propagation distance between the drive circuit 21 and the memory cell array 200 can be shortened. This reduces the parasitic resistance and parasitic capacitance between the drive circuit 21 and the memory cell array 200, thereby reducing power consumption and signal delay. This also allows the memory device 300 to be miniaturized. This also allows the memory capacity per unit area to be increased.

[0170] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0171] Third Embodiment In this embodiment, a storage system 400 having a storage device 300 will be described.

[0172] <Storage System 400> Figure 21 shows a block diagram of the storage system 400. The storage system 400 has a storage device 300 and a control device 310. The control device 310 has an arithmetic unit 311, an input / output device 312, a timer device 313, a setting register 314, and an error address register 315. The storage device 300 and the control device 310 are each connected to a CPU (Central Processing Unit) 450 via a bus line 410. The CPU 450 has the function of supplying control signals for the storage device 300 and the control device 310, data to be written to the storage device 300, and write destination addresses to the storage system 400 via the bus line 410. Note that the storage system 400 can also be connected to not only the CPU 450, but also a communication device 420, an external storage device 430, a GPU (Graphics Processing Unit) 440, and the like via the bus line 410.

[0173] The memory device 300 also has a function of supplying the address of a memory cell 100 in which both the first signal and the second signal are active and an abnormal state has occurred to the control device 310 without passing through the bus line 410. The control device 310 also has a function of supplying control signals (signal SET, signal CHK) for the second memory circuit 120 of the memory cell 100 included in the memory device 300.

[0174] The arithmetic unit 311 included in the control device 310 detects a memory cell 100 in which an abnormality has occurred using the first signal and the second signal and acquires the address of the memory cell 100. Data is input to and output from the control device 310 via the input / output device 312. The timer unit 313 determines, for example, the interval at which memory scrubbing is performed. The setting register 314 stores control signals, such as operating parameters of the control device 310, supplied via the bus line 410. The error address register 315 stores the address of the memory cell 100 in which an abnormality has occurred. The error address register 315 also stores the address of the memory cell 100 to which the abnormality has occurred. Therefore, it is preferable to use a non-volatile storage device as the error address register 315. Furthermore, if a volatile storage device is used as the error address register 315, it is preferable to store the contents of the error address register 315 in an external storage device 430 or the like after updating the information in the error address register 315.

[0175] Data to be written to the storage device 300 is supplied to the storage device 300 via a bus line 410. Data held in the storage device 300 is read out via the bus line 410.

[0176] The first signal and the second signal output from the memory cell 100 are supplied to the control device 310 without passing through the bus line 410. Note that the first signal and the second signal output from the memory cell 100 can also be supplied to the control device 310 via the bus line 410.

[0177] Furthermore, the control signal related to the second memory circuit 120 is supplied from the control device 310 to the memory device 300 without passing through the bus line 410. Note that the control signal related to the second memory circuit 120 can also be supplied to the memory device 300 via the bus line 410.

[0178] Some or all of the functions of the control device 310 may be performed by the CPU 450. In this case, the control of the storage device 300 is performed via the bus line 410, which may slow down the operation of the storage system 400. On the other hand, the area occupied by the storage system 400 can be reduced.

[0179] <Example of Operation> Next, the operation of the storage system 400 will be described.

[0180] [Data Write Operation] The following describes the operation of writing data to the storage device 300 of the storage system 400. Figure 22A is a flowchart illustrating the data write operation. Figure 22B is a block diagram illustrating the operating state of the storage system 400.

[0181] In step S331, the CPU 450 supplies data of the write destination address and the data to be written to the storage system 400 via the bus line 410. For example, the CPU 450 supplies data of the write destination address to the control device 310 and supplies data to be written to the storage device 300.

[0182] In step S332, the storage system 400 checks whether the write destination address includes or does not include the abnormal status address recorded in the error address register 315. If the write destination address does not include the abnormal status address, the process proceeds to step S334.

[0183] If the write destination address includes an abnormal status address, the process proceeds to step S333, in which the abnormal status address is reassigned to the reassignment destination address recorded in the error address register 315.

[0184] In step S334, data is written to the memory device 300. As described in the above embodiment, in the memory cell 100 to be written, the same data is written to the first memory circuit 110 and the second memory circuit 120. The control device 310 supplies a control signal to the second memory circuit 120 of the memory cell 100 to be written, and writes the data to the first memory circuit 110 and the second memory circuit 120 of the memory cell 100. In this manner, data can be written to the memory device 300.

[0185] [Read Operation 1] The following describes the operation of reading data from the storage device 300 of the storage system 400. Figure 23A is a flowchart illustrating read operation 1. Figure 23B is a block diagram illustrating the operating state of the storage system 400.

[0186] Read operation 1 is a read operation that is performed when memory scrubbing of the storage system 400, which will be described later, is performed relatively frequently.

[0187] In step S341, the CPU 450 designates the data at the address where the data to be read is stored in the storage system 400 via the bus line 410.

[0188] In step S342, the storage system 400 supplies the data held at the address specified by the CPU 450 of the storage device 300 to the CPU 450 via the bus line 410. In other words, the CPU 450 reads the data held at the specified address from the storage device 300.

[0189] [Read Operation 2] A description will now be given of read operation 2, which is different from read operation 1. Fig. 24 is a flowchart illustrating read operation 2. Figs. 25A and 25B are block diagrams illustrating the operating states of storage system 400.

[0190] Read operation 2 is a read operation that is performed when memory scrubbing of the storage system 400, which will be described later, is performed relatively infrequently, or when memory scrubbing is not performed.

[0191] In step S343, the CPU 450 designates the data at the address where the data to be read is stored via the bus line 410 to the storage system 400.

[0192] In step S344, the control device 310 of the storage system 400 supplies the signal PRE and the signal CHK to the memory cell 100 associated with the specified address in the storage device 300, and performs an error check operation on the memory cell 100. As described in the above embodiment, by performing the error check operation, data correction is performed on the memory cell 100 in which a soft error has occurred.

[0193] In step S345, it is determined whether or not there is an abnormal state in the memory cell 100 associated with the specified address.

[0194] If the memory cell 100 associated with the specified address has an abnormality, the process proceeds to step S346. In step S346, the address of the memory cell 100 is recorded as an abnormality address in the error address register 315. Also, a normally operating empty address is set as a destination address for the abnormality address, and the destination address is recorded in the error address register 315 (see FIG. 25A).

[0195] In step S347, the CPU 450 is notified that an abnormality has occurred in the read target address.

[0196] If it is determined in step S345 that there is no error in the memory cell 100 associated with the specified address, the process proceeds to step S348.

[0197] In step S348, the storage system 400 supplies the data held at the address specified by the CPU 450 of the storage device 300 to the CPU 450 via the bus line 410. In other words, the CPU 450 reads the data held at the specified address from the storage device 300 via the bus line 410 (see FIG. 25B).

[0198] Although read operation 2 takes longer to read data than read operation 1, it can improve the reliability of the read data.

[0199] [Memory Scrubbing Operation] A description will now be given of memory scrubbing operation in the storage system 400. FIG.

[0200] In step S351, the process waits for a certain period of time. The frequency of memory scrubbing is determined by the wait time in step S351.

[0201] In step S352, it is determined whether or not to perform memory scrubbing. If a command to perform memory scrubbing is issued from CPU 450, or if a command to stop memory scrubbing is issued after the command to perform memory scrubbing but not after, memory scrubbing is performed. Also, if a command to stop memory scrubbing is issued from CPU 450, or if a command to perform memory scrubbing is issued after the command to stop memory scrubbing but not after, memory scrubbing is not performed.

[0202] In step S353, the control device 310 performs an error checking operation by supplying the signals PRE and CHK to the memory cells 100 at all addresses in the memory device 300. The error checking operation corrects the data in the memory cells 100 in which a bit inversion has occurred due to a soft error to the correct value.

[0203] In step S354, the presence or absence of an abnormal state is checked for the memory cells 100 at all addresses that the storage device 300 has.

[0204] If no abnormal memory cell 100 is found, the process proceeds to step S351. If an abnormal memory cell 100 is found, the process proceeds to step S355. In step S355, the address of the memory cell 100 is recorded in the error address register 315. In addition, an empty address that operates normally is set as a destination address for the abnormal address, and the destination address is recorded in the error address register 315.

[0205] In step S356, it is confirmed whether a certain number or more of memory cells 100 in an abnormal state have occurred. If the number of memory cells 100 in an abnormal state is less than the certain number, the process proceeds to step S351. If the number of memory cells 100 in an abnormal state has increased and it is not possible to set a transfer destination address when writing data, or if the number of memory cells 100 in an abnormal state is greater than the certain number, the process proceeds to step S357.

[0206] In step S357, a state signal informing the CPU 450 of an abnormality in the storage system 400 is supplied to the CPU 450. Then, the process proceeds to step S351. The CPU 450, having received the state signal informing the abnormality, determines whether or not to shut down the storage system 400.

[0207] By performing the memory scrubbing operation at a certain frequency, data can be read by the above-described read operation 1. This increases the data read speed. Furthermore, the memory device 300 including the memory cell 100 according to one embodiment of the present invention can correct data in the MBU, thereby reducing the frequency of memory scrubbing operations. This reduces the power consumption of the storage system 400.

[0208] Furthermore, the memory device 300 or the storage system 400 according to one embodiment of the present invention functions as an ECC memory that does not require check bits. Note that data with check bits added may be stored in the memory device 300 or the storage system 400 according to one embodiment of the present invention. In other words, by using the memory device 300 or the storage system 400 according to one embodiment of the present invention as a conventional ECC memory that adds check bits to data before storing it, the ability to correct soft errors can be further improved. In other words, the reliability of the semiconductor device can be further improved.

[0209] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0210] Fourth Embodiment In this embodiment, a description will be given of an example of a planar configuration and a cross-sectional configuration of a second memory circuit 120 provided in the layer 20. The second memory circuit 120 is a type of semiconductor device.

[0211] In this embodiment, an example of a planar configuration and an example of a cross-sectional configuration of the second memory circuit 120a will be described as an example of the second memory circuit 120. Fig. 27 is a plan view of the second memory circuit 120a as viewed from the Z direction. Fig. 28A is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 27 as viewed from the X direction. Fig. 28B is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in Fig. 27 as viewed from the Y direction. Note that in the plan view of Fig. 27, some components such as insulating layers are omitted for clarity.

[0212] 27 , 28A, and 28B, the second memory circuit 120a, which is a type of semiconductor device, includes an insulating layer 154 and conductive layers 155 (conductive layers 155[1], 155[3], and 155[5]) on the insulating layer 154. The second memory circuit 120a also includes an insulating layer 157 on the insulating layer 154 and the conductive layer 155, an insulating layer 158 on the insulating layer 157, and an insulating layer 159 on the insulating layer 158. In this specification and other documents, the insulating layers 157, 158, and 159 may be collectively referred to as an insulating layer 156 or a spacer layer. The second memory circuit 120a also includes a conductive layer 161 (conductive layers 161[1] to 161[3]) and a conductive layer 106 (not shown in FIGS. 28A and 28B) on the insulating layer 159.

[0213] 27 and 28A , in a region overlapping with a portion of the conductive layer 155[1], an opening 162[1] is provided in the conductive layer 161[1], the insulating layer 159, the insulating layer 158, and the insulating layer 157. In another region overlapping with a portion of the conductive layer 155[1], an opening 162[2] is provided in the insulating layer 159, the insulating layer 158, and the insulating layer 157. In addition, a semiconductor layer 163[1] covering the opening 162[1] and a semiconductor layer 163[2] covering the opening 162[2] are provided.

[0214] The semiconductor layer 163[1] has a region overlapping the bottom of the opening 162[1] and a region overlapping the side surface of the opening 162[1]. That is, the semiconductor layer 163[1] has a region in contact with the insulating layer 156. The semiconductor layer 163[1] also has a region in contact with the conductive layer 155[1] and a region in contact with the conductive layer 161[1]. The semiconductor layer 163[1] may also have a region extending beyond the end of the conductive layer 161[1].

[0215] The semiconductor layer 163[2] has a region that overlaps with the bottom of the opening 162[2] and a region that overlaps with the side surface of the opening 162[2]. That is, the semiconductor layer 163[2] has a region that contacts the insulating layer 156. The semiconductor layer 163[2] also has a region that contacts the conductive layer 155[1] and a region that contacts the conductive layer 161[2]. The semiconductor layer 163[2] may also have a region that extends beyond the end of the conductive layer 161[2].

[0216] 28A , an insulating layer 164 is provided over the insulating layer 159, the conductive layer 161[1], the semiconductor layer 163[1], the conductive layer 161[2], and the semiconductor layer 163[2]. A conductive layer 165[1] and a conductive layer 165[2] are provided over the insulating layer 164. The conductive layer 165[1] has a region overlapping with the semiconductor layer 163[1]. The conductive layer 165[2] has a region overlapping with the semiconductor layer 163[2].

[0217] 28B, a conductive layer 165[4] is provided on the insulating layer 164. The conductive layer 165[4] has a region overlapping with a part of the conductive layer 161[1] and a region overlapping with a part of the conductive layer 161[3].

[0218] 28A , the insulating layer 164 and the conductive layer 165[1] each have an area overlapping with the opening 162[1]. The insulating layer 164 and the conductive layer 165[2] each have an area overlapping with the opening 162[2]. In the opening 162[1], the semiconductor layer 163[1] has an area overlapping with the conductive layer 161[1] via the insulating layer 164 and an area overlapping with the side surface of the opening 162[1] (the side surface of the insulating layer 156). In the opening 162[2], the semiconductor layer 163[2] has an area overlapping with the conductive layer 161[2] via the insulating layer 164 and an area overlapping with the side surface of the opening 162[2] (the other side surface of the insulating layer 156).

[0219] Here, the thickness of the semiconductor layer 163 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less. The thickness of the insulating layer 164 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. It is sufficient that at least a part of the insulating layer 164 has a region with the above-described thickness.

[0220] An opening 168 overlapping the conductive layer 161[1] is provided in a part of the insulating layer 164. In the opening 168, the conductive layer 161[1] and the conductive layer 165[2] are connected to each other.

[0221] 28A , an insulating layer 167 is provided on the insulating layer 164 and the insulating layer 166. The top surface of the insulating layer 166 is preferably flat. Alternatively, the top surfaces of the insulating layer 166, the conductive layer 165[1], and the conductive layer 165[2] may be aligned or approximately aligned (in the Z direction). For example, chemical mechanical polishing (CMP) or the like can be performed to improve the flatness of the top surface of the insulating layer 166. Furthermore, the CMP process can be performed to ensure that the top surfaces of the insulating layer 166, the conductive layer 165[1], and the conductive layer 165[2] are aligned or approximately aligned. The CMP process reduces the unevenness of the sample surface, improving the coverage of the insulating and conductive layers to be formed subsequently. Also, in FIG. 28A , the insulating layer 167 is provided on the conductive layer 165[1], the conductive layer 165[2], and the insulating layer 166.

[0222] 28B, an opening 169 overlapping with the conductive layer 161[3] is provided in a portion of the insulating layer 164. The conductive layer 161[3] and the conductive layer 165[4] are connected through the opening 169. The region where the conductive layer 161[1] and the conductive layer 165[4] overlap with each other via the insulating layer 164 functions as a capacitance element Cs. Therefore, a portion of the conductive layer 161[1] functions as one terminal of the capacitance element Cs, and a portion of the conductive layer 165[4] functions as the other terminal of the capacitance element Cs. Also, in FIG. 28B, an insulating layer 167 is provided on the conductive layer 165[2], the conductive layer 165[4], and the insulating layer 166.

[0223] The conductive layer 161[1] and the conductive layer 165[2] function as a node SN of the memory cell 100. The conductive layer 161[3] and the conductive layer 165[4] function as a node SNB of the memory cell 100.

[0224] 27 and 28A, the region overlapping with the opening 162[1] functions as the transistor Tr21. The region overlapping with the opening 162[2] functions as the transistor Tr22. Therefore, a portion of the conductive layer 161[1] functions as one of the source electrode and the drain electrode of the transistor Tr21. A portion of the conductive layer 155[1] functions as the other of the source electrode and the drain electrode of the transistor Tr21. For example, when a portion of the conductive layer 161[1] functions as the drain electrode of the transistor Tr21, a portion of the conductive layer 155[1] functions as the source electrode of the transistor Tr21. The conductive layer 155[1] functions as the node Q of the memory cell 100.

[0225] The semiconductor layer 163[1] functions as a semiconductor layer (a semiconductor layer including a channel formation region) in which the channel of the transistor Tr21 is formed, a part of the insulating layer 164 functions as a gate insulating layer, and the conductive layer 165[1] functions as a gate electrode.

[0226] Furthermore, a part of the conductive layer 161[2] functions as one of the source electrode and the drain electrode of the transistor Tr22. Another part of the conductive layer 155[1] functions as the other of the source electrode and the drain electrode of the transistor Tr22. For example, when a part of the conductive layer 161[2] functions as the drain electrode of the transistor Tr22, another part of the conductive layer 155[1] functions as the source electrode of the transistor Tr22. The semiconductor layer 163[2] functions as a semiconductor layer in which a channel of the transistor Tr22 is formed, another part of the insulating layer 164 functions as a gate insulating layer, and the conductive layer 165[2] functions as a gate electrode.

[0227] 27, transistors Tr23, Tr24, Tr25, and Tr26 have the same configuration as transistors Tr21 and Tr22. The configuration of transistor Tr23 can be understood by replacing conductive layer 155[1] with conductive layer 155[3], conductive layer 161[1] with conductive layer 161[3], opening 162[1] with opening 162[3], and semiconductor layer 163[1] with semiconductor layer 163[3] in the above description. Note that conductive layer 155[3] functions as node QB of memory cell 100.

[0228] Furthermore, the configuration of transistor Tr24 can be understood by replacing conductive layer 155[1] with conductive layer 155[3], conductive layer 161[2] with conductive layer 161[4], opening 162[5] with opening 162[6], and semiconductor layer 163[2] with semiconductor layer 163[4] in the above description.

[0229] The configuration of the transistor Tr25 can be understood by replacing the conductive layer 155[1] with the conductive layer 155[5], the conductive layer 161[2] with the conductive layer 161[5], the opening 162[2] with the opening 162[5], and the semiconductor layer 163[2] with the semiconductor layer 163[5] in the above description. In addition, in FIG. 27, a part of the conductive layer 161[2] functions as the conductive layer 161[5].

[0230] The configuration of the transistor Tr26 can be understood by replacing the conductive layer 155[3] with the conductive layer 155[6], the conductive layer 161[4] with the conductive layer 161[6], the opening 162[4] with the opening 162[6], and the semiconductor layer 163[4] with the semiconductor layer 163[6] in the above description. Also, in FIG. 27, a part of the conductive layer 161[4] functions as the conductive layer 161[6].

[0231] The conductive layer 165[1] is connected to the wiring 103. FIG. 27 shows an example in which part of the wiring 103 functions as the conductive layer 165[1]. A conductive layer 165[3] provided in the same layer as the conductive layer 165[1] is also connected to the wiring 103. FIG. 27 shows an example in which part of the wiring 103 functions as the conductive layer 165[3]. A conductive layer 165[5] and a conductive layer 165[6] provided in the same layer as the conductive layer 165[1] are connected to the wiring 105. FIG. 27 shows an example in which part of the wiring 105 functions as the conductive layer 165[5] and another part of the wiring 105 functions as the conductive layer 165[6]. The conductive layer 155[5] is connected to the wiring 106. The conductive layer 155[6] is connected to the wiring 108.

[0232] Transistors Tr21 to Tr26 shown in Figures 27, 28A, and 28B are transistors whose source electrodes and drain electrodes are arranged in the Z direction. That is, the sources and drains of transistors Tr21 to Tr26 are arranged at different heights. In other words, the sources and drains of transistors Tr21 to Tr26 are arranged at different positions in the Z direction. Such transistors are also called "vertical channel transistors," "vertical channel transistors," "vertical transistors," or "VFETs (Vertical Field Effect Transistors)."

[0233] A vertical transistor can occupy a smaller area than a conventional transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, by using a vertical channel transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using a vertical channel transistor in a semiconductor device, high integration of the semiconductor device can be achieved. Furthermore, the storage capacity per unit area of ​​a memory device using the semiconductor device can be increased.

[0234] Furthermore, in planar transistors, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. In vertical channel transistors, the channel formation region is formed along the side surface of the insulating layer 156 or 158. Therefore, in the vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the film thickness of the insulating layer 156 or 158. Therefore, the channel length of the transistor can be made into an extremely fine structure (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more) that is equal to or less than the exposure limit of photolithography. This increases the on-state current of the transistors Tr21 to Tr25, thereby improving frequency characteristics. By using vertical channel transistors, a semiconductor device with high operating speed can be provided.

[0235] Note that although a vertical channel transistor is described as an example of a transistor in this embodiment, the present invention is not limited thereto. For example, transistors with various structures, such as planar type, staggered type, FIN type, TRI-GATE type, top-gate type, bottom-gate type, or dual-gate type (a structure in which gates are arranged on both sides (e.g., above and below) of a channel formation region), can be used in the semiconductor device according to one embodiment of the present invention.

[0236] <Constituent Materials> An example of a material that can be used for the second memory circuit 120a, which is a type of semiconductor device, will be described.

[0237] [Substrate] When a semiconductor device is provided on a substrate, there are no significant limitations on the material used for the substrate. The material can be determined depending on the purpose, taking into consideration factors such as whether the substrate is light-transmitting or not and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Also usable are semiconductor substrates, flexible substrates, and resin substrates.

[0238] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrate, such as an SOI substrate. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0239] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Also, there are substrates containing metal nitrides, substrates containing metal oxides, etc. Furthermore, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

[0240] Examples of materials that can be used for flexible substrates or resin substrates include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0241] By using the above materials for the substrate, a lightweight semiconductor device can be provided.Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided.Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to breakage can be provided.

[0242] Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0243] [Insulating Layer] The insulating layer can be made of an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like. For example, the insulating layer can be made of a single layer or a stack of insulating materials selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like. Alternatively, a combination of oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

[0244] In this specification and elsewhere, a nitride oxide refers to a material containing more nitrogen than oxygen. An oxynitride refers to a material containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0245] As transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulating layers. By using a high-k material (a high dielectric constant material, a material with a high relative dielectric constant) for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, lead zirconate titanate (Pb(Zr,Ti)O ３ , also known as "PZT"), strontium titanate (SrTiO３ (also called "STO"), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant, such as bismuth trioxide (BST), can be used. On the other hand, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is preferable to select a material depending on the function required for the insulating layer.

[0246] Furthermore, examples of materials with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0247] Furthermore, materials with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or resin.

[0248] The method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[0249] For example, the insulating layer 154 and the insulating layer 167 are preferably formed using an insulating material that is impermeable to impurities. For example, an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Examples of insulating materials that are impermeable to impurities include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride.

[0250] By using an insulating material that is impervious to impurities for the insulating layer 154, diffusion of impurities from below can be suppressed, and the reliability of the transistor can be improved. That is, the reliability of a semiconductor device including a transistor can be improved. By using an insulating material that is impervious to impurities for the insulating layer 167, diffusion of impurities from above the insulating layer 167 can be suppressed, and the reliability of the transistor can be improved. That is, the reliability of a semiconductor device including a transistor can be improved.

[0251] Alternatively, an insulating layer that can function as a planarizing layer may be used as the insulating layer. Examples of materials that function as a planarizing layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimideamide, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors thereof. In addition to the above organic materials, low-k materials (low dielectric constant materials, materials with a small relative dielectric constant), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), and the like can also be used. Note that multiple insulating layers made of these materials may be stacked.

[0252] The siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane resin may have an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may also have a fluoro group.

[0253] Alternatively, a three-layer insulating layer (also referred to as "ZAZ") having aluminum oxide sandwiched between two layers of zirconium oxide may be used as the insulating layer 164 that functions as the dielectric of the capacitance element Cs. ZAZ is a material with a high relative dielectric constant, and by using ZAZ as the dielectric of the capacitance element Cs, the area occupied by the capacitance element Cs can be reduced.

[0254] [Conductive Layer] Examples of conductive materials that can be used for conductive layers such as various wirings and electrodes that constitute a semiconductor device include metal elements selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), and ruthenium (Ru), alloys containing the above-mentioned metal elements as components, and alloys combining the above-mentioned metal elements.

[0255] For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used. The method for forming the conductive material is not particularly limited, and various formation methods such as vapor deposition, atomic layer deposition (ALD), CVD, sputtering, and spin coating can be used. As the ALD method, either one or both of a thermal ALD method and a PEALD method (Plasma Enhanced ALD) can be used.

[0256] Alternatively, a Cu-X alloy (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive material. A layer formed of a Cu-X alloy can be processed by a wet etching process, thereby reducing manufacturing costs. Alternatively, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.

[0257] In addition, conductive materials that can be used for the conductive layer include conductive materials containing oxygen, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon oxide has been added. Furthermore, conductive materials containing nitrogen, such as titanium nitride, tantalum nitride, and tungsten nitride, can also be used. The conductive layer can also have a stacked structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above-mentioned metal element are appropriately combined.

[0258] For example, the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a tantalum nitride layer, or a three-layer structure in which a titanium layer, an aluminum layer is stacked on the titanium layer, and a titanium layer is further stacked on the aluminum layer.

[0259] Furthermore, a plurality of conductive layers formed from the above-described conductive materials may be stacked. For example, the conductive layer may have a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined. Alternatively, the conductive layer may have a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined. Alternatively, the conductive layer may have a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

[0260] For example, the conductive layer may have a three-layer structure in which a conductive layer containing at least one of indium and zinc and oxygen is stacked on a conductive layer containing copper, and a conductive layer containing at least one of indium and zinc and oxygen is further stacked on top of that. In this case, it is preferable that the side surface of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium and zinc and oxygen. Furthermore, for example, a plurality of conductive layers containing at least one of indium and zinc and oxygen may be stacked as the conductive layer.

[0261] [Semiconductor Layer] As the semiconductor layer, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. The semiconductor material is not limited to a simple semiconductor whose main component is a single element (e.g., silicon, germanium, etc.), but a compound semiconductor (e.g., silicon germanium, silicon carbide, gallium arsenide, nitride semiconductor, etc.) can also be used. Furthermore, as the compound semiconductor, an organic substance having semiconductor properties or a metal oxide having semiconductor properties (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may contain impurities as dopants.

[0262] For example, the semiconductor layer may be made of single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon. As the polycrystalline silicon, for example, low temperature polysilicon (LTPS) may be used.

[0263] Transistors using amorphous silicon for the semiconductor layer can be formed on large glass substrates and can be manufactured at low cost. Transistors using polycrystalline silicon for the semiconductor layer have high field-effect mobility and can operate at high speed. Transistors using microcrystalline silicon for the semiconductor layer have higher field-effect mobility and can operate at high speed than transistors using amorphous silicon.

[0264] The semiconductor layer may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0265] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0266] As described in the above embodiment, an oxide semiconductor has a band gap of 2 eV or more, and therefore, an OS transistor has an extremely low off-state current. The off-state current of an OS transistor per 1 μm of channel width in a room temperature environment is 1 a (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４A) or less. Furthermore, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in their characteristics. For example, OS transistors can perform favorable switching operations even in environments of 125° C. or higher and 200° C. or lower because they have a large ratio of on current to off current. Furthermore, a memory circuit or a memory element using an OS transistor is less susceptible to soft errors caused by radiation such as cosmic rays, thereby improving the reliability of the memory circuit or the memory element.

[0267] Therefore, in this embodiment and the like, it is preferable to use OS transistors as the transistors Tr21 to Tr25. Furthermore, since the OS transistor has a high withstand voltage between the source and drain, the channel length can be shortened. Therefore, the on-state current can be increased. OS transistors are suitable for vertical channel transistors.

[0268] Examples of metal oxides that can be used for the semiconductor layer of an OS transistor include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium.

[0269] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0270] For example, metal oxides that can be used for a semiconductor layer of an OS transistor include indium oxide (In oxide), indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Gal oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as “GZO”), and aluminum zinc oxide (Al—Zn oxide, also referred to as “AZO”). Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Gal-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0271] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0272] The metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0273] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0274] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0275] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0276] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be realized.

[0277] When an In-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc may be used. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a metal oxide in a range thereof, may be used.

[0278] When an In—Sn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin may be used, for example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a metal oxide in a range thereof may be used.

[0279] When an In-Sn-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of tin may be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of tin is preferably used. For example, the atomic ratios of metal elements may be In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, Metal oxides having a ratio of In:Sn:Zn=10:1:3, In:Sn:Zn=10:1:6, In:Sn:Zn=10:1:7, In:Sn:Zn=10:1:8, In:Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10, or similar ratios may also be used.

[0280] When an In-Al-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of aluminum may be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of aluminum may be used. For example, the atomic ratios of metal elements may be In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, Metal oxides having a composition of In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn=10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10, or similar metal oxides may also be used.

[0281] When an In—Ga—Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than that of gallium may be used. Furthermore, a metal oxide in which the atomic ratio of zinc to the number of atoms of gallium is preferably used. For example, the semiconductor layer may have an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, or In:Ga:Zn=6:1. :6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof may also be used.

[0282] When an In-M-Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M may be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc to the number of atoms of the element M is higher than the atomic ratio of the element M. For example, the semiconductor layer may have atomic ratios of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, or In:M:Zn=6:1: Alternatively, metal oxides of In:M:Zn=10:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides of these or similar ratios may be used.

[0283] When an In-M-Zn oxide is used for the semiconductor layer, the atomic ratio of the metal elements may be In:M:Zn = 1:3:2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:3:4 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:1 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:2 [atomic ratio] or a composition thereabout, or In:M:Zn = 4:2:3 [atomic ratio] or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as the element M.

[0284] When a plurality of metal elements are contained as the element M, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Gal-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned ranges.

[0285] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In-M-Zn oxide is used for the semiconductor layer, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is in the above-mentioned range.

[0286] As described above, by increasing the ratio of the number of indium atoms to the total number of metal element atoms among the main component elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. By using the transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced.

[0287] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0288] The metal oxide can be preferably formed by a sputtering method or an ALD method. When forming a metal oxide by a sputtering method, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0289] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0290] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature Stress (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature Stress (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and a NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0291] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on, and therefore the amount of variation in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0292] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS test can be obtained. Furthermore, when using a metal oxide that contains gallium, it is preferable to make the gallium content lower than the indium content. This allows for a highly reliable transistor to be realized.

[0293] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0294] The reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test is, for example, that the gallium contained in the metal oxide has a tendency to attract oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to create carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing fluctuations in threshold voltage.

[0295] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than that of gallium can be used for the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In > Ga and Zn > Ga for the semiconductor layer.

[0296] For example, the semiconductor layer of the OS transistor may contain metal elements having an atomic ratio of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn= Examples of the composition include In:Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, and metal oxides thereof having similar ratios can be used.

[0297] The semiconductor layer of an OS transistor preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to a PBTS test can be obtained. Including gallium in the metal oxide can prevent oxygen deficiency (V) in the metal oxide. Ｏ This has the effect of making oxygen vacancy less likely to occur.

[0298] A metal oxide containing no gallium may be used for the semiconductor layer of an OS transistor. For example, In—Zn oxide may be used for the semiconductor layer. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability. Furthermore, a metal oxide containing no gallium or zinc, such as indium oxide, may be used for the semiconductor layer. The use of a metal oxide containing no gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0299] For example, the semiconductor layer can be made of an oxide containing indium and zinc, in which the atomic ratio of the metal elements is, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these values.

[0300] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where element M is used instead of gallium. For the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.

[0301] A transistor having high reliability against application of a positive bias can be realized by using a metal oxide having a low content of element M in a semiconductor layer. By applying the transistor to a transistor that requires high reliability against application of a positive bias, a highly reliable semiconductor device can be realized.

[0302] The semiconductor layer may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer may have the same or substantially the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0303] The two or more metal oxide layers included in the semiconductor layer may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a similar composition and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a similar composition provided on the first metal oxide layer is suitable. Gallium or aluminum is particularly preferred as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.

[0304] Alternatively, for example, a stacked structure may be used, which includes a first metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition close thereto, and a second metal oxide layer having an atomic ratio of In:Zn=4:1 or a composition close thereto, which is provided on the first metal oxide layer.

[0305] The semiconductor layer is preferably a crystalline metal oxide layer. For example, a metal oxide layer having a c-axis aligned crystal (CAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer, the density of defect states in the semiconductor layer can be reduced, and a highly reliable display device can be realized.

[0306] The higher the crystallinity of a metal oxide layer used in a semiconductor layer, the more the density of defect states in the semiconductor layer can be reduced.On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0307] When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) during formation, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0308] The semiconductor layer of an OS transistor may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided over the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition. The stacked structure of metal oxide layers with the same composition can be formed using the same sputtering target, for example, which reduces manufacturing costs. For example, a stacked structure of two or more metal oxide layers with different crystallinity may be formed using the same sputtering target with different oxygen flow rates. Note that the two or more metal oxide layers included in the semiconductor layer may have different compositions.

[0309] When an oxide semiconductor is used for the semiconductor layer 163, it is preferable to use a material containing hydrogen for the insulating layers 157 and 159. When the insulating layer containing hydrogen is in contact with the oxide semiconductor, the oxide semiconductor in the region in contact with the insulating layer becomes n-type and can function as a source region or a drain region. For example, a material containing silicon, nitrogen, and hydrogen may be used for the insulating layer. Specifically, silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen may be used.

[0310] The thicknesses of the insulating layers 157 and 159 are preferably 1 nm to 15 nm, more preferably 2 nm to 10 nm, still more preferably 3 nm to 7 nm, and further preferably 3 nm to 5 nm. When an oxide semiconductor is used for the semiconductor layer 163, a region of the semiconductor layer 163 in contact with the insulating layer 157 containing hydrogen and a region of the semiconductor layer 163 in contact with the insulating layer 159 containing hydrogen function as a source region or a drain region. The sizes of the source region and the drain region formed in the semiconductor layer 163 can be controlled by adjusting the thicknesses of the insulating layers 157 and 159.

[0311] The thickness of the insulating layer 158 is preferably 1 nm to 50 nm, more preferably 2 nm to 30 nm, and further preferably 3 nm to 20 nm. By adjusting the thickness of the insulating layer 158, the size of the channel formation region of the semiconductor layer 163 can be controlled.

[0312] The thicknesses of the insulating layers 157, 158, and 159 are preferably set appropriately according to the characteristics desired for the transistors.

[0313] Furthermore, it is preferable that the insulating layers 157, 158, and 159 are successively formed without being exposed to the air environment during the formation of the insulating layers 157, 158, and 159. By successively forming the insulating layers 157, 158, and 159 without being exposed to the air environment during the formation of the insulating layers 157, 158, and 159, it is possible to prevent impurities or moisture from the air environment from adhering to the interface between the insulating layers 157 and 158 and the vicinity thereof, and to the interface between the insulating layers 158 and 159 and the vicinity thereof.

[0314] When an oxide semiconductor is used for the semiconductor layer 163, the conductive layer 155 in contact with the semiconductor layer 163 and the conductive layer 161 in contact with the semiconductor layer 163 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0315] On the other hand, when an oxide semiconductor is used for the semiconductor layer 163, it is preferable to use a material containing oxygen and in which hydrogen is reduced for the insulating layer 158. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 163, which is an oxide semiconductor, and the insulating layer 158 in which hydrogen is reduced makes it difficult for the semiconductor layer 163 to become n-type. Furthermore, contact between the semiconductor layer 163, which is an oxide semiconductor, and the insulating layer 158 containing oxygen reduces oxygen vacancies in the semiconductor layer 163, thereby stabilizing the characteristics of the transistor and improving its reliability.

[0316] When an oxide semiconductor is used for the semiconductor layer 163, the insulating layer 158 preferably contains excess oxygen. In this specification and the like, "excess oxygen" refers to oxygen that is released by heating. When a material containing excess oxygen is used for the insulating layer 158, a material that is impermeable to oxygen is preferably used for the insulating layers 157 and 159. Examples of the material that is impermeable to oxygen include an oxide containing one or both of aluminum and hafnium, and a nitride of silicon. By using a material that is impermeable to oxygen for the insulating layers 157 and 159, the excess oxygen contained in the insulating layer 158 is less likely to be released to the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure in which an insulating layer containing silicon and oxygen (insulating layer 158) is provided between two insulating layers containing silicon and nitrogen (insulating layer 157 and insulating layer 159) is preferably used.

[0317] Furthermore, by using an oxide semiconductor for the semiconductor layer 163 and using a material containing hydrogen for the insulating layers 157 and 159, hydrogen is supplied to a region of the semiconductor layer 163 in contact with the insulating layer 157 and a region of the semiconductor layer 163 in contact with the insulating layer 159, and each region of the semiconductor layer 163 becomes n-type. Therefore, the region of the semiconductor layer 163 in contact with the conductive layer 161 and the region of the semiconductor layer 163 in contact with the insulating layer 159 function as one of a source (source region) and a drain (drain region). Furthermore, the region of the semiconductor layer 163 in contact with the conductive layer 155 and the region of the semiconductor layer 163 in contact with the insulating layer 157 function as the other of the source (source region) and the drain (drain region).

[0318] 29A shows an enlarged cross-sectional view of the transistor Tr21 shown in FIG. 28A. In the above configuration, in the transistor Tr21, which is a VFET, the length of the side surface of the insulating layer 158 as viewed from the X direction or the Y direction is the channel length L (channel length L1) (see FIG. 29A). Therefore, the channel length L of the transistor Tr21 is determined according to the thickness t1 of the insulating layer 158.

[0319] Alternatively, the insulating layer 157 and the insulating layer 159 may be formed using a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride or silicon nitride oxide containing very little hydrogen may be used. In this case, the region of the semiconductor layer 163[1] in contact with the insulating layer 157 and the region of the semiconductor layer 163[1] in contact with the insulating layer 159 are not made n-type. Therefore, the region of the semiconductor layer 163[1] in contact with the conductive layer 161[1] functions as either a source (source region) or a drain (drain region). The region of the semiconductor layer 163[1] in contact with the conductive layer 155[1] functions as the other of the source (source region) or the drain (drain region). The region of the semiconductor layer 163[1] in contact with the insulating layer 158 functions as a channel formation region.

[0320] In this case, the sum of the lengths of the sides of insulating layer 157, insulating layer 158, and insulating layer 159 as viewed from the X direction or the Y direction is channel length L (channel length L2). Therefore, the channel length L of transistor Tr21 is determined according to thickness t2, which is the sum of the thicknesses of insulating layer 157, insulating layer 158, and insulating layer 159.

[0321] 30A and 30B show a modified example of FIG. 29A . For example, a configuration may be adopted in which only insulating layer 158 is provided without insulating layers 157 and 159, and insulating layer 158 is in contact with conductive layer 155[1] and conductive layer 161[1] (see FIG. 30A ). In this case, the length of the side surface of insulating layer 158 as viewed from the X or Y direction is the channel length L. Therefore, the channel length L of transistor Tr21 is determined according to the thickness t of insulating layer 158. In the configuration shown in FIG. 30A , insulating layer 158 may also be referred to as insulating layer 156. Note that channel length L shown in FIG. 30A is synonymous with channel length L2 shown in FIG. 29A , and thickness t shown in FIG. 30A is synonymous with thickness t2 shown in FIG. 29A .

[0322] Furthermore, when an oxide semiconductor is used for the semiconductor layer 163[1], a material containing hydrogen is used for the insulating layers 157 and 159, and a material containing excess oxygen is used for the insulating layer 158, hydrogen contained in the insulating layers 157 and 159 and excess oxygen contained in the insulating layer 158 are bonded to each other, and sufficient hydrogen is not supplied to a region of the semiconductor layer 163[1] in contact with the insulating layer 157 and a region of the semiconductor layer 163[1] in contact with the insulating layer 159, making it difficult to make the semiconductor layer 163[1] n-type. Similarly, sufficient oxygen is not supplied to a region of the semiconductor layer 163[1] in contact with the insulating layer 158.

[0323] To solve this problem, insulating layer 171, which is impervious to oxygen and nitrogen, may be provided between insulating layer 157 and insulating layer 158, and insulating layer 172, which is impervious to oxygen and nitrogen, may be provided between insulating layer 159 and insulating layer 158 (see FIG. 30B ). The material which is impervious to oxygen and nitrogen can be realized using, for example, silicon nitride. In the configuration shown in FIG. 30B , insulating layer 157, insulating layer 171, insulating layer 158, insulating layer 172, and insulating layer 159 may be collectively referred to as insulating layer 156.

[0324] By using a material that is difficult for oxygen to permeate for the insulating layers 171 and 172, bonding between hydrogen contained in the insulating layers 157 and 159 and excess oxygen contained in the insulating layer 158 is inhibited. Therefore, sufficient hydrogen is supplied to the region of the semiconductor layer 163[1] in contact with the insulating layer 157 and the region of the semiconductor layer 163[1] in contact with the insulating layer 159. Similarly, sufficient oxygen is supplied to the region of the semiconductor layer 163[1] in contact with the insulating layer 158.

[0325] In this case, the sum of the lengths of the sides of insulating layer 171, insulating layer 158, and insulating layer 172 as viewed from the X direction or the Y direction is the channel length L3. Therefore, the channel length L of transistor Tr21 is determined according to the thickness t3 obtained by adding up the thicknesses of insulating layer 171, insulating layer 158, and insulating layer 172.

[0326] In the transistor Tr21 according to one embodiment of the present invention, the channel length L is determined depending on the thickness of the insulating layer provided between the conductive layer 161[1] and the conductive layer 155[1]. Therefore, a transistor with a short channel length L can be manufactured with high precision. Furthermore, the variation in characteristics among the plurality of transistors Tr21 is reduced. Therefore, the operation of a semiconductor device including the transistor Tr21 is stabilized, and the reliability can be improved. Furthermore, the reduced variation in characteristics increases the degree of freedom in the circuit design of the semiconductor device, and the operating voltage can also be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0327] In this embodiment, a structure having three insulating layers (insulating layer 157, insulating layer 158, insulating layer 159) or five insulating layers (insulating layer 157, insulating layer 158, insulating layer 159, insulating layer 171, insulating layer 172) between the conductive layer 155[1] and the conductive layer 161[1] is shown, but the number of insulating layers between the conductive layer 155[1] and the conductive layer 161[1] is not limited to this. The insulating layer between the conductive layer 155[1] and the conductive layer 161[1] can be one or two layers, or can be four or six or more layers.

[0328] 31 , as long as there is no problem with the coverage of the semiconductor layer 163[1], the insulating layer 164, and the conductive layer 165[1], the side surface of the opening 162[1] may be perpendicular or approximately perpendicular to the surface on which the opening 162[1] is to be formed (for example, the top surface of the conductive layer 155[1]). By making the side surface of the opening 162[1] perpendicular or approximately perpendicular, the area occupied by the transistor Tr21 can be reduced. Therefore, the area occupied by the memory element including the transistor Tr21 can be reduced.

[0329] To improve the coverage of the semiconductor layer 163[1], insulating layer 164, and conductive layer 165[1] formed in the opening 162[1], the taper angle θ of the side surface of the opening 162[1], i.e., the taper angle θ of each of the side surfaces of the insulating layer 157, insulating layer 158, and insulating layer 159, is preferably 45 degrees or more and 90 degrees or less, and more preferably 50 degrees or more and 75 degrees or less. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface and the side surface of the layer (see FIG. 29A).

[0330] Furthermore, because the semiconductor layer 163[1] is provided in the opening 162[1], the perimeter of the opening 162[1] when viewed from the Z direction is the channel width W of the transistor Tr21 (see FIG. 29B). The perimeter can be determined, for example, at a position halfway through the thickness t1 or halfway through the thickness t2 of the insulating layer 158. Note that, if necessary, the perimeter of any position on the opening 162[1] may be used as the channel width W. For example, the perimeter of the bottom of the opening 162[1] may be used as the channel width W, or the perimeter of the top of the opening 162[1] may be used as the channel width W.

[0331] In the memory device of one embodiment of the present invention, the channel length L is preferably smaller than at least the channel width W. In one embodiment of the present invention, the channel length L is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W.

[0332] In addition, although the outline (planar shape) of the opening 162[1] as viewed from the Z direction is shown as a circle in Figure 29B, this is not limiting. For example, the outline of the opening 162[1] as viewed from the Z direction can be an ellipse (see Figure 29C) or a rectangle (see Figure 29D). Note that Figure 29D shows a rectangle with curved corners. For example, the outline of the opening 162[1] as viewed from the Z direction can be a shape that includes either or both straight and curved portions (see Figure 29E).

[0333] The opening 162[1] is preferably fine. For example, the maximum width of the opening 162[1] as viewed from the Z direction (or the maximum diameter if the opening 162[1] is circular) is preferably 60 nm or less, more preferably 50 nm or less, even more preferably 40 nm or less, and most preferably 30 nm or less. The maximum width of the opening 162[1] as viewed from the Z direction may be 20 nm or less. The minimum width of the opening 162[1] as viewed from the Z direction (or the minimum diameter if the opening 162[1] is circular) is preferably 1 nm or more, more preferably 5 nm or more. To form such a fine opening 162[1], it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0334] Figure 32A shows a variation of the VFET, transistor 651. Figure 32A shows a cross section of transistor 651.

[0335] 32A is also a modified example of the transistor Tr21. In the transistor Tr21, a part of the conductive layer 165 functioning as the gate electrode is provided inside the opening 162. On the other hand, in the transistor 651, the conductive layer 175 functioning as the gate electrode is provided outside the opening 162.

[0336] In the structure shown as the transistor Tr21 in FIG. 29A and the like, if the width of the opening 162 as viewed in the Z direction (or the diameter if the opening 162 is circular) is reduced for the purpose of miniaturization, the conductive layer 165 functioning as a gate electrode is less likely to be formed inside the opening 162. In the structure shown as the transistor 651, the conductive layer 175 functioning as a gate electrode is located outside the opening 162, and therefore the above-described concern does not arise. Therefore, the area of ​​the memory element can be easily reduced and miniaturized, and design flexibility can be increased. Furthermore, the memory density of a memory device using a memory element according to one embodiment of the present invention can be further increased.

[0337] 32A includes a conductive layer 175 over an insulating layer 157, an insulating layer 159 over the conductive layer 175, and a conductive layer 161 over the insulating layer 159. Furthermore, in a region overlapping with the conductive layer 155, an opening 162 penetrating the conductive layer 161, the insulating layer 159, the conductive layer 175, and the insulating layer 157 is included. In the opening 162, an insulating layer 181 including a region overlapping with a side surface of the opening 162 is included. The insulating layer 181 includes a region overlapping with a side surface of the conductive layer 161, a region overlapping with a side surface of the insulating layer 159, a region overlapping with a side surface of the conductive layer 175, and a region overlapping with a side surface of the insulating layer 157.

[0338] The semiconductor layer 163 is provided over the opening 162 and covers the opening 162. In the opening 162, the semiconductor layer 163 has a region overlapping with a side surface of the insulating layer 159, a region overlapping with a side surface of the conductive layer 175, and a region overlapping with a side surface of the insulating layer 157, with the insulating layer 181 interposed therebetween. The semiconductor layer 163 also has a region in contact with the conductive layer 155 and a region in contact with the conductive layer 161. The insulating layer 181 functions as a gate insulating layer of the transistor 651, and the conductive layer 175 functions as a gate electrode of the transistor 651.

[0339] In the transistor 651, the length of the side surface of the conductive layer 175 in the opening 162 is the channel length L (channel length L4) when viewed from the X or Y direction. Therefore, the channel length L of the transistor 651 is determined depending on the thickness t4 of the conductive layer 175. When viewed from the X or Y direction, a region of the semiconductor layer 163 that overlaps with the conductive layer 175 functions as a channel formation region.

[0340] The transistor 651 has a structure in which the channel formation region is electrically surrounded by the electric field of the conductive layer 175 functioning as a gate electrode, and therefore can also be said to have a GAA (Gate All Around) structure.

[0341] FIG. 32B shows a transistor 652, which is a variation of the transistor 651. FIG. 32B is a cross-sectional view of the transistor 652. The transistor 652 has a configuration in which a conductive layer 165 is added to the transistor 651. In the transistor 652, both the conductive layer 165 and the conductive layer 175 can function as gate electrodes. In the transistor 652, one of the conductive layer 165 and the conductive layer 175 may be referred to as a "gate electrode," and the other may be referred to as a "back gate electrode." Furthermore, one of the conductive layer 165 and the conductive layer 175 may be referred to as a "first gate electrode," and the other may be referred to as a "second gate electrode." FIG. 32C shows a circuit symbol for a transistor with a back gate.

[0342] The gate electrode and the back gate electrode are arranged to sandwich the semiconductor layer between them. Both the gate electrode and the back gate electrode are formed of conductive layers. When the gate electrode is used to control the on / off state of the transistor, the potential of the back gate electrode may be the same as that of the gate electrode, or may be ground potential (GND) or any other potential. The threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently of the gate electrode. Furthermore, since the gate electrode and the back gate electrode are formed of conductors, they have the function of preventing an electric field generated outside the transistor from acting on the semiconductor in which the channel is formed (particularly, an electric field shielding function against static electricity, etc.). By providing a back gate electrode in addition to the gate electrode, the characteristic variation between transistors can be reduced.

[0343] 32B , when the conductive layer 165 is used as a gate electrode, the distance from the upper surface of the conductive layer 155 to the lower surface of the conductive layer 161, as viewed in the X or Y direction, is the channel length L (channel length L5). In this case, the sum of the lengths of the side surfaces of the insulating layer 157, the conductive layer 175, and the insulating layer 159 at the opening 162, as viewed in the X or Y direction, is the channel length L5. Therefore, the channel formation region of the transistor 651 includes a region along the side surface of the insulating layer 157, a region along the conductive layer 175, and a region along the side surface of the insulating layer 159. The channel length L of the transistor 651 shown in FIG. 32B is determined according to a thickness t5 obtained by adding up the thicknesses of the insulating layer 157, the conductive layer 175, and the insulating layer 159.

[0344] <Configuration Example of Memory Cell> Figure 33 shows an example of the stacked configuration of a memory cell 100, which is a type of semiconductor device. The memory cell 100 shown in Figure 33 has a layer 20 including a second memory circuit 120a above a layer 10 including a first memory circuit 110. Figure 33 illustrates the configuration shown in Figure 28A as the second memory circuit 120a included in the layer 20. To reduce repetition of explanation, a description of the second memory circuit 120a will be omitted here.

[0345] 33 illustrates a transistor Tr80 as an example of a transistor included in the first memory circuit 110. The transistor Tr80 is provided over a substrate 371 and includes a conductive layer 376 functioning as a gate, an insulating layer 375 functioning as a gate insulating layer, a semiconductor region 373 formed of part of the substrate 371, and low-resistance regions 374a and 374b functioning as source and drain regions. The transistor Tr80 can be either a p-channel transistor or an n-channel transistor. The substrate 371 can be, for example, a single-crystal silicon substrate.

[0346] Here, the transistor Tr80 shown in FIG. 33 has a semiconductor region 373 (a part of the substrate 371) where a channel is formed, which has a convex shape. A conductive layer 376 is provided to cover the side and top surfaces of the semiconductor region 373 via an insulating layer 375. The conductive layer 376 may be made of a material that adjusts the work function. Such a transistor Tr80 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. An insulating layer may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0347] The transistor Tr80 shown in FIG. 33 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0348] Layer 10 and layer 20 may be provided with a wiring layer provided with an interlayer film, wiring, plugs, etc. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, wiring and a plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as wiring, and cases where a part of the conductive layer functions as a plug.

[0349] For example, an insulating layer 390, an insulating layer 391, an insulating layer 393, and an insulating layer 394 are stacked in this order as an interlayer film over the transistor Tr80. A conductive layer 395 and the like are embedded in the insulating layers 390, 391, 393, and 394. The conductive layer 395 is connected to the second memory circuit 120a provided in the layer 20. The conductive layers 392 and 395 function as contact plugs or wirings.

[0350] The insulating layer functioning as an interlayer film may also function as a planarizing film that covers the uneven shape below it. For example, the top surface of the insulating layer 391 may be subjected to CMP treatment or the like to improve the planarity.

[0351] A wiring layer may be provided over the insulating layer 394 and the conductive layer 395. For example, in FIG. 33 , an insulating layer 396, an insulating layer 382, ​​and an insulating layer 384 are stacked in this order over the insulating layer 394 and the conductive layer 395. A conductive layer 386 is formed in the insulating layer 396, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 386 functions as a contact plug or a wiring.

[0352] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0353] Embodiment 5 In this embodiment, a structural example of an OS transistor that can be used in a semiconductor device of one embodiment of the present invention will be described.

[0354] 34A, 34B, and 34C are a plan view and a cross-sectional view of a transistor 751 that can be used in a semiconductor device of one embodiment of the present invention. The transistor 751 can be used in, for example, the first memory circuit 110, the second memory circuit 120, and the correction circuit 130.

[0355] FIG. 34A is a plan view of the transistor 751. Also, FIGS. 34B and 34C are cross-sectional views of the transistor 751. Here, FIG. 34B is a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2 in FIG. 34A and is also a cross-sectional view of the transistor 751 in the channel length direction. Also, FIG. 34C is a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4 in FIG. 34A and is also a cross-sectional view of the transistor 751 in the channel width direction. Note that in the plan view of FIG. 34A, some elements are omitted for clarity.

[0356] As shown in Figures 34A to 34C, the transistor 751 includes a metal oxide 220a disposed on a substrate (not shown), a metal oxide 220b disposed on the metal oxide 220a, conductive layers 242a and 242b disposed spaced apart from each other on the metal oxide 220b, an insulating layer 280 disposed on the conductive layers 242a and 242b and having an opening formed between the conductive layers 242a and 242b, a conductive layer 260 disposed in the opening, an insulating layer 250 disposed among the metal oxide 220b, the conductive layers 242a and 242b, the insulating layer 280, and the conductive layer 260, and a metal oxide 220c disposed among the metal oxide 220b, the conductive layers 242a and 242b, the insulating layer 280, and the insulating layer 250. 34B and 34C , the upper surface of conductive layer 260 preferably substantially coincides with the upper surfaces of insulating layer 250, insulating layer 254, metal oxide 220c, and insulating layer 280. Note that, hereinafter, metal oxide 220a, metal oxide 220b, and metal oxide 220c may be collectively referred to as metal oxide 220. Furthermore, conductive layer 242a and conductive layer 242b may be collectively referred to as conductive layer 242.

[0357] 34A to 34C, an insulating layer 254 is preferably disposed between the insulating layer 224, the metal oxide 220a, the metal oxide 220b, the conductive layer 242a, the conductive layer 242b, and the metal oxide 220c and the insulating layer 280. Here, as shown in FIGS. 34B and 34C, the insulating layer 254 is preferably in contact with the side surfaces of the metal oxide 220c, the top and side surfaces of the conductive layer 242a, the top and side surfaces of the conductive layer 242b, the side surfaces of the metal oxide 220a and the metal oxide 220b, and the top surface of the insulating layer 224.

[0358] Although the transistor 751 has a three-layer structure of the metal oxide 220a, the metal oxide 220b, and the metal oxide 220c stacked in the channel formation region and its vicinity, the present invention is not limited to this. For example, a two-layer structure of the metal oxide 220b and the metal oxide 220c or a stacked structure of four or more layers may be used. Furthermore, each of the metal oxide 220a, the metal oxide 220b, and the metal oxide 220c may have a stacked structure of two or more layers.

[0359] For example, when metal oxide 220c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of metal oxide 220b, and the second metal oxide has a composition similar to that of metal oxide 220a.

[0360] Here, the conductive layer 260 functions as a gate electrode of the transistor, and the conductive layer 242a and the conductive layer 242b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 260 is formed so as to be embedded in the opening of the insulating layer 280 and in the region sandwiched between the conductive layer 242a and the conductive layer 242b. Here, the conductive layer 260, the conductive layer 242a, and the conductive layer 242b are arranged in a self-aligned manner with respect to the opening of the insulating layer 280. That is, in the transistor 751, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 260 can be formed without providing a margin for alignment, and therefore the area occupied by the transistor 751 can be reduced. This allows the area occupied by the semiconductor device to be reduced. Furthermore, the integration degree of the semiconductor device can be increased.

[0361] 34A to 34C , the conductive layer 260 preferably includes a conductive layer 260a provided inside the insulating layer 250 and a conductive layer 260b provided so as to be embedded inside the conductive layer 260a. Although the conductive layer 260 in the transistor 751 has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 260 may have a single-layer structure or a stacked structure of three or more layers.

[0362] The transistor 751 preferably includes an insulating layer 214 disposed over a substrate (not shown), an insulating layer 216 disposed over the insulating layer 214, a conductive layer 205 disposed so as to be embedded in the insulating layer 216, an insulating layer 222 disposed over the insulating layer 216 and the conductive layer 205, and an insulating layer 224 disposed over the insulating layer 222. A metal oxide 220a is preferably disposed over the insulating layer 224.

[0363] An insulating layer 274 functioning as an interlayer film and an insulating layer 281 are preferably provided over the transistor 751. Here, the insulating layer 274 is preferably provided in contact with top surfaces of the conductive layer 260, the insulating layer 250, the insulating layer 254, the metal oxide 220c, and the insulating layer 280.

[0364] The insulating layer 222, the insulating layer 254, and the insulating layer 274 preferably have a function of suppressing diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). For example, the insulating layer 222, the insulating layer 254, and the insulating layer 274 preferably have lower hydrogen permeability than the insulating layer 224, the insulating layer 250, and the insulating layer 280. The insulating layer 222 and the insulating layer 254 preferably have a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulating layer 222 and the insulating layer 254 preferably have lower oxygen permeability than the insulating layer 224, the insulating layer 250, and the insulating layer 280.

[0365] Here, insulating layer 224, metal oxide 220, and insulating layer 250 are separated by insulating layer 222 and insulating layer 274. Therefore, impurities such as hydrogen and excess oxygen contained in layers above insulating layer 274 and below insulating layer 222 can be prevented from being mixed into insulating layer 224, metal oxide 220, and insulating layer 250.

[0366] A conductive layer 245 (conductive layer 245a and conductive layer 245b) electrically connected to the transistor 751 and functioning as a plug is preferably provided. Note that the insulating layer 241 (insulating layer 241a and insulating layer 241b) is provided in contact with the side surface of the conductive layer 245 functioning as a plug. That is, the insulating layer 241 is provided in contact with the inner walls of the openings of the insulating layer 254, the insulating layer 280, the insulating layer 274, and the insulating layer 281. Alternatively, a first conductive layer of the conductive layer 245 may be provided in contact with the side surface of the insulating layer 241, and a second conductive layer of the conductive layer 245 may be provided further inside. Here, the height of the top surface of the conductive layer 245 and the height of the top surface of the insulating layer 281 can be made approximately the same. Note that, although the transistor 751 illustrates a structure in which the first conductive layer of the conductive layer 245 and the second conductive layer of the conductive layer 245 are stacked, the present invention is not limited to this. For example, the conductive layer 245 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the layers may be distinguished by adding an ordinal number to the order of formation.

[0367] In the transistor 751, an oxide semiconductor is preferably used for the metal oxide 220 (the metal oxide 220a, the metal oxide 220b, and the metal oxide 220c) including a channel formation region.

[0368] Furthermore, the thickness of the metal oxide 220b in a region that does not overlap with the conductive layer 242 may be thinner than the thickness of the region that overlaps with the conductive layer 242. This is formed by removing a portion of the upper surface of the metal oxide 220b when forming the conductive layers 242a and 242b. When a conductive film that will become the conductive layer 242 is formed on the upper surface of the metal oxide 220b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region located between the conductive layers 242a and 242b on the upper surface of the metal oxide 220b, it is possible to prevent a channel from being formed in that region.

[0369] Next, a detailed structure of a transistor 751 that can be used in a semiconductor device of one embodiment of the present invention will be described.

[0370] The conductive layer 205 is disposed to have a region overlapping with the metal oxide 220 and the conductive layer 260. The conductive layer 205 is preferably embedded in the insulating layer 216.

[0371] The conductive layer 205 includes a conductive layer 205a, a conductive layer 205b, and a conductive layer 205c. The conductive layer 205a is provided in contact with the bottom surface and sidewall of an opening provided in the insulating layer 216. The conductive layer 205b is provided so as to be embedded in a recess formed in the conductive layer 205a. Here, the top surface of the conductive layer 205b is lower than the top surface of the conductive layer 205a and the top surface of the insulating layer 216. The conductive layer 205c is provided in contact with the top surface of the conductive layer 205b and the side surface of the conductive layer 205a. Here, the height of the top surface of the conductive layer 205c is approximately the same as the height of the top surface of the conductive layer 205a and the height of the top surface of the insulating layer 216. In other words, the conductive layer 205b is configured to be enclosed by the conductive layer 205a and the conductive layer 205c.

[0372] The conductive layer 205a and the conductive layer 205c are made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0373] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205a and the conductive layer 205c, it is possible to prevent impurities such as hydrogen contained in the conductive layer 205b from diffusing into the metal oxide 220 via the insulating layer 224 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductive layer 205a and the conductive layer 205c, it is possible to prevent the conductive layer 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 205a can be formed as a single layer or a stack of the above conductive materials. For example, the conductive layer 205a can be formed using titanium nitride.

[0374] The conductive layer 205b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0375] Here, the conductive layer 260 may function as a first gate electrode. The conductive layer 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 751 can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 751 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V compared to not applying a negative potential to the conductive layer 205.

[0376] The conductive layer 205 is preferably provided to be larger than the channel formation region of the metal oxide 220. In particular, as shown in Fig. 34C, the conductive layer 205 preferably extends also in a region outside the end portion intersecting with the channel width direction of the metal oxide 220. In other words, outside the side surface of the metal oxide 220 in the channel width direction, the conductive layer 205 and the conductive layer 260 preferably overlap with each other via an insulating layer.

[0377] With the above structure, the channel formation region of the metal oxide 220 can be electrically surrounded by the electric field of the conductive layer 260 that functions as a first gate electrode and the electric field of the conductive layer 205 that functions as a second gate electrode.

[0378] The conductive layer 205 may be extended beyond the metal oxide 220 and used as wiring. However, without being limited to this, a conductive layer that functions as wiring may be provided below the conductive layer 205.

[0379] The insulating layer 214 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 751 from the substrate side. Therefore, the insulating layer 214 is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, the insulating layer 214 is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (i.e., through which the oxygen is less likely to permeate).

[0380] For example, aluminum oxide, silicon nitride, or the like is preferably used for the insulating layer 214. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 214 to the transistor 751 side. Alternatively, oxygen contained in the insulating layer 224 or the like can be prevented from diffusing to the substrate side of the insulating layer 214.

[0381] The insulating layer 216, the insulating layer 280, and the insulating layer 281, which function as interlayer films, preferably have a lower dielectric constant than the insulating layer 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 216, the insulating layer 280, and the insulating layer 281 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0382] The insulating layers 222 and 224 function as gate insulating layers.

[0383] Here, the insulating layer 224 in contact with the metal oxide 220 is preferably heated to release oxygen. For example, the insulating layer 224 may be formed using silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulating layer containing oxygen in contact with the metal oxide 220, oxygen vacancies in the metal oxide 220 can be reduced, and the reliability of the transistor 751 can be improved.

[0384] Specifically, an oxide material from which part of oxygen is released by heating is preferably used for the insulating layer 224. The oxide from which oxygen is released by heating is an oxide whose amount of released oxygen, converted into oxygen atoms, is 1.0×10 in thermal desorption spectroscopy (TDS) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0385] 34C , the thickness of insulating layer 224 in a region that does not overlap with insulating layer 254 and metal oxide 220b may be thinner than the thickness of the other regions. In insulating layer 224, the thickness of the region that does not overlap with insulating layer 254 and metal oxide 220b is preferably a thickness that allows sufficient diffusion of the oxygen.

[0386] Like the insulating layer 214 and the like, the insulating layer 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 751 from the substrate side. For example, the insulating layer 222 preferably has lower hydrogen permeability than the insulating layer 224. By surrounding the insulating layer 224, the metal oxide 220, the insulating layer 250, and the like with the insulating layer 222, the insulating layer 254, and the insulating layer 274, impurities such as water or hydrogen can be prevented from entering the transistor 751 from the outside.

[0387] Furthermore, the insulating layer 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, the insulating layer 222 preferably has lower oxygen permeability than the insulating layer 224. The insulating layer 222 preferably has a function of suppressing the diffusion of oxygen and impurities, which can suppress the diffusion of oxygen contained in the metal oxide 220 toward the substrate side. Furthermore, the conductive layer 205 can be prevented from reacting with oxygen contained in the insulating layer 224 or the metal oxide 220.

[0388] The insulating layer 222 may be an insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulating layer containing an oxide of one or both of aluminum and hafnium. When the insulating layer 222 is formed using such a material, the insulating layer 222 functions as a layer that suppresses release of oxygen from the metal oxide 220 and the intrusion of impurities such as hydrogen into the metal oxide 220 from the periphery of the transistor 751.

[0389] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulating layers. Alternatively, these insulating layers may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulating layers. For example, the insulating layer 222 may have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0390] The insulating layer 222 may be a single layer or a multilayer insulating layer containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, PZT, STO, or BST. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. By using a high-k material for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0391] Each of the insulating layer 222 and the insulating layer 224 can have a stacked structure of two or more layers. In this case, the insulating layer 222 and the insulating layer 224 are not limited to a stacked structure made of the same material, and can have a stacked structure made of different materials. For example, an insulating layer similar to the insulating layer 224 can be provided under the insulating layer 222.

[0392] The metal oxide 220 includes a metal oxide 220a, a metal oxide 220b on the metal oxide 220a, and a metal oxide 220c on the metal oxide 220b. By providing the metal oxide 220a below the metal oxide 220b, it is possible to suppress the diffusion of impurities from structures formed below the metal oxide 220a to the metal oxide 220b. Furthermore, by providing the metal oxide 220c on the metal oxide 220b, it is possible to suppress the diffusion of impurities from structures formed above the metal oxide 220c to the metal oxide 220b.

[0393] The metal oxide 220 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when the metal oxide 220 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the metal oxide 220a to the number of atoms of all elements constituting the metal oxide 220a is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 220b to the number of atoms of all elements constituting the metal oxide 220b. Furthermore, the atomic ratio of the element M contained in the metal oxide 220a to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 220b to In. Here, the metal oxide 220c can be the same as the metal oxide that can be used for the metal oxide 220a or the metal oxide 220b.

[0394] The energy of the conduction band minimum of the metal oxide 220a and the metal oxide 220c is preferably higher than the energy of the conduction band minimum of the metal oxide 220b. In other words, the electron affinity of the metal oxide 220a and the metal oxide 220c is preferably lower than the electron affinity of the metal oxide 220b. In this case, the metal oxide 220c is preferably a metal oxide that can be used for the metal oxide 220a. Specifically, the ratio of the number of atoms of the element M contained in the metal oxide 220c to the number of atoms of all elements constituting the metal oxide 220c is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 220b to the number of atoms of all elements constituting the metal oxide 220b. Furthermore, the atomic ratio of the element M contained in the metal oxide 220c to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 220c to In.

[0395] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxides 220a, 220b, and 220c. In other words, the energy level of the conduction band minimum at the junction between the metal oxides 220a, 220b, and 220c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the metal oxides 220a and 220b and at the interface between the metal oxides 220b and 220c.

[0396] Specifically, when the metal oxide 220a and the metal oxide 220b, or the metal oxide 220b and the metal oxide 220c, share a common element other than oxygen (as a main component), a mixed layer with a low defect level density can be formed. For example, when the metal oxide 220b is an In—Ga—Zn oxide, the metal oxide 220a and the metal oxide 220c may be made of an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like. The metal oxide 220c may also have a stacked structure. For example, a stacked structure of an In—Ga—Zn oxide and a Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of an In—Ga—Zn oxide and a gallium oxide on the In—Ga—Zn oxide, may be used. In other words, a stacked structure of an In—Ga—Zn oxide and an oxide not containing In may be used as the metal oxide 220c.

[0397] Specifically, metal oxide 220a may have an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. Metal oxide 220b may have an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts. Metal oxide 220c may have an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of Ga:Zn=2:1 or thereabouts, or an atomic ratio of Ga:Zn=2:5 or thereabouts. Specific examples of the metal oxide 220c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a ratio thereof near thereto and Ga:Zn=2:1 [atomic ratio] or a ratio thereof near thereto, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a ratio thereof near thereto and Ga:Zn=2:5 [atomic ratio] or a ratio thereof near thereto, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a ratio thereof near thereto and gallium oxide.

[0398] In this case, the main carrier path is the metal oxide 220b. By configuring the metal oxide 220a and the metal oxide 220c as described above, the defect state density at the interface between the metal oxide 220a and the metal oxide 220b and at the interface between the metal oxide 220b and the metal oxide 220c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 751 to achieve a high on-state current and high frequency characteristics. Note that when the metal oxide 220c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the metal oxide 220b and the metal oxide 220c, it is expected that the diffusion of constituent elements of the metal oxide 220c toward the insulating layer 250 can be suppressed. More specifically, by configuring the metal oxide 220c as a stacked structure and positioning an oxide not containing In above the stacked structure, it is possible to suppress In that may diffuse toward the insulating layer 250. The insulating layer 250 functions as a gate insulating layer, and diffusion of In leads to poor transistor characteristics. Therefore, by forming the metal oxide 220c into a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0399] Conductive layers 242 (conductive layers 242a and 242b) functioning as a source electrode and a drain electrode are provided on the metal oxide 220b. The conductive layer 242 is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when they absorb oxygen.

[0400] By providing the conductive layer 242 so as to be in contact with the metal oxide 220, the oxygen concentration may be reduced in the vicinity of the conductive layer 242 of the metal oxide 220. Furthermore, a metal compound layer containing the metal contained in the conductive layer 242 and components of the metal oxide 220 may be formed in the vicinity of the conductive layer 242 of the metal oxide 220. In such a case, the carrier concentration increases in the region of the metal oxide 220 in the vicinity of the conductive layer 242, and this region becomes a low-resistance region.

[0401] Here, the region between the conductive layer 242a and the conductive layer 242b is formed so as to overlap the opening of the insulating layer 280. This allows the conductive layer 260 to be disposed in a self-aligned manner between the conductive layer 242a and the conductive layer 242b.

[0402] The insulating layer 250 functions as a gate insulating layer. The insulating layer 250 is preferably disposed in contact with the upper surface of the metal oxide 220c. The insulating layer 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0403] The insulating layer 250 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulating layer 224. The thickness of the insulating layer 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

[0404] A metal oxide may be provided between the insulating layer 250 and the conductive layer 260. The metal oxide preferably suppresses oxygen diffusion from the insulating layer 250 to the conductive layer 260. This makes it possible to suppress oxidation of the conductive layer 260 due to oxygen in the insulating layer 250.

[0405] The metal oxide may function as part of the gate insulating layer. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulating layer 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulating layer with a stacked structure of the insulating layer 250 and the metal oxide, it is possible to achieve a stacked structure that is stable against heat and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as the gate insulating layer.

[0406] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium.

[0407] Although the conductive layer 260 is shown as a two-layer structure in FIGS. 34A to 34C, it can also be a single-layer structure or a stacked structure of three or more layers.

[0408] The conductive layer 260a is preferably a conductive layer having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0409] The conductive layer 260a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 260b caused by oxygen contained in the insulating layer 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0410] The conductive layer 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 260 also functions as wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductive layer 260b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0411] 34A and 34C , in a region of the metal oxide 220b that does not overlap with the conductive layer 242, in other words, in a channel formation region of the metal oxide 220, the side surfaces of the metal oxide 220 are arranged to be covered with the conductive layer 260. This makes it easier for the electric field of the conductive layer 260, which functions as the first gate electrode, to act on the side surfaces of the metal oxide 220. This increases the on-state current of the transistor 751, thereby improving the frequency characteristics.

[0412] Like the insulating layer 214, the insulating layer 254 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 751 from the insulating layer 280 side. For example, the insulating layer 254 preferably has lower hydrogen permeability than the insulating layer 224. Furthermore, as shown in FIGS. 34B and 34C , the insulating layer 254 preferably contacts the side surfaces of the metal oxide 220c, the top and side surfaces of the conductive layer 242a, the top and side surfaces of the conductive layer 242b, the side surfaces of the metal oxide 220a and the metal oxide 220b, and the top surface of the insulating layer 224. With this structure, hydrogen contained in the insulating layer 280 can be suppressed from entering the metal oxide 220 from the top surfaces or side surfaces of the conductive layer 242a, the conductive layer 242b, the metal oxide 220a, the metal oxide 220b, and the insulating layer 224.

[0413] Furthermore, the insulating layer 254 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., the insulating layer 254 is less likely to transmit oxygen). For example, the insulating layer 254 preferably has lower oxygen permeability than the insulating layer 280 or the insulating layer 224.

[0414] The insulating layer 254 is preferably formed by a sputtering method. By forming the insulating layer 254 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 224 near a region in contact with the insulating layer 254. This allows oxygen to be supplied from this region into the metal oxide 220 through the insulating layer 224. Here, the insulating layer 254 has a function of suppressing upward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 220 to the insulating layer 280. Furthermore, the insulating layer 222 has a function of suppressing downward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 220 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the metal oxide 220. This reduces oxygen vacancies in the metal oxide 220, and suppresses the transistor from becoming normally on.

[0415] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium is preferably formed as the insulating layer 254. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium, or the like is preferably used.

[0416] The insulating layer 280 is provided over the insulating layer 224, the metal oxide 220, and the conductive layer 242 with the insulating layer 254 interposed therebetween. For example, the insulating layer 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is released by heating.

[0417] The concentration of impurities such as water or hydrogen is preferably reduced in the insulating layer 280. The top surface of the insulating layer 280 may be planarized.

[0418] Similar to the insulating layer 214, the insulating layer 274 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the insulating layer 280 from above. As the insulating layer 274, for example, an insulating layer that can be used for the insulating layer 214, the insulating layer 254, or the like may be used.

[0419] An insulating layer 281 functioning as an interlayer film is preferably provided over the insulating layer 274. Like the insulating layer 224 and the like, the insulating layer 281 preferably has a reduced concentration of impurities such as water or hydrogen.

[0420] The conductive layer 245a and the conductive layer 245b are disposed in openings formed in the insulating layer 281, the insulating layer 274, the insulating layer 280, and the insulating layer 254. The conductive layer 245a and the conductive layer 245b are provided opposite to each other with the conductive layer 260 interposed therebetween. Note that the height of the top surfaces of the conductive layer 245a and the conductive layer 245b may be flush with the top surface of the insulating layer 281.

[0421] Note that insulating layer 241a is provided in contact with the inner walls of the openings of insulating layer 281, insulating layer 274, insulating layer 280, and insulating layer 254, and a first conductive layer of conductive layer 245a is formed in contact with the side surface of insulating layer 241a. Conductive layer 242a is located on at least a portion of the bottom of the opening, and conductive layer 245a is in contact with conductive layer 242a. Similarly, insulating layer 241b is provided in contact with the inner walls of the openings of insulating layer 281, insulating layer 274, insulating layer 280, and insulating layer 254, and a first conductive layer of conductive layer 245b is formed in contact with the side surface of insulating layer 241b. Conductive layer 242b is located on at least a portion of the bottom of the opening, and conductive layer 245b is in contact with conductive layer 242b.

[0422] The conductive layers 245a and 245b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layers 245a and 245b may have a stacked structure.

[0423] When the conductive layer 245 has a stacked structure, the conductive layers in contact with the metal oxide 220a, the metal oxide 220b, the conductive layer 242, the insulating layer 254, the insulating layer 280, the insulating layer 274, and the insulating layer 281 preferably contain the above-mentioned conductive layers having the function of suppressing the diffusion of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Furthermore, a conductive material having the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a stacked layer. The use of such a conductive material can suppress the absorption of oxygen added to the insulating layer 280 by the conductive layers 245a and 245b. Furthermore, impurities such as water or hydrogen from layers above the insulating layer 281 can be suppressed from entering the metal oxide 220 through the conductive layers 245a and 245b.

[0424] As the insulating layer 241a and the insulating layer 241b, for example, an insulating layer that can be used for the insulating layer 254 or the like may be used. The insulating layer 241a and the insulating layer 241b are provided in contact with the insulating layer 254, and therefore can prevent impurities such as water or hydrogen from the insulating layer 280 or the like from being mixed into the metal oxide 220 through the conductive layer 245a and the conductive layer 245b. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layer 245a and the conductive layer 245b.

[0425] Although not shown, a conductive layer functioning as wiring may be disposed in contact with the top surface of the conductive layer 245a and the top surface of the conductive layer 245b. The conductive layer functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer may have a stacked structure, for example, a stack of titanium or titanium nitride and the above-mentioned conductive material. The conductive layer may be formed so as to be embedded in an opening provided in the insulating layer.

[0426] <Transistor Configuration Example 2> Figure 35 shows a modification of the transistor 751 shown in Figure 34. Figures 35A, 35B, and 35C are plan views and cross-sectional views of a transistor 752 which is a modification of the transistor 751. Because the transistor 752 is a modification of the transistor 751, differences between the transistor 752 and the transistor 751 will be mainly described.

[0427] The transistor 752 has a structure in which the metal oxide 220c and the conductive layer 205c are removed from the structure of the transistor 751. Reducing the number of components of the transistor can reduce production costs. Furthermore, reducing the number of components of the transistor shortens the manufacturing process, improving the manufacturing yield.

[0428] The transistor 752 has a region where the insulating layer 254 and the insulating layer 222 are in contact with each other outside the metal oxide 220, and the side surfaces of the insulating layer 224 are covered with the insulating layer 254. Covering the side surfaces of the insulating layer 224 with the insulating layer 254 not only prevents oxygen from diffusing to the outside through the insulating layer 224 but also prevents excessive oxygen from being supplied to the metal oxide 220 from the insulating layer 224 side.

[0429] Note that an insulating layer may be provided between the insulating layer 280, the insulating layer 254, the conductive layer 242, and the metal oxide 220b and the insulating layer 250. Aluminum oxide, hafnium oxide, or the like is preferably used as the insulating layer. By providing the insulating layer, it is possible to suppress desorption of oxygen from the metal oxide 220 to the insulating layer 250, excessive supply of oxygen from the insulating layer 250 to the metal oxide 220, oxidation of the conductive layer 242, and the like.

[0430] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0431] Embodiment 6 In this embodiment, application examples of the memory cell 100, the memory device 300, or the memory system 400, which are semiconductor devices according to one embodiment of the present invention, will be described.

[0432] By using a semiconductor device according to one embodiment of the present invention in an electronic device, the electronic device can be less susceptible to soft errors and the reliability of the electronic device can be improved. Furthermore, by using a semiconductor device according to one embodiment of the present invention, the power consumption of the electronic device can be reduced. The reduced power consumption reduces heat generation from the circuit, thereby reducing adverse effects on the circuit itself, peripheral circuits, and modules. Furthermore, by using a semiconductor device according to one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the electronic device can be improved.

[0433] A semiconductor device according to one embodiment of the present invention can be used in various electronic components. For example, the semiconductor device can be applied to caches and registers of microprocessors such as CPUs, digital signal processors (DSPs), and graphics processing units (GPUs). Note that the microprocessor may be implemented by a programmable logic device (PLD), such as a field programmable gate array (FPGA) or a field programmable analog array (FPAA).

[0434] Therefore, the semiconductor device according to one embodiment of the present invention can be applied to, for example, various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). The semiconductor device can also be used in image sensors, Internet of Things (IoT), healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0435] 36A to 36J illustrate examples of electronic devices including a semiconductor device according to one embodiment of the present invention. Each electronic device includes an electronic component 700 including a semiconductor device according to one embodiment of the present invention.

[0436] 36A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0437] 36B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0438] 36C shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0439] 36A to 36C are examples of electronic devices, the semiconductor device according to one embodiment of the present invention can be used in devices other than the smartphone, wearable device, and desktop device. Examples of devices other than the smartphone, wearable device, and desktop device include a personal digital assistant (PDA), a notebook computer, and a workstation.

[0440] 36D also illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer that is compatible with IoT.

[0441] The semiconductor device according to one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet or the like.

[0442] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0443] 36E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0444] FIG. 36F further illustrates a stationary game console 7500, an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in FIG. 36F , the controller 7522 can include a display unit for displaying game images and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 36F , and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller with a trigger button and shaped like a gun can be used. In a music game, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures or voice.

[0445] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0446] As an example of a game machine, a portable game machine is shown in Fig. 36E. Also, a home-use stationary game machine is shown in Fig. 36F. Note that game machines according to an aspect of the present invention are not limited to portable game machines and home-use stationary game machines. Examples of game machines according to an aspect of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0447] [Mobile Object] The semiconductor device described in the above embodiment can be applied to a mobile object, such as an automobile, and the vicinity of the driver's seat of the automobile.

[0448] FIG. 36G illustrates an automobile 5700 as an example of a moving object.

[0449] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0450] In particular, the display device can enhance safety by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby compensating for a field of view obstructed by a pillar or the like, a blind spot on the driver's seat, etc. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be enhanced.

[0451] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects may include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0452] [Camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0453] 36H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0454] [Video Camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0455] 36I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0456] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0457] 36J is a cross-sectional schematic diagram showing an example of an ICD. An ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0458] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0459] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0460] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration of the treatment, and the like.

[0461] Furthermore, power can be received by the antenna 5404, and the power is charged in the battery 5401. Furthermore, the ICD main body 5400 has multiple batteries, thereby improving safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.

[0462] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0463] By applying the semiconductor device described in the above embodiment to the ICD main body 5400, it is possible to realize an ICD main body 5400 with low power consumption. Furthermore, the low power consumption allows the storage battery to be made smaller and lighter. Furthermore, the low power consumption allows the heat generation of the ICD main body 5400 to be reduced, thereby reducing the burden on the human body.

[0464] [Computer] The computer 5600 shown in Fig. 37A is an example of a large computer (supercomputer) mainly used for scientific and technological calculations. Scientific and technological calculations require high speed processing of huge amounts of calculations, which results in high power consumption and heat generation from chips. For example, in a data center with multiple supercomputers, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is estimated to be 10 ２４ (yotta) byte, or 10 ３０ It is expected to exceed quetta bytes.

[0465] By using a semiconductor device according to one embodiment of the present invention in the computer 5600, the computer 5600 can be less susceptible to soft errors and the reliability of the computer 5600 can be improved. Furthermore, by applying a semiconductor device according to one embodiment of the present invention to the computer 5600, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules. Furthermore, by using a semiconductor device according to one embodiment of the present invention, a supercomputer with low power consumption can be realized. This is expected to reduce the amount of digital data in the world and significantly contribute to combating global warming.

[0466] The computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The computer 5620 can have the configuration shown in the perspective view of FIG. 37B, for example. In FIG. 37B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0467] PC card 5621 shown in Figure 37C is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 37C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be used as reference.

[0468] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0469] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0470] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0471] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 700 can be used as the semiconductor device 5627.

[0472] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. The semiconductor device 5628 is, for example, a memory device.

[0473] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference in artificial intelligence, for example.

[0474] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0475] Embodiment 7 A semiconductor device of one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. In this embodiment, a specific example of application of the semiconductor device of one embodiment of the present invention to space equipment will be described with reference to FIG. 38 .

[0476] Fig. 38 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 38, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but outer space described in this specification also includes the thermosphere, mesosphere, and stratosphere.

[0477] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0478] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0479] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0480] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0481] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0482] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0483] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0484] 100: memory cell, 101: wiring, 102: wiring, 103: wiring, 104: wiring, 105: wiring, 106: wiring, 107: wiring, 110: first memory circuit, 120: second memory circuit, 200: memory cell array, 300: storage device

Claims

a first memory circuit including a transistor including silicon in a channel formation region and having a function of storing first data; a second memory circuit including a transistor including an oxide semiconductor in a channel formation region and having a function of storing second data; a function of making a logical value of the first data equal to a logical value of the second data by writing data to the first storage circuit and the second storage circuit; a function of outputting a first signal and making the first signal active when the logic value of the first data is "1" and the logic value of the second data is "0"; a function of outputting a second signal and making the second signal active when the logic value of the first data is "0" and the logic value of the second data is "1"; and when one of the first signal or the second signal is active, supplying third data, the logical value of which is equal to the logical value of the second data, to the first memory circuit. 　 In claim 1, The first memory circuit and the second memory circuit have an overlapping region. 　 In claim 1 or 2, the first memory circuit includes a first inverter circuit and a second inverter circuit; an output of the first inverter circuit and an input of the second inverter circuit are electrically connected; The semiconductor device has an output of the second inverter circuit and an input of the first inverter circuit electrically connected to each other. 　 A first memory circuit and a second memory circuit are included, the first memory circuit includes a first inverter circuit, a second inverter circuit, a first transistor, and a second transistor; an output of the first inverter circuit electrically connected to an input of the second inverter circuit; an output of the second inverter circuit electrically connected to an input of the first inverter circuit; an output of the first inverter circuit is electrically connected to a first wiring via a source and a drain of the first transistor; an output of the second inverter circuit is electrically connected to a second wiring via a source and a drain of the second transistor; the second memory circuit includes third to eighth transistors and a capacitor element, one of a source or a drain of the third transistor is electrically connected to an output of the first inverter circuit, an input of the second inverter circuit, and one of a source or a drain of the fourth transistor; the other of the source and the drain of the third transistor is electrically connected to one terminal of the capacitive element and to the gate of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to a third wiring; one of a source or a drain of the sixth transistor is electrically connected to an output of the second inverter circuit, an input of the first inverter circuit, and one of a source or a drain of the seventh transistor; the other of the source and the drain of the sixth transistor is electrically connected to the other terminal of the capacitive element and the gate of the seventh transistor; the other of the source and the drain of the seventh transistor is electrically connected to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to a fourth wiring; a gate of the third transistor electrically connected to a gate of the sixth transistor; a gate of the fifth transistor and a gate of the eighth transistor are electrically connected to a fifth wiring. 　 In claim 4, each of the first inverter circuit and the second inverter circuit has a transistor including silicon in a channel formation region; The semiconductor device, wherein the third transistor and the sixth transistor each include an oxide semiconductor in a channel formation region. 　 In claim 4 or claim 5, The semiconductor device, wherein each of the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor is a transistor including an oxide semiconductor in a channel formation region. 　 In claim 4 or claim 5, the potential of the output of the first inverter circuit is potential L, When the potential of the gate of the fourth transistor is potential H, The semiconductor device has a function of supplying a potential L to the third wiring. In claim 4 or claim 5, the potential of the output of the second inverter circuit is potential L; The semiconductor device has a function of supplying a potential L to the fourth wiring when the potential of the gate of the seventh transistor is a potential H. 　 In claim 4 or claim 5, The semiconductor device has a region in which the first memory circuit and the second memory circuit overlap each other.

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