Semiconductor memory device

Abstract

In this semiconductor memory device, a plurality of SRAM cells include a first SRAM cell (C1) and a second SRAM cell (C2) disposed side by side with the first SRAM cell (C1) in a first direction. In the first SRAM cell (C1), wires (72, 73) respectively corresponding to bit lines BLB, BL are formed in an M1 wiring layer, which is a metal wiring layer. In the second SRAM cell (C2), wires (212, 213) respectively corresponding to the bit lines BLB, BL are formed in a BM0 wiring layer, which is a wiring layer on the back surface of a transistor.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device, and in particular to a layout structure of a static random access memory (SRAM) cell (hereinafter, also simply referred to as a cell, as appropriate).

[0002] SRAMs are widely used in semiconductor integrated circuits.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltage, and improved operating speed through gate length reduction (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. One example of a three-dimensional transistor is the nanosheet FET (Field Effect Transistor).

[0004] Patent Document 1 discloses a layout structure of an SRAM cell in which a wiring layer is provided on the back surface of a substrate directly below a transistor, one of a pair of bit lines is provided in the wiring layer on the back surface side, and the other of the pair of bit lines is provided in the wiring layer on the front surface side.

[0005] FIG. 9 of U.S. Patent Application Publication No. 2021 / 0343332

[0006] In the technology of Patent Document 1, the bit line pairs are provided in different wiring layers, which causes imbalances in characteristics between the bit line pairs. Furthermore, since the bit line pairs are provided in different wiring layers, process variations in the wiring of the bit line pairs occur independently of each other, further exacerbating the imbalance in characteristics. This may result in reduced yield and reliability of the SRAM cells. To avoid this, a large design margin is required, which may result in performance degradation, such as a reduction in the operating speed of the semiconductor memory device.

[0007] The present disclosure aims to prevent a decrease in performance of a semiconductor memory device in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor.

[0008] The present disclosure provides a semiconductor memory device including a plurality of SRAM cells, each of the SRAM cells comprising a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the source, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, wherein the plurality of SRAM cells include a first SRAM cell and a second SRAM cell arranged next to the first SRAM cell in a first direction, the first bit line of the SRAM cell is formed in a metal wiring layer above the first to sixth transistors and includes a first wiring extending in a second direction; the second bit line of the first SRAM cell is formed in the metal wiring layer and includes a second wiring extending in the second direction; the first SRAM cell comprises a first active region constituting a channel, a source, and a drain of the third transistor of the first SRAM cell, the channel including a nanosheet extending in the second direction; a second active region constituting a channel, a source, and a drain of the fourth transistor of the first SRAM cell, the channel including a nanosheet extending in the second direction; a first power supply wiring formed in a first back wiring layer on the back side of the first to sixth transistors, extending in the second direction, and connected to the second power supply; and a second power supply wiring formed in the first back wiring layer, extending in the second direction, and connected to the second power supply, and formed at a position where a first region constituting the source of the third transistor in the first active region and the first power supply wiring overlap;a first via connecting the first region and the first power supply wiring, a second region constituting the source of the fourth transistor in the second active region, and a second via formed at a position where the second region and the second power supply wiring overlap, the second SRAM cell including a first bit line formed in the first backside wiring layer and including a third wiring extending in the second direction, the second bit line formed in the first backside wiring layer and including a fourth wiring extending in the second direction, the second SRAM cell including a channel, a source, and a drain of the third transistor of the second SRAM cell, the channel including a nanosheet extending in the second direction an active region; a fourth active region that forms the channel, source, and drain of the fourth transistor of the second SRAM cell and includes a nanosheet extending in the second direction as the channel; a third via that is formed at a position where a third region that forms the source of the third transistor in the third active region and the third wiring overlap and connects the third region to the third wiring; a fourth via that is formed at a position where a fourth region that forms the source of the fourth transistor in the fourth active region and the fourth wiring overlap and connects the fourth region to the fourth wiring; and a third power supply wiring that is formed in the metal wiring layer, extends in the second direction, and is connected to the second power supply.

[0009] According to the present disclosure, in the first SRAM cell, first and second wirings corresponding to the first and second bit lines, respectively, are formed in a metal wiring layer above the transistor. In the second SRAM cell C2, third and fourth wirings corresponding to the first and second bit lines BLB and BL, respectively, are formed in a first backside wiring layer, which is a wiring layer on the backside of the transistor. As a result, in the first SRAM cell and the second SRAM cell, the first and second bit lines constituting the bit line pair are formed in the same wiring layer, which reduces the likelihood of imbalance in characteristics between the bit line pair. Furthermore, because the first and second bit lines are formed in the same wiring layer, process variations in the wiring of the bit line pair do not occur independently of each other. This reduces the likelihood of reduced yield and reliability of the SRAM cell, eliminates the need for a large design margin, and thereby prevents performance degradation, such as a decrease in operating speed, of the semiconductor memory device.

[0010] According to the present disclosure, in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor, it is possible to prevent a decrease in performance of a semiconductor memory device.

[0011] 9A and 9B are plan views showing an example of a layout structure of a first SRAM cell according to an embodiment; cross-sectional views showing an example of a layout structure of a first SRAM cell according to an embodiment; cross-sectional views showing an example of a layout structure of a first SRAM cell according to an embodiment; circuit diagrams showing configurations of SRAM cells according to an embodiment; plan views showing an example of a layout structure of a second SRAM cell according to an embodiment; cross-sectional views showing an example of a layout structure of a second SRAM cell according to an embodiment; cross-sectional views showing an example of a layout structure of a second SRAM cell according to an embodiment; plan views showing an example of a layout of a circuit block included in a semiconductor integrated circuit device according to an embodiment; plan views showing an example of a layout of a circuit block included in a semiconductor integrated circuit device according to an embodiment; plan views of a region S1 in FIG. 9A; cross-sectional views of a region S1 in FIG. 9A; another configuration example of a semiconductor integrated circuit device according to an embodiment; plan views showing another example of a layout structure of a first SRAM cell according to an embodiment; plan views showing another example of a layout structure of a second SRAM cell according to an embodiment;

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells, and at least some of the plurality of SRAM cells include nanosheet FETs. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows. The nanosheet is formed of, for example, silicon. In the present disclosure, the transistor included in the SRAM cell is not limited to a nanosheet FET.

[0013] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0014] (Embodiment) A semiconductor memory device according to this embodiment includes a first SRAM cell C1 and a second SRAM cell C2.

[0015] (Configuration of the First SRAM Cell) Figures 1 to 3 show an example of the layout structure of the first SRAM cell according to this embodiment, with Figures 1(a) and 1(b) being plan views, and Figures 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, Figure 1(a) shows the upper part of the cell, which is the M1 and M2 wiring layers, and Figure 1(b) shows the lower part of the cell, which is a layer below the M1 and M2 wiring layers and includes the nanosheet FET. Figure 2(a) is a cross section along line X1-X1', Figure 2(b) is a cross section along line X2-X2', Figure 2(c) is a cross section along line X3-X3', Figure 3(a) is a cross section along line X4-X4', and Figure 3(b) is a cross section along line X5-X5'.

[0016] In the following description, in plan views such as FIG. 1, the horizontal direction of the drawing is the X direction (first direction), the vertical direction of the drawing is the Y direction (second direction), and the direction perpendicular to the substrate surface is the Z direction.

[0017] 4 is a circuit diagram showing the configuration of an SRAM cell according to this embodiment. The first SRAM cell C1 and the second SRAM cell C2 each have the SRAM circuit shown in FIG.

[0018] 4, the SRAM cells (first SRAM cell C1 and second SRAM cell C2) each include an SRAM circuit made up of load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 and PG2. The load transistors PU1 and PU2 are P-type FETs, while the drive transistors PD1 and PD2 and the access transistors PG1 and PG2 are N-type FETs.

[0019] The load transistor PU1 is provided between the power supply VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the load transistor PU1 and the drive transistor PD1 are connected to a second node NB, and they form an inverter INV1. The load transistor PU2 is provided between the power supply VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the load transistor PU2 and the drive transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0020] The access transistor PG1 is provided between the bit line BL and a first node NA, and has its gate connected to the word line WL. The access transistor PG2 is provided between the bit line BLB and a second node NB, and has its gate connected to the word line WL. The bit lines BL and BLB form a complementary bit line pair.

[0021] In an SRAM circuit, when the bit lines BL and BLB constituting a complementary bit line pair are driven to a high level and a low level, respectively, and the word line WL is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the bit lines BL and BLB are driven to a low level and a high level, respectively, and the word line WL is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the word line WL is driven to a low level while data is written to the first and second nodes NA and NB, respectively, the latch state is established and the data written to the first and second nodes NA and NB is held.

[0022] Furthermore, when the bit lines BL and BLB are precharged to a high level and the word line WL is driven to a high level, the states of the bit lines BL and BLB are determined according to the data written to the first and second nodes NA and NB, respectively, and data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the bit line BL is held at a high level and the bit line BLB is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the bit line BL is discharged to a low level and the bit line BLB is held at a high level.

[0023] As described above, the SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the bit lines BL, BLB and word lines WL.

[0024] In the following description, the solid lines running vertically and horizontally in plan views such as FIG. 1 and the solid lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0025] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. The SRAM cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0026] As shown in Figure 1B, the backside of the semiconductor chip on which the transistors are formed has wiring layers, BM0 (Backside Metal 0) and BM1 (Backside Metal 1). The BM1 wiring layer is located below the BM0 wiring layer, i.e., farther from the transistors. The BM0 wiring layer corresponds to the first backside wiring layer, and the BM1 wiring layer corresponds to the second backside wiring layer.

[0027] The BM0 wiring layer is formed with power supply wirings 11 to 13 extending in the Y direction from both the top and bottom of the cell. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wirings 12 and 13 supply a power supply voltage VSS.

[0028] The BM1 wiring layer is formed with a power supply wiring 121 extending in the X direction from both the left and right ends of the cell. The power supply wiring 121 supplies a power supply voltage VSS. The power supply wiring 121 is connected to the power supply wiring 12 through a via 131 and to the power supply wiring 13 through a via 132.

[0029] A plurality of active regions constituting the channel, source, and drain of the N-type transistor are formed in an N-type transistor region on a P-type substrate (PSub) (not shown). Specifically, active regions N1 and N2 are formed in the N-type transistor region. The active regions N1 and N2 overlap with power supply wiring 12 and 13, respectively, in a plan view.

[0030] In the N-type transistor region, an access transistor PG2, a drive transistor PD1, a drive transistor PD2, and an access transistor PG1 are formed. The access transistor PG2, the drive transistor PD1, the drive transistor PD2, and the access transistor PG1 each have a channel made of three overlapping sheet structures in a plan view, and each have nanosheets 21 to 24 extending in the Y direction. In other words, the access transistor PG2, the drive transistor PD1, the drive transistor PD2, and the access transistor PG1 are nanosheet FETs.

[0031] In the active region N1, a portion (region 42) that serves as the source of the drive transistor PD2 is connected to the power supply wiring 12 through a via 111 that is provided at a position that overlaps the power supply wiring 12 in a plan view. In the active region N2, a portion (region 43) that serves as the source of the drive transistor PD1 is connected to the power supply wiring 13 through a via 112 that is provided at a position that overlaps the power supply wiring 13 in a plan view.

[0032] A plurality of active regions constituting the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (NWell) (not shown). Specifically, active regions P1 and P2 are formed in the P-type transistor region. The active regions P1 and P2 overlap with the power supply wiring 11 in a plan view.

[0033] Load transistors PU1 and PU2 are formed in the P-type transistor region. The load transistors PU1 and PU2 each have a channel made of three overlapping sheets in a plan view, with nanosheets 25 and 26 extending in the Y direction. In other words, the load transistors PU1 and PU2 are nanosheet FETs. The width in the X direction of the nanosheets 21 to 24 is twice the width in the X direction of the nanosheets 25 and 26.

[0034] In the active region P1, the portion (region 46) that becomes the source of the load transistor PU1 is connected to the power supply wiring 11 through a via 113 that is provided at a position that overlaps the power supply wiring 11 in a plan view. In the active region P2, the portion (region 49) that becomes the source of the load transistor PU2 is connected to the power supply wiring 12 through a via 114 that is provided at a position that overlaps the power supply wiring 12 in a plan view.

[0035] As shown in FIG. 1B, gate wirings (Gate) 31 to 34 are formed extending in the X direction. The gate wiring 31 surrounds the outer periphery of the nanosheet 21 in the X and Z directions. The gate wiring 32 surrounds the outer periphery of the nanosheets 25 and 22 in the X and Z directions. The gate wiring 33 surrounds the outer periphery of the nanosheets 23 and 26 in the X and Z directions. The gate wiring 34 surrounds the outer periphery of the nanosheet 24 in the X and Z directions. The gate wiring 31 corresponds to the gate of the access transistor PG2. The gate wiring 32 corresponds to the gates of the load transistor PU1 and the drive transistor PD1. The gate wiring 33 corresponds to the gates of the drive transistor PD2 and the load transistor PU2. The gate wiring 34 corresponds to the gate of the access transistor PG1.

[0036] In the local wiring layer, local wirings 51 to 58 extending in the X direction are formed. Local wiring 51 is connected to region 40 in active region N1. Local wiring 52 is connected to region 46 in active region P1. Local wiring 53 is connected to region 43 in active region N2. Local wiring 54 is connected to region 41 in active region N1 and region 48 in active region P2. Local wiring 55 is connected to region 47 in active region P1 and region 44 in active region N2. Local wiring 56 is connected to region 42 in active region N1. Local wiring 57 is connected to region 49 in active region P2. Local wiring 58 is connected to region 45 in active region N2.

[0037] Region 40 is a portion of active region N1 that will become the source of access transistor PG2. Region 41 is a portion of active region N1 that will become the drain of access transistor PG2 and the drain of drive transistor PD2. Region 42 is a portion of active region N1 that will become the source of drive transistor PD2. Region 43 is a portion of active region N2 that will become the source of drive transistor PD1. Region 44 is a portion of active region N2 that will become the drain of drive transistor PD1 and the drain of access transistor PG1. Region 45 is a portion of active region N2 that will become the source of access transistor PG1. Region 46 is a portion of active region P1 that will become the source of load transistor PU1. Region 47 is a portion of active region P1 that will become the drain of load transistor PU1. Region 48 is a portion of active region P2 that will become the drain of load transistor PU2. Region 49 is a portion of active region P2 that will become the source of load transistor PU2.

[0038] The local wiring 54 is connected to the gate wiring 32 via a shared contact 61. The local wiring 55 is connected to the gate wiring 33 via a shared contact 62. The gate wiring 33, the local wiring 55, and the shared contact 62 correspond to a first node NA. The gate wiring 32, the local wiring 54, and the shared contact 61 correspond to a second node NB.

[0039] As shown in FIG. 1A, a power supply wiring 71 and wirings 72 and 73 extending in the Y direction from top to bottom of the cell in the drawing are formed in the M1 wiring layer, which is a metal wiring layer above the local wiring layer. Wires 74 and 75 are also formed. The power supply wiring 71 supplies a power supply voltage VDD. The wirings 72 and 73 correspond to bit lines BLB and BL. The power supply wiring 71 overlaps with the power supply wiring 11. The wiring 72 overlaps with the active region N1 and the power supply wiring 12 in a plan view. The wiring 73 overlaps with the active region N2 and the power supply wiring 13 in a plan view.

[0040] The power supply wiring 71 is connected to the local wiring 52 through a via 81, and is connected to the local wiring 57 through a via 82. The wiring 72 is connected to the local wiring 51 through a via 83. The wiring 73 is connected to the local wiring 58 through a via 84. The wiring 74 is connected to the gate wiring 31 through a contact (gate-contact) 85. The wiring 75 is connected to the gate wiring 34 through a contact 86.

[0041] In the M2 wiring layer, which is the layer above the M1 wiring layer, a wiring 91 is formed, which extends in the X direction from the left to the right ends of the cell in the drawing. The wiring 91 corresponds to the word line WL. The wiring 91 is connected to the wiring 74 through a via 101 and to the wiring 75 through a via 102.

[0042] With the above configuration, power supply wirings 12 and 13 that supply the power supply voltage VSS are formed in the BM0 wiring layer, which is the wiring layer on the back surface of the transistor. This eliminates the need to form power supply wirings that supply the power supply voltage VSS in the M1 wiring layer, which is the metal wiring layer, and allows the wiring widths of the wirings 72 and 73 that correspond to the bit lines BLB and BL, respectively, to be increased. This reduces the wiring resistance of the bit lines, thereby preventing a decrease in the operating speed of the semiconductor memory device.

[0043] Furthermore, wirings 72 and 73 corresponding to the bit lines BLB and BL, respectively, are formed in the M1 wiring layer. Power supply wirings 12 and 13 for supplying the power supply voltage VSS are formed in the BM0 wiring layer. This eliminates the need to form wirings corresponding to the bit lines BLB and BL, respectively, in the BM0 wiring layer, and allows the wiring width of the power supply wirings 12 and 13 for supplying the power supply voltage VSS in the BM0 wiring layer to be increased. This reduces the wiring resistance of the power supply wiring, thereby suppressing fluctuations in the power supply voltage, preventing a decrease in the operating speed of the semiconductor memory device, and improving operational stability.

[0044] Furthermore, power supply wiring 11, 71 that supplies power supply voltage VDD are formed in the BM0 wiring layer and the M1 wiring layer, respectively. This allows the wiring width of power supply wiring 11 formed in the BM0 wiring layer to be reduced, and the wiring width of power supply wiring 12, 13 that supplies power supply voltage VSS to be increased, thereby reducing the wiring resistance of the power supply wiring. Therefore, fluctuations in the power supply voltage are suppressed, which prevents a decrease in the operating speed of the semiconductor memory device and improves the stability of operation.

[0045] Furthermore, a power supply wiring 71 that supplies a power supply voltage VDD is formed between the wiring 72 and the wiring 73. This suppresses crosstalk noise between the wirings 72 and 73 that correspond to the bit lines BLB and BL, respectively, and therefore prevents deterioration in the performance and reliability of the semiconductor memory device.

[0046] (Second SRAM Cell) Figures 5 to 7 are diagrams showing examples of the layout structure of the second SRAM cell according to this embodiment. Specifically, Figure 5(a) shows the upper part of the cell, and Figure 5(b) shows the lower part of the cell. Figure 6(a) is a cross section taken along line X6-X6', Figure 6(b) is a cross section taken along line X7-X7', Figure 6(c) is a cross section taken along line X8-X8', Figure 7(a) is a cross section taken along line X9-X9', and Figure 7(b) is a cross section taken along line X10-X10'.

[0047] As described above, the second SRAM cell C2 has the SRAM circuit of FIG.

[0048] 5B, a power supply wiring 211 and wirings 212 and 213 are formed in the BM0 wiring layer, extending in the Y direction from the top to the bottom of the cell. The power supply wiring 211 supplies a power supply voltage VDD. The wirings 212 and 213 correspond to the bit lines BLB and BL, respectively.

[0049] The BM1 wiring layer is formed with a power supply wiring 121 extending in the X direction from both the left and right ends of the cell. The power supply wiring 121 supplies a power supply voltage VSS. Note that the power supply wiring 121 is not connected to other wiring, transistors, etc. within the second SRAM cell C2.

[0050] A plurality of active regions constituting the channel, source, and drain of the N-type transistor are formed in an N-type transistor region on a P-type substrate (not shown). Specifically, active regions N3 and N4 are formed in the N-type transistor region. In plan view, active regions N3 and N4 overlap with wirings 212 and 213, respectively.

[0051] In the N-type transistor region, an access transistor PG2, a drive transistor PD1, a drive transistor PD2, and an access transistor PG1 are formed. The access transistor PG2, the drive transistor PD1, the drive transistor PD2, and the access transistor PG1 each have a channel made of three overlapping sheet structures in a plan view, and each have nanosheets 221 to 224 extending in the Y direction. In other words, the access transistor PG2, the drive transistor PD1, the drive transistor PD2, and the access transistor PG1 are nanosheet FETs.

[0052] In the active region N3, the portion (region 240) that will become the source of the access transistor PG2 is connected to the wiring 212 through a via 311 that is provided at a position that overlaps the wiring 212 in a plan view. In the active region N4, the portion (region 245) that will become the source of the access transistor PG1 is connected to the wiring 213 through a via 312 that is provided at a position that overlaps the wiring 213 in a plan view.

[0053] A plurality of active regions constituting the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (not shown). Specifically, active regions P3 and P4 are formed in the P-type transistor region. The active regions P3 and P4 overlap with the power supply wiring 211 in plan view.

[0054] Load transistors PU1 and PU2 are formed in the P-type transistor region. The load transistors PU1 and PU2 each have a channel made of three overlapping sheets in a plan view, with nanosheets 225 and 226 extending in the Y direction. In other words, the load transistors PU1 and PU2 are nanosheet FETs. The width in the X direction of the nanosheets 221 to 224 is twice the width in the X direction of the nanosheets 225 and 226.

[0055] As shown in FIG. 5B, gate wirings (Gate) 231 to 234 are formed extending in the X direction. The gate wiring 231 surrounds the outer periphery of the nanosheet 221 in the X and Z directions. The gate wiring 232 surrounds the outer periphery of the nanosheets 225 and 222 in the X and Z directions. The gate wiring 233 surrounds the outer periphery of the nanosheets 223 and 226 in the X and Z directions. The gate wiring 234 surrounds the outer periphery of the nanosheet 224 in the X and Z directions. The gate wiring 231 corresponds to the gate of the access transistor PG2. The gate wiring 232 corresponds to the gates of the load transistor PU1 and the drive transistor PD1. The gate wiring 233 corresponds to the gates of the drive transistor PD2 and the load transistor PU2. The gate wiring 234 corresponds to the gate of the access transistor PG1.

[0056] In the local wiring layer, local wirings 251 to 258 extending in the X direction are formed. Local wiring 251 is connected to region 240 in active region N3. Local wiring 252 is connected to region 246 in active region P3. Local wiring 253 is connected to region 243 in active region N4. Local wiring 254 is connected to region 241 in active region N3 and region 248 in active region P4. Local wiring 255 is connected to region 247 in active region P3 and region 244 in active region N4. Local wiring 256 is connected to region 242 in active region N3. Local wiring 257 is connected to region 249 in active region P4. Local wiring 258 is connected to region 245 in active region N4.

[0057] Region 240 is a portion of active region N3 that will become the source of access transistor PG2. Region 241 is a portion of active region N3 that will become the drain of access transistor PG2 and the drain of drive transistor PD2. Region 242 is a portion of active region N3 that will become the source of drive transistor PD2. Region 243 is a portion of active region N4 that will become the source of drive transistor PD1. Region 244 is a portion of active region N4 that will become the drain of drive transistor PD1 and the drain of access transistor PG1. Region 245 is a portion of active region N4 that will become the source of access transistor PG1. Region 246 is a portion of active region P3 that will become the source of load transistor PU1. Region 247 is a portion of active region P3 that will become the drain of load transistor PU1. Region 248 is a portion of active region P4 that will become the drain of load transistor PU2. Region 249 is a portion of active region P4 that will become the source of load transistor PU2.

[0058] The local wiring 254 is connected to the gate wiring 232 via a shared contact 261. The local wiring 255 is connected to the gate wiring 233 via a shared contact 262. The gate wiring 233, the local wiring 255, and the shared contact 262 correspond to a first node NA. The gate wiring 232, the local wiring 254, and the shared contact 261 correspond to a second node NB.

[0059] As shown in FIG. 5A, power supply wiring 271-273 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer. Wiring 274 and 275 are also formed. Power supply wiring 271 supplies a power supply voltage VDD. Power supply wiring 272 and 273 supply a power supply voltage VSS. In a plan view, power supply wiring 271 overlaps with active regions P3 and P4 and power supply wiring 211. In a plan view, power supply wiring 272 overlaps with active region N3 and wiring 212. In a plan view, power supply wiring 273 overlaps with active region N4 and wiring 213.

[0060] The power supply wiring 271 is connected to the local wiring 252 through a via 281, and is connected to the local wiring 257 through a via 282. The power supply wiring 272 is connected to the local wiring 256 through a via 283. The power supply wiring 273 is connected to the local wiring 253 through a via 284. The wiring 274 is connected to the gate wiring 231 through a contact 285. The wiring 275 is connected to the gate wiring 234 through a contact 286.

[0061] In the M2 wiring layer, a wiring 291 is formed, which extends in the X direction from both the left and right ends of the cell in the drawing. The wiring 291 corresponds to the word line WL. The wiring 291 is connected to the wiring 274 through a via 301 and to the wiring 275 through a via 302.

[0062] With the above configuration, power supply wirings 272 and 273 that supply the power supply voltage VSS are formed in the M1 wiring layer, which is a metal wiring layer. This eliminates the need to form power supply wirings that supply the power supply voltage VSS in the BM0 wiring layer, which is the wiring layer on the back surface of the transistor, and allows the wiring widths of the wirings 212 and 213 that correspond to the bit lines BLB and BL, respectively, to be increased. This reduces the wiring resistance of the bit lines, making it possible to prevent a decrease in the operating speed of the semiconductor memory device.

[0063] Furthermore, power supply wirings 272 and 273 that supply a power supply voltage VSS are formed in the M1 wiring layer. Wirings 212 and 213 that correspond to the bit lines BLB and BL, respectively, are formed in the BM0 wiring layer. This eliminates the need to form wirings that correspond to the bit lines BLB and BL, respectively, in the M1 wiring layer, and allows the wiring width of the power supply wirings 272 and 273 that supply the power supply voltage VSS in the M1 wiring layer to be increased. This reduces the wiring resistance of the power supply wiring, thereby suppressing fluctuations in the power supply voltage, preventing a decrease in the operating speed of the semiconductor memory device, and improving operational stability.

[0064] Furthermore, power supply wiring 211, 271 that supplies power supply voltage VDD are formed in the BM0 wiring layer and the M1 wiring layer, respectively. This allows the wiring width of power supply wiring 271 formed in the M1 wiring layer to be reduced, and the wiring width of power supply wiring 272, 273 that supplies power supply voltage VSS to be increased, thereby reducing the wiring resistance of the power supply wiring. Therefore, fluctuations in the power supply voltage are suppressed, which prevents a decrease in the operating speed of the semiconductor memory device and improves the stability of operation.

[0065] Furthermore, a power supply wiring 211 that supplies a power supply voltage VDD is formed between the wiring 212 and the wiring 213. This suppresses crosstalk noise between the wirings 212 and 213 that correspond to the bit lines BLB and BL, respectively, and therefore prevents deterioration in the performance and reliability of the semiconductor memory device.

[0066] (Circuit Block Configuration) FIGS. 8 to 11 are diagrams showing examples of the layout of a circuit block included in a semiconductor integrated circuit device according to this embodiment. Specifically, FIG. 8 is a plan view of the M1 wiring layer in the circuit block, and FIG. 9 is a plan view of the BM0 wiring layer and the BM1 wiring layer in the circuit block. FIG. 10(a) is a plan view of the upper part of the cell in region S1 in FIGS. 8 and 9, FIG. 10(b) is a plan view of the lower part of the cell in region S1 in FIGS. 8 and 9, and FIG. 11 is a cross section taken along X11-X11' in FIG. 10. Note that FIG. 8 shows only the cell frame of the SRAM cell and the wiring formed in the M1 wiring layer, and FIG. 9 shows only the cell frame of the SRAM cell and the wiring formed in the BM0 wiring layer and the BM1 wiring layer.

[0067] A memory cell array A1 is formed in the circuit block of Figures 8 and 9. In the memory cell array A1, cell rows CR1 and cell rows CR2 are arranged alternately in the X direction. The cell row CR1 is composed of a plurality of first SRAM cells C1 arranged in the Y direction. The cell row CR2 is composed of a plurality of second SRAM cells C2 arranged in the Y direction. Note that in Figures 8 and 9, the second SRAM cells C2 of Figure 5 are arranged inverted in the X direction in the cell row CR2.

[0068] 8, in the cell column CR1, a plurality of first SRAM cells C1 arranged in the Y direction in the M1 wiring layer are commonly connected to a power supply line 71 (power supply line that supplies a power supply voltage VDD) and lines 72 and 73 (bit lines BLB and BL) extending in the Y direction. In the cell column CR2, a plurality of second SRAM cells C2 arranged in the Y direction in the M1 wiring layer are commonly connected to a power supply line 271 (power supply line that supplies a power supply voltage VDD) and power supply lines 272 and 273 (power supply lines that supply a power supply voltage VSS) extending in the Y direction.

[0069] Also, as shown in Figures 8 and 10(a), the wiring in the M1 wiring layer is arranged in the X direction from the left side of the drawing to the right side of the drawing in the order of wiring 72, power supply wiring 71, wiring 73, power supply wiring 273, power supply wiring 271, and power supply wiring 272.

[0070] 9 , in the cell column CR1, a plurality of first SRAM cells C1 arranged in the Y direction in the BM0 wiring layer are commonly connected to a power supply line 11 (a power supply line that supplies a power supply voltage VDD) and power supply lines 12 and 13 (a power supply line that supplies a power supply voltage VSS) extending in the Y direction. In the cell column CR2, a plurality of second SRAM cells C2 arranged in the Y direction in the BM0 wiring layer are commonly connected to a power supply line 211 (a line that supplies a power supply voltage VDD) and lines 212 and 213 (bit lines BLB and BL) extending in the Y direction. In the BM1 wiring layer, a plurality of power supply lines 121 (a power supply line that supplies a power supply voltage VSS) extending in the X direction are arranged in the Y direction, and each power supply line 121 is connected to the power supply lines 12 and 13 in the BM0 wiring layer via vias 131 and 132 (not shown in FIG. 9 ).

[0071] Also, as shown in Figures 9 and 10(b), the wiring in the BM1 wiring layer is arranged in the X direction from the left side of the drawing to the right side of the drawing in the order of power supply wiring 12, power supply wiring 11, power supply wiring 13, wiring 213, power supply wiring 211, and wiring 212.

[0072] With the above configuration, in the circuit block according to this embodiment, in the first SRAM cell C1, the wires 72 and 73 corresponding to the bit lines BLB and BL, respectively, are formed in the M1 wiring layer, which is a metal wiring layer. In the second SRAM cell C2, the wires 212 and 213 corresponding to the bit lines BLB and BL, respectively, are formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. As a result, in the first SRAM cell C1 and the second SRAM cell C2, the bit lines BL and BLB constituting the bit line pair are formed in the same wiring layer, which reduces the likelihood of imbalance in characteristics between the bit line pair. Furthermore, because the bit lines BLB and BL are formed in the same wiring layer, process variations in the wiring of the bit line pair do not occur independently of each other. This reduces the likelihood of reduced yield and reliability of the SRAM cells, eliminates the need for a large design margin, and thus reduces performance degradation, such as a decrease in the operating speed of the semiconductor memory device.

[0073] In the first SRAM cell C1, a power supply line 71 that supplies a power supply voltage VDD is formed in the M1 wiring layer between lines 72 and 73 that correspond to the bit lines BLB and BL, respectively. In the second SRAM cell C2, a power supply line 211 that supplies a power supply voltage VDD is formed in the BM0 wiring layer between lines 212 and 213 that correspond to the bit lines BLB and BL, respectively. This suppresses crosstalk noise between the lines that correspond to the bit lines BLB and BL, respectively, in the first SRAM cell C1 and the second SRAM cell C2, thereby preventing degradation in performance and reliability of the semiconductor memory device.

[0074] Furthermore, the BM0 wiring layer is formed with a plurality of power supply wirings 12 and 13 extending in the Y direction and supplying a power supply voltage VSS. The BM1 wiring layer is formed with a plurality of power supply wirings 121 extending in the X direction and supplying a power supply voltage VSS. The power supply wirings 12 and 13 are connected to the power supply wiring 121. As a result, the power supply wirings supplying the power supply voltage VSS are formed in a mesh pattern in the BM0 wiring layer and the BM1 wiring layer, which reduces the wiring resistance of the wirings supplying the power supply voltage and suppresses fluctuations in the power supply voltage, thereby suppressing a decrease in the operating speed of the semiconductor memory device and improving operational stability. Furthermore, the wirings in the BM1 wiring layer are arranged in the X direction from the left side of the drawing to the right side of the drawing in the order of power supply wiring 12, power supply wiring 11, power supply wiring 13, wiring 213, power supply wiring 211, and wiring 212. As a result, the wirings 212 and 213 corresponding to the bit lines BLB and BL, respectively, are not arranged adjacent to each other within the SRAM cell and between adjacent SRAM cells, thereby suppressing crosstalk noise between the wirings corresponding to the bit lines BLB and BL, respectively, and preventing deterioration in the performance and reliability of the semiconductor memory device.

[0075] Moreover, the wiring in the M1 wiring layer is arranged in the X direction from the left side of the drawing to the right side of the drawing in the order of wiring 72, power supply wiring 71, wiring 73, power supply wiring 273, power supply wiring 271, and power supply wiring 272. As a result, the wirings 72 and 73 corresponding to the bit lines BLB and BL, respectively, are not arranged adjacent to each other within the SRAM cell and between adjacent SRAM cells, so that crosstalk noise between the wirings corresponding to the bit lines BLB and BL, respectively, can be suppressed, and deterioration in performance and reliability of the semiconductor memory device can be prevented.

[0076] The power supply wiring formed on the back surface side of the transistor may be formed using a semiconductor chip separate from the semiconductor chip on which the transistor is formed.

[0077] Fig. 12(a) shows another example of the configuration of a semiconductor integrated circuit device according to the embodiment. The semiconductor integrated circuit device 400 shown in Fig. 12(a) is configured by stacking a first semiconductor chip 401 (chip A) and a second semiconductor chip 402 (chip B). Chip A has the above-mentioned SRAM cells and the like arranged therein. Chip B has power wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0078] 12(b) shows a cross section of the first SRAM cell C1 of FIG. 1 taken along line X1-X1' in this configuration example. As shown in FIG. 12(b), a wiring layer provided on the surface of chip B has a power supply wiring 11 that supplies VDD and power supply wirings 12 and 13 that supply VSS formed thereon. The power supply wiring 11 is connected to region 46 of chip A through a via 113 provided at a position overlapping the power supply wiring 11 in a planar view. The power supply wiring 13 is connected to region 43 of chip A through a via 112 provided at a position overlapping the power supply wiring 13 in a planar view. Although not shown, the power supply wiring 12 is connected to region 42 of chip A through a via 111 provided at a position overlapping the power supply wiring 12 in a planar view. In this case, although not shown, the power supply wiring 211 and wirings 212 and 213 of the second SRAM cell C2 are also formed in a wiring layer provided on the surface of the chip B, similar to the power supply wirings 11 to 13 of the first SRAM cell C1.

[0079] (Variation 1) Fig. 13 is a plan view showing another example of the layout structure of the first SRAM cell according to the embodiment, and Fig. 14 is a plan view showing another example of the layout structure of the second SRAM cell according to the embodiment. Specifically, Fig. 13 shows the lower part of the first SRAM cell C1, and Fig. 14 shows the lower part of the second SRAM cell C2. Note that in this variation, the upper part of the first SRAM cell C1 in Fig. 13 is the same as Fig. 1A, and the upper part of the second SRAM cell C2 in Fig. 14 is the same as Fig. 5A.

[0080] 13 and 14, compared with FIGS. 1 and 5, a power supply wiring 122 is formed in the BM1 wiring layer instead of the power supply wiring 121.

[0081] Specifically, a power supply line 122 extending in the X direction is formed in the BM1 wiring layer. The power supply line 122 supplies a power supply voltage VDD. In the first SRAM cell C1 of FIG. 13, the power supply line 122 is connected to the power supply line 11 in the BM0 wiring layer through a via 133. In the second SRAM cell C2 of FIG. 14, the power supply line 122 is connected to the power supply line 211 in the BM0 wiring layer through a via 331.

[0082] When the first SRAM cell C1 of FIG. 13 and the second SRAM cell C2 of FIG. 14 are arranged in the circuit block of FIGS. 8 and 9, multiple power supply wirings 122 are arranged side by side in the Y direction in the BM1 wiring layer.

[0083] According to this modification, the power supply voltage VDD supplied to the first SRAM cell C1 and the second SRAM cell C2 can be strengthened.

[0084] In addition, the same effects as those in FIGS. 1 and 5 can be obtained.

[0085] 8 and 9, the first SRAM cell C1 of Fig. 13 and the second SRAM cell C2 of Fig. 14 may be arranged in place of some or all of the first SRAM cell C1 of Fig. 1 and the second SRAM cell C2 of Fig. 5. In this case, for example, the first SRAM cell C1 of Fig. 13 and the second SRAM cell C2 of Fig. 14 may be arranged in place of the first SRAM cell C1 of Fig. 1 and the second SRAM cell C2 of Fig. 5 every N rows (N is an integer of 2 or more) in the Y direction.

[0086] (Variation 2) Figure 15 is a plan view showing another example of the layout structure of the first SRAM cell according to the embodiment, and Figure 16 is a plan view showing another example of the layout structure of the second SRAM cell according to the embodiment. Specifically, Figure 15 shows the lower part of the first SRAM cell C1, and Figure 16 shows the lower part of the second SRAM cell C2. Note that in this variation, the upper part of the first SRAM cell C1 in Figure 15 is the same as Figure 1A, and the upper part of the second SRAM cell C2 in Figure 16 is the same as Figure 5A.

[0087] 15 and 16, compared with FIGS. 1 and 5, power supply wirings 123 and 124 are formed in the BM1 wiring layer instead of the power supply wiring 121.

[0088] Specifically, power supply wirings 123 and 124 extending in the X direction are formed in the BM1 wiring layer. The power supply wiring 123 is formed at the top of the drawing and supplies a power supply voltage VDD. The power supply wiring 124 is formed at the bottom of the drawing and supplies a power supply voltage VSS. In the first SRAM cell C1 of FIG. 15, the power supply wiring 123 is connected to the power supply wiring 11 in the BM0 wiring layer via a via 134. In the first SRAM cell C1 of FIG. 15, the power supply wiring 124 is connected to the power supply wiring 12 in the BM0 wiring layer via a via 135 and to the power supply wiring 13 in the BM0 wiring layer via a via 136. In the second SRAM cell C2 of FIG. 16, the power supply wiring 123 is connected to the power supply wiring 211 in the BM0 wiring layer via a via 332.

[0089] When the first SRAM cell C1 of FIG. 15 and the second SRAM cell C2 of FIG. 16 are arranged in the circuit blocks of FIGS. 8 and 9, the power supply wirings 123 and 124 are arranged alternately in the Y direction in the BM1 wiring layer.

[0090] According to this modification, the power supply voltages VDD and VSS supplied to the first SRAM cell C1 and the second SRAM cell C2 can be strengthened.

[0091] In addition, the same effects as those in FIGS. 1 and 5 can be obtained.

[0092] 15 and 16, the power supply wirings 123 and 124 are formed at the upper and lower ends of the drawings, but this is not limited to this. Furthermore, the wiring widths of the power supply wirings 123 and 124 may be the same or different.

[0093] In the first SRAM cell C1 in each of the above-described embodiments and modifications, power supply wirings 11 and 71 that supply the power supply voltage VDD are formed in the BM0 wiring layer and the M1 wiring layer, respectively. However, it is sufficient if at least one of the power supply wirings 11 and 71 is formed. For example, if only the power supply wiring 71 in the M1 wiring layer is formed, the wiring width of the power supply wirings 12 and 13 in the BM0 wiring layer that supply the power supply voltage VSS can be increased, thereby strengthening the power supply voltage VSS supplied to the first SRAM cell C1. On the other hand, if only the power supply wiring 11 in the BM0 wiring layer is formed, the wiring width of the wirings 72 and 73 corresponding to the bit lines BLB and BL in the M1 wiring layer can be increased, thereby reducing the wiring resistance of the bit lines and preventing a decrease in the operating speed of the semiconductor memory device.

[0094] Furthermore, in the second SRAM cell C2 in each of the above-described embodiments and modifications, the power supply wirings 211 and 271 that supply the power supply voltage VDD are formed in the BM0 wiring layer and the M1 wiring layer, respectively. However, it is sufficient if at least one of the power supply wirings 211 and 271 is formed. For example, if only the power supply wiring 211 in the BM0 wiring layer is formed, the wiring width of the power supply wirings 272 and 273 in the M1 wiring layer that supply the power supply voltage VSS can be increased, thereby strengthening the power supply voltage VSS supplied to the second SRAM cell C2. On the other hand, if only the power supply wiring 271 in the M1 wiring layer is formed, the wiring width of the wirings 212 and 213 corresponding to the bit lines BLB and BL in the BM0 wiring layer can be increased, thereby reducing the wiring resistance of the bit lines and preventing a decrease in the operating speed of the semiconductor memory device.

[0095] Furthermore, in each of the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0096] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0097] In addition, in the above-described embodiments and modifications, the width in the X direction of the nanosheets 21 to 24 is twice the width in the X direction of the nanosheets 25 and 26, but this is not limited to this. The width in the X direction of each of the nanosheets 21 to 26 may be determined taking into consideration the operational stability of the SRAM circuit, etc.

[0098] In addition, in each of the above-described embodiments and modifications, the shared contacts 61 and 62 may be manufactured in the same process as the contacts (gate contacts) and local wiring, or may be manufactured in a separate process.

[0099] Furthermore, in each of the above-described embodiments and modified examples, the power supply that supplies the power supply voltage VDD to the sources (regions 46, 49) of the load transistors PU1, PU2 in the first SRAM cell C1 and the sources (regions 246, 249) of the load transistors PU1, PU2 in the second SRAM cell C2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

[0100] According to the present disclosure, in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor, it is possible to prevent a decrease in performance of a semiconductor memory device.

[0101] 11-13, 71, 121-124, 211, 271-273 Power supply wiring 111-114, 311-314 Vias 21-26 Nanosheets 31-34 Gate wiring 40-49, 240-249 Areas 72, 73, 212, 213 Wiring C1 First SRAM cell C2 Second SRAM cell PU1, PU2 Load transistors PD1, PD2 Drive transistors PG1, PG2 Access transistors BL, BLB Bit lines WL Word lines

Claims

1. A semiconductor memory device including a plurality of SRAM cells, wherein the SRAM cells comprise: a first transistor having a source connected to a first power supply supplying a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply supplying a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, wherein the plurality of SRAM cells are: a first SRAM cell; the first SRAM cell includes a second SRAM cell arranged in a first direction, the first bit line of the first SRAM cell being formed in a metal wiring layer above the first to sixth transistors and including a first wiring extending in a second direction, the second bit line of the first SRAM cell being formed in the metal wiring layer and including a second wiring extending in the second direction, the first SRAM cell including: a first active region constituting a channel, a source and a drain of the third transistor of the first SRAM cell and including a nanosheet extending in the second direction as the channel; a second active region constituting a channel, a source and a drain of the fourth transistor of the first SRAM cell and including a nanosheet extending in the second direction as the channel; a first power supply wiring formed in a first back wiring layer on the back side of the first to sixth transistors, extending in the second direction and connected to the second power supply; and a second power supply wiring formed in the first back wiring layer, extending in the second direction and connected to the second power supply.the first active region includes a first region constituting a source of the third transistor and the first power supply wiring, the first via being formed at a position where the first region and the first power supply wiring overlap, and the first region and the first via being connected to the first region and the first power supply wiring; and the second active region includes a second region constituting a source of the fourth transistor and the second power supply wiring, the second via being formed at a position where the second region and the second power supply wiring overlap, the first bit line of the second SRAM cell is formed in the first backside wiring layer and includes a third wiring extending in the second direction, the second bit line of the second SRAM cell is formed in the first backside wiring layer and includes a fourth wiring extending in the second direction, the second SRAM cell comprising: a third active region constituting a channel, source and drain of the third transistor of the second SRAM cell, the channel of the third active region including a nanosheet extending in the second direction; and a fourth active region constituting a channel, source and drain of the fourth transistor of the second SRAM cell, the channel of the fourth active region including a nanosheet extending in the second direction. a third via formed at a position where a third region constituting a source of the third transistor in the third active region and the third wiring overlap, connecting the third region and the third wiring; a fourth via formed at a position where a fourth region constituting a source of the fourth transistor in the fourth active region and the fourth wiring overlap, connecting the fourth region and the fourth wiring; and a third power supply wiring formed in the metal wiring layer, extending in the second direction, and connected to the second power supply.

2. A semiconductor memory device according to claim 1, wherein the first SRAM cell is formed in the metal wiring layer, extends in the second direction, is formed between the first and second wirings, and further comprises a fourth power supply wiring connected to the first power supply.

3. A semiconductor memory device according to claim 1, wherein the first SRAM cell further comprises: a fifth active region constituting the channel, source and drain of the first transistor of the first SRAM cell, the channel being a nanosheet extending in the second direction; a sixth active region constituting the channel, source and drain of the second transistor of the first SRAM cell, the channel being a nanosheet extending in the second direction; a fifth power supply wiring formed in the first backside wiring layer, extending in the second direction and connected to the first power supply; a fifth via formed at a position where the fifth region constituting the source of the first transistor in the fifth active region overlaps with the fifth power supply wiring and connecting the fifth region to the fifth power supply wiring; and a sixth via formed at a position where the sixth region constituting the source of the second transistor in the sixth active region overlaps with the fifth power supply wiring and connecting the sixth region to the fifth power supply wiring.

4. A semiconductor memory device according to claim 1, wherein the second SRAM cell further comprises: a sixth power supply wiring formed in the metal wiring layer, extending in the second direction, and connected to the second power supply; and a seventh power supply wiring formed in the metal wiring layer, extending in the second direction, formed between the third and sixth power supply wirings, and connected to the first power supply.

5. A semiconductor memory device according to claim 1, wherein the second SRAM cell further comprises: a seventh active region constituting the channel, source and drain of the first transistor of the second SRAM cell, the channel being a nanosheet extending in the second direction; an eighth active region constituting the channel, source and drain of the second transistor of the second SRAM cell, the channel being a nanosheet extending in the second direction; an eighth power supply wiring formed in the first backside wiring layer, extending in the second direction and connected to the first power supply; a seventh via formed at a position where the seventh region constituting the source of the first transistor in the seventh active region overlaps with the eighth power supply wiring and connecting the seventh region to the eighth power supply wiring; and an eighth via formed at a position where the eighth region constituting the source of the second transistor in the eighth active region overlaps with the eighth power supply wiring and connecting the eighth region to the eighth power supply wiring.

6. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells are formed in a second back wiring layer below the first back wiring layer, and further comprises a ninth power supply wiring extending in the first direction and connected to the first and second power supply wirings.

7. A semiconductor memory device according to claim 1, wherein the first SRAM cell is formed in the metal wiring layer, extends in the second direction, is formed between the first and second wirings, and further comprises a fourth power supply wiring connected to the first power supply; the second SRAM cell is further comprised of a sixth power supply wiring formed in the metal wiring layer, extends in the second direction, and is connected to the second power supply; and a seventh power supply wiring formed in the metal wiring layer, extends in the second direction, is formed between the third and sixth power supply wirings, and is connected to the first power supply; and in the plurality of SRAM cells, a first cell row including a plurality of the first SRAM cells aligned in the second direction and a second cell row including a plurality of the second SRAM cells aligned in the second direction are alternately arranged in the first direction; and in the first cell row, the plurality of first SRAM cells are commonly connected to the same first wiring, the same second wiring, and the same fourth power supply wiring; a second SRAM cell array that includes a first power supply line and a second power supply line, the second SRAM cell array including ...

8. In the semiconductor memory device according to claim 1, the first SRAM cell further comprises: a fifth active region constituting the channel, source and drain of the first transistor of the first SRAM cell, the channel being a nanosheet extending in the second direction; a sixth active region constituting the channel, source and drain of the second transistor of the first SRAM cell, the channel being a nanosheet extending in the second direction; a fifth power supply wiring formed in the first backside wiring layer, extending in the second direction and connected to the first power supply; a fifth via formed at a position where the fifth region constituting the source of the first transistor in the fifth active region overlaps with the fifth power supply wiring and connects the fifth region to the fifth power supply wiring; and a sixth via formed at a position where the sixth region constituting the source of the second transistor in the sixth active region overlaps with the fifth power supply wiring and connects the sixth region to the fifth power supply wiring; and the second SRAM cell further comprises: a seventh active region constituting the channel, source and drain of the first transistor of the second SRAM cell, the channel being a nanosheet extending in the second direction; an eighth active region constituting the channel, source and drain of the second transistor of the second SRAM cell, the channel being a nanosheet extending in the second direction; an eighth power supply wiring formed in the first backside wiring layer, extending in the second direction and connected to the first power supply; a seventh via formed at a position where the seventh region constituting the source of the first transistor in the seventh active region and the eighth power supply wiring overlap, connecting the seventh region and the eighth power supply wiring; and an eighth via formed at a position where the eighth region constituting the source of the second transistor in the eighth active region and the eighth power supply wiring overlap, connecting the eighth region and the eighth power supply wiring.a first cell row including a plurality of first SRAM cells arranged in the second direction and a second cell row including a plurality of second SRAM cells arranged in the second direction, the first SRAM cells being arranged alternately in the first direction; in the first cell row, the first SRAM cells are commonly connected to the same first power supply wiring, the same second power supply wiring, and the same fifth power supply wiring; and in the second cell row, the second SRAM cells are commonly connected to the same third wiring, the same fourth wiring, and the same eighth power supply wiring.

9. A semiconductor memory device according to claim 8, wherein the plurality of SRAM cells are formed in a second back wiring layer below the first back wiring layer, extend in the first direction, and have a plurality of ninth power supply wirings connected to the second power supply, and the first and second power supply wirings in the first SRAM cells arranged side by side in the first direction are commonly connected to the same ninth power supply wiring.

10. In the semiconductor memory device according to claim 1, the first SRAM cell further comprises: a fifth active region constituting the channel, source and drain of the first transistor of the first SRAM cell, the channel being a nanosheet extending in the second direction; a sixth active region constituting the channel, source and drain of the second transistor of the first SRAM cell, the channel being a nanosheet extending in the second direction; a fifth power supply wiring formed in the first backside wiring layer, extending in the second direction and connected to the first power supply; a fifth via formed at a position where the fifth region constituting the source of the first transistor in the fifth active region overlaps with the fifth power supply wiring and connects the fifth region to the fifth power supply wiring; and a sixth via formed at a position where the sixth region constituting the source of the second transistor in the sixth active region overlaps with the fifth power supply wiring and connects the sixth region to the fifth power supply wiring; and the second SRAM cell further comprises: a seventh active region constituting the channel, source and drain of the first transistor of the second SRAM cell, the channel being a nanosheet extending in the second direction; an eighth active region constituting the channel, source and drain of the second transistor of the second SRAM cell, the channel being a nanosheet extending in the second direction; an eighth power supply wiring formed in the first backside wiring layer, extending in the second direction and connected to the first power supply; a seventh via formed at a position where the seventh region constituting the source of the first transistor in the seventh active region and the eighth power supply wiring overlap, connecting the seventh region and the eighth power supply wiring; and an eighth via formed at a position where the eighth region constituting the source of the second transistor in the eighth active region and the eighth power supply wiring overlap, connecting the eighth region and the eighth power supply wiring.The semiconductor memory device is characterized in that the plurality of SRAM cells are formed in a second back wiring layer below the first back wiring layer, and further comprises a tenth power supply wiring extending in the first direction and connected to the fifth and eighth power supply wirings.

11. A semiconductor memory device according to claim 10, wherein the plurality of SRAM cells are formed in the second back wiring layer, and further comprises a ninth power supply wiring extending in the first direction and connected to the first and second power supply wirings.

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