Light detection device

Abstract

[Problem] To quickly switch currents on a signal line. [Solution] This light detection device comprises: a plurality of pixels each having a photoelectric conversion element; a plurality of signal lines for transmitting a plurality of pixel signals obtained by photoelectric conversion by the plurality of pixels; a plurality of first current sources provided corresponding to the plurality of signal lines; a bias circuit for generating a bias current; a first wire set to a voltage level corresponding to the bias current; a second wire connected to the plurality of first current sources; and one or more buffer circuits connected to the first wire and the second wire to set a voltage level of the second wire according to the voltage level of the first wire.

Description

Photodetector

[0001] The present disclosure relates to a light detection device.

[0002] In existing solid-state imaging devices (image sensors), pixel signals photoelectrically converted by multiple pixels arranged in a column direction are transmitted over common signal lines (also called vertical signal lines) and analog-to-digital conversion processing is performed on a column-by-column basis. Multiple signal lines extending in the column direction are arranged in the row direction.

[0003] Since multiple pixels are connected to one signal line, the load capacitance becomes large and it takes time for the signal level of the pixel signal on the signal line to stabilize. For this reason, in Patent Document 1, multiple current sources are provided for each of the multiple signal lines arranged in the row direction, and the current flowing through the signal line is quickly extracted to the ground node.

[0004] JP 2015-207973 A

[0005] In a solid-state imaging device, various operations must be performed during one horizontal scanning period, such as resetting the floating diffusion, reading the reset level, starting exposure, transferring signals, and reading the signal level, and the current that must be passed through the signal line varies for each operation.

[0006] However, in existing solid-state imaging devices, it is common to provide bias current from a common bias circuit to each current source connected to each signal line. When multiple current sources are connected to a bias circuit, the load capacitance of the bias line that provides the bias current increases, slowing the response of the bias current and making it difficult to quickly switch the bias current during one horizontal scanning period.

[0007] Therefore, the present disclosure provides a photodetector that can quickly switch the current on the signal line.

[0008] In order to solve the above problems, according to the present disclosure, there is provided a photodetection device comprising: a plurality of pixels each having a photoelectric conversion element; a plurality of signal lines for transmitting a plurality of pixel signals photoelectrically converted by the plurality of pixels; a plurality of first current sources provided corresponding to the plurality of signal lines; a bias circuit for generating a bias current; a first wiring set to a voltage level according to the bias current; a second wiring connected to the plurality of first current sources; and one or more buffer circuits connected to the first wiring and the second wiring and for setting the voltage level of the second wiring according to the voltage level of the first wiring.

[0009] One first current source may be provided for one buffer circuit, or two or more first current sources may be provided for one buffer circuit.

[0010] Two or more of the buffer circuits may be connected to a common second wiring.

[0011] The bias circuit may include a first transistor and a second current source that generates a current flowing through the first transistor, and the buffer circuit may include a second transistor that forms a current mirror circuit with the first transistor and a third current source that generates a current flowing through the second transistor.

[0012] The third current source may include a third transistor that flows, between its drain and source, a current that is the same as a current that flows between the drain and source of the second transistor, and each of the plurality of first current sources may include a fourth transistor that forms a current mirror circuit with the third transistor.

[0013] The second current source may be a constant current source that supplies a constant current, and the bias current may be constant.

[0014] The one or more buffer circuits may dynamically switch the currents flowing through the plurality of first current sources.

[0015] The bias circuit may include a variable current source that generates a variable, controllable bias current.

[0016] The buffer circuit may include a plurality of second transistors that form a current mirror circuit with the first transistor, and a plurality of switches that switch whether or not a current flows between the drain and source of each of the plurality of second transistors, and the third current source may flow a current corresponding to the number of second transistors that flow a current between the drain and source of the plurality of second transistors.

[0017] The third current source may pass a larger current as the number of second transistors passing a current between their drains and sources among the plurality of second transistors increases.

[0018] Two or more of the buffer circuits may be provided, and each of the two or more buffer circuits may have a switch that switches whether or not a current flows between the drain and source of the second transistor.

[0019] The first wiring may be controlled to a voltage level according to variable control of the bias current by the bias circuit or variable control of the current flowing through the first wiring by the buffer circuit, and the one or more buffer circuits may control the second wiring to a voltage level according to the voltage level of the first wiring.

[0020] Each of the plurality of first current sources may be connected to a corresponding one of the plurality of signal lines.

[0021] and a plurality of analog-to-digital converters that convert the plurality of pixel signals transmitted through the plurality of signal lines into digital signals, each of the plurality of analog-to-digital converters having a comparator that compares the pixel signal with a reference signal, the comparator may have the first current source.

[0022] The digital signal processing circuit may further include a plurality of analog-to-digital converters that convert the plurality of pixel signals transmitted through the plurality of signal lines into digital signals, and a ramp buffer that buffers the reference signal and inputs it to the comparator, wherein the ramp buffer may include the first current source.

[0023] The display device may include a pixel array section having the plurality of pixels arranged in a first direction and a second direction; and a drive section that sequentially drives the plurality of pixel groups arranged in the second direction, with each pixel group including two or more of the pixels arranged in the first direction as a unit, wherein the one or more buffer circuits may dynamically switch the currents flowing through the plurality of first current sources within a period in which each of the plurality of pixel groups arranged in the second direction is driven.

[0024] When the plurality of first current sources are connected to the plurality of signal lines, the current flowing through the plurality of first current sources may be larger when the plurality of pixels are reset within the period and when the accumulated charge of the photoelectric conversion element is transferred to a floating diffusion than in other cases.

[0025] The digital signal processing device includes a plurality of analog-to-digital converters that convert the plurality of pixel signals transmitted through the plurality of signal lines into digital signals, each of the plurality of analog-to-digital converters having: a comparator that compares a reference signal with the pixel signal; a counter that performs a counting operation until the reference signal matches the pixel signal based on the comparison result of the comparator; and a ramp buffer that buffers the reference signal and inputs it to the comparator, and if the comparator has the first current source, a larger current may flow in the corresponding first current source while the counter is performing a counting operation within the period.

[0026] and a ramp buffer that buffers the reference signal and inputs it to the comparator, and if the ramp buffer has the first current source, the current flowing in the corresponding first current source may be increased while the counter is performing a counting operation within the period.

[0027] The buffer circuit may include a signal holding section that holds a charge according to a voltage level of the first wiring, and a switch that switches whether or not the charge is to be held in the signal holding section.

[0028] 7 is a block diagram showing a schematic configuration of a photodetector according to the present disclosure. FIG. 8 is a circuit diagram of one pixel in a pixel array unit. FIG. 9 is a schematic perspective view showing an example of a photodetector according to the present disclosure having a two-layer structure. FIG. 10 is a schematic perspective view showing an example of a photodetector according to the present disclosure having a three-layer structure. FIG. 11 is a block diagram showing the internal configuration of the load MOS circuit and column signal processing circuit shown in FIG. 1. FIG. 12 is a block diagram showing main parts of a photodetector according to a first embodiment. FIG. 13 is a circuit diagram showing a specific configuration of a buffer circuit 31. FIG. 14 is a circuit diagram showing a modification of the buffer circuit of FIG. 6. FIG. 15 is a block diagram showing main parts of a photodetector according to a modification of the first embodiment. FIG. 16 is a circuit diagram showing a specific configuration of a buffer circuit according to a modification of the first embodiment. FIG. 17 is a circuit diagram showing a buffer circuit according to a modification of FIG. 18. FIG. 19 is a block diagram showing main parts of a photodetector according to a second embodiment. FIG. 19 is a circuit diagram showing a specific configuration of a buffer circuit according to the second embodiment. FIG. 19 is a block diagram showing main parts of a photodetector according to a third embodiment. FIG. 19 is a timing chart showing an example in which a bias circuit variably controls the current flowing through a second current source within one horizontal scanning period. FIG. 19 is a circuit diagram showing a specific configuration of a buffer circuit according to a first modification of the third embodiment. 10. A block diagram of a photodetector according to a second modified example of the third embodiment. A diagram showing an example of turning on a switch 39 arranged between the output node of the buffer circuit and a local bias line. A diagram showing an example of turning off a switch 39 arranged between the output node of the buffer circuit and a local bias line. A block diagram showing a main part of a photodetector according to a fourth embodiment. A timing diagram showing changes in current flowing through the current source of the load MOS circuit, the current source of the comparator, and the current source of the ramp buffer within one horizontal scanning period. A block diagram of a photodetector according to a fifth embodiment. A block diagram showing an example of the schematic configuration of a vehicle control system. An explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0029] Hereinafter, an embodiment of a photodetector will be described with reference to the drawings. The following description will focus on the main components of the photodetector, but the photodetector may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0030] 1 is a block diagram showing a schematic configuration of a photodetector 1 according to the present disclosure. As shown in FIG. 1, the photodetector 1 according to the present disclosure includes a pixel array unit 2, a vertical scanning circuit 3, a load MOS (Metal Oxide Semiconductor) circuit 4, a column signal processing circuit 5, a timing control circuit 6, a digital-to-analog converter (DAC) 7, and a bias circuit 8.

[0031] The pixel array unit 2 has a plurality of pixels 10 arranged in a first direction X and a second direction Y. In this specification, the first direction X is sometimes referred to as the row direction, and the second direction Y is sometimes referred to as the column direction. In addition, in this specification, a group of pixels in one row is called a pixel row, and a group of pixels in one column is called a pixel column.

[0032] The timing control circuit 6 synchronizes with a vertical synchronization signal XVS supplied from a control unit (not shown) and controls the operation timing of the vertical scanning circuit 3, the DAC 7, and the column signal processing circuit 5. The DAC 7 generates a reference signal (ramp signal) Ramp used when performing analog-to-digital conversion (hereinafter referred to as AD conversion) in the column signal processing circuit 5. The reference signal Ramp is, for example, a sawtooth waveform signal.

[0033] The vertical scanning circuit 3 sequentially drives a plurality of row scanning lines L1. The row scanning lines L1 are provided for each pixel row aligned in the second direction Y. When the vertical scanning circuit 3 drives one of the row scanning lines L1, pixel signals from the pixels 10 in the corresponding pixel row are sent to a plurality of vertical signal lines VSL. The pixel signals on the plurality of vertical signal lines VSL are input to a column signal processing circuit 5 via load MOS circuits 4.

[0034] As will be described later, the load MOS circuit 4 has a constant current source that supplies a constant current to each vertical signal line VSL.

[0035] The column signal processing circuit 5 performs AD conversion on the pixel signals on each vertical signal line VSL and performs CDS (Correlated Double Sampling) on ​​the AD-converted digital pixel signals. In this specification, the output of the column signal processing circuit 5 is referred to as image data. The image data is image data captured in a part or the entire area of ​​the pixel array unit 2 in units of frames.

[0036] The bias circuit 8 generates a bias current for controlling the current flowing in a current source (first current source) directly or indirectly connected to the vertical signal line VSL. The bias circuit 8 may be built into the timing control circuit 6 or the like. The bias circuit 8 may control the current flowing in a current source provided in the load MOS circuit 4. The bias circuit 8 may also control the current flowing in a current source of a comparator for analog-to-digital conversion provided in the column signal processing circuit 5. The bias circuit 8 may also control the current flowing in a current source of a ramp buffer that buffers a reference signal input to the above-mentioned comparator.

[0037] 2 is a circuit diagram of one pixel 10 in the pixel array unit. The pixel 10 has a photoelectric conversion element 11, a transfer transistor 12, a reset transistor 13, an amplification transistor 14, and a selection transistor 15.

[0038] The photoelectric conversion element 11 accumulates electric charges corresponding to the amount of incident light. The photoelectric conversion element 11 is, for example, a photodiode. The transfer transistor 12 switches whether or not to transfer the accumulated electric charges of the photoelectric conversion element 11 to the floating diffusion FD. The reset transistor 13 switches whether or not to set the floating diffusion FD to a reset signal level by discharging the electric charges of the floating diffusion FD to a power supply voltage node. The amplification transistor 14, together with the selection transistor 15, forms a source follower circuit and generates a pixel signal corresponding to the accumulated electric charges of the floating diffusion FD and outputs it to a signal line (hereinafter also referred to as a vertical signal line VSL). The selection transistor 15 outputs the pixel signal to the vertical signal line VSL when the selection signal SEL is at a high level.

[0039] Although not shown in FIG. 2, the pixel 10 may be provided with at least one of a drain transistor and a conversion efficiency switching transistor.

[0040] The photodetector 1 according to the present disclosure can be realized as a chip with a stacked structure. FIG. 3A is a schematic perspective view showing an example of a photodetector 1 according to the present disclosure having a two-layer structure. The photodetector 1 in FIG. 3A includes a first substrate 16 disposed on the light incident surface side and a second substrate 17 laminated on the first substrate 16. The first substrate 16 is provided with, for example, a photoelectric conversion element 11, a transfer transistor 12, a reset transistor 13, an amplifier transistor 14, and a selection transistor 15 for each pixel 10. The second substrate 17 is provided with, for example, a vertical scanning circuit 3, a load MOS circuit 4, a column signal processing circuit 5, a timing control circuit 6, a digital-to-analog converter (DAC) 16, and a bias circuit 8. The first substrate 16 and the second substrate 17 are bonded and transmit signals using, for example, a copper-copper connection (CCC). Alternatively, the first substrate 16 and the second substrate 17 may be bonded using vias or bumps other than CCC.

[0041] 3B is a schematic perspective view showing an example of a photodetector 1 according to the present disclosure having a three-layer structure. The photodetector 1 in FIG. 3B includes a first substrate 16 disposed on the light incident surface side, a second substrate 17 laminated on the first substrate 16, and a third substrate 18 laminated on the second substrate 17. For example, the photoelectric conversion element 11 and the transfer transistor 12 of each pixel 10 are disposed on the first substrate 16. The pixel transistors other than the transfer transistor 12 of each pixel 10 (such as the reset transistor 13, the amplification transistor 14, and the selection transistor 15) are disposed on the second substrate 17. In addition, the vertical scanning circuit 3, the load MOS circuit 4, the column signal processing circuit 5, the timing control circuit 6, the digital-to-analog converter (DAC) 16, and some of the bias circuit 8 are disposed on the second substrate 17, while the remaining circuits are disposed on the third substrate 18. The first substrate 16 and the second substrate 17 are joined and signal transmitted by, for example, a TSV (Through Silicon Via), and the second substrate 17 and the third substrate 18 are joined and signal transmitted by, for example, a CCC.

[0042] 4 is a block diagram showing the internal configuration of the load MOS circuit 4 and the column signal processing circuit 5 shown in FIG. 1. The load MOS circuit 4 has a plurality of current sources 20, each connected to a plurality of vertical signal lines VSL arranged in a first direction X and extending in a second direction Y. Each vertical signal line VSL is provided for each pixel column extending in the second direction Y. Each current source 20 supplies a constant current to the corresponding vertical signal line VSL. The current source 20 can be a first current source, which will be described later.

[0043] The column signal processing circuit 5 has a plurality of analog-to-digital converters (hereinafter, referred to as ADCs) 21 and a digital signal processing unit 22. Each of the plurality of ADCs 21 is provided corresponding to one of the vertical signal lines VSL. The ADC 21 converts the pixel signal on the corresponding vertical signal line VSL into a digital pixel signal in synchronization with a control signal L2 from the timing control circuit 6 shown in FIG. 1 and using a reference signal (ramp signal) Ramp from the DAC 7 shown in FIG. 3. The digital pixel signal output from the ADC 21 is supplied to the digital signal processing unit 22. The ADC 21 is, for example, a single-slope ADC having a comparator and a counter.

[0044] The digital signal processor 22 performs signal processing such as CDS processing between pixel signals of the reset level and pixel signals of the signal charges for each vertical signal line VSL, and outputs image data. The digital signal processor 22 outputs image data in units of frames.

[0045] Each embodiment of the photodetector 1 according to the present disclosure described below is characterized in that a current flowing through a current source (hereinafter, sometimes referred to as a first current source) directly or indirectly connected to a vertical signal line VSL is controlled. A first current source is provided for each vertical signal line VSL, and therefore, multiple first current sources are provided for multiple vertical signal lines VSL.

[0046] First Embodiment FIG. 5 is a block diagram showing the main components of a photodetector 1 according to a first embodiment. FIG. 5 shows a block configuration of a bias circuit 8 and a column signal processing circuit 5. The column signal processing circuit 5 has a plurality of buffer circuits 31 and a plurality of column signal processing units 32. The following mainly describes an example in which the column signal processing circuit 5 has a plurality of vertical signal lines VSL and a plurality of buffer circuits 31, but a minimum configuration may include only one vertical signal line VSL and one buffer circuit 31. Each column signal processing unit 32 has a corresponding first current source 33. In addition, each column signal processing unit 32 has, for example, an ADC 21. The ADC 21 has, for example, a comparator and a ramp buffer.

[0047] The bias circuit 8 generates a bias current. A bias line (first wiring) L11 is connected to the bias circuit 8. The bias line L11 is set to a voltage level according to the bias current generated by the bias circuit 8. A plurality of buffer circuits 31 in the column signal processing circuit 5 are connected to the bias line L11.

[0048] 5 shows an example in which the first current source 33 is provided inside the column signal processing unit 32. As will be described later, the column signal processing unit 32 has a comparator for analog-to-digital conversion and a ramp buffer that generates a reference signal to be input to the comparator. The first current source 33 may be a current source for the comparator or a current source for the ramp buffer. The first current source 33 may also be a current source provided in the load MOS circuit 4. In this case, the buffer circuit 31 may be provided inside the load MOS circuit 4.

[0049] The bias circuit 8 includes a first transistor Q1 and a second current source 34. The first transistor Q1 is, for example, a PMOS transistor, and its source is connected to a power supply voltage node and its drain is connected to the second current source 34. The gate and drain of the first transistor Q1 are short-circuited. A bias line L11 (first wiring) is connected to the gate of the first transistor Q1. A plurality of buffer circuits 31 are connected to the bias line L11. The output nodes of the plurality of buffer circuits 31 are connected to a common local bias line L12 (second wiring).

[0050] In this way, by connecting the output nodes of multiple buffer circuits 31 to a common local bias line L12, the signal levels of the output signals of multiple buffer circuits 31 can be averaged, and even if the output signals of individual buffer circuits 31 contain noise, the local bias line L12 becomes less susceptible to the effects of that noise.

[0051] 6 is a circuit diagram showing a specific configuration of the buffer circuit 31. The buffer circuit 31 has a second transistor Q2 and a third current source 35. The second transistor Q2 is, for example, a PMOS transistor. The second transistor Q2 and the first transistor Q1 in the bias circuit 8 form a current mirror circuit.

[0052] More specifically, the gate of the first transistor Q1 and the gate of the second transistor Q2 are connected to each other, and a current proportional to the source-drain current of the first transistor Q1 flows between the source and drain of the second transistor Q2.

[0053] The third current source 35 includes, for example, a third transistor Q3. The third transistor Q3 is, for example, an NMOS transistor. The gate and drain of the third transistor Q3 are connected to the local bias line L12, and the source is connected to the ground node.

[0054] A first current source 33 in the column signal processing unit 32 is connected to the local bias line L12. The first current source 33 has a fourth transistor Q4. The fourth transistor Q4 is, for example, an NMOS transistor. The gate of the fourth transistor Q4 is connected to the local bias line L12. For example, when the first current source 33 is a load MOS circuit 4, the drain of the fourth transistor Q4 is connected to the vertical signal line VSL, and the source is connected to the ground node.

[0055] 5 and 6, the bias line L11 connected to the bias circuit 8 has a voltage level corresponding to the current flowing in the second current source 34 in the bias circuit 8. A current proportional to the current flowing in the second current source 34 in the bias circuit 8 flows between the drain and source of the second transistor Q2 in each buffer circuit 31 connected to the bias line L11 and through the third current source 35. The third transistor Q3 constituting the third current source 35 and the fourth transistor Q4 constituting the first current source 33 form a current mirror circuit, so the first current source 33 can pass a current proportional to the current flowing in the third current source 35.

[0056] In this embodiment, a local bias line L12 to which a plurality of buffer circuits 31 are connected is provided separately from the bias line L11 connected to the bias circuit 8, and a plurality of column signal processing units 32 are connected to the local bias line L12 without being connected to the bias line L11. Therefore, the load on the bias line L11 does not increase, and the settling time of the voltage level of the bias line L11 can be shortened.

[0057] The circuit configuration of the buffer circuit 31 is not necessarily limited to that shown in FIG. 6 . FIG. 7 is a circuit diagram showing a modified example of the buffer circuit 31 of FIG. 6 . The buffer circuit 31 of FIG. 7 is configured by adding a sample-and-hold capacitor 36 and a switch 37 to the buffer circuit 31 of FIG. 6 . The capacitor 36 is connected between the gate and source of the second transistor Q2. The switch 37 is connected between the bias line L11 and the gate of the second transistor Q2. The source of the second transistor Q2 is connected to the power supply voltage node. When the switch 37 is turned on, the gate of the second transistor Q2 has the same potential as the bias line L11, and a charge corresponding to the voltage difference between the power supply voltage and the voltage of the bias line L11 is held in the capacitor 36. When the switch 37 is turned off, the capacitor 36 holds the charge it had just before the switch 37 was turned off. The switch 37 is turned on in synchronization with the timing at which the pixel signal at the reset level of each pixel 10 is transmitted via the vertical signal line VSL, and then turned off. The capacitor 36 holds the charge at the reset level immediately before the switch 37 is turned off. Since kTC noise occurs when the switch 37 changes from on to off, the charge stored in the capacitor 36 includes charge due to the kTC noise, but since the kTC noise does not change between the reset level and the signal level, the potential of the bias line L11 becomes a potential level that has been subjected to CDS processing and that cancels out the kTC noise.

[0058] Although FIGS. 5 to 7 show an example in which the first transistor Q1 made of a PMOS transistor is provided in the bias circuit 8, the first transistor Q1 can also be configured as an NMOS transistor.

[0059] Fig. 8 is a block diagram showing a main part of the photodetector 1 according to a modified example of the first embodiment, and Fig. 9 is a circuit diagram showing a specific configuration of the buffer circuit 31 according to the modified example of the first embodiment. The photodetector 1 according to the modified example differs from those shown in Figs. 5 and 6 in the configurations of the bias circuit 8 and the buffer circuit 31.

[0060] 8, the bias circuit 8 according to one modification includes a first transistor Q1 formed of an NMOS transistor and a second current source 34. The source of the first transistor Q1 is connected to the ground node, and the gate and drain of the first transistor Q1 are shorted. One end of the second current source 34 is connected to the gate and drain of the first transistor Q1, and the other end of the second current source 34 is connected to the power supply voltage node.

[0061] 9, a buffer circuit 31 according to one modification includes a third current source 35 having a second transistor Q2 formed of an NMOS transistor and a third transistor Q3 formed of a PMOS transistor. The drain of the second transistor Q2 is connected to the gate and drain of the third transistor Q3. The source of the second transistor Q2 is connected to the ground node. The gate of the second transistor Q2 is connected to a bias line L11. The source of the third transistor Q3 is connected to a power supply voltage node, and the gate of the third transistor Q3 is connected to a local bias line L12.

[0062] The first current source 33 includes a fourth transistor Q4, which is an NMOS transistor. The gate of the fourth transistor Q4 is connected to the local bias line L12.

[0063] Fig. 10 is a circuit diagram of a buffer circuit 31 according to a modification of Fig. 7. Fig. 10 is obtained by adding a capacitor 36 and a switch 37 to the buffer circuit 31 of Fig. 9. The capacitor 36 in Fig. 10 is connected between the gate of the second transistor Q2 and the ground node. The switch 37 is connected between the gate of the second transistor Q2 and the bias line L11.

[0064] As described above, in the first embodiment, a plurality of buffer circuits 31 are commonly connected to the bias line L11 connected to the bias circuit 8, and a local bias line L12 is commonly connected to the output nodes of the plurality of buffer circuits 31. A plurality of first current sources 33 are connected to the local bias line L12. This prevents the plurality of first current sources 33 from being connected to the bias line L11, thereby reducing the load capacitance of the bias line L11. This shortens the settling time of the bias line L11.

[0065] Furthermore, since the output nodes of the buffer circuits 31 are connected to the common local bias line L12, noise and signal variations in the output signals of the buffer circuits 31 can be reduced.

[0066] Furthermore, by providing a capacitor 36 and a switch 37 in each buffer circuit 31 to sample and hold the voltage of the bias line L11, it is possible to perform CDS (Correlated Double Sampling) processing in each buffer circuit 31 to detect the difference between the reset level and the signal level, thereby suppressing horizontal stripe noise.

[0067] Second Embodiment In the first embodiment, an example in which one buffer circuit 31 corresponds to one first current source 33 has been described. However, in the second embodiment described below, one buffer circuit 31 corresponds to two or more first current sources 33.

[0068] FIG. 11 is a block diagram showing the main components of a photodetector 1 according to a second embodiment. FIG. 11 shows a block configuration of a bias circuit 8 and a column signal processing circuit 5. The bias circuit 8 in FIG. 11 has a circuit configuration similar to that of the bias circuit 8 in FIG. 6. The column signal processing circuit 5 in FIG. 11 differs from the column signal processing circuit 5 in FIG. 6 in that multiple column signal processing units 32 are connected to one buffer circuit 31. This allows the total number of buffer circuits 31 to be reduced compared to the first embodiment, thereby reducing the circuit size of the column signal processing circuit 5. Note that the first current source 33 may be provided in the load MOS circuit 4, and therefore the column signal processing unit 32 in FIG. 11 may be a circuit including the current source 20 in the load MOS circuit 4.

[0069] Each buffer circuit 31 is connected to a bias line L11 and a local bias line L12. All buffer circuits 31 are connected to a common bias line L11 and a common local bias line L12. This makes it possible to average out variations in the output signals of the buffer circuits 31.

[0070] Fig. 12 is a circuit diagram showing a specific configuration of a buffer circuit 31 according to the second embodiment. The buffer circuit 31 according to the second embodiment shown in Fig. 12 includes a second transistor Q2 formed of a PMOS transistor and a third current source 35 formed of an NMOS transistor, similar to Fig. 6. A plurality of column signal processing units 32, each including a plurality of first current sources 33, are connected to a local bias line L12.

[0071] The first current source 33 provided in each column signal processing unit 32 has a fourth transistor Q4. A plurality of fourth transistors Q4 connected to the local bias line L12 are provided for one buffer circuit 31. The plurality of fourth transistors Q4 form a current mirror circuit together with an NMOS transistor Q3 that forms a third current source 35 in the buffer circuit 31. The voltage level of the bias line L11 changes in response to the bias current flowing through the bias circuit 8, the voltage level of the local bias line L12 changes in response to the voltage level of the bias line L11, the current flowing through the third current source 35 changes in response to the voltage level of the local bias line L12, and the current flowing through the third current source 35 changes in response to the current flowing through the third current source 35.

[0072] In the second embodiment, as in the first embodiment, multiple column signal processing units 32 are not connected to the bias line L11, so the load capacitance of the bias line L11 can be reduced and the settling time of the bias line L11 can be shortened.

[0073] In addition, in the second embodiment, multiple column signal processing units 32 are provided for one buffer circuit 31, so the total number of buffer circuits 31 can be reduced compared to the first embodiment, and the area of ​​the column signal processing circuit 5 can be reduced.

[0074] Furthermore, in the second embodiment, the multiple column signal processing units 32 provided for each individual buffer circuit 31 are all connected to a common local bias line L12, so that the output signals of the buffer circuits 31 can be averaged, and the signal processing of the multiple column signal processing units 32 is no longer affected by variations in the individual buffer circuits 31.

[0075] (Third Embodiment) In the first and second embodiments, an example was described in which the bias current generated by the bias circuit 8 was constant, but the bias circuit 8 can variably control the bias current to vary the voltage level of the bias line L11. Even if the bias circuit 8 keeps the bias current constant, the buffer circuit 31 can vary the current flowing through the bias line L11 to variably control the voltage level of the bias line L11. By variably controlling the voltage level of the bias line L11, the current flowing through the first current source 33 provided in the column signal processing unit 32 can be varied.

[0076] FIG. 13 is a block diagram showing essential parts of a photodetector 1 according to a third embodiment. The photodetector 1 according to the third embodiment differs from that shown in FIG. 6 in the circuit configuration of the bias circuit 8. The buffer circuit 31 according to the third embodiment can dynamically switch the current flowing through a plurality of first current sources 33. The bias circuit 8 according to the third embodiment has a first transistor Q1 formed of a PMOS transistor and a second current source 34 formed of a variable current source. The bias circuit 8 can variably control the voltage level of a bias line L11 connected to the gate of the first transistor Q1 by controlling the current (bias current) flowing through the second current source 34.

[0077] A plurality of buffer circuits 31 are connected to the bias line L11. Output nodes of the plurality of buffer circuits 31 are connected to a common local bias line L12. The bias circuit 8 controls the bias current flowing through the second current source 34, thereby variably controlling the voltage level of the bias line L11. The plurality of buffer circuits 31 control the voltage level of the local bias line L12 in accordance with the voltage level of the bias line L11. In this way, in the third embodiment, the voltage level of the local bias line L12 can be variably controlled. As in the first and second embodiments, a plurality of column signal processing units 32 are connected to the local bias line L12.

[0078] Since the multiple column signal processing units 32 are not connected to the bias line L11, the load capacitance of the bias line L11 can be reduced. Therefore, when the bias circuit 8 variably controls the bias current flowing through the second current source 34, the voltage level of the bias line L11 can be quickly variably controlled. When the voltage level of the bias line L11 changes, the voltage level of the local bias line L12 also changes. As a result, the bias circuit 8 variably controls the bias current, thereby variably controlling the voltage level of the local bias line L12.

[0079] In the third embodiment, the bias circuit 8 variably controls the bias current flowing through the second current source 34, thereby enabling the current flowing through the first current source 33 of the column signal processing unit 32 to be quickly switched, and therefore, for example, it becomes possible to variably control the current flowing through the first current source 33 during one horizontal scanning period.

[0080] 14 is a timing diagram showing an example in which the bias circuit 8 variably controls the current flowing through the second current source 34 within one horizontal scanning period. This example shows an example in which the bias circuit 8 increases the bias current flowing through the second current source 34 between times t1 and t2 within one horizontal scanning period, and decreases the bias current flowing through the second current source 34 after time t2. In the photodetector 1 according to the third embodiment, since multiple column signal processing units 32 are not connected to the bias line L11, the bias circuit 8 variably controls the current flowing through the second current source 34, thereby enabling the voltage level of the bias line L11 to be rapidly changed. When the voltage level of the bias line L11 changes, the voltage level of the local bias line L12 also changes rapidly, enabling rapid variably control of the current flowing through each first current source 33 provided in each of the multiple column signal processing units 32.

[0081] FIG. 13 shows an example in which the voltage level of the bias line L11 is varied by variably controlling the bias current flowing through the bias circuit 8, but it is also possible to vary the voltage level of the bias line L11 by a method other than variable control of the bias current.

[0082] FIG. 15 is a circuit diagram showing a specific configuration of a buffer circuit 31 according to a first modification of the third embodiment. The photodetector 1 according to the first modification has a block configuration similar to that shown in FIG. 13. The buffer circuit 31 included in the photodetector 1 according to the first modification has a plurality of second transistors Q2. Each of the second transistors Q2 is, for example, a PMOS transistor. The gates of the second transistors Q2 are all connected to the bias line L11. Thus, the second transistors Q2 and the first transistor Q1 of the bias circuit 8 form a current mirror circuit. The sources of the second transistors Q2 are connected to a power supply voltage node, and the drains are connected to the local bias line L12 via corresponding switches 38.

[0083] The switches 38 connected to the drains of the second transistors Q2 can be individually turned on or off. In this specification, when a switch 38 is on, the drain of the corresponding second transistor Q2 is connected to the local bias line L12, and when a switch 38 is off, the connection between the drain of the corresponding second transistor Q2 and the local bias line L12 is cut off.

[0084] The voltage level of the local bias line L12 can be variably controlled in stages by individually controlling the on / off states of the multiple switches 38. More specifically, the more switches 38 that are in the on state, the higher the voltage level of the local bias line L12 can be.

[0085] In the photodetector 1 according to the first modification, the voltage level of the local bias line L12 is variably controlled by switching on or off a plurality of switches 38 while maintaining the bias current flowing through the bias circuit 8 and the voltage level of the bias line L11 constant. This allows the voltage level of the local bias line L12 to be variably controlled more quickly than changing the voltage level of the bias line L11 by variably controlling the bias current flowing through the buffer circuit 31.

[0086] FIG. 16 is a block diagram of a photodetector 1 according to a second modification of the third embodiment. The photodetector 1 according to the second modification includes a column signal processing circuit 5 having a different configuration from that of the first modification. The column signal processing circuit 5 according to the second modification includes a plurality of buffer circuits 31 connected to a bias line L11 and a plurality of column signal processing units 32 connected to the plurality of buffer circuits 31. Each of the plurality of buffer circuits 31 can individually switch whether or not to connect the output node of the corresponding buffer circuit 31 to the local bias line L12. For example, by providing a switch 39 (see FIG. 17A described later) between the output node of each buffer circuit 31 and the local bias line L12, it becomes possible to individually switch whether or not to connect the output node of the buffer circuit 31 to the local bias line L12.

[0087] 16 shows an example in which the output node of the buffer circuit 31 indicated by the solid line is connected to the local bias line L12, and the output node of the buffer circuit 31 indicated by the dashed line is disconnected from the local bias line L12. The more buffer circuits 31 whose output nodes are connected to the local bias line L12, the higher the voltage level of the local bias line L12 can be, and the same effect as the switching control of the multiple switches 38 according to the first modification can be obtained.

[0088] 17A is a diagram showing an example in which a switch 39 disposed between the output node of the buffer circuit 31 and the local bias line L12 is turned on, and FIG. 17B is a diagram showing an example in which the switch 39 disposed between the output node of the buffer circuit 31 and the local bias line L12 is turned off. When the switch 39 is turned on, the current flowing through the second transistor Q2 in the buffer circuit 31 flows to the local bias line L12 via the switch 39, and the voltage level of the local bias line L12 rises. On the other hand, when the switch 39 is turned off, no current flows from the second transistor Q2 to the local bias line L12, and the voltage of the local bias line L12 drops.

[0089] 17A and 17B show only one second transistor Q2 and one switch 39, but in reality there are multiple second transistors Q2 and multiple switches 39. The more switches 39 that are turned on, the more current flows from the second transistor Q2 to the local bias line L12, and the higher the voltage level of the local bias line L12 becomes.

[0090] In the first modified example shown in FIG. 15 , it was necessary to provide a plurality of second transistors Q2 and a plurality of switches 38 in the buffer circuit 31. However, in the second modified example, the number of second transistors Q2 and switches 39 provided in the buffer circuit 31 can be reduced compared to the first modified example, and the circuit scale of the column signal processing circuit 5 can be reduced.

[0091] As described above, in the third embodiment, the bias current flowing through the bias circuit 8 is variably controlled, or the voltage level of the local bias line L12 is variably controlled by switching control of the plurality of buffer circuits 31, so that it is possible to quickly switch the current flowing through the first current sources 33 of the plurality of column signal processing units 32. According to the third embodiment, it is possible to quickly switch the current flowing through the first current source 33 within one horizontal scanning period, thereby improving the image quality of the captured image.

[0092] Fourth Embodiment In a fourth embodiment, the current flowing through the first current source 33 is switched multiple times within one horizontal scanning period.

[0093] 18 is a block diagram showing a main part of a photodetector 1 according to the fourth embodiment, which shows pixels 10, load MOS circuits 4, and column signal processing circuits 5 connected to a vertical signal line VSL.

[0094] The load MOS circuit 4 has a transistor that constitutes a current source 20. By controlling the gate voltage of this transistor, the current flowing through the vertical signal line VSL can be drawn into the ground node via the transistor.

[0095] The column signal processing circuit 5 has a column signal processing section 32 for each vertical signal line VSL. The column signal processing section 32 has a comparator 41 and a ramp buffer 42. The ramp buffer 42 buffers and outputs a reference signal (ramp signal) generated by the DAC 7. The ramp buffer 42 has a PMOS transistor 43 and a current source 44.

[0096] The comparator 41 compares the pixel signal on the vertical signal line VSL with a reference signal output from the ramp buffer 42. A signal indicating the comparison result of the comparator 41 is input to a counter (not shown), which generates a digital signal corresponding to the pixel signal. The comparator 41 has a current source 45.

[0097] 19 is a timing chart showing changes in current flowing through the current source 20 of the load MOS circuit 4, the current source 45 of the comparator 41, and the current source 44 of the ramp buffer 42 within one horizontal scanning period. In the photodetector 1 according to the fourth embodiment, one horizontal scanning period is provided with a reset period T1, an auto-zero (AZ) period T2 of the comparator 41, a settling period T3 of the vertical signal line VSL, a reset level count period T4, a signal transfer period T5 from the photoelectric conversion element 11 to the floating diffusion FD, a settling period T6 of the vertical signal line VSL, and a signal level count period T7.

[0098] The current flowing through the current source 20 of the load MOS circuit 4 increases from the reset period T1 to partway through the settling period T3 and from the signal transfer period T5 to partway through the settling period T6, and decreases otherwise.

[0099] The current flowing through the current source 45 of the comparator 41 increases from the middle of the settling period T3 to the count period T4 of the reset level and from the middle of the settling period T6 to the count period T7 of the signal level, but decreases otherwise.

[0100] The current flowing through the current source 44 of the ramp buffer 42 increases during the count period T4 of the reset level and from midway through the settling period T6 to the count period T7 of the signal level, and decreases otherwise.

[0101] In this way, the periods in which the current increases and decreases within one horizontal scanning period differ depending on the type of current source, so it is desirable to finely control the current flowing through each individual current source.

[0102] The first current source 33 described in the first to third embodiments is at least one of the current source 20 in the load MOS circuit 4, the current source 45 of the comparator 41, and the current source 44 of the ramp buffer 42 in Fig. 18. By controlling the bias current flowing through the bias circuit 8 described in the first to third embodiments or by controlling the switching of the buffer circuit 31, the current flowing from the local bias line L12 to the first current source 33 can be quickly and variably controlled based on the timing in Fig. 19.

[0103] More specifically, since the timing at which the current increases or decreases differs for each of the current source 20 in the load MOS circuit 4, the current source 45 of the comparator 41, and the current source 44 of the ramp buffer 42 in FIG. 18, the bias circuit 8 and the buffer circuit 31 described in the first to third embodiments may be provided for each current source, and the current flowing through each current source may be controlled within one horizontal scanning period.

[0104] As described above, in the fourth embodiment, the current sources connected directly or indirectly to the vertical signal line VSL have different periods during one horizontal scanning period in which the current should be increased and the current should be decreased, and therefore, by switching and controlling the bias circuit 8 or the buffer circuit 31 described in the first to third embodiments, it is possible to quickly switch the current flowing through each current source during one horizontal scanning period. This makes it possible to increase the frame rate of the photodetector 1 and also to reduce power consumption by eliminating the need to flow unnecessary current through the bias line L11.

[0105] Fifth Embodiment As described in the fourth embodiment, each vertical signal line VSL is connected to a plurality of current sources whose currents need to be switched and controlled. For example, when a plurality of circuits, each having a current source, are connected to a single vertical signal line VSL, individually controlling the currents flowing through the current sources of the plurality of circuits requires providing a bias circuit 8 and a buffer circuit 31 for each current source, which increases the circuit size. The photodetector 1 according to the fifth embodiment controls a plurality of current sources connected to a single vertical signal line VSL without increasing the circuit size.

[0106] 20 is a block diagram of a photodetector 1 according to a fifth embodiment. A plurality of column processing sections 46 are connected to each vertical signal line VSL, and each column processing section 46 is provided with a current source (first current source). The photodetector 1 according to the fifth embodiment has a bias line L11 and a local bias line L12 arranged in a direction intersecting the plurality of vertical signal lines VSL. A control line L13 extends from the local bias line L12 substantially parallel to each vertical signal line VSL. This control line L13 is connected to, for example, the gate of a transistor constituting the current source of each column processing section 46.

[0107] This makes it possible to synchronously control the currents flowing through the multiple current sources of the multiple column processing sections 46 via the corresponding control lines L13 for each vertical signal line VSL.

[0108] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0109] FIG. 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0110] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 21 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0111] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0112] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0113] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0114] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0115] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0116] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0117] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0118] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0119] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 21, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0120] FIG. 22 is a diagram showing an example of the installation position of the imaging unit 12031.

[0121] In FIG. 22, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0122] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0123] 22 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0124] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0125] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0126] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0127] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0128] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 among the components described above. Specifically, the light detection device 1 according to each embodiment can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0129] The present technology can be configured as follows:

[0130] (1) A photodetector comprising: a plurality of pixels each having a photoelectric conversion element; a plurality of signal lines transmitting a plurality of pixel signals photoelectrically converted by the plurality of pixels; a plurality of first current sources provided corresponding to the plurality of signal lines; a bias circuit that generates a bias current; a first wiring set to a voltage level according to the bias current; a second wiring connected to the plurality of first current sources; and one or more buffer circuits connected to the first wiring and the second wiring and setting the voltage level of the second wiring according to the voltage level of the first wiring. (2) The photodetector according to (1), wherein one first current source is provided for one buffer circuit, or two or more first current sources are provided for one buffer circuit. (3) The photodetector according to (1) or (2), wherein two or more buffer circuits are connected to a common second wiring. (4) The photodetector according to any one of (1) to (3), wherein the bias circuit includes a first transistor and a second current source that generates a current flowing through the first transistor, and the buffer circuit includes a second transistor that forms a current mirror circuit with the first transistor, and a third current source that generates a current flowing through the second transistor. (5) The photodetector according to (4), wherein the third current source includes a third transistor that flows, between its drain and source, a current that is the same as the current flowing between the drain and source of the second transistor, and each of the plurality of first current sources includes a fourth transistor that forms a current mirror circuit with the third transistor. (6) The photodetector according to (4) or (5), wherein the second current source is a constant current source that flows a constant current, and the bias current is constant. (7) The photodetector according to (4) or (5), wherein the one or more buffer circuits dynamically switch the current flowing through the plurality of first current sources. (8) The photodetector according to (7), wherein the bias circuit has a variable current source that generates the variably controllable bias current.(9) The photodetector according to (7), wherein the buffer circuit includes a plurality of the second transistors forming a current mirror circuit with the first transistor, and a plurality of switches that switch whether or not a current flows between the drain and source of each of the plurality of second transistors, and the third current source flows a current corresponding to the number of second transistors that flow a current between the drain and source of the plurality of second transistors. (10) The photodetector according to (9), wherein the third current source flows a larger current as the number of second transistors that flow a current between the drain and source of the plurality of second transistors increases. (11) The photodetector according to (7), wherein two or more buffer circuits are provided, and each of the two or more buffer circuits has a switch that switches whether or not a current flows between the drain and source of the second transistor. (12) The photodetector according to any one of (1) to (11), wherein the first wiring is controlled to a voltage level according to variable control of the bias current by the bias circuit or variable control of the current flowing through the first wiring by the buffer circuit, and the one or more buffer circuits control the second wiring to a voltage level according to the voltage level of the first wiring. (13) The photodetector according to any one of (1) to (12), wherein each of the plurality of first current sources is connected to a corresponding one of the plurality of signal lines. (14) The photodetector according to any one of (1) to (12), further comprising: a plurality of analog-to-digital converters that convert the plurality of pixel signals transmitted through the plurality of signal lines into digital signals, each of the plurality of analog-to-digital converters having a comparator that compares the pixel signal with a reference signal, and the comparator having the first current source. (15) The photodetector according to any one of (1) to (12), further comprising: a plurality of analog-to-digital converters that convert the plurality of pixel signals transmitted through the plurality of signal lines into digital signals, The photodetector according to (14), further comprising: a ramp buffer that buffers the reference signal and inputs the buffered reference signal to the comparator; and the ramp buffer includes the first current source.(16) The photodetector according to any one of (1) to (12), comprising: a pixel array unit having the plurality of pixels arranged in a first direction and a second direction; and a drive unit configured to sequentially drive the plurality of pixel groups arranged in the second direction, with each pixel group including two or more of the pixels arranged in the first direction as a unit, wherein the one or more buffer circuits dynamically switch currents flowing to the plurality of first current sources within a period in which each of the plurality of pixel groups arranged in the second direction is driven. (17) The photodetector according to (16), wherein, when the plurality of first current sources are connected to the plurality of signal lines, the currents flowing to the plurality of first current sources are made larger when the plurality of pixels are reset and when accumulated charge in the photoelectric conversion element is transferred to a floating diffusion within the period than when other times. (18) The photodetector according to (16), further comprising a plurality of analog-to-digital converters that convert the pixel signals transmitted through the signal lines into digital signals, each of the analog-to-digital converters comprising: a comparator that compares a reference signal with the pixel signal; a counter that performs a counting operation until the reference signal matches the pixel signal based on a comparison result of the comparator; and a ramp buffer that buffers the reference signal and inputs it to the comparator, wherein if the comparator has the first current source, a current flowing in the corresponding first current source is increased while the counter is performing the counting operation within the period. (19) The photodetector according to (18), further comprising: a ramp buffer that buffers the reference signal and inputs it to the comparator, wherein if the ramp buffer has the first current source, a current flowing in the corresponding first current source is increased while the counter is performing the counting operation within the period. (20) The photodetector device according to any one of (1) to (19), wherein the buffer circuit includes: a signal holding unit that holds an electric charge according to the voltage level of the first wiring; and a switch that switches whether or not the electric charge is held in the signal holding unit.

[0131] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0132] 1 Photodetector device, 2 Pixel array section, 3 Vertical scanning circuit, 4 Load MOS circuit, 5 Column signal processing circuit, 6 Timing control circuit, 7 Digital-to-analog converter (DAC), 8 Bias circuit, 10 Pixel, 11 Photoelectric conversion element, 12 Transfer transistor, 13 Reset transistor, 14 Amplification transistor, 15 Selection transistor, 16 First substrate, 17 Second substrate, 18 Third substrate, 20 Current source, 21 Analog-to-digital converter (hereinafter, ADC), 22 Digital signal processing section, 31 Buffer circuit, 32 Column signal processing section, 33 First current source, 34 Second current source, 35 Third current source, 36 Capacitor, 37 Switch, 38 Switch, 39 Switch, 41 Comparator, 42 Ramp buffer, 43 Transistor, 44 Current source, 45 Current source, 46 Column processing section

Claims

1. A photodetection device comprising: a plurality of pixels each having a photoelectric conversion element; a plurality of signal lines transmitting a plurality of pixel signals photoelectrically converted by the plurality of pixels; a plurality of first current sources corresponding to the plurality of signal lines; a bias circuit generating a bias current; a first wiring set to a voltage level corresponding to the bias current; a second wiring connected to the plurality of first current sources; and one or more buffer circuits connected to the first wiring and the second wiring and setting the voltage level of the second wiring according to the voltage level of the first wiring.

2. The photodetection device according to claim 1, wherein one first current source is provided for one buffer circuit, or two or more first current sources are provided for one buffer circuit.

3. The photodetector according to claim 1, wherein two or more of said buffer circuits are connected to a common second wiring.

4. The photodetector device of claim 1, wherein the bias circuit comprises: a first transistor; and a second current source that generates a current flowing through the first transistor; and the buffer circuit comprises: a second transistor that forms a current mirror circuit with the first transistor; and a third current source that generates a current flowing through the second transistor.

5. The photodetector device according to claim 4, wherein the third current source has a third transistor that flows, between its drain and source, a current that is the same as the current that flows between the drain and source of the second transistor, and each of the plurality of first current sources has a fourth transistor that forms a current mirror circuit with the third transistor.

6. The photodetector according to claim 4, wherein the second current source is a constant current source that supplies a constant current, and the bias current is constant.

7. The photodetection device according to claim 4, wherein the one or more buffer circuits dynamically switch currents flowing through the plurality of first current sources.

8. The photodetector device according to claim 7, wherein the bias circuit includes a variable current source that generates the variably controllable bias current.

9. The photodetector according to claim 7, wherein the buffer circuit comprises: a plurality of second transistors forming a current mirror circuit with the first transistor; and a plurality of switches for switching whether or not a current flows between the drain and source of each of the plurality of second transistors; and the third current source flows a current according to the number of second transistors among the plurality of second transistors that pass a current between their drains and sources.

10. The photodetector device according to claim 9, wherein the third current source passes a larger current as the number of second transistors passing a current between their drains and sources among the plurality of second transistors increases.

11. The photodetection device according to claim 7, wherein two or more of the buffer circuits are provided, and each of the two or more buffer circuits has a switch that switches whether or not a current flows between the drain and source of the second transistor.

12. The photodetector device of claim 1, wherein the first wiring is controlled to a voltage level according to variable control of the bias current by the bias circuit or variable control of the current flowing through the first wiring by the buffer circuit, and the one or more buffer circuits control the second wiring to a voltage level according to the voltage level of the first wiring.

13. The photodetector according to claim 1, wherein each of the plurality of first current sources is connected to a corresponding one of the plurality of signal lines.

14. The photodetection device according to claim 1, further comprising: a plurality of analog-to-digital converters for converting the plurality of pixel signals transmitted through the plurality of signal lines into digital signals, each of the plurality of analog-to-digital converters having a comparator for comparing the pixel signal with a reference signal, the comparator having the first current source.

15. The photodetection device according to claim 14, further comprising: a plurality of analog-to-digital converters that convert the plurality of pixel signals transmitted through the plurality of signal lines into digital signals; and a ramp buffer that buffers the reference signal and inputs it to the comparator, the ramp buffer having the first current source.

16. The photodetection device according to claim 1, comprising: a pixel array section having the plurality of pixels arranged in a first direction and a second direction; and a drive section which sequentially drives the plurality of pixel groups arranged in the second direction, with each pixel group including two or more of the pixels arranged in the first direction as a unit; wherein the one or more buffer circuits dynamically switch the currents flowing through the plurality of first current sources during a period in which each of the plurality of pixel groups arranged in the second direction is driven.

17. The photodetection device according to claim 16, wherein, when the plurality of first current sources are connected to the plurality of signal lines, a current flowing through the plurality of first current sources is made larger when the plurality of pixels are reset within the period and when the accumulated charge of the photoelectric conversion element is transferred to a floating diffusion than in other cases.

18. The photodetection device according to claim 16, further comprising a plurality of analog-to-digital converters for converting the plurality of pixel signals transmitted through the plurality of signal lines into digital signals, each of the plurality of analog-to-digital converters having: a comparator for comparing a reference signal with the pixel signal; a counter for performing a counting operation until the reference signal matches the pixel signal based on a comparison result of the comparator; and a ramp buffer for buffering the reference signal and inputting it to the comparator, and when the comparator has the first current source, a larger current is caused to flow through the corresponding first current source while the counter is performing a counting operation within the period.

19. The photodetection device according to claim 18, further comprising: a ramp buffer which buffers the reference signal and inputs it to the comparator; and if the ramp buffer has the first current source, a current flowing through the corresponding first current source is increased while the counter is performing a counting operation within the period.

20. The photodetector according to claim 1, wherein the buffer circuit comprises: a signal holding section that holds an electric charge according to a voltage level of the first wiring; and a switch that switches whether or not the electric charge is held in the signal holding section.

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