Semiconductor device, system, and method for manufacturing semiconductor device

Abstract

The present invention achieves a normally-off operation in an FET having a diamond layer including a hydrogen termination region. In an embodiment in which it is assumed that a channel formation region 105 is composed of a first region P1 and a second region P2, in a state where a gate voltage of "0V" is applied to a gate electrode 111, the hole concentration of the first region P1 is smaller than the hole concentration of the second region P2.

Description

Semiconductor device, system, and method for manufacturing semiconductor device

[0001] The present invention relates to a semiconductor device, a system, and a manufacturing technique for a semiconductor device, and relates to a technique that is effective when applied to a semiconductor device including, for example, a field effect transistor that uses diamond as a semiconductor material.

[0002] Japanese Patent Application Laid-Open No. 2018-6572 (Patent Document 1) describes a technology relating to a diamond semiconductor device including a field effect transistor with normally-off operating characteristics.

[0003] Japanese Patent Application Laid-Open No. 2017-50485 (Patent Document 2) describes a technique relating to manufacturing conditions for obtaining a hydrogen-terminated diamond FET that operates normally off.

[0004] Japanese Patent Laid-Open Publication No. 2022-104826 (Patent Document 3) describes a technology relating to a field effect transistor that has high radiation resistance and can also ensure circuit characteristics.

[0005] Japanese Patent Laid-Open No. 2020-161587 (Patent Document 4) describes a technology related to a semiconductor device including a field effect transistor that has high carrier mobility, excellent switching characteristics, and is capable of normally-off operation with low gate leakage current.

[0006] JP 2018-6572 A JP 2017-50485 A JP 2022-104826 A JP 2020-161587 A

[0007] For example, field effect transistors (hereinafter sometimes referred to as FETs) using wide bandgap semiconductor materials, which have a bandgap larger than that of silicon, have superior characteristics to FETs using silicon, and for this reason, FETs using wide bandgap semiconductor materials are expected to be the next generation of FETs.

[0008] In this regard, diamond is a wide bandgap semiconductor material with a bandgap of 5.5 eV and has excellent properties such as a high breakdown voltage, high thermal conductivity, and high mobility. For these reasons, diamond is expected to be the next-generation wide bandgap semiconductor material following silicon carbide (SiC) and gallium nitride (GaN).

[0009] However, FETs using diamond have hurdles to overcome in order to improve their performance, and improvements are needed to put them to practical use. For example, it is difficult to achieve normally-off operation in FETs using diamond, and improvements are needed to obtain FETs at a practical level that achieve normally-off operation.

[0010] The term "normally off" refers to an FET being in an off state when a gate voltage of 0 V is applied to the gate electrode. Specifically, an FET configured such that no channel is formed in the channel formation region immediately below the gate electrode when a gate voltage of 0 V is applied to the gate electrode is called a "normally off FET." On the other hand, an FET configured such that a channel is formed in the channel formation region immediately below the gate electrode even when a gate voltage of 0 V is applied to the gate electrode is called a "normally on FET." In this specification, the application of a gate voltage of 0 V to the gate electrode may be referred to as "no gate voltage being applied to the gate electrode." In this case, "normally off" can also be expressed as an FET being in an off state when no gate voltage is applied to the gate electrode.

[0011] The semiconductor device in one embodiment is a semiconductor device including a field effect transistor, and the field effect transistor has a diamond layer including a hydrogen termination region, a channel formation region formed in the diamond layer, an insulating film formed on an upper surface of the diamond layer, and a gate electrode formed on the insulating film.

[0012] The channel formation region includes a first region overlapping the gate electrode in a plan view and a second region not overlapping the gate electrode in a plan view, and when the field-effect transistor is in an off state, the hole concentration in the first region is lower than the hole concentration in the second region.

[0013] The semiconductor device in one embodiment is a semiconductor device including a field effect transistor, and the field effect transistor has a diamond layer including a hydrogen termination region, a channel formation region formed in the diamond layer, an insulating film formed on an upper surface of the diamond layer, and a gate electrode formed on the insulating film.

[0014] Here, the insulating film includes a first insulating region that overlaps with the gate electrode in a plan view and a second insulating region that does not overlap with the gate electrode in a plan view, and the amount of negative charge in the second insulating region is greater than the amount of negative charge in the first insulating region, or the amount of positive charge in the first insulating region is greater than the amount of positive charge in the second insulating region.

[0015] The semiconductor device in one embodiment is a semiconductor device including a field effect transistor, and the field effect transistor has a diamond layer including a hydrogen termination region, a channel formation region formed in the diamond layer, an insulating film formed on an upper surface of the diamond layer, and a gate electrode formed on the insulating film.

[0016] Here, in the off state of the field effect transistor, the hole concentration in the channel formation region is 10 １２ / cm ２ The following is the result.

[0017] In one embodiment, a method for manufacturing a semiconductor device includes a field effect transistor, and includes the steps of: (a) forming a diamond layer including a hydrogen-terminated region; and (b) reducing the hole concentration in the hydrogen-terminated region.

[0018] According to one embodiment, a normally-off operation can be achieved in a FET having a diamond layer including a hydrogen-terminated region.

[0019] FIG. 1 is a diagram for explaining a surface conduction FET in an embodied mode. FIG. 2 is a diagram showing a manufacturing process of a semiconductor device in an embodied mode. FIG. 3 is a diagram showing a manufacturing process of a semiconductor device following FIG. 4. FIG. 5 is a diagram showing a manufacturing process of a semiconductor device following FIG. 6. FIG. 7 is a diagram showing a manufacturing process of a semiconductor device following FIG. 7. FIG. 8 is a graph showing the drain current-gate voltage characteristics of a surface conduction FET manufactured without performing a hole concentration adjustment process. FIG. 9 is a graph showing the drain current-gate voltage characteristics of a surface conduction FET manufactured by performing a hole concentration adjustment process. FIG. 10 is a diagram schematically showing a surface conduction FET having an "overlap structure" in Modification 1.

[0020] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0021] <Usefulness of diamond as a semiconductor material> For example, in the fields of future mobile communications, satellite communications or ultra-small radar, FETs capable of high-power and high-frequency transmission are required.In this regard, semiconductor materials such as silicon (Si) and gallium arsenide (GaAs) reach their power density limits at frequencies above several GHz.For this reason, wide bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN) and diamond are being considered for use in FETs.In particular, diamond has the highest thermal conductivity of all materials (four times that of SiC, 16 times that of GaN) and the highest breakdown field strength of all semiconductor materials (three times that of SiC, 10 times that of GaN).In addition, the hole mobility and hole saturation velocity in diamond are equivalent to the electron mobility and electron saturation velocity in silicon.

[0022] This shows that diamond's high thermal conductivity provides excellent heat dissipation properties, making it possible to suppress heat generation in semiconductor devices and enabling high-temperature operation of the semiconductor device. Furthermore, diamond's high breakdown field strength makes it less likely for the semiconductor device to be destroyed even when high voltages are applied, making it suitable for semiconductor devices used in high-power applications. Furthermore, diamond's high carrier mobility suggests that diamond has great potential as a semiconductor device for high-frequency applications.

[0023] From the above, it can be seen that diamond as a semiconductor material is considered promising for realizing next-generation semiconductor devices, including FETs capable of high-power and high-frequency operation.

[0024] <The difficulty of producing n-type diamond> As mentioned above, diamond is a wide band gap semiconductor material, and it is considered that by introducing the n-type impurity called donor into diamond, n-type diamond can be produced.Specifically, it is considered that by supplying electrons from the donor level of donor to the conduction band of diamond, n-type diamond can be realized.

[0025] Here, nitrogen can be mentioned as donor, but in diamond, the donor level of nitrogen is not near conduction band, but exists in the "deep level" away from conduction band.Specifically, the donor level of nitrogen exists at the energy position that is 1.7 eV lower than the conduction band of diamond.This means that in diamond, the activation energy that makes electrons excite from the donor level of nitrogen to the conduction band of diamond becomes large.

[0026] For this reason, even if nitrogen, which is a donor, is introduced into diamond, it is difficult to increase the number of electrons supplied to the conduction band, and as a result, it is difficult to make the diamond into which nitrogen has been introduced function as an n-type diamond.

[0027] On the other hand, it is thought that p-type diamond can be produced by introducing p-type impurities called acceptors into diamond.Specifically, it is thought that by exciting electrons from the valence band of diamond to the acceptor level of acceptor, holes are generated in the valence band of diamond, and p-type diamond can be realized.

[0028] Here, boron can be mentioned as an acceptor, and the acceptor level of this boron exists near the valence band of diamond.Specifically, boron as an acceptor forms an acceptor level at the energy position that is 0.37 eV higher than the valence band of diamond.In other words, in diamond, the acceptor level of boron does not constitute a "deep level" like the donor level of nitrogen.Therefore, the activation energy for exciting electrons from the valence band of diamond to the acceptor level of boron is not so large.As a result, it is easier to make p-type diamond in diamond than to make n-type diamond.

[0029] Therefore, as the FET that uses diamond to manufacture, it is not the n-channel FET that generally requires n-type diamond, but the p-channel FET that uses p-type diamond, which is easier to manufacture than n-type diamond.In other words, the FET that uses diamond to manufacture is realized as the FET that uses holes as carriers, not the FET that uses electrons as carriers.In particular, as the FET that uses diamond to manufacture, there is a p-channel FET that is called "surface conduction FET".The following will explain this "surface conduction FET".

[0030] <Surface-conduction FET> When diamond is hydrogen-terminated, there is a phenomenon in which holes (two-dimensional hole gas) are induced on the surface of the hydrogen-terminated diamond. An FET that utilizes this phenomenon is called a "surface-conduction FET." In other words, a "surface-conduction FET" is an FET that uses the two-dimensional hole gas induced on the surface of the hydrogen-terminated diamond as the FET channel, and performs switching operations by controlling the conduction / non-conduction of the channel by changing the gate voltage applied to the gate electrode. This "surface-conduction FET" has the advantage of being able to operate at high temperatures with high voltage resistance. This is because hydrogen-terminating diamond forms a "C-H" bond, and the "C-H" bond is stronger than the "C-C" bond of diamond.

[0031] The mechanism by which holes are induced on the surface of hydrogen-terminated diamond has not been fully elucidated, but two theories are considered to be the most likely.

[0032] First, one theory is the "transfer doping model." This theory states that electrons in the valence band of diamond move to a level determined by the chemical potential of the surface due to differences in chemical potential caused by adsorbates or changes in the pH of the surface, and holes are generated near the surface from which these electrons are removed.

[0033] On the other hand, there is another theory, the "negative ion model." This theory is as follows: In other words, in the "C-H" bond created by hydrogen-terminating diamond, hydrogen becomes positively charged while carbon becomes negatively charged due to the difference in electronegativity. As a result, negative ions in the atmosphere are adsorbed onto the positively charged hydrogen, and these adsorbed negative ions attract holes to the surface of the diamond.

[0034] Although the mechanism is not fully understood, holes are actually induced on the surface of hydrogen-terminated diamond. This phenomenon has been utilized to create a superior FET called a "surface conduction FET," which is capable of high-temperature operation with high breakdown voltage.

[0035] However, in a "surface conduction FET", a two-dimensional hole gas is induced in the hydrogen-terminated region of the diamond layer even when no gate voltage is applied to the gate electrode. This means that in a "surface conduction FET", a channel made of two-dimensional hole gas is formed in the hydrogen-terminated region even when no gate voltage is applied to the gate electrode. In other words, in a "surface conduction FET", a channel made of two-dimensional hole gas is formed in the hydrogen-terminated region even when a gate voltage of 0 V is applied to the gate electrode. Therefore, unless some ingenuity is applied, a "surface conduction FET" will inevitably tend to become a "normally-on FET". In other words, the mainstream of "surface conduction FETs" is the "normally-on FET".

[0036] <Usefulness of "Normally-Off FET"> In this regard, when comparing a "normally-on FET" with a "normally-off FET," the "normally-off FET" is more desirable from the standpoints of safety and power consumption. This is because the "normally-off FET" (1) does not conduct electricity in the event of a system failure, such as when a gate voltage is no longer supplied to the gate electrode, thereby preventing FET runaway due to current conduction. In other words, the "normally-off FET" has the advantage of being excellent in fail-safe and having high safety. The "normally-off FET" also has the advantage of (2) being able to reduce dark current during high-temperature operation and to prevent malfunctions caused by noise. Furthermore, (3) being able to reduce power consumption because it does not conduct electricity when no gate voltage is supplied to the gate electrode (i.e., when 0 V is applied to the gate electrode). As such, the advantages (1) to (3) above make the "normally-off FET" superior to the "normally-on FET" from the standpoints of system safety and reduced power consumption.

[0037] For example, "normally-off FETs" are the most important type of power device. Specifically, power devices are widely used in transportation equipment that uses large amounts of power, such as automobiles, railway vehicles, and airplanes. For this reason, safety is of the utmost importance, and "normally-off FETs," which output "0" when broken, are the minimum requirement for power devices.

[0038] Furthermore, from the viewpoint of reducing standby power consumption, a "normally off FET" that allows almost no leakage current to flow in the off state is also effective.

[0039] Therefore, in order to use a "surface-conduction FET" in a system, it is important to realize a "normally-off FET" in the "surface-conduction FET." In other words, a "normally-off FET" is essential to building a system that is both safe and high-performance, and some ingenuity is required to realize a "normally-off FET" in a "surface-conduction FET," where "normally-on FETs" are the mainstream.

[0040] Therefore, the present inventors have devised a way to turn a "surface conduction FET" into a "normally-off FET" by utilizing the following findings.

[0041] <Knowledge Used by the Inventors> Hereinafter, knowledge used by the inventors will be described.

[0042] For example, it is known that when a vacuum is drawn while applying a constant voltage to the surface of a hydrogen-terminated diamond layer, the current value decreases, while when exposed to the atmosphere, the current value recovers to almost its original value. This can be understood as meaning that when a vacuum is drawn, the two-dimensional hole gas induced in the hydrogen-terminated diamond layer disappears, while when exposed to the atmosphere, two-dimensional hole gas is generated. Therefore, the above-mentioned phenomenon suggests that molecules contained in the atmosphere are necessary to induce two-dimensional hole gas in a hydrogen-terminated diamond layer. In other words, it is thought that conductivity does not occur simply by hydrogen-terminating the diamond layer, but that conductivity occurs only when surface adsorbates consisting of negative ions adhere to the hydrogen-terminated diamond layer. Based on this finding, the present inventor has devised a way to turn a "surface conduction FET" into a "normally-off FET." The technical concept of this embodiment, which incorporates this devise, will be explained below.

[0043] <Basic idea of ​​the embodiment> The basic idea of ​​the present embodiment is to realize a "surface conduction FET" as a "normally-off FET" based on the above-mentioned findings, by controlling the amount of surface adsorbates adhering to the surface of the hydrogen-terminated diamond layer, it is possible to control the conductivity of the hydrogen-terminated diamond layer. More specifically, the basic idea is to eliminate the conductivity of the channel formation region by desorbing the surface adsorbates in the channel formation region formed in the hydrogen-terminated diamond layer. In other words, the basic idea is to reduce the hole concentration in the channel formation region by desorbing the surface adsorbates in the channel formation region formed in the hydrogen-terminated diamond layer.

[0044] According to this basic concept, in the off state where no gate voltage is applied to the gate electrode, the hole concentration in the channel formation region can be reduced to a level where the device is not conductive. On the other hand, when a negative gate voltage is applied to the gate electrode, a two-dimensional hole gas is induced in the channel formation region located directly below the gate electrode, as if attracted by this negative potential. As a result, in the on state where a negative gate voltage is applied to the gate electrode, the hole concentration in the channel formation region can be increased to a level where the device is conductive. In this way, according to the basic concept, a "surface conduction FET" can be realized as a "normally off FET."

[0045] The following describes embodiments that embody the basic concept described above. Note that the embodiments are merely examples of the basic concept, and it goes without saying that the technical concept of this embodiment is not limited to the embodiments described below.

[0046] <Embodiments> <<Configuration of Surface-Conduction FET>> FIG. 1 is a diagram illustrating a surface-conduction FET 100 in an embodiment.

[0047] 1, a surface conduction FET 100 has a diamond substrate 101 into which nitrogen is introduced, and an undoped layer 102 is provided on the diamond substrate 101. For example, the top surface of the undoped layer 102 is a (001) plane.

[0048] Here, a diamond substrate 101 into which nitrogen has been introduced is used, but this is not limited to this, and for example, the surface conduction FET 100 may be fabricated on a free-standing film consisting of a non-doped layer 102.

[0049] The non-doped layer 102 may be configured to have an off-angle of several degrees (for example, 3 degrees) in the <110> direction with respect to the (001) plane.

[0050] Here, the non-doped layer 102 referred to in this specification is a diamond layer in which the nitrogen impurity concentration is 10%, which is the lower limit of detection by a measuring device using SIMS (Secondary Ion Mass Spectrometry). １６ / cm３ Diamond layer having a thickness of less than 100 nm.

[0051] A hydrogen termination region 103 and an oxygen termination region 104 are formed on the surface of the non-doped layer 102. As a result, a channel formation region 105 having a two-dimensional hole gas is formed in the hydrogen termination region 103 of the non-doped layer 102.

[0052] 1, the channel formation region 105 has a first region P1 that overlaps with the gate electrode 111 and a second region P2 that does not overlap with the gate electrode 111. More specifically, the channel formation region 105 includes the first region P1 that overlaps with the gate electrode 111 in a planar view and the second region P2 that does not overlap with the gate electrode 111 in a planar view. In other words, the first region P1 is a region located directly below the gate electrode 111, and the second region P2 is a region that is arranged so as to sandwich the first region P1.

[0053] At this time, when a gate voltage of 0 V is applied to the gate electrode of the surface conduction FET 100, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2. Specifically, when a gate voltage of 0 V is applied to the gate electrode of the surface conduction FET 100, the hole concentration in the first region P1 is 10 １２ / cm ２ It is preferably 10 or less. １１ / cm ２ On the other hand, the hole concentration in the second region P2 is 10 １３ / cm ２ It is more than enough.

[0054] Next, a contact layer 106 and a contact layer 107 are provided on the non-doped layer 102. Each of the contact layers 106 and 107 is a p-type layer in which, for example, boron, which is a p-type impurity (acceptor), is introduced at a high concentration. ＋ Specifically, a high concentration of boron is introduced into each of the contact layers 106 and 107 so as to form an ohmic contact with the non-doped layer 102. Specifically, the concentration of boron is, for example, 5×10 １９ / cm ３That's it, 1 x 10 ２２ / cm ３ The thickness of each of the contact layer 106 and the contact layer 107 is, for example, about 20 nm to 300 nm.

[0055] It should be noted that the contact layers 106 and 107 do not necessarily need to be provided, and for example, a source electrode and a drain electrode made of gold electrodes or the like may be formed directly on the hydrogen-terminated non-doped layer 102 to establish ohmic contact.

[0056] A source electrode 108 is provided on the contact layer 106. Meanwhile, a drain electrode 109 is provided on the contact layer 107. Subsequently, an insulating film 110 is provided on the non-doped layer 102 between the contact layer 106 and the contact layer 107, and a gate electrode 111 is provided on this insulating film 110.

[0057] 1 , the insulating film 110 has a first insulating region R1 that overlaps with the gate electrode 111 and a second region R2 that does not overlap with the gate electrode 111. More specifically, the insulating film 110 includes the first insulating region R1 that overlaps with the gate electrode 111 in a planar view and the second insulating region R2 that does not overlap with the gate electrode 111 in a planar view. In other words, the first insulating region R1 is a region that contacts the gate electrode 111, and the second insulating region R2 is a region that does not contact the gate electrode 111. At this time, the insulating film 110 is negatively charged, and the amount of negative charge in the second insulating region R2 is greater than the amount of negative charge in the first insulating region R1.

[0058] The source electrode 108, the drain electrode 109, and the gate electrode 111 are each made of, for example, gold (Au), ruthenium (Ru), aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), chromium (Cr), lead (Pb), zinc (Zn), platinum (Pt), or a combination thereof (e.g., Ti / Mo / Au). The source electrode 108, the drain electrode 109, and the gate electrode 111 each have a thickness of, for example, about 10 nm or more and 500 nm or less.

[0059] On the other hand, the insulating film 110 is, for example, an aluminum oxide film (Al ２ O ３ ), silicon oxide film (SiO ２ ), calcium fluoride film (CaF ２ ), hafnium oxide film (HfO ２ ), aluminum nitride film (AlN), boron nitride film (BN), silicon nitride film (Si ３ N ４ ), silicon oxynitride film (SiON), tantalum oxide film (Ta ２ O ５ ), titanium oxide film (TiO ２ ), tungsten oxide film (WO ３ ), lanthanum fluoride film (LaF ３ ), or magnesium fluoride film (MgF ２ ) The thickness of the gate insulating film 110 is, for example, about 5 nm to 1000 nm. When manufacturing a fine surface conduction FET 100, it is desirable that the thickness of the gate insulating film 110 be 100 nm or less.

[0060] 1, the gate electrode 111 does not overlap with the contact layer 106, and the gate electrode 111 does not overlap with the contact layer 107. Furthermore, in a plan view, the gate electrode 111 does not overlap with the contact layer 106, and the gate electrode 111 does not overlap with the contact layer 107.

[0061] The surface conduction FET 100 is configured as described above.

[0062] <<Operation of Surface Conduction FET>> Next, the operation of the surface conduction FET 100 will be described.

[0063] The surface conduction FET 100 is a p-channel FET, and has a channel formation region 105 having a two-dimensional hole gas formed near the surface of the non-doped layer 102. The channel formation region 105 has a first region P1 located directly below the gate electrode 111 and a second region P2 located outside both ends of the gate electrode 111.

[0064] In the surface conduction FET according to the embodiment, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2. For example, when 0 V is applied to the gate electrode 111, the hole concentration in the first region P1 is 10 １２ / cm ２ while the hole concentration in the second region P2 is 10 １３ / cm ２ 1, the amount of negative charge in the second insulating region R2 of the insulating film 110 is greater than the amount of negative charge in the first insulating region R1 of the insulating film 110, and as a result, the second region P2 in contact with the second insulating region R2 attracts more holes than the first region P2 in contact with the first insulating region R1.

[0065] As a result, when 0 V is applied to the gate electrode 111, the second region P2 is conductive, but the first region P1 is not conductive. In other words, a channel due to two-dimensional hole gas is formed in the second region P2, but a channel sufficient to provide conductivity is not formed in the first region P1. In other words, a channel is not formed throughout the entire channel formation region 105 including the first region P1 and the second region P2.

[0066] Therefore, when 0 V is applied to the gate electrode 111, the surface conduction FET 100 is turned off. That is, when 0 V is applied to the gate electrode 111, even if a potential difference is applied between the source electrode 108 and the drain electrode 109, no channel is formed in the first region P1 of the channel formation region 105, and therefore no hole current flows between the source electrode 108 and the drain electrode 109. Therefore, the surface conduction FET 100 in this embodiment is a "normally-off FET."

[0067] In contrast, when a negative potential equal to or greater than the threshold voltage is applied to the gate electrode 111, holes are attracted to the gate electrode 111 at the negative potential, resulting in an increase in the hole concentration in the first region P1 located directly below the gate electrode 111. As a result, a channel due to the two-dimensional electron gas is formed not only in the second region P2 but also in the first region P1. That is, a channel is formed throughout the entire channel formation region 105 including the first region P1 and the second region P2.

[0068] As a result, with a potential equal to or higher than the threshold voltage applied to the gate electrode 111, for example, a positive potential is applied to the source electrode 108, while a reference potential of 0 V is applied to the drain electrode 109. As a result, a hole current flows through the path of the source electrode 108 → the contact layer 106 → the second region P2 of the channel formation region 105 → the first region P1 of the channel formation region 105 → the second region P2 of the channel formation region 105 → the contact layer 107 → the drain electrode 109.

[0069] As described above, by controlling the gate voltage applied to the gate electrode 111, the switching operation (ON / OFF operation) of the surface conduction type FET 100 can be realized.

[0070] In particular, in the embodiment, the surface conduction FET 100 can be operated as a "normally-off FET."

[0071] <<Method for Manufacturing Surface-Conduction FET>> Next, a method for manufacturing a semiconductor device including a surface-conduction FET will be described.

[0072] First, as shown in Fig. 2, for example, an undoped layer 102 is formed on a nitrogen-containing diamond substrate 101. The undoped layer 102 is a diamond layer, and can be formed by using, for example, the MPCVD method. ４ / H ２ The thickness of the non-doped layer 102 is, for example, about several μm.

[0073] Here, it is desirable to grow the layer by CVD so that the top surface of the non-doped layer is the (001) plane. This is because, from the viewpoint of improving flatness, the (001) plane is excellent for growing high-quality films by CVD, and as a result, it is advantageous in that it is easy to manufacture semiconductor devices including high-performance surface-conduction FETs. Furthermore, from the viewpoint of forming high-quality films by CVD, it is desirable to provide an off-angle of several degrees. Specifically, in this embodiment, an off-angle of 3 degrees is provided in the <110> direction with respect to the (001) plane.

[0074] By providing an off-angle, the number of steps can be increased, which makes it easier for growth species flowing on the surface to reach the edge of the steps, promoting step-flow growth and suppressing the occurrence of abnormal growth.

[0075] 3, the contact layer 106 and the contact layer 107 are selectively grown on the non-doped layer 102. The contact layer 106 and the contact layer 107 are each formed of p ＋ The contact layers 106 and 107 are made of p-type diamond layers. The contact layers 106 and 107 can be formed by using, for example, the HFCVD method. At this time, boron is introduced as a p-type impurity. The impurity concentration of boron is, for example, 10 ２１ / cm ３ The thickness of each of the contact layers 106 and 107 is, for example, about 0.2 μm. Note that the hydrogen termination region 103A is formed in this process. Alternatively, hydrogen termination may be performed using hydrogen plasma generated in a separate CVD apparatus.

[0076] Next, as shown in Fig. 4, photolithography and hydrogen plasma treatment are used to selectively form hydrogen termination region 103 (conductive region), and photolithography and oxygen plasma treatment are used to selectively form oxygen termination region 104 (insulating region). Note that if hydrogen termination region 103A is formed in the step shown in Fig. 3, the step of forming hydrogen termination region 103 shown in Fig. 4 may be omitted.

[0077] Thereafter, when the diamond substrate 101 is exposed to the atmosphere, surface adsorbates 120 consisting of negative ions are adsorbed to the hydrogen-terminated region 103. As a result, holes that constitute a two-dimensional hole gas are induced throughout the channel formation region 105, as shown in FIG.

[0078] 5, a step of reducing the hole concentration of the holes (two-dimensional hole gas) induced in the hydrogen-terminated region 103 is performed. Specifically, this step is performed by desorbing surface adsorbates attached to the hydrogen-terminated region 103. This is because holes are induced when surface adsorbates adsorb to the hydrogen-terminated region 103, and therefore, it is believed that desorbing the surface adsorbates can reduce the hole concentration in the hydrogen-terminated region 103. In particular, the hole concentration is reduced in the channel-forming region, which is the hydrogen-terminated region 103.

[0079] The process of desorbing surface adsorbates attached to the hydrogen-terminated region 103 can be achieved by, for example, performing hydrogen plasma treatment in a vacuum. This makes the channel formation region non-conductive. The hydrogen plasma treatment is performed under conditions of 50 mTorr (1 Torr = 1.33 × 10 ２ For example, the conditions are: 1 Pa, ICP: 500 W, bias: 50 W, and time: 10 min. However, since the conditions can vary significantly depending on the device structure and the equipment used, it is necessary to determine the conditions for each measurement environment.

[0080] The hydrogen plasma treatment in a vacuum that is performed to desorb surface adsorbates is performed not only on the hydrogen-terminated region 103 but also on the oxygen-terminated region 104. In this regard, it has been confirmed that performing the above-described hydrogen plasma treatment in a vacuum on the oxygen-terminated region 104 does not deteriorate the insulating properties of the oxygen-terminated region 104 (the oxygen-terminated region 104 is maintained). In other words, it has been confirmed that the hydrogen plasma treatment in a vacuum can desorb surface adsorbates attached to the hydrogen-terminated region 103 while sufficiently reducing the side effect of degrading the insulating properties of the oxygen-terminated region 104.

[0081] 6, an insulating film 110 is formed to cover the hydrogen-terminated region 103 and the oxygen-terminated region 104. The insulating film 110 is made of, for example, an aluminum oxide film, and can be formed by using an ALD method at a film formation temperature of about 300°C.

[0082] Thereafter, photolithography and etching techniques are used to pattern the insulating film 110. The insulating film 110 is patterned by forming openings in the insulating film 110 and removing the hydrogen-terminated region 103 exposed from the openings to expose portions of the upper surfaces of the contact layers 106 and 107.

[0083] 7, a metal film is formed on the patterned insulating film 110. The metal film is made of, for example, a ruthenium film and can be formed by using a sputtering method. In this case, the thickness of the metal film is, for example, about 100 nm.

[0084] Then, the metal film is patterned using photolithography and etching techniques, thereby forming the source electrode 108, the drain electrode 109, and the gate electrode 111, each made of the metal film.

[0085] 8, a negative charging process is performed on the region (second insulating region R2) of the insulating film 110 exposed from the gate electrode 111. Specifically, an oxygen plasma process is performed on the insulating film 110. Here, the input power and the process time can be adjusted depending on the device used and the degree of charging process to be performed.

[0086] Such oxygen plasma treatment supplies excess oxygen to the aluminum oxide film constituting the insulating film 110 or changes the film quality, resulting in the second insulating region R2 of the insulating film 110 exposed to the oxygen plasma becoming negatively charged. On the other hand, the first insulating region R1 of the insulating film 110 overlapping the gate electrode 110 is not exposed to the oxygen plasma and is therefore not charged. As a result, the amount of negative charge in the second insulating region R2 becomes greater than the amount of negative charge in the first insulating region R1.

[0087] 8, the second region P2 of the channel formation region 105, which does not overlap with the gate electrode 111 in plan view, is in contact with the second insulating region R2, which has a large amount of negative charge. Holes are attracted to this negative charge, resulting in a high hole concentration. In contrast, the first region P1 of the channel formation region 105, which overlaps with the gate electrode 111 in plan view, is in contact with the first insulating region R1, which has almost no negative charge, and therefore maintains a low hole concentration. In this way, when the field-effect transistor is in the off state, the channel formation region 105 is composed of the first region P1, which has a low hole concentration, and the second region P2, which has a high hole concentration. As a result of the above, the semiconductor device according to the embodied embodiment can be manufactured.

[0088] According to the embodiment, a surface-conduction FET can be made into a "normally-off FET" simply by adding (1) a step of desorbing surface adsorbates (hydrogen plasma treatment in a vacuum) and (2) a step of performing negative charging treatment (oxygen plasma treatment). That is, the method for manufacturing a semiconductor device according to the embodiment can make a surface-conduction FET into a "normally-off FET" through a simple manufacturing process. Furthermore, the ability to manufacture the FET through a simple manufacturing process also leads to improved manufacturing yield, and therefore the method for manufacturing a semiconductor device according to the embodiment is extremely useful from the perspective of practical application with mass production in mind.

[0089] <<Features of Realized Embodiments>> For example, as shown in Fig. 1 , a surface-conduction FET 100 in a realized embodiment has a "non-overlapping structure." The "non-overlapping structure" is an FET structure in which the entire channel formation region 105 does not overlap with the gate electrode 111, as shown in Fig. 1 , but rather the channel formation region 105 has a region that does not overlap with the gate electrode 111 in plan view. That is, in the "non-overlapping structure," the channel formation region 105 has a first region P1 that overlaps with the gate electrode 111 and a second region P2 that does not overlap with the gate electrode 111. The "non-overlapping structure" configured in this manner has the following advantages.

[0090] 1, in the "non-overlapping structure," the distance between the gate electrode 111 and the source electrode 108 is increased. This means that the gate-source capacitance, which is the parasitic capacitance between the gate electrode 111 and the source electrode 108, can be reduced.

[0091] Similarly, in the "non-overlapping structure," the distance between the gate electrode 111 and the drain electrode 109 is increased. This means that the gate-drain capacitance, which is the parasitic capacitance between the gate electrode 111 and the drain electrode 109, can be reduced.

[0092] Therefore, the "non-overlap structure" can reduce the gate-source capacitance and gate-drain capacitance, thereby suppressing signal delay and a decrease in switching speed caused by parasitic capacitance. In other words, the "non-overlap structure" can improve the frequency characteristics of the surface-conduction FET 100. This can improve the amplification factor in an amplifier circuit, for example. In this way, the surface-conduction FET 100 having the "non-overlap structure" has the advantage of being able to improve performance.

[0093] Furthermore, increasing the distance between the gate electrode 111 and the source electrode 108 means that the gate-source breakdown voltage can be improved. Similarly, increasing the distance between the gate electrode 111 and the drain electrode 109 means that the gate-drain breakdown voltage can be improved. As a result, the surface-conduction FET 100 having the "non-overlap structure" has a high dielectric strength voltage, and therefore has the advantage of being able to be driven at a high voltage. For this reason, the surface-conduction FET 100 having the "non-overlap structure" is very useful when applied to transistors for power electronics, which require high-voltage operation.

[0094] From the above, it can be seen that the surface-conduction FET 100 having the "non-overlapping structure" has excellent performance, and furthermore, if this surface-conduction FET 100 is a "normally-off FET", it is desirable because further improvement in performance can be achieved.

[0095] Therefore, in the embodiment, a "normally-off type FET" is realized by implementing a technique to embody the basic concept in the surface conduction type FET 100 having the "non-overlapping structure."

[0096] The following describes the features employed in the embodiment.

[0097] 1, the characteristic feature of the embodiment is that, assuming that the channel formation region 105 is composed of a first region P1 and a second region P2, when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2 (representation A). In detail, when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the first region P1 is low enough to not be conductive, while the hole concentration in the second region P2 is high enough to be conductive. For example, when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the first region P1 is 10 １２ / cm ２ Less than (preferably 10 １１ / cm ２ The hole concentration in the second region P2 is 10 １３ / cm ２ The concentration is above this.

[0098] As a result, according to the characteristic point, when a gate voltage of "0 V" is applied to the gate electrode 111, no channel is formed in the first region P1 located directly below the gate electrode 111. Therefore, the surface conduction FET 100 is in an off state when a gate voltage of "0 V" is applied to the gate electrode 111. That is, when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the second region P2 is high enough to be conductive, so a channel is formed in the second region P2, but no channel is formed in the first region P1 as described above. Therefore, when a gate voltage of "0 V" is applied to the gate electrode 111, no channel is formed throughout the channel formation region 105, so the surface conduction FET 100 is in an off state.

[0099] In contrast, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, holes are attracted to this negative potential. This increases the hole concentration in the first region P1 located directly below the gate electrode 111. In other words, a two-dimensional hole gas is induced in the first region P1. As a result, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, a channel is formed in the first region P1.

[0100] Furthermore, since the hole concentration in the second region P2 is high enough to be conductive, a channel is formed in the second region P2 even when a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 111. Therefore, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, a channel is formed throughout the channel formation region 105, resulting in an on-state.

[0101] In this way, according to the feature of the embodiment, the surface-conduction FET 100 having the "non-overlapping structure" can be made into a "normally-off FET." Therefore, according to the feature, the performance of the surface-conduction FET 100 can be improved.

[0102] The features of the above-described embodiment are realized, for example, in a method for manufacturing a semiconductor device including: (1) a step of desorbing surface adsorbates (hydrogen plasma treatment in a vacuum); and (2) a step of negatively charging the insulating film 110 (oxygen plasma treatment).

[0103] 1, the characteristic feature of the embodiment described above can be expressed as follows: For example, as shown in Fig. 1, the characteristic feature of the embodiment is that, assuming that the insulating film 110 includes a first insulating region R1 that overlaps with the gate electrode 111 and a second insulating region R2 that does not overlap with the gate electrode 111, the amount of negative charge in the second insulating region R2 is larger than the amount of negative charge in the first insulating region R1 (expression B).

[0104] This expression is possible because the first region P1 is located directly below the first insulating region R1, while the second region P2 is located directly below the second insulating region R2. In other words, the second region P2, which is located below the second insulating region R2, which has a larger negative charge amount than the first insulating region R1, has an increased number of holes attracted to negative charges. Therefore, the hole concentration in the second region P2 is greater than the hole concentration in the first region P1. Consequently, adopting the configuration of expression B inevitably results in the configuration of expression A. In this way, the characteristic features in the embodied aspects can be expressed as expression A or expression B.

[0105] In the embodied embodiment, surface adsorbates attached to the hydrogen-terminated region 103 are desorbed. This improves the mobility of holes (carriers) in the channel. This is because the surface adsorbates attached to the upper surface of the channel formation region 105 are removed, reducing Coulomb scattering of holes (carriers) caused by the surface adsorbates. As a result, the embodied embodiment improves frequency characteristics by improving the mobility of holes.

[0106] <<Verification of Effects>> Next, a description will be given of the results of verifying that the surface conduction FET can be realized as a "normally-off FET" according to the embodiment.

[0107] In an embodiment, for example, a surface conduction FET is manufactured by a semiconductor device manufacturing method including: (1) a step of desorbing surface adsorbates (hydrogen plasma treatment in a vacuum); and (2) a step of negatively charging the insulating film 110 (oxygen plasma treatment).

[0108] Here, the steps (1) and (2) are collectively referred to as a hole concentration adjusting step.

[0109] First, the drain current-gate voltage characteristics of a surface conduction FET manufactured without performing the hole concentration adjustment process will be described. Fig. 9 is a graph showing the drain current-gate voltage characteristics of a surface conduction FET manufactured without performing the hole concentration adjustment process.

[0110] 9, the horizontal axis represents gate voltage (V), while the vertical axis represents drain current (A). As shown in FIG. 9, when the gate voltage is "0 V," a drain current having a current value seven orders of magnitude larger than the off level flows. This indicates that a surface-conduction FET manufactured without carrying out the hole concentration adjustment step is manufactured as a "normally-on FET."

[0111] Next, the drain current-gate voltage characteristics of a surface-conduction FET manufactured by performing the hole concentration adjustment process will be described. FIG. 10 is a graph showing the drain current-gate voltage characteristics of a surface-conduction FET manufactured by performing the hole concentration adjustment process. In FIG. 10, the horizontal axis represents gate voltage (V), while the vertical axis represents drain current (A). As shown in FIG. 10, when the gate voltage is "0 V," it can be seen that the drain current has a current value smaller than the lower limit of measurement. This indicates that the surface-conduction FET manufactured by performing the hole concentration adjustment process is manufactured as a "normally-off FET." In particular, the results shown in FIG. 10 have been confirmed for multiple surface-conduction FETs, and by performing the hole concentration adjustment process in the embodied embodiment, a "normally-off FET" is realized with good reproducibility.

[0112] Furthermore, when the hole concentration directly below the gate electrode was measured using the Hall effect measurement and the drain current-gate voltage characteristics at a gate voltage of 0 V, the hole concentration was found to be 10 １１ / cm ２ It was experimentally confirmed that the hole concentration directly under the gate electrode when the gate voltage was "0 V" was 10 or less, although the on / off ratio (ratio of on current to off current) was slightly deteriorated. １２ / cm ２ It has been confirmed that the surface conduction FET described below may also be practically usable as a "normally-off FET."

[0113] The above facts support the idea that, according to the embodiment, a surface conduction FET can be manufactured and used as a "normally-off FET."

[0114] <Modification 1> In the embodiment, an example has been described in which a "normally-off FET" is realized by applying the basic concept to a surface-conduction FET having a "non-overlapping structure." In this regard, Modification 1 will describe an example in which a "normally-off FET" is realized by applying the basic concept to a surface-conduction FET having an "overlapping structure." In other words, the basic concept can be widely applied not only to surface-conduction FETs having a "non-overlapping structure," but also to surface-conduction FETs having an "overlapping structure."

[0115] 11 is a cross-sectional view schematically showing a surface-conduction FET 200 having an "overlapping structure" according to Modification 1. In Fig. 11, the "overlapping structure" refers to an FET structure in which the entire channel formation region 105 overlaps with the gate electrode 111 in plan view.

[0116] In the surface conduction FET 200 having such an "overlap structure," when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the channel formation region 105 is low enough to not have conductivity. Specifically, the hole concentration in the channel formation region 105 is 10 １２ / cm ２ Below, preferably 10 １１ / cm ２ As a result, when a gate voltage of "0 V" is applied to the gate electrode 111, no channel is formed in the channel formation region 105. As a result, the surface conduction FET 200 having the "overlap structure" is turned off.

[0117] On the other hand, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, holes are attracted to this negative potential. As a result, the hole concentration increases to a level that provides conductivity throughout the entire channel formation region 105 that overlaps the gate electrode 111 in a planar manner. In other words, a two-dimensional hole gas is induced throughout the entire channel formation region 105. As a result, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, a channel is formed throughout the entire channel formation region 105.

[0118] Therefore, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, a channel is formed throughout the entire channel formation region 105, and the surface conduction FET 200 having the "overlap structure" is turned on.

[0119] In this way, according to the first modification, the surface conduction type FET 200 having the "overlap structure" can be operated as a "normally-off type FET."

[0120] The surface-conduction FET 200 having the "overlap structure" of the present modification 1 can be manufactured simply by adding a step of desorbing surface adsorbates (hydrogen plasma treatment in a vacuum). That is, the surface-conduction FET 200 having the "overlap structure" of the present modification 1 does not require a step of negatively charging the insulating film 110 (oxygen plasma treatment). This is because, in the surface-conduction FET 200 having the "overlap structure," the entire channel-forming region 105 overlaps with the gate electrode 111, and therefore, when the surface-conduction FET 200 is turned on, the channel modulation effect from the gate electrode 111 can be applied to the entire channel-forming region 105. That is, unlike the surface-conduction FET 100 having the "non-overlap structure" of the embodied embodiment, the surface-conduction FET 200 having the "overlap structure" of the present modification 1 does not have a second region P2 (a region that does not overlap with the gate electrode 111 in plan view) where the channel modulation effect is not effective. Therefore, the hole concentration of the second region P2 does not need to be high enough to provide conductivity.

[0121] Therefore, according to the first modification, the surface conduction type FET 200 can be made into a "normally-off type FET" by a manufacturing process that is even simpler than that of the embodied mode.

[0122] <Modification 2> <<Extension of basic idea>> The basic idea is to reduce the hole concentration in the channel formation region formed in the hydrogen-terminated diamond layer to a concentration that does not have conductivity by desorbing surface adsorbates. In this regard, the above-mentioned basic idea is not limited to the means of desorbing surface adsorbates, but can be extended to the idea of ​​reducing the hole concentration in the channel formation region to a concentration that does not have conductivity by any means.

[0123] An example that embodies the expanded basic concept will be described below. Specifically, in this modification 2, a means other than desorbing surface adsorbates is employed as a means for reducing the hole concentration in the channel formation region to a level at which the channel formation region is not conductive.

[0124] In this second modification, the surface adsorbates attached to the hydrogen-terminated region are not desorbed. As a result, in the surface conduction FET of this second modification, the hole concentration in the channel formation region is high enough to provide conductivity. In other words, a channel is formed in the channel formation region when a gate voltage of "0 V" is applied to the gate electrode. Therefore, in this case, the FET becomes a "normally on FET," and it is necessary to reduce the hole concentration in the channel formation region to a concentration that does not provide conductivity by some means.

[0125] In this regard, focusing on the "non-overlapping structure," in this second modification, for example, in FIG. 1 , the first insulating region R1 of the insulating film 110 located on the first region P1 of the channel formation region 105 is positively charged. As a result, a repulsive force is applied from the positively charged first insulating region R1 to the holes induced in the first region P1. As a result, the holes are repelled away from the first region P1 by the repulsive force, and the hole concentration in the first region P1 is reduced to a concentration that does not have conductivity. That is, in this second modification, instead of a means of desorbing surface adsorbates, a means of positively charging the first insulating region R1 of the insulating film 110 is adopted as a means for reducing the hole concentration in the channel formation region 105 to a concentration that does not have conductivity.

[0126] As a result, according to the present modification 2, when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the channel formation region 105 is reduced to a concentration that does not provide conductivity. In other words, according to the present modification 2, when a gate voltage of "0 V" is applied to the gate electrode 111, no channel is formed in the first region P1 of the channel formation region 105. As a result, according to the present modification 2, the surface conduction FET 100 can be made into a "normally-off FET." Note that, because the second insulating region R2 of the insulating film 110 is not positively charged, no repulsive force acts in the second region P2 of the channel formation region 105. As a result, a hole concentration that provides conductivity is maintained in the second region P2.

[0127] In this way, in this second modification, the expanded basic idea of ​​reducing the hole concentration in the channel formation region 105 to a concentration that does not have conductivity by some means is realized by positively charging the first insulating region R1 of the insulating film 110.

[0128] As a result, in this second modification, assuming that the channel formation region 105 is composed of a first region P1 and a second region P2 as shown in FIG. 1, when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2 (expression A). In detail, when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the first region P1 is low enough to not have conductivity, while the hole concentration in the second region P2 is high enough to have conductivity. For example, when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the first region P1 is 10 １２ / cm ２ Less than (preferably 10 １１ / cm ２ The hole concentration in the second region P2 is 10 １３ / cm ２ The concentration is above this.

[0129] The configuration of the second modification described above can be realized by a method for manufacturing a semiconductor device that includes a step of positively charging the first insulating region R1 of the insulating film 110.

[0130] 1 , the configuration of the present modification 2 can be expressed as follows: For example, assuming that the insulating film 110 includes a first insulating region R1 that overlaps with the gate electrode 111 and a second insulating region R2 that does not overlap with the gate electrode 111, the configuration of the present modification 2 can be expressed as follows: the amount of positive charge in the first insulating region R1 is greater than the amount of positive charge in the second insulating region R2 (expression C).

[0131] This expression is possible because the first region P1 is located directly below the first insulating region R1, while the second region P2 is located directly below the second insulating region R2. In other words, in the first region P1 located below the first insulating region R1, which has a larger positive charge amount than the second insulating region R2, the number of holes decreases due to repulsive forces from the positive charges. Therefore, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2. Consequently, adopting the configuration of expression C inevitably results in the configuration of expression A. In this way, the configuration in this modification 2 can be expressed as expression A or expression C.

[0132] The surface-conduction FET 100 having the "non-overlapping structure" in the present modified example 2 can be manufactured simply by adding a step of positively charging the first insulating region R1 of the insulating film 110. Therefore, according to the present modified example 2, the surface-conduction FET having the "non-overlapping structure" can be made into a "normally-off FET" by a simple manufacturing process.

[0133] The technical idea of ​​the present modified example 2 can be applied not only to a surface-conduction type FET having a "non-overlapping structure" but also to a surface-conduction type FET having an "overlapping structure".

[0134] For example, in a surface conduction FET 200 having an "overlap structure" shown in FIG. 11, the insulating film 110 is positively charged, thereby realizing the expanded basic idea of ​​reducing the hole concentration in the channel formation region 105 to a level at which the channel formation region 105 is not conductive.

[0135] <Application Examples> Next, application examples of the surface conduction FET according to this embodiment will be described.

[0136] The surface-conduction FET according to the present embodiment has high potential as a semiconductor device and is expected to be applied to a variety of systems. An example of a system to which the surface-conduction FET according to the present embodiment can be applied will be described below.

[0137] <<Application to power conversion systems>> The most important issues in realizing a sustainable society are the depletion of energy resources and the excessive emission of greenhouse gases such as carbon dioxide. For this reason, power conversion systems that are both energy efficient and emit little carbon dioxide are becoming increasingly important. Most power conversion systems are composed of power modules in which power electronics transistors, which are switching elements, and diodes, which are rectifying elements, are connected in parallel.

[0138] For example, a power conversion system applied to a railway vehicle will be described.

[0139] Electric power is supplied to railway vehicles from overhead lines via a pantograph. The high-voltage AC voltage supplied to the railway vehicle from the overhead lines via the pantograph is stepped down to, for example, AC voltage by an insulated main transformer. This stepped-down AC voltage is then converted to DC voltage by a converter. The DC voltage converted by the converter is then converted to three-phase AC voltage, each phase of which is shifted by 120 degrees, by an inverter via a capacitor. The three-phase AC voltage converted by the inverter is then supplied to a three-phase motor. As a result, the three-phase motor is driven to rotate the wheels, thereby allowing the railway vehicle to run.

[0140] As described above, the power conversion system of a railway vehicle includes an inverter. For example, the inverter is composed of six power electronics transistors and six freewheel diodes. As described above, power devices such as power electronics transistors and freewheel diodes are used as main components that perform switching and rectification functions.

[0141] In this regard, the surface conduction FET of this embodiment can be used as a power electronics transistor. This is because diamond has a larger band gap than silicon, resulting in a higher breakdown field strength than silicon. In other words, a power electronics transistor using diamond has a higher breakdown field strength than silicon, making it easier to ensure a high breakdown voltage than a power electronics transistor using silicon as the substrate material. Furthermore, a surface conduction FET using diamond has a high carrier density, making it possible to reduce the on-resistance. In other words, a surface conduction FET using diamond as the substrate material can achieve both a high breakdown voltage and a low on-resistance, which are in a trade-off relationship.

[0142] Here, for example, a "normally-off FET" is the most important in power devices. Specifically, power devices are widely used in power conversion systems that utilize large amounts of power, such as in automobiles, railroad cars, and airplanes, and safety is of utmost importance in power conversion systems. For this reason, a "normally-off FET" that outputs "0" when broken is required in power conversion systems. In this regard, the surface-conduction FET of this embodiment realizes a "normally-off FET." Therefore, it is useful to use the surface-conduction FET of this embodiment as a power electronics transistor, which is a component of a power conversion system.

[0143] <<Application to communication systems>> In recent years, the trend toward broadband information and communications has led to a demand for higher frequency and output in the high-frequency transistors that support communication systems. At the same time, from the perspective of energy conservation, there is also a demand for energy efficiency in high-frequency transistors. In this regard, diamond can be cited as a semiconductor material that meets the above requirements.

[0144] For example, the operating frequencies and output power of broadcasting terrestrial stations, communication satellites, and radar exceed the capabilities of current semiconductors, so vacuum tubes called traveling wave tubes are still in use, and there is a demand for improved reliability, efficiency, and miniaturization through the use of semiconductors.

[0145] Therefore, if high frequency transistors using diamond as a semiconductor material are put into practical use, it will be possible to dramatically improve the high frequency characteristics and high output characteristics in communication systems including broadcasting terrestrial stations, communication satellites, radars, etc. Therefore, using the surface conduction FET of this embodiment as a high frequency transistor, which is a component of the above-mentioned communication system, is very useful from the viewpoint of improving the high frequency characteristics and high output characteristics of the communication system.

[0146] <<Applications to harsh environment systems>> Silicon has low resistance to gamma rays and neutrons. In contrast, diamond is a single-element crystal made of carbon, and is a semiconductor with the same crystal structure as silicon. In diamond, the carbon elements that make up the crystal are strongly bonded to each other. For this reason, diamond has the characteristics of having a large band gap, high carrier mobility, and low intrinsic carrier density even at high temperatures, which allows semiconductor devices using diamond to operate at high speeds, with low loss, and at high temperatures.

[0147] Furthermore, semiconductor devices using diamond have the characteristics of X-ray resistance of 10 MGy or more, and neutron resistance that is four orders of magnitude higher than that of silicon. That is, diamond has the characteristic of generating very few electron-hole pairs under high temperature or radiation. Therefore, the surface conduction FET of this embodiment using diamond with excellent radiation resistance and high temperature resistance is suitable for use as a harsh environment transistor, which is a component of a harsh environment system placed in a harsh environment where radiation exists or a harsh environment system placed in a high-temperature environment. In other words, by using the surface conduction FET of this embodiment in a harsh environment system, the performance of the harsh environment system can be improved.

[0148] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0149] REFERENCE SIGNS LIST 100 Surface conduction type FET 200 Surface conduction type FET 101 Diamond substrate 102 Non-doped layer 103 Hydrogen termination region 103A Hydrogen termination region 104 Oxygen termination region 105 Channel formation region 106 Contact layer 107 Contact layer 108 Source electrode 109 Drain electrode 110 Insulating film 111 Gate electrode 120 Surface adsorbate P1 First region P2 Second region R1 First insulating region R2 Second insulating region

Claims

1. A semiconductor device including a field effect transistor, the field effect transistor having: a diamond layer including a hydrogen termination region; a channel formation region formed in the diamond layer; an insulating film formed on an upper surface of the diamond layer; and a gate electrode formed on the insulating film, the channel formation region including a first region overlapping with the gate electrode in a planar view; and a second region not overlapping with the gate electrode in a planar view, and when the field effect transistor is in an off state, a hole concentration in the first region is smaller than a hole concentration in the second region.

2. A semiconductor device including a field effect transistor, the field effect transistor having: a diamond layer including a hydrogen termination region; a channel formation region formed in the diamond layer; an insulating film formed on an upper surface of the diamond layer; and a gate electrode formed on the insulating film, the insulating film including a first insulating region overlapping with the gate electrode in a planar view; and a second insulating region not overlapping with the gate electrode in a planar view, the second insulating region having a larger amount of negative charge than the first insulating region.

3. A semiconductor device including a field effect transistor, the field effect transistor having: a diamond layer including a hydrogen termination region; a channel formation region formed in the diamond layer; an insulating film formed on an upper surface of the diamond layer; and a gate electrode formed on the insulating film, the insulating film including a first insulating region overlapping with the gate electrode in a planar view; and a second insulating region not overlapping with the gate electrode in a planar view, and a positive charge amount of the first insulating region is greater than a positive charge amount of the second insulating region.

4. A semiconductor device including a field effect transistor, the field effect transistor having: a diamond layer including a hydrogen termination region; a channel formation region formed in the diamond layer; an insulating film formed on an upper surface of the diamond layer; and a gate electrode formed on the insulating film, wherein, in an off state of the field effect transistor, a hole concentration in the channel formation region is greater than or equal to 10 １２ / cm ２ The following is the result.

5. In the semiconductor device described in claim 1, the insulating film includes a first insulating region that overlaps with the gate electrode in a planar view, and a second insulating region that does not overlap with the gate electrode in a planar view, and the amount of negative charge of the second insulating region is greater than the amount of negative charge of the first insulating region.

6. In the semiconductor device according to claim 1, the off state of the field effect transistor means a state in which the gate voltage applied to the gate electrode is 0V.

7. A semiconductor device according to claim 1, wherein the top surface of the diamond layer is a (001) surface.

8. A semiconductor device according to claim 1, wherein the diamond layer has an off-angle of 3 degrees in the <110> direction with respect to the (001) plane.

9. The semiconductor device according to claim 1, wherein when the field effect transistor is in an off state, the hole concentration of the first region is 10 １２ / cm ２ The following is the result.

10. The semiconductor device according to claim 1, wherein when the field effect transistor is in an off state, the hole concentration of the first region is 10 １１ / cm ２ The following is the result.

11. A semiconductor device according to claim 1, wherein the insulating film includes any one of an aluminum oxide film, a silicon oxide film, a calcium fluoride film, a hafnium oxide film, an aluminum nitride film, a boron nitride film, a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, a titanium oxide film, a tungsten oxide film, a lanthanum fluoride film, or a magnesium fluoride film.

12. In the semiconductor device described in claim 2, the channel formation region includes a first region that overlaps with the gate electrode in a planar view, and a second region that does not overlap with the gate electrode in a planar view, and when the field effect transistor is in an off state, the hole concentration of the first region is smaller than the hole concentration of the second region.

13. In the semiconductor device according to claim 2, the off state of the field effect transistor means a state in which the gate voltage applied to the gate electrode is 0V.

14. A semiconductor device according to claim 2, wherein the top surface of the diamond layer is a (001) surface.

15. A semiconductor device according to claim 2, wherein the diamond layer has an off-angle of 3 degrees in the <110> direction with respect to the (001) plane.

16. The semiconductor device according to claim 2, wherein when the field effect transistor is in an off state, the hole concentration of the first region is 10 １２ / cm ２ The following is the result.

17. The semiconductor device according to claim 2, wherein when the field effect transistor is in an off state, the hole concentration of the first region is 10 １１ / cm ２ The following is the result.

18. A semiconductor device according to claim 2, wherein the insulating film includes any one of an aluminum oxide film, a silicon oxide film, a calcium fluoride film, a hafnium oxide film, an aluminum nitride film, a boron nitride film, a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, a titanium oxide film, a tungsten oxide film, a lanthanum fluoride film, or a magnesium fluoride film.

19. The semiconductor device according to claim 4, wherein when the field effect transistor is in an off state, the hole concentration in the channel formation region is 10 １１ / cm ２ The following is the result.

20. A semiconductor device according to claim 4, wherein, in a plan view, the channel formation region overlaps with the gate electrode.

21. A system including a semiconductor device according to any one of claims 1 to 20.

22. A method for manufacturing a semiconductor device including a field effect transistor, comprising: (a) forming a diamond layer including a hydrogen-terminated region; and (b) reducing the hole concentration in the hydrogen-terminated region.

23. A method for manufacturing a semiconductor device as defined in claim 22, wherein the step (b) includes a step of desorbing surface adsorbates attached to the hydrogen-terminated region.

24. A method for manufacturing a semiconductor device as defined in claim 23, wherein the step (b) includes a step of performing a hydrogen plasma treatment in a vacuum.

25. A method for manufacturing a semiconductor device as defined in claim 22, comprising the steps of: (c) forming an insulating film on the diamond layer; (d) forming a gate electrode on the insulating film; and (e) subjecting a region of the insulating film exposed from the gate electrode to an electrification treatment.

26. A method for manufacturing a semiconductor device as defined in claim 25, wherein the step (e) includes a step of performing an oxygen plasma treatment.

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