Three-dimensional flash memory for preventing collapse of stacked structure and manufacturing method therefor

Abstract

Disclosed are a three-dimensional flash memory for preventing collapse of a stacked structure and a manufacturing method therefor. According to one embodiment of the present invention, the three-dimensional flash memory comprises: stacked structures each including gate electrodes that extend in a horizontal direction on a substrate and are stacked and spaced apart in a vertical direction, and vertical channel structures that penetrate the gate electrodes and extend in the vertical direction, wherein each of the vertical channel structures includes a data storage pattern and a vertical channel pattern; an isolation trench provided in the vertical direction between the stacked structures such that the stack structures are separated from each other; and a common source line formed in the isolation trench, wherein the isolation trench has at least one connection part that supports between the stacked structures in order to prevent the stacked structures from collapsing through the isolation trench before the common source line is formed.

Description

Three-dimensional flash memory preventing collapse of a laminated structure and its manufacturing method

[0001] The following examples relate to a three-dimensional flash memory that prevents collapse of a laminated structure and a method for manufacturing the same.

[0002] Flash memory devices are electrically erasable programmable read-only memories (EEPROM) that control the input and output of data electrically by Fowler-Nordheimtunneling or hot electron injection, and can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

[0003] In order to meet the high performance and low price demands of consumers, it is necessary to increase the integration density in these flash memory devices, and a three-dimensional structure in which memory cell transistors are arranged vertically to form a cell string has been proposed.

[0004] However, 3D flash memory has a problem in that the stacked structures collapse through the separation trench where the common source line is formed between the stacked structures due to the vertical stacking.

[0005] Therefore, the embodiments below propose a technique for solving the problems of the existing three-dimensional flash memory described above.

[0006] One embodiment proposes a three-dimensional flash memory structure including at least one connector within an isolation trench and a method of manufacturing the same to prevent collapse of the laminated structure.

[0007] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0008] According to one embodiment, a three-dimensional flash memory may be characterized by including stacked structures including gate electrodes that are formed to extend horizontally on a substrate and are spaced apart in a vertical direction and stacked, and vertical channel structures that penetrate the gate electrodes and extend in the vertical direction, each of the vertical channel structures including a data storage pattern and a vertical channel pattern; a separation trench provided in the vertical direction between the stacked structures so as to separate the stacked structures; and a common source line formed within the separation trench, wherein at least one connecting portion that supports between the stacked structures is included within the separation trench to prevent the stacked structures from collapsing through the separation trench before the common source line is formed.

[0009] According to one aspect, the at least one connecting portion may be formed of an insulating material to electrically isolate the laminated structures.

[0010] According to another aspect, the three-dimensional flash memory may further include a connecting wire arranged on top of the common source line, connecting portions of the common source line segmented by the at least one connecting portion.

[0011] According to another aspect, the three-dimensional flash memory may further include insulating spacers surrounding the side surfaces of the common source line within the separation trench.

[0012] According to one embodiment, a method for manufacturing a three-dimensional flash memory includes the steps of: preparing a semiconductor structure including gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart and stacked; forming a separation trench in the semiconductor structure in the vertical direction to generate stacked structures separated by the separation trench; and forming a common source line within the separation trench, wherein the step of generating the stacked structures may be characterized by forming the separation trench while leaving at least one connecting portion that supports between the stacked structures on the semiconductor structure to prevent the stacked structures from collapsing through the separation trench.

[0013] According to one embodiment, a method for manufacturing a three-dimensional flash memory includes the steps of: preparing a semiconductor structure including sacrificial layers that are vertically spaced apart and stacked while extending horizontally on a substrate; forming a separation trench in the vertical direction in the semiconductor structure to generate stacked structures separated by the separation trench; forming a common source line in the separation trench; removing the sacrificial layers from each of the stacked structures; and forming gate electrodes in spaces from which the sacrificial layers have been removed, wherein the step of generating the stacked structures may be characterized by forming the separation trench while leaving at least one connecting portion that supports between the stacked structures on the semiconductor structure to prevent the stacked structures from collapsing through the separation trench.

[0014] According to one aspect, the step of forming the common source line may further include a step of replacing the at least one connecting portion with an insulating material after forming the common source line.

[0015] According to another aspect, the replacing step may include: a step of removing a portion corresponding to the at least one connecting portion from the semiconductor structure to secure a space; and a step of filling the secured space with the insulating material to replace the at least one connecting portion with the insulating material.

[0016] According to another aspect, the step of forming the common source line may further include the step of arranging a connecting wire on top of the common source line so as to connect portions of the common source line segmented by the at least one connecting portion to each other after replacing the at least one connecting portion with the insulating material.

[0017] According to another aspect, the step of forming the common source line may further include the step of forming insulating spacers surrounding the side of the common source line within the separation trench.

[0018] According to another aspect, the method for manufacturing the three-dimensional flash memory may further include a step of forming vertical channel structures extending in the vertical direction so as to penetrate the gate electrodes or the sacrificial layers, each of the vertical channel structures including a data storage pattern and a vertical channel pattern.

[0019] One embodiment proposes a three-dimensional flash memory having a structure including at least one connector within an isolation trench and a method for manufacturing the same, thereby preventing collapse of the stacked structure.

[0020] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0021] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memory according to one embodiment.

[0022] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment.

[0023] FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.

[0024] FIG. 4 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, and corresponds to a cross-section taken along line B-B' of FIG. 2.

[0025] FIG. 5 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0026] FIGS. 6A to 6F are plan views illustrating the structure of a three-dimensional flash memory to explain the manufacturing method illustrated in FIG. 5.

[0027] FIGS. 7a to 7f are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain the manufacturing method illustrated in FIG. 5, and correspond to cross-sections taken along line A-A' of FIGS. 6a to 6f.

[0028] FIGS. 8a to 8f are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain the manufacturing method illustrated in FIG. 5, and correspond to cross-sections taken along the line B-B' of FIGS. 6a to 6f.

[0029] FIG. 9 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to another embodiment.

[0030] FIG. 10 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to one embodiment.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0032] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0033] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0034] Hereinafter, with reference to the drawings, a three-dimensional flash memory having a structure including at least one connecting portion within a separation trench to prevent collapse of the laminated structure and a method for manufacturing the same are described in detail.

[0035]

[0036] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memory according to one embodiment.

[0037] Referring to FIG. 1, an array of a three-dimensional flash memory according to one embodiment may include a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a plurality of cell strings (CSTR) disposed between the common source line (CSL) and the bit lines (BL0, BL1, BL2).

[0038] The bit lines (BL0, BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0039] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, BL2). The cell strings (CSTR) may be commonly connected to the common source line (CSL) provided between the bit lines (BL0, BL1, BL2) and one common source line (CSL). At this time, a plurality of common source lines (CSL) may be provided, and the plurality of common source lines (CSL) may be two-dimensionally arranged while extending in the first direction (D1) and being spaced apart from each other along the second direction (D2). The plurality of common source lines (CSL) may be electrically identically voltage-applied, but the present invention is not limited thereto, and each of the plurality of common source lines (CSL) may be electrically independently controlled so that different voltages may be applied.

[0040] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may be composed of a ground select transistor (GST) connected to a common source line (CSL), first and second string select transistors (SST1, SST2) connected to bit lines (BL0, BL1, BL2) and connected in series, memory cell transistors (MCT) and an erase control transistor (ECT) disposed between the ground select transistor (GST) and the first and second string select transistors (SST1, SST2) and connected in series. In addition, each of the memory cell transistors (MCT) may include a data storage element.

[0041] For example, each of the cell strings (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, and the second string select transistor (SST2) may be connected to one of the bit lines (BL0, BL1, BL2). However, the present invention is not limited thereto, and each of the cell strings (CSTR) may include one string select transistor. As another example, the ground select transistor (GST) in each of the cell strings (CSTR) may be composed of a plurality of MOS transistors connected in series, similar to the first and second string select transistors (SST1, SST2).

[0042] A cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from common source lines (CSL). That is, the memory cell transistors (MCT) may be connected in series along a third direction (D3) between a first string select transistor (SST1) and a ground select transistor (GST). An erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each of the cell strings (CSTR) may further include dummy cell transistors (DMC) connected between the first string select transistor (SST1) and an uppermost one of the memory cell transistors (MCT) and between the ground select transistor (GST) and a lowermost one of the memory cell transistors (MCT).

[0043] According to an embodiment, a first string select transistor (SST1) may be controlled by first string select lines (SSL1-1, SSL1-2, SSL1-3), and a second string select transistor (SST2) may be controlled by second string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may be controlled by a dummy word line (DWL), respectively. The ground select transistor (GST) may be controlled by the ground select lines (GSL0, GSL1, GSL2), and the erase control transistor (ECT) may be controlled by the erase control line (ECL). A plurality of erase control transistors (ECT) may be provided. Common source lines (CSL) can be commonly connected to the sources of erase control transistors (ECT).

[0044] The gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and thus may be in an equipotential state. However, the present invention is not limited thereto, and even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be independently controlled.

[0045] Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) extend along a first direction (D1), are spaced apart from each other in a second direction (D2) and can be arranged two-dimensionally. Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) provided at substantially the same level from common source lines (CSL) can be electrically isolated from each other. In addition, erase control transistors (ECT) of different cell strings (CSTR) can be controlled by a common erase control line (ECL). The erase control transistors (ECT) may generate gate-induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and / or the common source lines (CSL) during an erase operation of the memory cell array, and gate-induced leakage current may be generated in the string select transistor (SST) and / or the erase control transistors (ECT).

[0046] The string selection line (SSL) described above may be represented as an upper selection line (USL), and the ground selection line (GSL) may be represented as a lower selection line.

[0047]

[0048] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment, FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to a cross-section taken along line A-A' in FIG. 2, and FIG. 4 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to a cross-section taken along line B-B' in FIG. 2.

[0049] Referring to FIGS. 2 to 4, the substrate (SUB) may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductive type impurity (e.g., a P-type impurity).

[0050] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0051] Each of the stacked structures (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0052] Referring back to FIG. 1, each of the gate electrodes (EL1, EL2, EL3) may be one of the erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) sequentially stacked on the substrate (SUB).

[0053] Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), gold (Au), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0054] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in multiple numbers as needed. The first gate electrode (EL1) may correspond to any one of the ground selection lines (GSL0, GSL1, GLS2) illustrated in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) illustrated in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3) illustrated in FIG. 1.

[0055] Although not shown, each end of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). The third gate electrode (EL3) may have the shortest length in the first direction (D1) and the longest distance from the substrate (SUB) in the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and the shortest distance from the substrate (SUB) in the third direction (D3). By means of the step structure, each of the stacked structures (ST) can have a thickness that decreases as it moves away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a plan view.

[0056] Each of the interlayer insulating films (ILDs) may have a different thickness. For example, the lowermost and uppermost interlayer insulating films (ILDs) may have a smaller thickness than the other interlayer insulating films (ILDs). However, this is merely an example and is not limiting, and the thickness of each of the interlayer insulating films (ILDs) may be different depending on the characteristics of the semiconductor device, or may be set to be the same for all. The interlayer insulating films (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating films (ILDs) may be formed of silicon oxide.

[0057] A plurality of channel holes (CH) penetrating through a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be a plurality of cell strings (CSTR) as illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical channel structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical channel structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical channel structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0058] Rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. For example, as illustrated in FIG. 2, rows of two vertical channel structures (VS) may penetrate one of the stacked structures (ST). However, the present invention is not limited thereto, and rows of one vertical channel structure (VS) may penetrate one of the stacked structures (ST), or rows of three or more vertical channel structures (VS) may penetrate one of the stacked structures (ST). In a pair of adjacent rows, the vertical channel structures (VS) corresponding to one row may be shifted in a first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent row. In a plan view, the vertical channel structures (VS) may be arranged in a zigzag shape along the first direction (D1). However, without being limited or restricted thereto, the vertical channel structures (VS) may also form an array arranged side by side in rows and columns.

[0059] Each of the vertical channel structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical channel structures (VS) is illustrated as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0060] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a vertical filled pattern (VFP), and a conductive pad (PAD). In each of the vertical channel structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with an open bottom, and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom. The vertical filled pattern (VFP) may fill a space surrounded by the vertical channel pattern (VCP) and the conductive pad (PAD).

[0061] A data storage pattern (DSP) may cover the inner sidewall of each of the channel holes (CH), surround the outer sidewall of the vertical channel pattern (VCP) on the inner side, and contact the sidewalls of the gate electrodes (EL1, EL2, EL3) on the outer side. The data storage pattern (DSP) is a data storage element that traps charges by a voltage applied through the second gate electrodes (EL2) and represents a data value by a change in the trapped charges, or changes the state of the charges (e.g., a polarization state) by a voltage applied through the gate electrodes (EL2) and represents a data value by a change in the state of the charges, and may be, for example, an ONO (Oxide-Nitride-Oxide) or a ferroelectric pattern.

[0062] A vertical channel pattern (VCP) may cover an inner wall of a data storage pattern (DSP). The vertical channel pattern (VCP) may include a first portion (VCP1) and a second portion (VCP2) on the first portion (VCP1).

[0063] A first portion (VCP1) of the vertical channel pattern (VCP) may be provided at a lower portion of each of the channel holes (CH) and may be in contact with the substrate (SUB). The first portion (VCP1) of the vertical channel pattern (VCP) may be used to block, suppress, or minimize leakage current in each of the vertical channel structures (VS) and / or as an epitaxial pattern. The thickness of the first portion (VCP1) of the vertical channel pattern (VCP) may be, for example, greater than the thickness of the first gate electrode (EL1). A side wall of the first portion (VCP1) of the vertical channel pattern (VCP) may be surrounded by a data storage pattern (DSP). An upper surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located at a higher level than an upper surface of the first gate electrode (EL1). More specifically, the upper surface of the first part (VCP1) of the vertical channel pattern (VCP) may be located between the upper surface of the first gate electrode (EL1) and the lower surface of the lowest one of the second gate electrodes (EL2). The lower surface of the first part (VCP1) of the vertical channel pattern (VCP) may be located at a level lower than the upper surface of the substrate (SUB) (i.e., the lower surface of the lowest one of the interlayer insulating films (ILD). A part of the first part (VCP1) of the vertical channel pattern (VCP) may overlap with the first gate electrode (EL1) in the horizontal direction. Hereinafter, the horizontal direction means any direction extending on a plane parallel to the first direction (D1) and the second direction (D2).

[0064] A second portion (VCP2) of the vertical channel pattern (VCP) may extend in a third direction (D3) from an upper surface of the first portion (VCP1). The second portion (VCP2) of the vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the vertical buried pattern (VFP), and may correspond to the second gate electrodes (EL2). Accordingly, the second portion (VCP2) of the vertical channel pattern (VCP) may form memory cells together with regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP), as described above.

[0065] The upper surface of the second part (VCP2) of the vertical channel pattern (VCP) may be substantially coplanar with the upper surface of the vertical buried pattern (VFP). The upper surface of the second part (VCP2) of the vertical channel pattern (VCP) may be located at a level higher than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the second part (VCP2) of the vertical channel pattern (VCP) may be located between the upper surface and the lower surface of the third gate electrode (EL3).

[0066] A vertical channel pattern (VCP) is a component that transfers charges or holes to a data storage pattern (DSP), and may be formed of single-crystalline silicon or polysilicon to form or boost a channel by an applied voltage. However, without being limited thereto, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing leakage current. For example, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material including at least one of In, Zn, or Ga having excellent leakage current characteristics. The vertical channel pattern (VCP) may be formed of, for example, a ZnOx series material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Therefore, the vertical channel pattern (VCP) can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and can improve transistor characteristics (e.g., threshold voltage distribution and speed of program / read operation) of at least one of the gate electrodes (EL1, EL2, EL3), thereby improving electrical characteristics of the three-dimensional flash memory.

[0067] A vertical buried pattern (VFP) may be surrounded by a second portion (VCP2) of a vertical channel pattern (VCP). An upper surface of the vertical buried pattern (VFP) may be in contact with a conductive pad (PAD), and a lower surface of the vertical buried pattern (VFP) may be in contact with a first portion (VCP1) of the vertical channel pattern (VCP). The vertical buried pattern (VFP) may be spaced apart from the substrate (SUB) in a third direction (D3). In other words, the vertical buried pattern (VFP) may be electrically floated from the substrate (SUB).

[0068] The vertical buried pattern (VFP) can be formed of a material that helps the diffusion of charges or holes in the vertical channel pattern (VCP). More specifically, the vertical buried pattern (VFP) can be formed of a material with excellent charge or hole mobility. For example, the vertical buried pattern (VFP) can be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material that is not doped with impurities, or a polycrystalline semiconductor material. For a more specific example, the vertical buried pattern (VFP) can be formed of polysilicon doped with the same first conductivity type impurities as the substrate (SUB), for example, a P-type impurity. That is, the vertical buried pattern (VFP) can improve the electrical characteristics of the 3D flash memory, thereby increasing the speed of the memory operation.

[0069] Referring back to FIG. 1, the vertical channel structures (VS) may correspond to channels of an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT).

[0070] A conductive pad (PAD) may be provided on a top surface of a second part (VCP2) of a vertical channel pattern (VCP) and a top surface of a vertical buried pattern (VFP). The conductive pad (PAD) may be connected to an upper portion of the vertical channel pattern (VCP) and an upper portion of the vertical buried pattern (VFP). A side wall of the conductive pad (PAD) may be surrounded by a data storage pattern (DSP). An upper surface of the conductive pad (PAD) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating films (ILDs). A lower surface of the conductive pad (PAD) may be located at a level lower than an upper surface of the third gate electrode (EL3). More specifically, the lower surface of the conductive pad (PAD) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the conductive pad (PAD) may overlap the third gate electrode (EL3) in a horizontal direction.

[0071] The conductive pad (PAD) may be formed of a semiconductor or conductive material doped with impurities. For example, the conductive pad (PAD) may be formed of a semiconductor material doped with impurities different from those of the vertically buried pattern (VFP) (more precisely, impurities of a second conductive type (e.g., N-type) different from those of the first conductive type (e.g., P-type).

[0072] The challenge pad (PAD) can reduce the contact resistance between the bit line (BL) and the vertical channel pattern (VCP) (or vertical buried pattern (VFP)) described below.

[0073] Above, the vertical channel structures (VS) have been described as having a structure including a conductive pad (PAD), but they are not limited thereto and may have a structure in which the conductive pad (PAD) is omitted. In this case, since the conductive pad (PAD) is omitted from the vertical channel structures (VS), the vertical channel pattern (VCP) and the vertical buried pattern (VFP) may be formed to extend in the third direction (D3) so that the upper surfaces of each of the vertical channel patterns (VCP) and the vertical buried pattern (VFP) are substantially coplanar with the upper surfaces of each of the stacked structures (ST) (i.e., the upper surfaces of the uppermost of the interlayer insulating films (ILDs)). In addition, in this case, the bit line contact plug (BLPG) described later may be directly in contact with and electrically connected to the vertical channel pattern (VCP) instead of being indirectly electrically connected to the vertical channel pattern (VCP) through the conductive pad (PAD).

[0074] Additionally, although the vertical channel structures (VS) are described as including vertically embedded patterns (VFPs), the vertically embedded patterns (VFPs) are not limited thereto and may be omitted.

[0075] In addition, although the vertical channel pattern (VCP) has been described as having a structure including a first portion (VCP1) and a second portion (VCP2), it is not limited thereto and may have a structure in which the first portion (VCP1) is excluded. For example, the vertical channel pattern (VCP) may be provided between a vertical buried pattern (VFP) formed to extend to the substrate (SUB) and a data storage pattern (DSP) and may be formed to extend to the substrate (SUB) so as to contact the substrate (SUB). In this case, a lower surface of the vertical channel pattern (VCP) may be positioned at a level lower than an uppermost surface of the substrate (SUB) (a lower surface of the lowest of the interlayer insulating films (ILDs)), and an upper surface of the vertical channel pattern (VCP) may be substantially coplanar with an upper surface of the vertical buried pattern (VFP).

[0076] Between adjacent laminated structures (ST), a separation trench (TR) extending in a first direction (D1) and extending in a third direction (D3) may be provided to separate the laminated structures (ST).

[0077] A common source line (CSL) may be provided within the isolation trench (TR). More specifically, the common source line (CSL) may be provided on a substrate (SUB) within the isolation trench (TR). The common source line (CSL) may have a plate shape extending in a first direction (D1) and a third direction (D3). In this case, the common source line (CSL) may have a shape in which a width in the second direction (D2) increases as it goes in the third direction (D3).

[0078] The common source line (CSL) may be formed of a semiconductor material doped with a second conductivity type impurity (e.g., an N-type impurity). The upper surface of the common source line (CSL) may be substantially coplanar with the upper surface of each of the stacked structures (ST) (i.e., the upper surface of the uppermost one of the interlayer insulating films (ILDs).

[0079] Insulating spacers (SP) may be interposed between the common source line (CSL) and the stacked structures (ST). The insulating spacers (SP) may be formed to surround the side surfaces of the common source line (CSL) within the isolation trench (TR), thereby facing each other and provided between adjacent stacked structures (ST). For example, the insulating spacers (SP) may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0080] The separation trench (TR) may include at least one connecting member (CN) that supports between the stacked structures (ST) as a structure to prevent the stacked structures (ST) from collapsing through the separation trench (TR) before the common source line (CSL) is formed.

[0081] At least one connecting member (CN) may be formed of an insulating material to electrically isolate the stacked structures (ST). For example, the insulating material may be silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0082] As at least one connection (CN) is formed of an insulating material in this way, the common source line (CSL) can be segmented into a plurality of parts (P1, P2, P3) by at least one connection (CN).

[0083] Accordingly, the three-dimensional flash memory may further include a connection wiring (CL) that is arranged on top of the common source line (CSL) and connects the segmented portions (P1, P2, P3) of the common source line (CSL) to each other by at least one connection portion (CN). The connection wiring (CL) may be formed to extend in a first direction (D1) to connect the segmented portions (P1, P2, P3) to each other. The conductive material forming the connection wiring (CL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0084] A capping insulating film (CAP) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source line (CSL). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating films (ILD), an upper surface of the conductive pad (PAD), and an upper surface of the common source line (CSL). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating films (ILD). The aforementioned connection wiring (CL) may be provided inside the capping insulating film (CAP), and a bit line contact plug (BLPG) electrically connected to the conductive pad (PAD) may be provided. The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0085] A bit line (BL) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of a plurality of bit lines (BL0, BL1, BL2) illustrated in FIG. 1, and may be formed by extending along a second direction (D2) using a conductive material. The conductive material forming the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0086] A bit line (BL) may be electrically connected to vertical channel structures (VS) via a bit line contact plug (BLPG). Here, the connection of the bit line (BL) to the vertical channel structures (VS) may mean that the bit line (BL) is connected to a vertical channel pattern (VCP) included in the vertical channel structures (VS).

[0087] A three-dimensional flash memory having such a structure can perform a program operation, a read operation, and an erase operation based on a voltage applied to each of the cell strings (CSTR), a voltage applied to a string select line (SSL), a voltage applied to each of the word lines (WL0-WLn), a voltage applied to a ground select line (GSL), and a voltage applied to a common source line (CSL). For example, the three-dimensional flash memory can perform a program operation by forming a channel in a vertical channel pattern (VCP) to transfer charges or holes to a data storage pattern (DSP) of a target memory cell based on a voltage applied to each of the cell strings (CSTR), a voltage applied to a string select line (SSL), a voltage applied to each of the word lines (WL0-WLn), a voltage applied to a ground select line (GSL), and a voltage applied to a common source line (CSL).

[0088] In addition, the three-dimensional flash memory according to one embodiment is not limited or restricted to the described structure, and can be implemented in various structures assuming that it includes a vertical channel pattern (VCP), a data storage pattern (DSP), gate electrodes (EL1, EL2, EL3), a bit line (BL), a common source line (CSL), at least one connection portion (CN) and a connection wiring (CL) according to an implementation example.

[0089] For example, a three-dimensional flash memory can be implemented with a structure including a back gate (BG) instead of a vertically buried pattern (VFP) that contacts the inner wall of a vertical channel pattern (VCP). In this case, the back gate (BG) can be formed by extending along a vertical direction (e.g., a third direction (D3)) with a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), gold (Au), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) so as to be at least partially surrounded by the vertical channel pattern (VCP) so as to apply a voltage for a memory operation to the VCP.

[0090]

[0091] FIG. 5 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment, and FIGS. 6a to 6f are plan views illustrating a structure of a three-dimensional flash memory for explaining the manufacturing method illustrated in FIG. 5, and FIGS. 7a to 7f are cross-sectional views illustrating a structure of a three-dimensional flash memory for explaining the manufacturing method illustrated in FIG. 5, corresponding to cross-sections taken along lines A-A' in FIGS. 6a to 6f, and FIGS. 8a to 8f are cross-sectional views illustrating a structure of a three-dimensional flash memory for explaining the manufacturing method illustrated in FIG. 5, corresponding to cross-sections taken along lines B-B' in FIGS.

[0092] Hereinafter, a method for manufacturing a three-dimensional flash memory according to one embodiment is described for manufacturing a three-dimensional flash memory having a structure described with reference to FIGS. 2 to 4 based on a gate-first technique, and is assumed to be performed by an automated and mechanized manufacturing system.

[0093] In addition, the following manufacturing method is described as manufacturing a three-dimensional flash memory having a structure including components other than a bit line contact plug (BLPG), a bit line (BL), and a capping insulating film (CAP) for convenience of explanation. The excluded bit line contact plug (BLPG), bit line (BL), and capping insulating film (CAP) can be formed through additional steps (not shown) after the steps (S510 to S530) described below.

[0094] In addition, since the constituent materials constituting each component of the 3D flash memory are described with reference to FIGS. 2 to 4, a detailed description thereof is omitted.

[0095] In step (S510), the manufacturing system can prepare a semiconductor structure (SEMI-STR) including gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD) that are alternately stacked in the vertical direction while extending horizontally on a substrate (SUB) as shown in FIGS. 6a, 7a, and 8a.

[0096] Although the drawing shows that the semiconductor structure (SEMI-STR) includes vertical channel structures (VS) penetrating gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD), it is not limited thereto and may further include channel holes (CH) penetrating the gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD), or only the gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD) may be included without including vertical channel structures (VS) or channel holes (CH).

[0097] When a semiconductor structure (SEMI-STR) including only gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD) is prepared in step (S510), channel holes (CH) may be formed through additional steps (not shown) after steps (S510 to S530) and vertical channel structures (VS) may be formed within the channel holes (CH).

[0098] When a semiconductor structure (SEMI-STR) including gate electrodes (EL1, EL2, EL3), interlayer insulating films (ILD), and channel holes (CH) is prepared in step (S510), vertical channel structures (VS) can be formed within the channel holes (CH) through additional steps (not shown) after steps (S510 to S530).

[0099] In step (S520), the manufacturing system can form a separation trench (TR) in a vertical direction in a semiconductor structure (SEMI-STR) as illustrated in FIGS. 6b, 7b, and 8b to produce stacked structures (ST) separated by the separation trench (TR).

[0100] In particular, in step (S520), the manufacturing system can form the isolation trench (TR) while leaving at least one connecting portion (CN) supporting between the stacked structures (ST) on the semiconductor structure (SEMI-STR) to prevent the stacked structures (ST) from collapsing through the isolation trench (TR).

[0101] In step (S530), the manufacturing system can form a common source line (CSL) within the isolation trench (TR) as illustrated in FIGS. 6c, 7c, and 8c.

[0102] At this time, the manufacturing system can form insulating spacers (SP) that surround the sides of the common source line (CSL) within the isolation trench (TR).

[0103] In the steps (S520 to S530) described above, a separation trench (TR) is formed, and at least one remaining connection portion (CN) may be formed by a portion of the gate electrodes (EL1, EL2, EL3) and the interlayer insulating films (ILD), as illustrated in FIG. 8C. Accordingly, the stacked structures (ST) may be electrically connected, and the manufacturing system may replace the material forming the at least one connection portion (CN) so that the stacked structures (ST) may be electrically isolated.

[0104] More specifically, although not depicted as a separate drawing in FIG. 5, the manufacturing system may replace at least one connection (CN) with an insulating material after forming the common source line (CSL) in step (S530).

[0105] For example, the manufacturing system can secure space by removing a portion corresponding to at least one connection (CN) in a semiconductor structure (SEMI-STR) as illustrated in FIGS. 6d, 7d, and 8d, and then fill the secured space with an insulating material as illustrated in FIGS. 6e, 7e, and 8e to replace at least one connection (CN) with an insulating material.

[0106] Additionally, since at least one connection (CN) is formed of an insulating material, the common source line (CSL) can be segmented into a plurality of parts (P1, P2, P3) by at least one connection (CN).

[0107] Accordingly, the manufacturing system can place a connection wire (CL) on top of the common source line (CSL) so that the common source line (CSL) connects the segmented parts (P1, P2, P3) by the at least one connection (CN) to each other, after replacing at least one connection (CN) with an insulating material as illustrated in FIGS. 6f, 7f and 8f in step (S530).

[0108]

[0109] FIG. 9 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to another embodiment.

[0110] Hereinafter, a method for manufacturing a three-dimensional flash memory according to another embodiment is described for manufacturing a three-dimensional flash memory having a structure described with reference to FIGS. 2 to 4 based on a gate replacement technique, and is assumed to be performed by an automated and mechanized manufacturing system.

[0111] In addition, the following manufacturing method is described as manufacturing a three-dimensional flash memory having a structure including components other than a bit line contact plug (BLPG), a bit line (BL), and a capping insulating film (CAP) for convenience of explanation. The excluded bit line contact plug (BLPG), bit line (BL), and capping insulating film (CAP) can be formed through additional steps (not shown) after the steps (S910 to S950) described below.

[0112] In addition, since the constituent materials constituting each component of the 3D flash memory are described with reference to FIGS. 2 to 4, a detailed description thereof is omitted.

[0113] In step (S910), the manufacturing system can prepare a semiconductor structure (SEMI-STR) including sacrificial layers and interlayer insulating films (ILDs) alternately stacked in the vertical direction while extending horizontally on a substrate (SUB).

[0114] Although the drawing shows that the semiconductor structure (SEMI-STR) includes vertical channel structures (VS) penetrating sacrificial layers and interlayer dielectric layers (ILD), it is not limited thereto and may further include channel holes (CH) penetrating the sacrificial layers and interlayer dielectric layers (ILD), or may include only sacrificial layers and interlayer dielectric layers (ILD) without including vertical channel structures (VS) or channel holes (CH).

[0115] When a semiconductor structure (SEMI-STR) including only sacrificial layers and interlayer insulating films (ILD) is prepared in step (S910), channel holes (CH) may be formed through additional steps (not shown) after steps (S910 to S950) and vertical channel structures (VS) may be formed within the channel holes (CH).

[0116] When a semiconductor structure (SEMI-STR) including sacrificial layers, interlayer insulating films (ILD) and channel holes (CH) is prepared in step (S910), vertical channel structures (VS) can be formed within the channel holes (CH) through additional steps (not shown) after steps (S910 to S950).

[0117] In step (S920), the manufacturing system can form a separation trench (TR) in a vertical direction in a semiconductor structure (SEMI-STR) to produce stacked structures (ST) separated by the separation trench (TR).

[0118] In particular, in step (S920), the manufacturing system can form the isolation trench (TR) while leaving at least one connecting portion (CN) supporting between the stacked structures (ST) on the semiconductor structure (SEMI-STR) to prevent the stacked structures (ST) from collapsing through the isolation trench (TR).

[0119] At step (S930), the manufacturing system can form a common source line (CSL) within a separation trench (TR).

[0120] At this time, the manufacturing system can form insulating spacers (SP) that surround the sides of the common source line (CSL) within the isolation trench (TR).

[0121] In the steps (S920 to S930) described above, a separation trench (TR) is formed, and at least one remaining connection portion (CN) is composed of sacrificial layers and a portion of interlayer insulating films (ILD). However, considering that gate electrodes (EL1, EL2, EL3) will be formed in spaces where the sacrificial layers are removed in the step (S950) described below, the stacked structures (ST) can ultimately be electrically connected. Accordingly, the manufacturing system can replace a material forming at least one connection portion (CN) so that the stacked structures (ST) can be electrically isolated.

[0122] More specifically, although not depicted as a separate drawing in FIG. 5, the manufacturing system may replace at least one connection (CN) with an insulating material after forming the common source line (CSL) in step (S930).

[0123] For example, the manufacturing system can remove a portion corresponding to at least one connection (CN) in a semiconductor structure (SEMI-STR) to secure space, and then fill the secured space with an insulating material to replace at least one connection (CN) with an insulating material.

[0124] Additionally, since at least one connection (CN) is formed of an insulating material, the common source line (CSL) can be segmented into a plurality of parts (P1, P2, P3) by at least one connection (CN).

[0125] Accordingly, the manufacturing system can place a connection wire (CL) on top of the common source line (CSL) so that the common source line (CSL) connects the segmented parts (P1, P2, P3) by the at least one connection (CN) to each other after replacing at least one connection (CN) with an insulating material in step (S930).

[0126] In step (S940), the manufacturing system can remove sacrificial layers from each of the laminated structures (ST).

[0127] In step (S950), the manufacturing system can form gate electrodes (EL1, EL2, EL3) in spaces from which sacrificial layers have been removed.

[0128]

[0129] FIG. 10 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to one embodiment.

[0130] Referring to FIG. 10, an electronic system (1000) including a three-dimensional flash memory according to embodiments may include a main substrate (1001), a controller (1002) mounted on the main substrate (1001), one or more semiconductor packages (1003), and a DRAM (1004).

[0131] The semiconductor package (1003) and DRAM (1004) can be interconnected with the controller (1002) by wiring patterns (1005) provided on the main substrate (1001).

[0132] The main board (1001) may include a connector (1006) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1006) may vary depending on the communication interface between the electronic system (1000) and the external host.

[0133] The electronic system (1000) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (1000) may operate by power supplied from an external host, for example, through a connector (1006). The electronic system (1000) may further include a PMIC (Power Management Integrated Circuit) that distributes power supplied from the external host to a controller (1002) and a semiconductor package (1003).

[0134] The controller (1002) can write data to the semiconductor package (1003) or read data from the semiconductor package (1003), and can improve the operating speed of the electronic system (1000).

[0135] The DRAM (1004) may be a buffer memory to mitigate the speed difference between the semiconductor package (1003), which is a data storage space, and an external host. The DRAM (1004) included in the electronic system (1000) may also function as a type of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package (1003). When the electronic system (1000) includes the DRAM (1004), the controller (1002) may further include a DRAM controller for controlling the DRAM (1004) in addition to the NAND controller for controlling the semiconductor package (1003).

[0136] A semiconductor package (1003) may include first and second semiconductor packages (1003a, 1003b) that are spaced apart from each other. The first and second semiconductor packages (1003a, 1003b) may each be a semiconductor package including a plurality of semiconductor chips (1020). Each of the first and second semiconductor packages (1003a, 1003b) may include a package substrate (1010), semiconductor chips (1020) on the package substrate (1010), adhesive layers (1030) disposed on a lower surface of each of the semiconductor chips (1020), connection structures (1040) that electrically connect the semiconductor chips (1020) and the package substrate (1010), and a molding layer (1050) that covers the semiconductor chips (1020) and the connection structures (1040) on the package substrate (1010).

[0137] The package substrate (1010) may be a printed circuit board including package upper pads (1011). Each of the semiconductor chips (1020) may include input / output pads (1021). Each of the semiconductor chips (1020) may include the three-dimensional flash memory described above with reference to FIGS. 1 to 4. More specifically, each of the semiconductor chips (1020) may include gate stack structures (1022) and memory channel structures (1023). The gate stack structures (1022) may correspond to the stack structures (ST) described above, and the memory channel structures (1023) may correspond to the vertical channel structures (VS) described above.

[0138] The connection structures (1040) may be, for example, bonding wires that electrically connect the input / output pads (1021) and the package upper pads (1011). Accordingly, in each of the first and second semiconductor packages (1003a, 1003b), the semiconductor chips (1020) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (1011) of the package substrate (1010). According to embodiments, in each of the first and second semiconductor packages (1003a, 1003b), the semiconductor chips (1020) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (1040).

[0139] Unlike the illustration, the controller (1002) and the semiconductor chips (1020) may be included in a single package. The controller (1002) and the semiconductor chips (1020) may be mounted on a separate interposer substrate different from the main substrate (1001), and the controller (1002) and the semiconductor chips (1020) may be connected to each other by wiring provided on the interposer substrate.

[0140] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0141] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Stacked structures including gate electrodes that are formed horizontally and vertically spaced apart from each other and are stacked on a substrate, and vertical channel structures that penetrate the gate electrodes and extend in the vertical direction, each of the vertical channel structures including a data storage pattern and a vertical channel pattern; A separation trench provided in the vertical direction between the laminated structures so that the laminated structures are separated; and A common source line formed within the above separation trench Including, Within the above separation trench, A three-dimensional flash memory characterized in that it includes at least one connecting member that supports between the stacked structures to prevent the stacked structures from collapsing through the separation trench before the common source line is formed.

2. In paragraph 1, At least one of the above connecting portions, A three-dimensional flash memory characterized in that it is formed of an insulating material to electrically isolate the above-mentioned laminated structures.

3. In paragraph 2, The above three-dimensional flash memory, A connecting wire that is arranged on top of the common source line and connects the parts of the common source line segmented by the at least one connecting portion. A three-dimensional flash memory characterized by further including:

4. In paragraph 1, Insulating spacers surrounding the sides of the common source line within the above separation trench A three-dimensional flash memory characterized by further including:

5. A step of preparing a semiconductor structure including gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart and stacked; A step of forming a separation trench in the vertical direction in the semiconductor structure to create laminated structures separated by the separation trench; and A step of forming a common source line within the above separation trench; Including, The step of creating the above laminated structures is: A method for manufacturing a three-dimensional flash memory, characterized in that the step of forming the separation trench while leaving at least one connecting portion supporting between the stacked structures on the semiconductor structure to prevent the stacked structures from collapsing through the separation trench.

6. A step of preparing a semiconductor structure including sacrificial layers that are formed horizontally on a substrate and are vertically spaced apart and stacked; A step of forming a separation trench in the vertical direction in the semiconductor structure to create laminated structures separated by the separation trench; A step of forming a common source line within the above separation trench; A step of removing the sacrificial layers from each of the above laminated structures; and A step of forming gate electrodes in spaces where the above sacrificial layers have been removed. Including, The step of creating the above laminated structures is: A method for manufacturing a three-dimensional flash memory, characterized in that the step of forming the separation trench while leaving at least one connecting portion supporting between the stacked structures on the semiconductor structure to prevent the stacked structures from collapsing through the separation trench.

7. In either of paragraphs 5 or 6, The step of forming the above common source line is: After forming the above common source line, a step of replacing at least one connecting portion with an insulating material A method for manufacturing a three-dimensional flash memory, characterized in that it further includes.

8. In paragraph 7, The above replacement step is, A step of securing space by removing a portion corresponding to at least one connecting portion in the semiconductor structure; and A step of filling the above-mentioned space with the insulating material and replacing at least one connecting portion with the insulating material. A method for manufacturing a three-dimensional flash memory, characterized by including:

9. In paragraph 7, The step of forming the above common source line is: After replacing at least one of the above connecting portions with the insulating material, a step of arranging a connecting wire on top of the common source line so that the common source line connects the portions segmented by the at least one connecting portion to each other. A method for manufacturing a three-dimensional flash memory, characterized in that it further includes.

10. In either of paragraphs 5 or 6, A step of forming insulating spacers surrounding the side of the common source line within the above separation trench. A method for manufacturing a three-dimensional flash memory, characterized in that it further includes.

11. In either of paragraphs 5 or 6, A step of forming vertical channel structures extending in the vertical direction so as to penetrate the gate electrodes or the sacrificial layers, each of the vertical channel structures including a data storage pattern and a vertical channel pattern. A method for manufacturing a three-dimensional flash memory, characterized in that it further includes.

Images