Self-calibration method of the phase shifter for phased-array radar applications

Abstract

An efficient calibration algorithm for generating the control coefficients of an analog phase shifter circuit employing an in-phase and quadrature signal adder architecture is presented to reduce the complexity and cost of signal phase calibration in phased-array transmission systems.

Description

Docket No. BMD0302WO SELF-CALIBRATION METHOD OF THE PHASE SHIFTER FOR PHASED-ARRAY RADAR APPLICATIONS CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of prior filed U.S. Provisional Patent Application No. 63 / 523,252 filed on June 26, 2023, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to techniques for calibrating phased-array radar. BACKGROUND

[0003] Autonomous driving and Advanced-Driver Assistance Systems (“ADAS”) automate, adapt and enhance vehicles for safety and better driving. Object and image detection requirements are critical and specify the time required to capture data, process it and turn it into action. All of the aforementioned tasks are to be performed while ensuring accuracy, consistency, and cost optimization.

[0004] The capability of a system is often defined by the ability of a sensor, such as a radar system, to detect and classify objects in a field of view. For example, for a radar device , the ability to form and steer the electromagnetic beam determines the range and angular resolution of the device detection performance.

[0005] The signals propagate through the front-end of a wireless transmit and receive system and radiate from antenna elements. The Phase Shifter is a key component of wireless transmit and receive front-end systems. The direction of transmitted radio frequency (RF) signals is controlled by adjusting the transmit signal phase of a plurality of transmitted signals. The Phase Shifter must be calibrated accurately and efficiently in order to provide high performance directional beams and angular resolution with reasonably low calibration time costs. Inaccurate calibration of the Phase Shifter causes non-ideal operation of the wireless system, and lengthy calibration time increases the system cost.Docket No. BMD0302WO SUMMARY

[0006] One aspect provides An analog phase shifter comprising: a quadrature signal generator configured to generate an in-phase signal and a quadrature signal; a first variable gain amplifier configured to receive the in-phase signal and an in-phase pre-distorted amplification coefficient; a second variable gain amplifier configured to receive the quadrature signal and a quadrature pre- distorted amplification coefficient; the first variable gain amplifier is configured to generate an in- phase output signal based on the in-phase pre-distorted amplification coefficient, wherein the in- phase pre-distorted amplification coefficient reduces non-idealities and gain compression behavior of the analog phase shifter; and the second variable gain amplifier is configured to generate a quadrature output signal based on the quadrature pre-distorted amplification coefficient, wherein the quadrature pre-distorted amplification coefficient reduces non-idealities and gain compression behavior of the analog phase shifter.

[0007] Another aspect provides a self-calibrating method for a phase shifter. The method includes generating an in-phase signal and a quadrature signal; defining a plurality of output phase states and a predistortion signal amplitude; computing predistortion phase states and predistortion half phase states corresponding to a predefined output phase resolution; generating a set of predistortion in-phase values based on the predistortion phase states; generating a set of predistortion quadrature values based on the predistortion half phase states; determining, for each predistortion in-phase value in the set of predistortion in-phase values, an in-phase modulation variable based on each predistortion in-phase value, in-phase ideal coefficients, and an in-phase offset; determining, for each predistortion quadrature value in the set of predistortion quadrature values, an quadrature modulation variable based on each predistortion quadrature value, quadrature ideal coefficients, and a quadrature offset; modulating the in-phase signal based on the in-phase modulation variables; and modulating the quadrature signal based on the quadrature modulation variables.

[0008] These and additional features provided by the embodiments described herein will be more fully understood in view of the following detailed description, in conjunction with the drawings.

[0009] Other aspects provide: one or more apparatuses operable, configured, or otherwise adapted to perform any portion of any method described herein (e.g., such that performance mayDocket No. BMD0302WO be by only one apparatus or in a distributed fashion across multiple apparatuses); one or more non- transitory, computer-readable media comprising instructions that, when executed by one or more processors of one or more apparatuses, cause the one or more apparatuses to perform any portion of any method described herein (e.g., such that instructions may be included in only one computer- readable medium or in a distributed fashion across multiple computer-readable media, such that instructions may be executed by only one processor or by multiple processors in a distributed fashion, such that each apparatus of the one or more apparatuses may include one processor or multiple processors, and / or such that performance may be by only one apparatus or in a distributed fashion across multiple apparatuses); one or more computer program products embodied on one or more computer-readable storage media comprising code for performing any portion of any method described herein (e.g., such that code may be stored in only one computer-readable medium or across computer-readable media in a distributed fashion); and / or one or more apparatuses comprising one or more means for performing any portion of any method described herein (e.g., such that performance would be by only one apparatus or by multiple apparatuses in a distributed fashion). By way of example, an apparatus may comprise a processing system, a device with a processing system, or processing systems cooperating over one or more networks. An apparatus may comprise one or more memories; and one or more processors configured to cause the apparatus to perform any portion of any method described herein. In some examples, one or more of the processors may be preconfigured to perform various functions or operations described herein without requiring configuration by software.

[0010] The following description and the appended figures set forth certain features for purposes of illustration. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The embodiments set forth in the drawings are illustrative and exemplary in nature and not intended to limit the subject matter defined by the claims. The following detailed description of the illustrative embodiments can be understood when read in conjunction with the following drawings, where like structure is indicated with like reference numerals.

[0012] FIG. 1 illustrates a block diagram of an analog phase shifter and its functions, in accordance with one or more implementations of the subject technology.Docket No. BMD0302WO

[0013] FIG. 2 illustrates signals in accordance with one or more implementations of the subject technology.

[0014] FIG. 3 illustrates an antenna system having beamforming capability for controlling transmission signals radiating from antenna array.

[0015] FIG. 4 depicts an illustrative flowchart for an example method for self-calibration of the phase shifter for phased-array radar applications. DETAILED DESCRIPTION

[0016] The present disclosure generally relates to systems and methods for controlling the phase of a signal. It is appreciated that the detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configurations in which the subject technology may be practiced. The appended drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the subject of technology. However, the subject technology is not limited to the specific details set forth herein and may be practiced using one or more implementations. In one or more instances, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the subject technology. In other instances, well-known methods and structures may not be described in detail to avoid unnecessarily obscuring the description of the examples. Also, the examples may be used in combination with each other. The examples described herein provide methods for phase control to solve the problems of systems.

[0017] FIG. 1 illustrates an analog phase shifter circuit 150 employing an IQ (In-phase and Quadrature-phase) signal adder architecture. The analog phase shifter circuit 150 consists of a quadrature signal generator circuit 155 that generates a pair of in-phase and quadrature signals from an input signal. The in-phase and quadrature signals each are input to a separate variable gain amplifier (VGA) circuit 160. The signal amplification factor of each VGA may be controlled by a separate digital-to-analog-converter circuit 165. The output of each VGA is summed by a signal summer 170 to generate the output signal. By controlling the gain of each VGA circuit 160 separately, a phase shift of the output signal versus the input signal can be achieved. A computing apparatus 180 may include one or more memories and one or more processors coupled to the oneDocket No. BMD0302WO or more memories. The computing apparatus 180 may be communicatively coupled to the analog phase shifter circuit 150 and configured to carry out one or more methods described herein.

[0018] An analog phase shifter circuit employing an IQ signal adder architecture such as that illustrated in FIG. 1 is a conventional circuit design approach to implement a Radio-Frequency (RF) signal phase shifting function. The calibration process of the IQ adder phase shifter block involves finding the accurate combination of input In-phase (I) and quadrature-phase (Q) signal amplitudes in order to generate the desired output signal with a specific phase. The I and Q signal amplification factors are depicted in FIG.1 as AI and AQ. Conventionally, the calibration process deploys a search algorithm to explore possible values of IQ signal amplification factors, AI and AQ, to achieve the desired output signal phase with minimum phase error. This process is time- consuming because it requires exhaustive measurement of the generated output signal at each (AI , AQ) configuration.

[0019] In the embodiment of the present invention, modulation of the IQ signal amplification factors of the analog IQ adder phase shifter block is utilized to eliminate the calibration process of finding the proper combination of IQ signal amplitude to generate a desired output signal phase. The apparatus introduces a methodology for constructing the IQ signal amplification factors such that the phase shifter block produces a desired output without the need for calibration. The IQ signal amplification coefficients are first created according to the ideal mathematical behavior of the IQ adder transfer function. In the next step, the ideal IQ amplification coefficients, AI and AQ, are pre-distorted to cancel the non-idealities and gain compression behavior of IQ transistor circuitry. In this method, the described pre-distortion function modulates the ideal mathematically derived AI and AQ signals with a non-linear function.

[0020] In one implementation of the aforementioned pre-distortion modulation method, the IQ signal amplitude modulating coefficients, AI and AQ, are generated using the pseudo code steps illustrated below. Let ‘N’ represent the bit-wise precision of the signal amplification factors for the IQ VGA amplifiers 160 shown in FIG. 1. In this case the I-signal and Q-signal each can linearly change between 0 to 2N-1 amplitude states, where ‘0’ denotes the minimum VGA gain and 2N-1 denotes the maximum VGA gain Let ‘M’ represent the bit-wise precision of the output phase resolution. In this case the phase shifter block can generate a signal with 2Mdifferent phase states spanning from 0 to 2π – (2π÷ 2M) with equal phase granularity of (2π)÷ 2M. In this example, 2Mlook-up-table (LUT) entries are generated for the AI and AQ coefficient values to result in 2MDocket No. BMD0302WO output signal phase states. In the pseudo-code below the AI_modulated and AQ_modulated variables each represent a vector of 2Mcoefficients. # Defining output phase states in radian # Output_Phase_States(OPS) = 0 to (2π – (2π ÷ 2M)) with (2π ÷ 2M)step size OPS = [0, 0.0491, 0.0982, 0.1473, …,6.1850, 6.2341] # for M = 7 # Predistortion_Signal_Amplitude(PSA) = 8 PSA = 8 AI_ideal = (2N-1- PSA)*Cosine(OPS) + 2N-1AQ_ideal = (2N-1- PSA)*Sine(OPS) + 2N-1AQ_offset = α AI_offset = β # Creating the pre-distorted signal # Predistortion_Phase_States(PDPS) = 0 to (2π –step size PDPS = [0, 0.0982, 0.1963, …, 6.0868, 6.1850] # for M = 7 # Predistortion_Half_Phase_States(PHPS) = 0 to (π – (2π ÷ 2M-1)) with (2π ÷ 2M-1)step size PHPS = [0, 0.0982, 0.1963, …, 2.9452, 3.0434] # for M = 7 AI_predistortion = Concatenation{PSA*(Sine(PDPS), -1*PSA*(Sine(PDPS)} AI_modulated = Round(AI_ideal + AI_predistortion) - AI_offset AQ_predistortion = Concatenation{-1*PSA*(Sine(PHPS), -1*PSA*(Sine(PDPS), PSA *(Sine(PHPS)} AQ_modulated = round(AQ_ideal - AQ_predistortion) - AQ_offsetDocket No. BMD0302WO LUT = [AI_modulated , AQ_modulated]

[0021] Through the use of the method illustrated by the pseudo code above, the IQ phase calibration process is greatly simplified and time-reduced. Additionally, the above-described method can increase the accuracy of the resulting phase shift.

[0022] FIG. 2 illustrates signals in accordance with one or more implementations of the subject technology. For example, FIG. 2 illustrates illustrative examples of an AI_predistortion signal, AI_modulated signal, AI_ideal signal, AQ_predistortion signal, AQ_modulated, and AQ_ideal signal.

[0023] FIG. 3 illustrates an antenna system 300 having beamforming capability with RFIC beamformer 302, having phase shifter 320, VGA 322, for controlling transmission signals radiating from antenna array 314. The RFIC beamformer 302 includes multiple transmission channels 330 coupled to antenna elements 310 within antenna array 314, wherein each transmission path includes a RFIC beamformer, such as RFIC beamformer 302. In this example, the RFIC beamformer 302 is illustrated in a schematic format with a simplified transmit (Tx) module for purposes of explanation and clarity of understanding; however, an antenna system may include receive (Rx) or a combination of both (Tx / Rx). Each channel of an antenna system is defined by a transmission path from a transceiver (not shown) to an antenna element, such as antenna element 310.

[0024] Along each transmission path 330 corresponding to a channel are phase shift components, which in this example are analog components, and a variable gain amplifier (VGA). The output of each channel is a signal RFoutthat is input to an antenna element, such as signal RFout(n) to antenna element 310. There is one input to each channel. In some embodiments, the <I,Q> signals are defined by the DAC module 316, resulting in 256 states or data points for DAC 320 and 256 states for DAC 324. The <I,Q> performance results in (256*256) which is 65,536 states. The VGA module 322 is actuated by voltage control realized by an 8-bit DAC 312.

[0025] As in the systems described herein, a phase shifter module includes a variable gain amplifier as illustrated in FIG.4. Variable Gain Amplifier (VGA) is a key component of wireless transmit and receive systems. The system controls the signal level of radio frequency (RF) signals by adjusting the bias voltage of the VGA. The signal propagates through a frontend of the system and radiates from antenna elements. Signals processed by RF building blocks are subject to a timeDocket No. BMD0302WO delay which is dictated by the phase of the RF block. The phase of a VGA inherently varies with the gain setting due to the transistor characteristics. This behavior causes non-ideal operation of the wireless system.

[0026] Some multi-path wireless systems, such as a beamforming transmitter / receiver, require each path of a VGA to have independent gain control while maintaining a constant phase across all channels. Using a phase variant VGA in this scenario would require calibrating the entire system across different gain settings to counterbalance the phase offsets created by the VGA. This calibration is a time-consuming process requiring adjustment of a phase shifter, which allows controlling the beam direction, for every gain step. A phase invariant VGA eliminates this calibration process, therefore streamlining the production of a beamforming system.

[0027] FIG. 4 depicts an example method for self-calibrating a phase shifter.

[0028] In this example, method 400 begins at step 410 with generating an in-phase signal and a quadrature signal.

[0029] Method 400 proceeds to step 415 with defining a plurality of output phase states and a predistortion signal amplitude.

[0030] Method 400 proceeds to step 420 with computing predistortion phase states and predistortion half phase states corresponding to a predefined output phase resolution.

[0031] Method 400 proceeds to step 425 with generating a set of predistortion in-phase values based on the predistortion phase states.

[0032] Method 400 proceeds to step 430 with generating a set of predistortion quadrature values based on the predistortion half phase states.

[0033] Method 400 proceeds to step 435 with determining, for each predistortion in-phase value in the set of predistortion in-phase values, an in-phase modulation variable based on each predistortion in-phase value, in-phase ideal coefficients, and an in-phase offset.

[0034] Method 400 proceeds to step 440 with determining, for each predistortion quadrature value in the set of predistortion quadrature values, an quadrature modulation variable based on each predistortion quadrature value, quadrature ideal coefficients, and a quadrature offset.Docket No. BMD0302WO

[0035] Method 400 proceeds to step 445 with modulating the in-phase signal based on the in- phase modulation variables.

[0036] Method 400 proceeds to step 450 with modulating the quadrature signal based on the quadrature modulation variables.

[0037] Note that FIG. 4 is just one example of a method, and other methods including fewer, additional, or alternative steps are possible consistent with this disclosure. Example Clauses

[0038] Implementation examples are described in the following numbered clauses:

[0039] Clause 1: An analog phase shifter comprising: a quadrature signal generator configured to generate an in-phase signal and a quadrature signal; a first variable gain amplifier configured to receive the in-phase signal and an in-phase pre-distorted amplification coefficient; a second variable gain amplifier configured to receive the quadrature signal and a quadrature pre-distorted amplification coefficient; the first variable gain amplifier is configured to generate an in-phase output signal based on the in-phase pre-distorted amplification coefficient, wherein the in-phase pre-distorted amplification coefficient reduces non-idealities and gain compression behavior of the analog phase shifter; and the second variable gain amplifier is configured to generate a quadrature output signal based on the quadrature pre-distorted amplification coefficient, wherein the quadrature pre-distorted amplification coefficient reduces non-idealities and gain compression behavior of the analog phase shifter.

[0040] Clause 2: The analog phase shifter of Clause 1, further comprising a summation component configured to sum the in-phase output signal and the quadrature output signal into an output signal.

[0041] Clause 3: The analog phase shifter of anyone of Clauses 1-2, further comprising a computing apparatus configured to generate the in-phase pre-distorted amplification coefficient, wherein the computing apparatus comprises one or more memories and one or more processors coupled to the one or more memories and configured to cause the computing apparatus to: define a plurality of output phase states and a predistortion signal amplitude; compute predistortion phase states corresponding to a predefined output phase resolution; generate a set of predistortion in- phase values based on the predistortion phase states; and determine, for each predistortion in-Docket No. BMD0302WO phase value in the set of predistortion in-phase values, the in-phase pre-distorted amplification coefficient based on each predistortion in-phase value, in-phase ideal coefficients, and an in-phase offset.

[0042] Clause 4: The analog phase shifter of Clause 3, wherein to define the plurality of output phase states comprises defining the output phase states in radians from 0 to (2π-(2π / 2^M)) with a step size of (2π / 2^M ), where M is the predefined output phase resolution.

[0043] Clause 5: The analog phase shifter of Clause 3, wherein to compute the predistortion in- phase states comprises defining predistortion phase states from 0 to to (2π-(2π / 2^(M-1) )) with a step size of (2π / 2^(M-1) ), where M is the predefined output phase resolution.

[0044] Clause 6: The analog phase shifter of Clause 3, wherein to generate the set of predistortion in-phase values follows: Concatenation{PSA*(sin(PDPS) ), -1*PSA*(sin(PDPS))}, where PSA is the predistortion signal amplitude and PDPS is the predistortion phase states.

[0045] Clause 7: The analog phase shifter of Clause 3, wherein to determine the in-phase pre- distorted amplification coefficient follows: Round(A_(I_ideal)+A_(I_predistortion) )- A_(I_offset), where A_(I_ideal) corresponds to the in-phase ideal coefficients, A_(I_predistortion) corresponds to each predistortion in-phase value, and A_(I_offset) corresponds to the in-phase offset.

[0046] Clause 8: The analog phase shifter of Clause 1, further comprising a computing apparatus configured to generate the quadrature pre-distorted amplification coefficient, wherein the computing apparatus comprises one or more memories and one or more processors coupled to the one or more memories and configured to cause the computing apparatus to: define a plurality of output phase states and a predistortion signal amplitude; compute predistortion half phase states corresponding to a predefined output phase resolution; generating a set of predistortion quadrature values based on the predistortion half phase states; and determine, for each predistortion quadrature value in the set of predistortion quadrature values, an quadrature pre-distorted amplification coefficient based on each predistortion quadrature value, quadrature ideal coefficients, and a quadrature offset.Docket No. BMD0302WO

[0047] Clause 9: The analog phase shifter of Clause 8, wherein to define the plurality of output phase states comprises defining the output phase states in radians from 0 to (2π-(2π / 2^M )) with a step size of (2π / 2^M ), where M is the predefined output phase resolution.

[0048] Clause 10: The analog phase shifter of Clause 8, wherein to compute the predistortion half phase states comprises defining the predistortion half phase states from 0 to to (π-(2π / 2^(M- 1) )) with a step size of (2π / 2^(M-1) ), where M is the predefined output phase resolution.

[0049] Clause 11: The analog phase shifter of Clause 8, wherein to generate the set of predistortion quadrature values follows: Concatenation{-1*PSA*(sin(PHPS) ),- 1*PSA*(sin(PDPS) ),PSA* (sin(PHPS) )}, where PSA is the predistortion signal amplitude, PHPS is the predistortion half phase states, and PDPS is the predistortion phase states.

[0050] Clause 12: The analog phase shifter of Clause 8, wherein to determine the quadrature pre-distorted amplification coefficient follows: Round(A_(Q_ideal)+A_(Q_predistortion) )- A_(Q_offset), where A_(Q_ideal) corresponds to the quadrature ideal coefficients, A_(Q_predistortion) corresponds to each predistortion quadrature value, and A_(Q_offset) corresponds to the quadrature offset.

[0051] Clause 13: A self-calibrating method for a phase shifter, the method comprising: generating an in-phase signal and a quadrature signal; defining a plurality of output phase states and a predistortion signal amplitude; computing predistortion phase states and predistortion half phase states corresponding to a predefined output phase resolution; generating a set of predistortion in-phase values based on the predistortion phase states; generating a set of predistortion quadrature values based on the predistortion half phase states; determining, for each predistortion in-phase value in the set of predistortion in-phase values, an in-phase modulation variable based on each predistortion in-phase value, in-phase ideal coefficients, and an in-phase offset; determining, for each predistortion quadrature value in the set of predistortion quadrature values, an quadrature modulation variable based on each predistortion quadrature value, quadrature ideal coefficients, and a quadrature offset; modulating the in-phase signal based on the in-phase modulation variables; and modulating the quadrature signal based on the quadrature modulation variables.Docket No. BMD0302WO

[0052] Clause 14: The method of Clause 13, wherein defining the plurality of output phase states comprises defining the output phase states in radians from 0 to (2π-(2π / 2^M )) with a step size of (2π / 2^M ), where M is the predefined output phase resolution.

[0053] Clause 15: The method of Clause 13, wherein computing the predistortion in-phase states comprises defining predistortion phase states from 0 to to (2π-(2π / 2^(M-1) )) with a step size of (2π / 2^(M-1) ), where M is the predefined output phase resolution.

[0054] Cause 16: The method of Clause 13, wherein computing the predistortion half phase states comprises defining the predistortion half phase states from 0 to to (π-(2π / 2^(M-1) )) with a step size of (2π / 2^(M-1) ), where M is the predefined output phase resolution.

[0055] Clause 17: The method of Clause 13, wherein generating the set of predistortion in-phase values follows: Concatenation{PSA*(sin(PDPS) ),-1*PSA*(sin(PDPS) ) }, where PSA is the predistortion signal amplitude and PDPS is the predistortion phase states.

[0056] Clause 18: The method of Clause 13, wherein generating the set of predistortion quadrature values follows: Concatenation{-1*PSA*(sin(PHPS) ),-1*PSA*(sin(PDPS) ),PSA* (sin(PHPS) )}, where PSA is the predistortion signal amplitude, PHPS is the predistortion half phase states, and PDPS is the predistortion phase states.

[0057] Clause 19: The method of Clause 13, wherein determining the in-phase modulation variable follows: Round(A_(I_ideal)+A_(I_predistortion) ) - A_(I_offset), where A_(I_ideal) corresponds to the in-phase ideal coefficients, A_(I_predistortion) corresponds to each predistortion in-phase value, and A_(I_offset) corresponds to the in-phase offset.

[0058] Clause 20: The method of Clause 13, wherein determining the quadrature modulation variable follows: Round(A_(Q_ideal)+A_(Q_predistortion) ) - A_(Q_offset), where A_(Q_ideal) corresponds to the quadrature ideal coefficients, A_(Q_predistortion) corresponds to each predistortion quadrature value, and A_(Q_offset) corresponds to the quadrature offset.

[0059] It is appreciated that the previous description of the disclosed examples is provided to enable any person skilled in the art to make or use the present disclosure. Various configurations and transistor scenarios may be improved by the methods and circuits described herein. Various modifications to these examples will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other examples without departing from the spirit orDocket No. BMD0302WO scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. Additional Considerations

[0060] The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and / or “comprising,” or “includes” and / or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof. The term “or a combination thereof” means a combination including at least one of the foregoing elements.

[0061] It is appreciated that the previous description of the disclosed examples is provided to enable any person skilled in the art to make or use the present disclosure. Various configurations and transistor scenarios may be improved by the methods and circuits described herein. Various modifications to these examples will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other examples without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0062] As used herein, the phrase “at least one of” preceding a series of items, with the terms “and” or “or” to separate any of the items, modifies the list as a whole rather than each member of the list (i.e., each item). The phrase “at least one of” does not require the selection of at least one item; rather, the phrase allows a meaning that includes at least one of any one of the items, and / or at least one of any combination of the items, and / or at least one of each of the items. By way of example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.Docket No. BMD0302WO

[0063] Furthermore, to the extent that the term “include,” “have,” or the like is used in the description or the claims, such term is intended to be inclusive in a manner similar to the term “comprise” as “comprise” is interpreted when employed as a transitional word in a claim.

[0064] A reference to an element in the singular is not intended to mean “one and only one” unless specifically stated, but rather “one or more.” The term “some” refers to one or more. Underlined and / or italicized headings and subheadings are used for convenience only, do not limit the subject technology, and are not referred to in connection with the interpretation of the description of the subject technology. All structural and functional equivalents to the elements of the various configurations described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and intended to be encompassed by the subject technology. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the above description.

[0065] While this specification contains many specifics, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of particular implementations of the subject matter. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub combination or variation of a sub combination.

[0066] The subject matter of this specification has been described in terms of particular aspects, but other aspects can be implemented and are within the scope of the following claims. For example, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. The actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. Moreover, theDocket No. BMD0302WO separation of various system components in the aspects described above should not be understood as requiring such separation in all aspects, and it should be understood that the described program components and systems can generally be integrated together in a single hardware product or packaged into multiple hardware products. Other variations are within the scope of the following claim.

Claims

Docket No. BMD0302WO CLAIMS 1. An analog phase shifter comprising: a quadrature signal generator configured to generate an in-phase signal and a quadrature signal; a first variable gain amplifier configured to receive the in-phase signal and an in-phase pre-distorted amplification coefficient; a second variable gain amplifier configured to receive the quadrature signal and a quadrature pre-distorted amplification coefficient; the first variable gain amplifier is configured to generate an in-phase output signal based on the in-phase pre-distorted amplification coefficient, wherein the in-phase pre-distorted amplification coefficient reduces non-idealities and gain compression behavior of the analog phase shifter; and the second variable gain amplifier is configured to generate a quadrature output signal based on the quadrature pre-distorted amplification coefficient, wherein the quadrature pre- distorted amplification coefficient reduces non-idealities and gain compression behavior of the analog phase shifter.

2. The analog phase shifter of claim 1, further comprising a summation component configured to sum the in-phase output signal and the quadrature output signal into an output signal.

3. The analog phase shifter of claim 1, further comprising a computing apparatus configured to generate the in-phase pre-distorted amplification coefficient, wherein the computing apparatus comprises one or more memories and one or more processors coupled to the one or more memories and configured to cause the computing apparatus to: define a plurality of output phase states and a predistortion signal amplitude; compute predistortion phase states corresponding to a predefined output phase resolution; generate a set of predistortion in-phase values based on the predistortion phase states; andDocket No. BMD0302WO determine, for each predistortion in-phase value in the set of predistortion in-phase values, the in-phase pre-distorted amplification coefficient based on each predistortion in-phase value, in- phase ideal coefficients, and an in-phase offset.

4. The analog phase shifter of claim 3, wherein to define the plurality of output phase states comprises defining the output phase states in radians from 0 towith a step size of where M is the predefined output phase resolution.

5. The analog phase shifter of claim 3, wherein to compute the predistortion in-phase states comprises defining predistortion phase states from 0 to to with a step size ofwhere M is the predefined output phase resolution.

6. The analog phase shifter of claim 3, wherein to generate the set of predistortion in-phase values follows: ^^^^^^^^^^^^^^^^^ ∗^sin^^^^^^^, −1 ∗ ^^^ ∗^sin^^^^^^^ ^, where PSA is the predistortion signal amplitude and ^^^^ is the predistortion phase states.

7. The analog phase shifter of claim 3, wherein to determine the in-phase pre-distorted amplification coefficient follows: ^^^^^^^^_^^^^^+ ^^_^^^^^^^^^^^^^^ −corresponds to the in-phase ideal coefficients, ^^_^^^^^^^^^^^^^corresponds to each predistortion in-phase value, and ^^_^^^^^^corresponds to the in-phase offset.

8. The analog phase shifter of claim 1, further comprising a computing apparatus configured to generate the quadrature pre-distorted amplification coefficient, wherein the computing apparatus comprises one or more memories and one or more processors coupled to the one or more memories and configured to cause the computing apparatus to: define a plurality of output phase states and a predistortion signal amplitude;Docket No. BMD0302WO compute predistortion half phase states corresponding to a predefined output phase resolution; generating a set of predistortion quadrature values based on the predistortion half phase states; and determine, for each predistortion quadrature value in the set of predistortion quadrature values, an quadrature pre-distorted amplification coefficient based on each predistortion quadrature value, quadrature ideal coefficients, and a quadrature offset.

9. The analog phase shifter of claim 8, wherein to define the plurality of output phase states comprises defining the output phase states in radians from 0 to with a step size ofwhere M is the predefined output phase resolution.

10. The analog phase shifter of claim 8, wherein to compute the predistortion half phase states comprises defining the predistortion half phase states from 0 to to ^^ − with a step sizewhere M is the predefined output phase resolution.

11. The analog phase shifter of claim 8, wherein to generate the set of predistortion quadrature values follows: ^^^^^^^^^^^^^^−1 ∗ ^^^ ∗^sin^^^^^^^, −1 ∗ ^^^ ∗^sin^^^^^^^,^^^ ∗ ^sin^^^^^^^^, where PSA is the predistortion signal amplitude, ^^^^ is the predistortion half phase states, and ^^^^ is the predistortion phase states.

12. The analog phase shifter of claim 8, wherein to determine the quadrature pre-distorted amplification coefficient follows: ^^^^^^^^_^^^^^+ ^^_^^^^^^^^^^^^^^ − ^^_^^^^^^, where ^^_^^^^^corresponds to the quadrature ideal coefficients, ^^_^^^^^^^^^^^^^corresponds to each predistortion quadrature value, and ^^_^^^^^^corresponds to the quadrature offset.

13. A self-calibrating method for a phase shifter, the method comprising:Docket No. BMD0302WO generating an in-phase signal and a quadrature signal; defining a plurality of output phase states and a predistortion signal amplitude; computing predistortion phase states and predistortion half phase states corresponding to a predefined output phase resolution; generating a set of predistortion in-phase values based on the predistortion phase states; generating a set of predistortion quadrature values based on the predistortion half phase states; determining, for each predistortion in-phase value in the set of predistortion in-phase values, an in-phase modulation variable based on each predistortion in-phase value, in-phase ideal coefficients, and an in-phase offset; determining, for each predistortion quadrature value in the set of predistortion quadrature values, an quadrature modulation variable based on each predistortion quadrature value, quadrature ideal coefficients, and a quadrature offset; modulating the in-phase signal based on the in-phase modulation variables; and modulating the quadrature signal based on the quadrature modulation variables.

14. The method of claim 13, wherein defining the plurality of output phase states comprises defining the output phase states in radians from 0 towith a step sizewhere M is the predefined output phase resolution.

15. The method of claim 13, wherein computing the predistortion in-phase states comprises defining predistortion phase states from 0 with a step sizewhereM is the predefined output phase resolution.

16. The method of claim 13, wherein computing the predistortion half phase states comprises defining the predistortion half phase states from 0 to to ^^ − with a step sizewhere M is the predefined output phase resolution.Docket No. BMD0302WO 17. The method of claim 13, wherein generating the set of predistortion in-phase values follows: ^^^^^^^^^^^^^^^^^ ∗ ^sin^^^^^^^, −1 ∗ ^^^ ∗ ^sin^^^^^^^ ^, where PSA is the predistortion signal amplitude and ^^^^ is the predistortion phase states.

18. The method of claim 13, wherein generating the set of predistortion quadrature values follows: ^^^^^^^^^^^^^^−1 ∗ ^^^ ∗^sin^^^^^^^, −1 ∗ ^^^ ∗^sin^^^^^^^,^^^ ∗^sin^^^^^^^^, where PSA is the predistortion signal amplitude, ^^^^ is the predistortion half phase states, and ^^^^ is the predistortion phase states.

19. The method of claim 13, wherein determining the in-phase modulation variable follows: ^^^^^^^^_^^^^^+ ^^_^^^^^^^^^^^^^^ − ^^_^^^^^^, where ^^_^^^^^corresponds to the in-phase ideal coefficients, ^^_^^^^^^^^^^^^^corresponds to each predistortion in-phase value, and ^^_^^^^^^corresponds to the in-phase offset.

20. The method of claim 13, wherein determining the quadrature modulation variable follows: ^^^^^^^^_^^^^^+ ^^_^^^^^^^^^^^^^^ − ^^_^^^^^^, where ^^_^^^^^corresponds to the quadrature ideal coefficients, ^^_^^^^^^^^^^^^^corresponds to each predistortion quadrature value, and ^^_^^^^^^corresponds to the quadrature offset.

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