A closed-loop control method for zero voltage switching converters

Abstract

Herein is disclosed a controller for an auxiliary resonant commutated pole (ARCP) converter, the controller comprising: a sensor section comprising: a ZVD sensor configured to measure a voltage across a switch of the converter, and detect when the voltage across the switch equals zero; a dv / dt sensor configured to measure a change in the voltage over time across the switch, and detect a voltage transition across the switch; and a gate sensor configured to measure a gate-source voltage of the switch, and detect when the gate-source voltage is sufficient for the switch to transition between OFF and ON; and a control section configured to: receive measurements from the ZVD sensor, the dv / dt sensor, and the gate sensor; and generate a control signal for the switch based at least in part on the measurements received from the ZVD sensor, the dv / dt sensor, and the gate sensor.

Description

A CLOSED-LOOP CONTROL METHOD FOR ZERO VOLTAGE SWITCHING CONVERTERSCross-Reference to Related Applications[1] This application claims priority from application No. 63 / 524,976, filed 5 July 2023. For purposes of the United States, this application claims the benefit under 35 U.S.C. §1 19 of application No. 63 / 524,976, filed 5 July 2023, and entitled Closed-loop Control Method for Zero Voltage Switching Converters, which is hereby incorporated herein by reference for all purposes.Technical Field[2] This disclosure is directed to systems and methods for control of zero voltage switching converters. More particularly, the present disclosure is directed to systems and methods for closed-loop control of zero voltage switching converters.Background[3] Power converters play an important role in various industries such as transportation, entertainment, energy and food chains, as well as in applications like electrical drives, electric vehicles (EVs), renewable energy harvesting, power conditioning, and the like. In recent years, with increased attention to carbon-emission reduction and renewable energy harvesting, their penetration in power systems has been increasing.[4] Because of converter switches’ non-idealities, they generate losses which can be divided into two parts, conduction losses and switching losses. These losses appear as heat on the switches. This heat reduces the lifetime of the switches, and efficiency and the reliability of the converter. In addition to causing heat, the switching losses limit the maximum switching frequency that the converter can run at. The limited switching frequency also hinders the converter’s ability to achieve better output power quality, higher power density, and lower cost.Increasing switching frequency leads to better power quality, smaller passive component values and consequently to a more compact and cost-effective converter.[5] One way to reach higher switching frequency is to reduce the switching losses thereby lowering junction temperature of the switching devices. Lower losses also help to save energy and reduce carbon emissions, thereby making the power system more environmentally friendly. Therefore, reducing losses is of great interest. Besides, considering an increasing number of sensitive loads in a power grid like data processing system, and the like, the electromagnetic compatibility (EMC) of power converters is also an important issue that needs attention.[6] Switching losses in a power semiconductor device arise as a result of the overlapping of rising and falling edges of the voltage across the device with falling and rising edges of the current flowing through the device, respectively.[7] One way to reduce the switching losses is by shortening the overlapping time via increasing rising and falling rates of the current and the voltage. To do so, wide-bandgap devices have been introduced to the market. Although wide-bandgap devices have lower losses compared to silicon-based devices, their utilization involves dealing with problems like electromagnetic interference (EMI) challenges and problems related to rapid changes in voltage over time (referred to as “dv / dt”) which may damage some loads like motors.[8] Another way of reducing the switching losses is adapting a zero voltage switching scheme based on a resonance circuit. A resonance circuit brings the voltage over the switching device to zero before a switching event and eliminates the overlap between transition edges of voltage and current, which leads to zero switching losses. This can be known as “soft-switching”.[9] Several soft-switching methods have been proposed to reduce switching losses in DC / DC, AC / DC, and DC / AC converters. However, many of these methods, which may be referred to as “open-loop control”, use the nominal value of the components and known working points in calculating proper switching times to provide zero voltage switching, while components not only have tolerances in their values but also their values depend on their working conditionslike temperature, voltage, and the like. Furthermore, actual components have parasitic parameters such as output capacitance of the switches, parasitic inductance, and the like, that are also working-condition dependant in nature. Furthermore, these is some deviation on working point because of change in temperature, the nature of a load powered by the converter, and source conditions. Therefore, such open-loop control suffers from partial hard switching and losses induced by incorrect switching times due to the above-referenced deviations.

[0010] There is a need for an improved method of zero voltage switching. Furthermore, there is a need for and improved method of zero voltage switching able to at least partially compensate for errors introduced by non-idealities, component tolerances, dynamically-changing behaviors, and the like.Summary

[0011] According to a part of the disclosure, there is provided a closed-loop zero voltage switching (ZVS) control system suitable for converters with building block of two complementary switches. One embodiment can be a zero-voltage switching auxiliary resonant commutated pole (ARCP)-based converter. ARCP proposed in U.S. Patent No. 5,047,913 by R. De Doncker et al. reduces switching losses for a two-level converter pole. Many open-loop control have been proposed to control this configuration. However, despite complicated mathematic, they suffer from partial hard switching and / or excessive transition time which limits their applications [1-3].

[0012] The converter with proposed control can have any number of phases. Each phase of this converter comprises of a main section, an auxiliary section, a sensor section, and a control section. Main switches synthesize reference voltage at the output of the phase using DC-link voltage. The auxiliary circuit facilitates zero voltage switching of the main switches. The sensor section provides control section with needed data to achieve near-guaranteed optimized zero voltage switching. The control section provides gate signals for the main and the auxiliaryswitches based on the feedback signals from the sensor section to control the main and the auxiliary circuits and to provide desired voltage at the output while guarantee zero voltage switching of the main switches and zero current switching of the auxiliary switches. These tasks are done by regulating switches’ ON and OFF time intervals and overlap interval of ON state of auxiliary and main switches based on the feedback signals. This method finds optimum point for near-guaranteed zero voltage switching using 3 sensors named gate sensor, dv / dt sensor, and zero-voltage-detection sensor.

[0013] According to a part of the disclosure, there is a power conversion device comprising: (a) a power section that is a converter based on auxiliary resonant commutated pole (ARCP); and (ii) the control section which uses information about system state and last switching condition provided by a network of sensors, to provide appropriate gating pulses for power section to synthesize reference output signal, guarantee zero voltage switching of main switches and zero current switching of auxiliary switches.

[0014] The device comprises an arbitrary number of phases converting AC / DC, DC / AC or DC / DC. The control section uses feedback signals dv / dt, gate and ZVD or any number of these sensors applied to control ZVS converters. The control section uses feedback signals gate and ZVD to synthesize reference signal at converter output and guarantee zero voltage switching at any condition and working point. The control section uses feedback signals dv / dt and gate to synthesize reference signal at converter output and guarantee zero voltage switching at any condition and working point. The algorithm is used for dynamically finding optimum transition time.

[0015] One example embodiment of the invention provides a controller for an auxiliary resonant commutated pole (ARCP) converter, the controller comprising: a sensor section comprising: a ZVD sensor configured to measure a voltage across a switch of the converter, and detect when the voltage across the switch equals zero; a dv / dt sensor configured to measure a change in the voltage over time across the switch, and detect a voltage transition across the switch; and a gate sensor configured to measure a gate-source voltage of the switch, and detect when the gate-source voltage is sufficient for the switch to transition between OFF and ON; and a control section configured to: receive measurements from the ZVD sensor, the dv / dt sensor, and the gate sensor; and generate a control signal for the switch based at least in part on the measurements received from the ZVD sensor, the dv / dt sensor, and the gate sensor.

[0016] In some embodiments of the invention, the control section is further configured to receive a load current, a first DC link voltage VC1 , and a second DC link voltage VC2, wherein one or both of VC1 and VC2 can be measured directly or indirectly, and generate the control signal for the switch based at least in part on one or more of the load current, VC1 , and VC2.

[0017] In some embodiments of the invention, the controller is configured to determine one of VC1 and VC2 from a DC voltage.

[0018] In some embodiments of the invention, the switch is a main switch of the converter.

[0019] In some embodiments of the invention, the switch is an auxiliary switch of the converter.

[0020] In some embodiments of the invention, the control section is further configured to: determine a resonance time of the converter; and generate the control signal based at least in part on the resonance time.

[0021] In some embodiments of the invention, the control section further comprises a feedforward section, and control section is further configured to: determine an ideal switch signal for the switch with the feed-forward section; and generate the control signal based at least in part on the ideal switch signal.

[0022] In some embodiments of the invention, the sensor section further comprises a DC-link voltage sensor and a load current sensor, and determining the ideal switch signal for the switch comprises determining the ideal switch signal at least based in part on a DC-link voltage measured with the DC-link voltage sensor and a load current measured with the load current sensor.

[0023] In some embodiments of the invention, determining the ideal switch signal comprises determining the ideal switch signal based at least in part on one or more nominal values of one or more electrical components of the converter.

[0024] In some embodiments of the invention, generating the control signal for the switch comprises determining a charging time for the switch, and generating the control signal comprises generating the control signal based at least in part on the charging time.

[0025] In some embodiments of the invention, generating the control signal for the switch comprises determining a dead time for the switch, and generating the control signal comprises generating the control signal based at least in part on the dead time.

[0026] One example embodiment of the invention provides a controller for an auxiliary resonant commutated pole (ARCP) converter, the controller comprising: a sensor section comprising: a first ZVD sensor configured to measure a voltage across a first switch of the converter, and detect when the voltage across the first switch equals zero; a first dv / dt sensor configured to measure a change in the voltage over time across the first switch, and detect a voltage transition across the first switch; and a first gate sensor configured to measure a gate-source voltage of the first switch, and detect when the gate-source voltage is sufficient for the first switch to transition between OFF and ON; a second ZVD sensor configured to measure a voltage across a second switch of the converter, and detect when the voltage across the second switch equals zero; a second dv / dt sensor configured to measure a change in the voltage over time across the second switch, and detect a voltage transition across the second switch; and a second gate sensor configured to measure a gate-source voltage of the second switch, and detect when the gate-source voltage is sufficient for the second switch to transition between OFF and ON; and a control section configured to: receive measurements from the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor; generate a first control signal for the first switch based at least in part on the measurements received from one or more of: the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor;and generate a second control signal for the second switch based at least in part on the measurements received from one or more of: the first control signal, the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor.

[0027] In some embodiments of the invention, the first switch is one of a first main switch of the converter and a first auxiliary switch of the converter.

[0028] In some embodiments of the invention, the second switch is one of a second main switch of the converter and a second auxiliary switch of the converter.

[0029] One example embodiment of the invention provides a method for controlling an auxiliary resonant commutated pole (ARCP) converter, the method comprising: receiving a ZVD sensor signal from a ZVD sensor, wherein the ZVD sensor signal represents a voltage across a switch of the ARCP converter; receiving a dv / dt sensor signal from a dv / dt sensor, wherein the dv / dt sensor signal represents a change in the voltage over time across the switch; receiving a gate sensor signal from a gate sensor, wherein the gate sensor signal represents a gate-source voltage of the switch; and generating a control signal for the switch based at least in part on the ZVD sensor signal, the dv / dt sensor signal, and the gate sensor signal.

[0030] In some embodiments of the invention, the ZVD sensor signal indicates when the voltage across the switch equals zero.

[0031] In some embodiments of the invention, the dv / dt sensor signal indicates when a voltage transition across the switch occurs.

[0032] In some embodiments of the invention, the gate sensor signal indicates when the voltage is sufficient for the switch to transition between OFF and ON.

[0033] In some embodiments of the invention, the switch is a main switch of the converter.

[0034] In some embodiments of the invention, the switch is an auxiliary switch of the converter.Brief Description of the Drawings

[0036] For a beter understanding of the embodiment(s) described herein and to show more clearly how the embodiment(s) may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings in which:

[0037] FIG. 1A is a schematic diagram of one phase of an auxiliary resonant commutated pole (ARCP) converter according to an example embodiment of the present invention;

[0038] FIG. 1 B is a block diagram of a control system for the ARCP converter depicted in Fig. 1A, according to an example embodiment of the present invention;

[0039] FIG. 2 is a flowchart of a control method for an ARCP converter according to an example embodiment of the present invention;

[0040] FIG. 3 is a flowchart of a feed-forward section of the control method depicted in Fig. 2, according to an example embodiment of the present invention;

[0041] FIG. 4 is a flowchart of a method for determining a dynamic half-resonance time, according to an example embodiment of the present invention;

[0042] FIG. 5 is a schematic diagram of a zero voltage sensor according to an example embodiment of the present invention;

[0043] FIG. 6 is a schematic diagram of a dv / dt sensor according to an example embodiment of the present invention;

[0044] FIG. 7 is a schematic diagram of a gate sensor according to an example embodiment of the present invention.8RECTIFIED SHEET (RULE 91 )

[0044] FIG. 7 is a schematic diagram of a gate sensor according to an example embodiment of the present invention.Description

[0045] For simplicity and clarity of illustration, where considered appropriate, reference numerals may be repeated among the Figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiment or embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein may be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the embodiments described herein. It should be understood at the outset that, although exemplary embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described below.

[0046] Various terms used throughout the present description may be read and understood as follows, unless the context indicates otherwise: “or” as used throughout is inclusive, as though written “and / or”; singular articles and pronouns as used throughout include their plural forms, and vice versa; similarly, gendered pronouns include their counterpart pronouns so that pronouns should not be understood as limiting anything described herein to use, implementation, performance, etc. by a single gender; “exemplary” should be understood as “illustrative” or “exemplifying” and not necessarily as “preferred” over other embodiments. Further definitions for terms may be set out herein; these may apply to prior and subsequent instances of those terms, as will be understood from a reading of the present description. It will also be noted that the use of the term “a” or “an” will be understood to denote “at least one” inall instances unless explicitly stated otherwise or unless it would be understood to be obvious that it must mean “one”.

[0047] Modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

[0048] Herein is disclosed a control circuit and method for zero voltage switching converters. This control method uses one or more feedback sensors which may include: one or more main switch gate sensors, a zero voltage sensor, and a one or more main switch dv / dt sensors, a closed-loop algorithm that makes use of the feedback sensors, in tandem with a feed-forward loop which uses the load current, converter parameters and nominal value of the component, and other algorithms described herein, calculates the next gate timings to achieve nearguaranteed ZVS. A similar method is presented by Hamond et. al. in US Patent No. 10,367,413. However, the method described in the patent has limitations in providing near-guaranteed ZVS because of lack of a sensor (for ARCP case, dv / dt sensor); also, because that method does not have feedforward loop so that, in case of sudden load change, there will be hard switching in some cases. Furthermore, US Patent No. 10,367,413 does not consider all possible causes of failure to achieve soft switching and fails to consider the true nature of components, so that the timing is not optimum. To solve these problems, the present disclosure provides a complete circuit and method for near-guaranteed ZVS for converters with a building-block of two complementary switches. The control method near-guarantees ZVS in nearly all working and environment conditions and manufacturing tolerances including systems with high dynamics of load or DC link voltage, environment with wide temperature change, and component values with large tolerances (e.g. 30%). The ZVS reduces stress on the switches, and further reduces losses and EMI of the converter. In addition, the disclosed circuit and method can reduce manufacturingconverters with synchronous rectifiers, and the like. For example, three of circuit 101 may be pole paralleled on the DC side to comprise a 3-phase inverter, which is a well-known and utilized converter in the industry. Power converter 101 further comprises auxiliary circuit 110 to facilitate zero voltage switching. The methods presented here can be beneficial for all the converters utilizing a similar building-block of two complementary switches.

[0050] In a pole, two semiconductor switches are connected in series between a positive rail and a negative rail of DC link 120, and the middle point is phase output. These two switches always act in complementary mode and synthesize the analog reference waveform by modulation of the DC-link voltage. The auxiliary circuit 110 is connected to the middle point of the DC link 140 and phase output 130. Resonance capacitors 111 , 112 (collectively “Cr”) are connected in parallel with main switches 121 , 122 respectively of the converter. The auxiliary circuit 110 also includes two switches 113, 114 and an inductor 115 which are connected in series, as depicted in Fig. 1A. The converter’s main power semiconductors or switches 121 , 122, with help of the auxiliary circuit 110, switch at zero voltage (soft switching), leading to a considerable reduction of switching losses of the converter and EMIs related to switching.

[0051] In this configuration depicted in Fig. 1A, in order to ensure that the main switches 121 , 122 of the converter switch at zero voltage, the resonant inductor (“Lr”) 115 has to be charged to a calculated level of current before starting switch state transition in the main switches 121 , 122, and enough time for transition should be provided. Several control methods proposed for such a converter use an open-loop approach and calculate the time required to charge this current into the resonance inductor and the transition time based on nominal value of the components and the load current; see references [A], [B] and [C] below. There are tolerances in any given passive component’s values and in some active components like MosFET’s drainsource capacitor values are variable. These variations lead to calculation errors which further lead to errors in the calculated time causing one or more of: partial hard switching, extra conduction and switching losses, stress on the components, and high dv / dt. For example, a manufacturing positive tolerance in the inductor inductance value can cause that inductor to be nRECTIFIED SHEET (RULE 91 )in any given passive component’s values and in some active components like MosFET’s drainsource capacitor values are variable. These variations lead to calculation errors which further lead to errors in the calculated time causing one or more of: partial hard switching, extra conduction and switching losses, stress on the components, and high dv / dt. For example, a manufacturing positive tolerance in the inductor inductance value can cause that inductor to be undercharged compared to the actual required current. Since energy stored in the inductor is not enough to do the soft-switching, there will be partial hard switching with high dv / dt.

[0052] In a pole, the switches act in complimentary mode, it means in every instant only one switch is on. In the transition from one switch to another one, a time interval called deadtime is inserted in which neither of the main switches is ON. The proposed control method adjusts the timing for switching the main switches 121 , 122 based on the last and / or history of transition / s condition and predicted transition time for next step to achieve near-guaranteed zero voltage switching. The described approach considerably reduces switching and conduction losses, voltage stress on the switches, EMI, filtering of dv / dt and heat management requirements, and makes the converter more compact and efficient compared to soft-switching converters controlled by open-loop methods.

[0053] Fig. 1 B shows a block diagram of the disclosed system. As Fig. 1 B shows, the system includes three sections named power section 101 , control section 102, and sensor section 103. Fig. 1A shows an embodiment of a pole of power section 101. As Fig. 1A shows, the pole includes two sections named main section 120 and auxiliary section 110. The main section includes two switches T1 121 and T2 122, two associated antiparallel diodes 125 and 126, and two DC-link capacitors C1 123 and C2 124 which can be shared with other poles in the converter structure. The auxiliary section 110 includes two resonance capacitors 111 , 112 shown as Cr1 and Cr2 in parallel with the main switches 121 , 122 shown as T1 and T2 respectively, two auxiliary switches 113, 114 shown as Ta1 and Ta2 respectively and, two auxiliary diodes 116, 117 shown as Da1 and Da2, and one resonance inductor 115 shown as Lr. Main switches 121 , 122 are connected in series between positive rail of the DC link 150 and negative rail 160 of the DC link 140 in the manner that the drain of the upper switch 121 is connected to the positive railsimilar capacitors connected in series between the positive rail 150 of the DC link 140 and the negative rail 160 of the DC link 140. These capacitors split the DC link voltage into two voltages, VC1 171 and VC2 172 respectively, where each nominally should be VDC / 2.

[0055] Auxiliary switches and diodes along with resonance inductor make auxiliary branch which is connected between output point 130 of the converter and the middle point of the DC link 140 (midpoint). In this branch, an auxiliary diode (117,118) is connected in parallel with each auxiliary switch (113,114) respectively. Auxiliary switches are used to charge the inductor 115 to a predetermined required current level to fully discharge and charge resonance capacitors as required. This current is called the Auxiliary Branch Current (lx). To calculate this current, the load current (“IL”) that flows on branch 130 needs to be sensed and fed back to the control algorithm. Afterwards, the charging time can be calculated considering mid-point voltage and the transition time also can be calculated considering lx and the resonance time of LC tank comprising resonance inductor 115 and capacitors 111 ,112.

[0056] Sensor section 103 determines various electrical measurements of power section 101 and provides the electrical measurements to control section 102 for control of power section 101 . The electrical measurements may include:• VDS-TI - a voltage across diode D1 , 125, also being the voltage between the source and drain of switch T1 , 121 ;• VGS-TI - a voltage between the ground and source of switch T1 , 121 ;• VDS-T2 - a voltage across diode D2, 126, also being the voltage between the source and drain of switch T2, 122;• VGS T2- a voltage between the ground and source of switch T2, 122;• a signal from one or more ZVD sensors, which measure a voltage over a main switch of the converter and detect the time the voltage over the switch reached zero;• a signal from one or more a dv / dt sensors, which uses measured a voltage over a main switch of the converter and quantifies the time of the voltage transition over the switch, and13RECTIFIED SHEET (RULE 91 )• a signal from one or more ZVD sensors, which measure a voltage over a main switch of the converter and detect the time the voltage over the switch reached zero;• a signal from one or more a dv / dt sensors, which uses measured a voltage over a main switch of the converter and quantifies the time of the voltage transition over the switch, and• a signal from one or more gate sensors, which measure a gate-source voltage of a main switch of the converter and detects turn ON and turn OFF times of the switch, optionally considering the miller effect.

[0057] Control section 102 utilizes the signals provided by sensor section 103 along with a control algorithm to control main and auxiliary sections. Fig. 2 shows an example embodiment of the control algorithm. After getting VC1 and VC2 voltages and load current IL from sensors 103 associated with 171 , 172 and 173, respectively, in Fig. 1A by 201 , feed-forward section 202 provides charging time and dead time (CT and DT, respectively) timing for next switching occurrence based on load current and VC1 and VC2 voltages and the nominal value of the components. However, in the reality the components have non-idealities and tolerances in their nominal values which leads to error in the calculated times and thus failure to ZVS. Therefore, a closed-loop section or block 203 is devised to compensate for such errors. Since there is a closed-loop section to compensate for errors, the formulation in the feed-forward section can be simplified compared to known open-loop methods. There is no need to consider circuit loss effect on timing and precise calculation of timing is not needed.

[0058] In some embodiments a control section may be used to keep DC capacitor voltages balanced; midpoint balance control block 204 such as, but not limited to, the control system described in US 63 / 451 ,758, the content of which is incorporated by reference herein in its entirety.

[0059] After calculating final charging time and dead time (CT’ and DT’, respectively), gating pulses are generated by block 207 considering the reference voltages.

[0060] Fig. 3 shows the feed-forward section of the control algorithm. In some embodiments the charging time CT can be calculated by the general equation CT = IL / VCXand the transition timeDT (dead-time between main switches- i.e., when both switches 121 , 122 are in an OFF state) equal to the half of the resonance time DT = Obviously half of the resonance timedepends on the resonance components value Lr and Cr. In some embodiments, after getting VC1 and VC2 and load current IL value from sensors (block 301), control algorithm examines whether the load current is going to help transition or not (block 302). If the IL helps transition, feed-forward control assigns zero to CT and half of the resonance time to the DT (block 303). In another embodiment CT can get negative values and CT and DT will be calculated by block 306 instead block 303. If IL does not help switching transition, CT is calculate by formula mentioned above in block 304. This section or block 305 outputs approximate DT and CT values which will be fed to closed-loop section or block 203 of FIG. 2.

[0061] The algorithm also finds the actual resonance time of the resonance circuit using the measurements. This value is a land mark for the algorithm to keep transition time almost constant and avoid high dv / dt. This detection can be done using dv / dt and gate sensors and along with load current measurement, or alternatively, zvd and gate sensors along with load current measurement.

[0062] Using these sensors, the closed loop algorithm determines the cause of the failure to perfect ZVS is because of the one or couple of the following reasons: short / long transition time, short / long charging time, short / long discharging time. For example, if gate sensor senses that the main switch is turned ON before drain-source voltage of that switch drop to zero, there is two possibility charging time is low or transition time is shorter than needed; using the other sensor information, Algorithm detect exact cause and takes compensatory measures.

[0063] Since it is difficult to know or measure the value of the resonance components (Lr and Cr), especially when mass production is involved, then it is favorable to detect or estimate the half resonance time value by means of utilizing feedback sensors. Hence, in some embodimentsHalf of the Resonance time (“HR”) is found dynamically while the inverter is switching in order to consider effect of the components’ manufacturing tolerances, main and auxiliary switches response delays and other non-idealities on the HR. Fig.4 shows the algorithm for finding HR, dynamically. HR will be equal 405 to dv / dt 401 only if zero voltage is detected before gate threshold is reached (POL=1) 402 and IL is larger than minimum value 403 (or smaller than negative of minimum value), CT is bigger than zero and less than maximum allowable value 404. If the embodiment includes finding HR dynamically, 400, then the value found for HR is replacing the value of half the resonance time found in 306 for DT. Algorithm 400 can also be run for each phase individually in the case of multi-phase inverter, hence optimizing each phase for its own Lr and Cr, as well as switching delays and other non-idealities.

[0064] Closed-loop block 203 uses the information provided by sensors to figure out the effect of the circuit non-idealities and tolerance on the ZVS quality, then it manipulates the timing provided by the feed-forward section to attempt to get near-guaranteed optimum ZVS.

[0065] In some embodiments feed-forward section 202 can be omitted and ZVS is achieved using only the closed-loop section 203. In these embodiments Initial deadtime is set to maximum expected deadtime with zero charging time, then control system uses feedback values from sensors to initiate close-loop control.

[0066] By applying firing pulses generated by block 207 in FIG. 2, the effect of non-idealities is compensated for and optimum ZVS is near-guaranteed. Therefore, compared to open-loop ZVS converter, in the present embodiments stress on the component is lower and converter will have longer lifetime. Furthermore, conduction and switching losses, and EMI will be lower.

[0067] Closed-loop section uses information provided by sensor section to guarantee zero voltage switching. To determine exact switching behavior, three types of sensors are needed, namely: (1) a ZVD sensor which measure voltage over the main switches and detect the time voltage over the switch reached zero, (2) a dv / dt sensor which uses measured voltage over the main switch and quantifies the time of the voltage transition over the switch, and (3) a gatesensor which measures gate-source voltage of the main switches and detect turn ON and turn OFF times of the switch considering miller effect.

[0068] Fig. 5 shows one embodiment of a ZVD sensor. The sensor comprises a comparator which compares drain voltage of a transistor with a reference voltage and outputs logic “1 ” if the drain voltage is more than reference voltage. To keep electronic circuit safe and within an allowable voltage range, drain high voltage is reflected in the C1 using R1 , D3, and D4. Whenever drain voltage is more than around 5V, diode D3 stops conducting and capacitor C1 voltage is clamped at almost 5V, and when drain voltage is less than 5V, D3 conducts and C1 voltage follows drain voltage. Therefore, drain zero voltage which interest us can be sensed by sensing C1 voltage.

[0069] Fig. 6 shows one embodiment of a dv / dt sensor. It includes of a comparator and a high- pass filter. The shown dv / dt sensor only detects falling edges which is of interest to a closed- loop algorithm. When drain voltage is transition, high-pass filter absorbs current from resistor R2 and capacitor C3 causing C3’s voltage to fall below the reference voltage of the comparator. Therefore, comparator outputs logic “1 ”, in this case. When drain voltage is settled, C1 does not pass current (i.e., there is no current flowing through C1 when the voltage across C1 is constant) and voltage of C3 settles at 5V which is above reference voltage of the comparator, and therefore, the comparator outputs logic “0” . Use of this sensor is critical to the embodiment and correct operation of ZVS, as it enables to differentiate and compensate non-ideal-ZVS cases.

[0070] Fig. 8 shows the gate signal sensor. This sensor comprises of a comparator, a voltage divider, and a low-pass filter. The voltage divider conditions gate signal into acceptable limits. When voltage level of the gate is more than the reference voltage which is regulated to end of the miller plateau, the comparator outputs logic “1 ”. Comparator has a hysteresis made by resistor R5. The hysteresis is in such an amount that falling edge threshold of the comparator is at lower level of the miller plateau. Therefore, if the gate voltage is less than the lower limit of the miller plateau, comparator outputs logic “0”. Using these sensors, failure to achieve perfectZVS and its cause can be detected. However, in some embodiment, there is no need to use all of these sensors.

[0071] In an aspect, there is provided a control method for zero voltage switching converter which compensate deleterious effects of the component non-idealities, changing characteristics, due to temperature, voltage and current working point, as well as delays in the switching circuit. This control can be utilized in any converter with a pole of two complementary switches. One embodiment is a converter based on auxiliary resonant commutated pole (ARCP) with an arbitrary number of phases in which each phase includes two main switches with associated anti-parallel diodes that are connected between the phase output and positive and negative rails of a DC link. The switches can be, for example, IGBT or MOSFET. Two resonance capacitors are connected in paralleled with each main switch. In another aspect, there is provided a DC link with split voltage that has two capacitors, one connected in series between a positive rail of the DC link and a midpoint, and the other between the midpoint and the negative rail. An auxiliary branch can include two switches and a variable inductor that is connected between a midpoint of the DC link and an output of the phase. In an aspect of a control method, one can use only feed-back section and omit the feedforward section. Furthermore, in some embodiment depending on acceptable partial hard switching one or more of sensors may be omitted. Since the closed-loop section is a logic-based method and open-loop section benefits from very simple mathematical computations, the control is well- suited for digital implementation and high-speed switching application.

[0072] Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages.

[0073] Persons skilled in the art will appreciate that there are yet more alternative implementations and modifications possible, and that the above examples are only illustrations of one or more implementations. The scope, therefore, is only to be limited by the claims appended hereto and any amendments made thereto.Interpretation of Terms

[0074] Unless the context clearly requires otherwise, throughout the description and the claims:• “comprise”, “comprising”, and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”;• “connected”, “coupled”, or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, or a combination thereof;• “herein”, “above”, “below”, and words of similar import, when used to describe this specification, shall refer to this specification as a whole, and not to any particular portions of this specification;• “or”, in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list;• the singular forms “a”, “an”, and “the” also include the meaning of any appropriate plural forms.

[0075] Words that indicate directions such as “vertical”, “transverse”, “horizontal”, “upward”, “downward”, “forward”, “backward”, “inward”, “outward”, “vertical”, “transverse”, “left”, “right”, “front”, “back”, “top”, “bottom”, “below”, “above”, “under”, and the like, used in this description and any accompanying claims (where present), depend on the specific orientation of the apparatus described and illustrated. The subject matter described herein may assume various alternative orientations. Accordingly, these directional terms are not strictly defined and should not be interpreted narrowly.

[0076] Embodiments of the invention may be implemented using specifically designed hardware, configurable hardware, programmable data processors configured by the provision of software (which may optionally comprise “firmware”) capable of executing on the data processors, specialpurpose computers or data processors that are specifically programmed, configured, or constructed to perform one or more steps in a method as explained in detail herein and / or combinations of two or more of these. Examples of specifically designed hardware are: logic circuits, application-specific integrated circuits (“ASICs”), large scale integrated circuits (“LSIs”), very large scale integrated circuits (“VLSIs”), and the like. Examples of configurable hardware are: one or more programmable logic devices such as programmable array logic (“PALs”), programmable logic arrays (“PLAs”), and field programmable gate arrays (“FPGAs”)). Examples of programmable data processors are: microprocessors, digital signal processors (“DSPs”), embedded processors, graphics processors, math co-processors, general purpose computers, server computers, cloud computers, mainframe computers, computer workstations, and the like. For example, one or more data processors in a control circuit for a device may implement methods as described herein by executing software instructions in a program memory accessible to the processors.

[0077] For example, while processes or blocks are presented in a given order, alternative examples may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternative or subcombinations. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times.

[0078] In addition, while elements are at times shown as being performed sequentially, they may instead be performed simultaneously or in different sequences. It is therefore intended that the following claims are interpreted to include all such variations as are within their intended scope.

[0079] Where a component (e.g. a switch, processor, assembly, device, circuit, etc.) is referred to above, unless otherwise indicated, reference to that component (including a reference to a “means”) should be interpreted as including as equivalents of that component any component which performs the function of the described component (i.e., that is functionally equivalent),including components which are not structurally equivalent to the disclosed structure which performs the function in the illustrated exemplary embodiments of the invention.

[0080] Various features are described herein as being present in “some embodiments”. Such features are not mandatory and may not be present in all embodiments. Embodiments of the invention may include zero, any one or any combination of two or more of such features. This is limited only to the extent that certain ones of such features are incompatible with other ones of such features in the sense that it would be impossible for a person of ordinary skill in the art to construct a practical embodiment that combines such incompatible features. Consequently, the description that “some embodiments” possess feature A and “some embodiments” possess feature B should be interpreted as an express indication that the inventors also contemplate embodiments which combine features A and B (unless the description states otherwise or features A and B are fundamentally incompatible).

[0081] It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions, omissions, and subcombinations as may reasonably be inferred. The scope of the claims should not be limited by the preferred embodiments set forth in the examples, but should be given the broadest interpretation consistent with the description as a whole.References

[0082] [A] T. D. Batzel and K. Adams, "Variable timing control for ARCP voltage source inverters operating at low DC voltage, "2012 IEEE Transportation Electrification Conference and Expo (ITEC), Dearborn, Ml, USA, 2012, pp. 1-8, doi: 10.1109 / ITEC.2012.6243478.

[0083] [B] Ke Ma, Dehong Xu, Tao Zhang and S. Igarashi, "The evaluation of control strategies for Auxiliary Resonant Commutated Pole inverter, "2009 IEEE Energy Conversion Congress and Exposition, San Jose, CA, 2009, pp. 810-816, doi: 10.1109 / ECCE.2009.5315974.

[0084] [C] J. Voss, J. Henn and R. W. De Doncker, "Control techniques of the auxiliary-resonant commutated pole with special regards on the dual-active bridge DC-DC converter," in CPSS Transactions on Power Electronics and Applications, vol. 3, no. 4, pp. 352-361 , Dec. 2018, doi: 10.24295 / CPSSTPEA.2018.00034.

Claims

Claims1 . A controller for an auxiliary resonant commutated pole (ARCP) converter, the controller comprising: a sensor section comprising: a ZVD sensor configured to measure a voltage across a switch of the converter, and detect when the voltage across the switch equals zero; a dv / dt sensor configured to measure a change in the voltage over time across the switch, and detect a voltage transition across the switch; and a gate sensor configured to measure a gate-source voltage of the switch, and detect when the gate-source voltage is sufficient for the switch to transition between OFF and ON; and a control section configured to: receive measurements from the ZVD sensor, the dv / dt sensor, and the gate sensor; and generate a control signal for the switch based at least in part on the measurements received from the ZVD sensor, the dv / dt sensor, and the gate sensor.

2. The controller according to claim 1 , wherein the control section is further configured to receive a load current, a first DC link voltage VC1 , and a second DC link voltage VC2, wherein one or both of VC1 and VC2 can be measured directly or indirectly, and generate the control signal for the switch based at least in part on one or more of the load current, VC1 , and VC2.

3. The controller according to claim 2, wherein the controller is configured to determine one of VC1 and VC2 from a DC voltage.

4. The controller according to any one of claims 1 to 3, wherein the switch is a main switch of the converter.

5. The controller according to any one of claims 1 to 3, wherein the switch is an auxiliary switch of the converter.

6. The controller according to any one of claims 1 to 5, wherein the control section is further configured to: determine a resonance time of the converter; and generate the control signal based at least in part on the resonance time.

7. The controller according to any one of claims 1 to 6, wherein the control section further comprises a feed-forward section, and control section is further configured to: determine an ideal switch signal for the switch with the feed-forward section; and generate the control signal based at least in part on the ideal switch signal.

8. The controller according to claim 7, wherein the sensor section further comprises a Delink voltage sensor and a load current sensor, and determining the ideal switch signal for the switch comprises determining the ideal switch signal at least based in part on a Delink voltage measured with the DC-link voltage sensor and a load current measured with the load current sensor.

9. The controller according to either of claims 7 and 8, wherein determining the ideal switch signal comprises determining the ideal switch signal based at least in part on one or more nominal values of one or more electrical components of the converter.

10. The controller according to any one of claims 1 to 9, wherein generating the control signal for the switch comprises determining a charging time for the switch, and generating thecontrol signal comprises generating the control signal based at least in part on the charging time.

11. The controller according to any one of claims 1 to 10, wherein generating the control signal for the switch comprises determining a dead time for the switch, and generating the control signal comprises generating the control signal based at least in part on the dead time.

12. A controller for an auxiliary resonant commutated pole (ARCP) converter, the controller comprising: a sensor section comprising: a first ZVD sensor configured to measure a voltage across a first switch of the converter, and detect when the voltage across the first switch equals zero; a first dv / dt sensor configured to measure a change in the voltage over time across the first switch, and detect a voltage transition across the first switch; and a first gate sensor configured to measure a gate-source voltage of the first switch, and detect when the gate-source voltage is sufficient for the first switch to transition between OFF and ON; a second ZVD sensor configured to measure a voltage across a second switch of the converter, and detect when the voltage across the second switch equals zero; a second dv / dt sensor configured to measure a change in the voltage over time across the second switch, and detect a voltage transition across the second switch; and a second gate sensor configured to measure a gate-source voltage of the second switch, and detect when the gate-source voltage is sufficient for the second switch to transition between OFF and ON; and a control section configured to:receive measurements from the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor; generate a first control signal for the first switch based at least in part on the measurements received from one or more of: the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor; and generate a second control signal for the second switch based at least in part on the measurements received from one or more of: the first control signal, the first ZVD sensor, the second ZVD sensor, the first dv / dt sensor, the second dv / dt sensor, the first gate sensor, and the second gate sensor.

13. The controller according to claim 12, wherein the first switch is one of a first main switch of the converter and a first auxiliary switch of the converter.

14. The controller according to either of claims 12 and 13, wherein the second switch is one of a second main switch of the converter and a second auxiliary switch of the converter.

15. A method for controlling an auxiliary resonant commutated pole (ARCP) converter, the method comprising: receiving a ZVD sensor signal from a ZVD sensor, wherein the ZVD sensor signal represents a voltage across a switch of the ARCP converter; receiving a dv / dt sensor signal from a dv / dt sensor, wherein the dv / dt sensor signal represents a change in the voltage over time across the switch; receiving a gate sensor signal from a gate sensor, wherein the gate sensor signal represents a gate-source voltage of the switch; and generating a control signal for the switch based at least in part on the ZVD sensor signal, the dv / dt sensor signal, and the gate sensor signal.

16. The method according to claim 15, wherein the ZVD sensor signal indicates when the voltage across the switch equals zero.

17. The method according to either of claims 15 and 16, wherein the dv / dt sensor signal indicates when a voltage transition across the switch occurs.

18. The method according to any one of claims 15 to 17, wherein the gate sensor signal indicates when the voltage is sufficient for the switch to transition between OFF and ON.

19. The method according to any one of claims 15 to 18, wherein the switch is a main switch of the converter.

20. The method according to any one of claims 15 to 18, wherein the switch is an auxiliary switch of the converter.

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