Multi-antenna signal cascade apparatus based on linear frequency modulation signal

Abstract

The present invention relates to the technical field of signal processing. Provided are a multi-antenna signal cascade apparatus based on a linear frequency modulation signal. The multi-antenna signal cascade apparatus comprises: a plurality of linear frequency modulation chips, which are cascaded in sequence, wherein each of the linear frequency modulation chips is connected to a receiving antenna and is used for processing a linear frequency modulation signal received by the receiving antenna, so as to obtain a corresponding signal frequency component, and the last cascaded linear frequency modulation chip is further used for combining the signal frequency components obtained by performing processing by means of the remaining linear frequency modulation chips, so as to obtain a linear frequency modulation signal having a preset signal-to-noise ratio. The beneficial effects of the present invention lie in that input linear frequency modulation signals are received by using multiple antennas, and multiple linear frequency modulation chips are cascaded to combine the input linear frequency modulation signals, such that the signal-to-noise ratios of the signals can be effectively increased while reducing the number of interfaces required on the linear frequency modulation chips and reducing the design complexity, thereby increasing the transmission distance of a system.

Description

A multi-antenna signal cascade device based on linear frequency modulation signal Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a multi-antenna signal cascade device based on linear frequency modulation signals. Background Art

[0002] In common communication systems, a single antenna is typically used for transmission and reception. This approach offers the advantage of simplicity, but lacks directivity. It's impossible to achieve directivity for a single antenna by controlling the phases of multiple antennas to increase the transmit and receive power in a particular direction, thereby improving the system's gain and transmission range. To further improve the gain of communication systems, existing technologies often utilize multi-antenna transceiver systems, such as MIMO (Multiple-Input Multiple-Output) technology. MIMO uses multiple antennas at both the transmitter and receiver, creating multiple channels between the transmitter and receiver, significantly increasing channel capacity. MIMO systems utilize the multipath effect of signals to improve system communication quality. In a MIMO system, both the transmitter and receiver communicate using multiple, simultaneously operating antennas. The transmitter transmits multiple RF signals simultaneously, and the receiver combines these signals to improve the signal-to-noise ratio. However, existing signal combining methods are complex and the signal-to-noise ratio cannot be flexibly adjusted.

[0003] Summary of the Invention

[0004] To address the problems existing in the prior art, the present invention provides a multi-antenna signal cascade device based on a linear frequency modulation signal, comprising a plurality of linear frequency modulation chips, each of which is cascaded in sequence. Each linear frequency modulation chip is connected to a receiving antenna and is configured to process the linear frequency modulation signal received by the receiving antenna to obtain a corresponding signal frequency component. The last linear frequency modulation chip in the cascade is further configured to combine the signal frequency components processed by the remaining linear frequency modulation chips to obtain a linear frequency modulation signal with a preset signal-to-noise ratio.

[0005] Preferably, each of the linear frequency modulation chips includes:

[0006] a signal processing module, wherein an input end of the signal processing module is connected to the receiving antenna, and an output end of the signal processing module is respectively connected to the first conversion interface and the signal combining module;

[0007] The first conversion interfaces of the remaining linear frequency modulation chips except the last linear frequency modulation chip are cascaded in sequence, so as to receive the signal frequency component output by the previous linear frequency modulation chip and the signal frequency component of the same through the first conversion interface and send them to the next linear frequency modulation chip;

[0008] An input end of the signal merging module of the last linear frequency modulation chip is connected to the first conversion interface of the previous linear frequency modulation chip to receive the signal frequency components sent by the previous linear frequency modulation chip and its own signal frequency components, and perform merging processing to obtain a linear frequency modulation signal with the preset signal-to-noise ratio.

[0009] Preferably, the system further includes a control chip, which is connected to each of the linear frequency modulation chips respectively, and the output end of the signal processing module of each of the linear frequency modulation chips is connected to the first conversion interface through a first switch, and is connected to the signal merging module through a second switch;

[0010] The control chip includes a control unit for controlling the first switch of the last linear frequency modulation chip to be opened and the second switch to be closed, and controlling the first switch of each of the remaining linear frequency modulation chips to be closed and the second switch to be opened, so as to realize sequential cascading of the linear frequency modulation chips.

[0011] Preferably, the control chip further includes a calculation unit connected to the control unit, configured to calculate the number of cascaded chips based on a required signal-to-noise ratio and a pre-acquired single signal signal-to-noise ratio of each linear frequency modulation chip, and determine the last linear frequency modulation chip based on the number of cascaded chips;

[0012] The control unit is further configured to control the first switch of the last linear frequency modulation chip to be opened and the second switch to be closed, and to control the first switch of the remaining linear frequency modulation chips before the chip number to be closed and the second switch to be opened.

[0013] Preferably, the control chip further comprises a storage unit connected to the calculation unit, for storing the chip numbers of the linear frequency modulation chips, wherein the chip numbers are arranged in sequence according to the cascade order;

[0014] The calculation unit determines the chip number of the last linear frequency modulation chip according to the number of the cascaded chips and sends the chip number to the control unit.

[0015] Preferably, the calculation unit calculates the number of cascade chips according to the following calculation formula:

[0016] in,

[0017] Among them, m is used to represent the number of cascaded chips, SNR1 is used to represent the required signal-to-noise ratio, SNR2 is used to represent the single signal signal-to-noise ratio, s is used to represent the signal frequency component, and n is used to represent the single signal noise of the linear frequency modulation chip.

[0018] Preferably, the signal processing module includes a radio frequency front end, an analog-to-digital converter, a digital filter, a digital intermediate frequency mixer and a Fourier transform unit connected in sequence, the radio frequency front end is connected to the corresponding receiving antenna as the input end of the signal processing module, and the output end of the Fourier transform unit is the output end of the signal processing module.

[0019] Preferably, the signal merging module comprises a maximum ratio merging unit and a digital demodulator connected in sequence, and an input end of the maximum ratio merging unit is connected to an output end of the signal processing module.

[0020] Preferably, the system further includes a plurality of second conversion interfaces, wherein the input end of the signal merging module of the last linear frequency modulation chip in the cascade is connected to the first conversion interface of the previous linear frequency modulation chip via the corresponding second conversion interface, and the first conversion interfaces of the remaining linear frequency modulation chips are respectively connected to the first conversion interfaces of adjacent linear frequency modulation chips via the corresponding second conversion interfaces.

[0021] Preferably, the first conversion interface is a parallel-to-serial conversion interface, and the second conversion interface is a parallel-to-serial conversion interface.

[0022] The above technical solution has the following advantages or beneficial effects:

[0023] 1) The input linear frequency modulation signal is received by multiple antennas and multiple linear frequency modulation chips are cascaded to merge the input linear frequency modulation signals. This can reduce the number of interfaces required on the linear frequency modulation chip, reduce the complexity of the design, and effectively improve the signal-to-noise ratio of the signal, thereby increasing the transmission distance of the system;

[0024] 2) Transmitting the frequency components of the linear frequency modulation signal instead of the linear frequency modulation signal itself can reduce the amount of transmitted data, reduce computing delay and computing power consumption;

[0025] 3) The number of cascaded linear frequency modulation chips can be flexibly adjusted based on the required signal-to-noise ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a schematic structural diagram of a multi-antenna signal cascade device based on a linear frequency modulation signal in a preferred embodiment of the present invention;

[0027] FIG2 is a schematic structural diagram of a control chip in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0029] In a preferred embodiment of the present invention, in response to the above-mentioned problems existing in the prior art, a multi-antenna signal cascade device based on a linear frequency modulation signal is provided. As shown in Figures 1 and 2, the device includes a plurality of linear frequency modulation chips 100. The linear frequency modulation chips 100 are sequentially cascaded. Each linear frequency modulation chip 100 is connected to a receiving antenna 200 and is configured to process the linear frequency modulation signal received by the receiving antenna 200 to obtain corresponding signal frequency components. The last linear frequency modulation chip 100 in the cascade is further configured to combine the signal frequency components processed by the remaining linear frequency modulation chips 100 to obtain a linear frequency modulation signal with a preset signal-to-noise ratio.

[0030] Specifically, in this embodiment, multiple chirp chips 100 are sequentially cascaded, so that, except for the last chirp chip 100, each of the remaining chirp chips 100 only needs to process the chirp signal it receives to obtain the corresponding signal frequency components and then send them to the next chirp chip 100 in the cascade. Similarly, the last chirp chip 100 can receive the signal frequency components of the remaining chirp chips 100, and then combine them with its own signal frequency components to perform unified signal merging processing. This can achieve single-channel transmission and multi-channel reception, effectively improve the signal-to-noise ratio, and save power consumption.

[0031] In a preferred embodiment of the present invention, each linear frequency modulation chip 100 includes:

[0032] A signal processing module 101, wherein the input end of the signal processing module 101 is connected to the receiving antenna 200, and the output end of the signal processing module 101 is connected to the first conversion interface 102 and the signal combining module 103 respectively;

[0033] The first conversion interfaces 102 of the remaining linear frequency modulation chips 100 except the last linear frequency modulation chip 100 are sequentially cascaded, so as to receive the signal frequency component output by the previous linear frequency modulation chip 100 and its own signal frequency component through the first conversion interface 102 and send them to the next linear frequency modulation chip 100;

[0034] The input end of the signal merging module 103 of the last linear frequency modulation chip 100 is connected to the first conversion interface 102 of the previous linear frequency modulation chip 100 to receive the signal frequency components sent by the previous linear frequency modulation chip 100 and its own signal frequency components, and combine them to obtain a linear frequency modulation signal with a preset signal-to-noise ratio.

[0035] Specifically, in this embodiment, after the signal processing module 101 of each linear frequency modulation chip 100 processes the received linear frequency modulation signal to obtain signal frequency components, there are two optional transmission paths. The first transmission path is to send the signal frequency components to the first conversion interface 102, that is, no signal merging processing is required, and its purpose is to send the signal frequency components obtained by its own processing to the next linear frequency modulation signal. The second transmission path is to send the signal frequency components to the signal merging module 103 for signal fusion processing. One of the two transmission paths is selectively connected.

[0036] As can be seen, the last chirp chip 100 does not need to send signal frequency components to the next chirp chip 100, so its first transmission path is in a non-conductive state. The remaining chirp chips 100 all need to send signal frequency components to the next chirp chip 100, so their first transmission paths need to be conductive. The last chirp chip 100 needs to combine the signal frequency components of the remaining chirp chips 100 with its own signal frequency components, so its second transmission path needs to be conductive. The remaining chirp chips 100 do not need to perform further signal processing, so their second transmission paths do not need to be conductive.

[0037] Therefore, flexible control of linear frequency modulation signal processing can be achieved by controlling the conduction state of the two transmission paths of each linear frequency modulation chip 100. Based on this, a preferred embodiment of the present invention further includes a control chip 300 connected to each linear frequency modulation chip 100. The output end of the signal processing module 101 of each linear frequency modulation chip 100 is connected to the first conversion interface 102 via the first switch S1 and is connected to the signal merging module 103 via the second switch S2.

[0038] The control chip 300 includes a control unit 301 for controlling the first switch S1 of the last linear frequency modulation chip 100 to be opened and the second switch S2 to be closed, and controlling the first switch S1 of each of the remaining linear frequency modulation chips 100 to be closed and the second switch S2 to be opened, so as to realize the sequential cascading of the linear frequency modulation chips 100.

[0039] Specifically, in this embodiment, the conduction state of the two transmission paths is achieved by controlling the opening and closing of the first switch S1 and the second switch S2. Furthermore, because the first switch S1 and the second switch S2 of each chirp chip 100 can be independently controlled, the number of cascaded chips can be flexibly controlled. For example, if there are n chirp chips 100, and they are cascaded sequentially, namely, chirp chip #1, chirp chip #2, to chirp chip #n, in actual use, it is not necessary to make chirp chip #n the last chirp chip. Instead, the signal-to-noise ratio can be flexibly adjusted based on the required signal-to-noise ratio.

[0040] More specifically, the number of cascaded chips is flexibly adjusted by the control chip 300. In a preferred embodiment of the present invention, the control chip 300 further includes a calculation unit 302, connected to the control unit 301, configured to calculate the number of cascaded chips based on a required signal-to-noise ratio and a pre-acquired single signal signal-to-noise ratio of each linear frequency modulation chip 100, and determine the last linear frequency modulation chip 100 based on the number of cascaded chips.

[0041] The control unit 301 is further configured to control the first switch S1 of the last chirp chip 100 to be opened and the second switch S2 to be closed, and to control the first switches S1 of the remaining chirp chips 100 before the chip number to be closed and the second switches S2 to be opened.

[0042] Specifically, in this embodiment, if the calculated number of cascaded chips is 5, then the 5# linear frequency modulation chip is used as the last linear frequency modulation chip 100. The first switch S1 of the 5# linear frequency modulation chip is controlled to be disconnected, so that the 6# linear frequency modulation chip and the subsequent linear frequency modulation chips in the cascade will not receive the signal frequency component. The second switch S2 of the 5# linear frequency modulation chip is controlled to be closed. The first switches S1 of the 1# linear frequency modulation chip to the 4# linear frequency modulation chip are closed, and the second switches S2 are disconnected. Then, the signal frequency component output by the 1# linear frequency modulation chip is sent to the first conversion interface 102 of the 2# linear frequency modulation chip via the first conversion interface 102 of the 1# linear frequency modulation chip. The first conversion interface 102 of the 2# linear frequency modulation chip combines the signal frequency component output by the 1# linear frequency modulation chip with its own signal frequency component and sends the combined signal to the first conversion interface 102 of the 3# linear frequency modulation chip, and so on. The signal frequency components are combined as follows:

[0043] The signal frequency component output by the 1# linear frequency modulation chip is signal frequency component 1, and the signal frequency component output by the 1# linear frequency modulation chip is signal frequency component 2. Then, the data structure after merging by the first conversion interface 102 of the 2# linear frequency modulation chip is preferably (signal frequency component 1, signal frequency component 2), and the data structure after merging by the first conversion interface 102 of the 3# linear frequency modulation chip is preferably (signal frequency component 1, signal frequency component 2, signal frequency component 3), and so on. In other words, after adding its own signal frequency component to the received signal frequency component, a data packet is formed and sent to the next linear frequency modulation chip. Ultimately, all the signal frequency components are concentrated in the last linear frequency modulation chip for merging and demodulation to output a linear frequency modulation signal.

[0044] As can be seen, the cascaded approach eliminates the need for coordinating signal reception and establishing separate connection interfaces for each chirp chip, compared to a method where each chirp chip processes and demodulates the chirp signal separately and then merges the signals through a separate signal fusion chip. This reduces overall design complexity. Furthermore, by transmitting the frequency components of the chirp signal as frequency information rather than the signal itself, the amount of data transmitted can be reduced, thereby lowering computational latency and power consumption.

[0045] In a preferred embodiment of the present invention, the control chip 300 further includes a storage unit 303 connected to the calculation unit 302 for storing the chip numbers of each linear frequency modulation chip 100, and the chip numbers are arranged in sequence according to the cascade order;

[0046] The calculation unit 302 determines the chip number of the last chirp chip 100 according to the number of cascaded chips and sends the chip number to the control unit 301 .

[0047] In a preferred embodiment of the present invention, the calculation unit 302 calculates the number of cascaded chips according to the following calculation formula:

[0048] in,

[0049] Here, m represents the number of cascaded chips, SNR1 represents the required signal-to-noise ratio, SNR2 represents the single-signal signal-to-noise ratio, s represents the signal frequency component, and n represents the single-signal noise of the linear frequency modulation chip.

[0050] In a preferred embodiment of the present invention, the signal processing module 101 includes a radio frequency front end RF, an analog-to-digital converter ADC, a digital filter Filter, a digital intermediate frequency mixer Mixer and a Fourier transform unit FFT connected in sequence. The radio frequency front end RF is connected to the corresponding receiving antenna 200 as the input end of the signal processing module 101, and the output end of the Fourier transform unit FFT is the output end of the signal processing module 101.

[0051] In a preferred embodiment of the present invention, the signal combining module 103 includes a maximum ratio combining unit MRC and a digital demodulator Demod connected in sequence, and an input end of the maximum ratio combining unit MRC is connected to an output end of the signal processing module 101 .

[0052] Specifically, in this embodiment, the maximum ratio combining (MRC) unit in the last chirp chip 100 performs the final signal-to-noise ratio calculation and signal fusion. Based on the signal-to-noise ratio data sent by each chip, the output percentage is determined based on the relative size of the signal-to-noise ratio of the signal in question relative to the signal-to-noise ratio of all signals. A signal frequency component with an increased signal-to-noise ratio is then output. This signal's signal-to-noise ratio is ultimately optimized and then sent to the digital demodulator (Demod) to recover the information. The calculation of the single-signal signal-to-noise ratio is defined by the following formula:

[0053] Where s represents the signal frequency component, n represents the single signal noise of the linear frequency modulation chip, and σ represents the root mean square. The signal-to-noise ratio is calculated by combining n signals according to the following formula:

[0054] That is to say, when n signals are combined, the lowest signal-to-noise ratio can be improved Based on this, the external control chip 300 can be used to improve the signal-to-noise ratio according to the demand. The number n of chips in the chipset is determined, and then the on / off status of the first switch S1 and the second switch S2 in each linear frequency modulation chip is determined. Since the number of receiving antennas used is proportional to the degree of signal-to-noise ratio optimization, the number of receiving antennas can also be selected as needed.

[0055] In a preferred embodiment of the present invention, multiple second conversion interfaces 400 are further included. The input end of the signal merging module 103 of the last chirp chip 100 in the cascade is connected to the first conversion interface 102 of the previous chirp chip 100 via the corresponding second conversion interface 400. The first conversion interfaces 102 of the remaining chirp chips 100 are connected to the first conversion interfaces 102 of adjacent chirp chips 100 via the corresponding second conversion interfaces 400.

[0056] Specifically, in this embodiment, serial-to-parallel conversion and parallel-to-serial conversion are implemented through the first conversion interface 102 and the second conversion interface 400 to achieve combined transmission of signal frequency components. The above-mentioned second conversion interface 400 can be integrated on the linear frequency modulation chip 100 or can be set separately, which is not limited here.

[0057] In a preferred embodiment of the present invention, the first conversion interface 102 is a parallel-to-serial conversion interface, and the second conversion interface 400 is a parallel-to-serial conversion interface.

[0058] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A multi-antenna signal cascade device based on linear frequency modulation signal, characterized in that: It comprises a plurality of linear frequency modulation chips, each of which is cascaded in sequence, and each of which is connected to a receiving antenna and is used to process the linear frequency modulation signal received by the receiving antenna to obtain a corresponding signal frequency component, and the last linear frequency modulation chip in the cascade is also used to combine the signal frequency components obtained by processing the remaining linear frequency modulation chips to obtain a linear frequency modulation signal with a preset signal-to-noise ratio.

2. The multi-antenna signal cascade device according to claim 1, characterized in that: Each of the linear frequency modulation chips comprises: A signal processing module, wherein an input end of the signal processing module is connected to the receiving antenna, and an output end of the signal processing module is respectively connected to a first conversion interface and a signal combining module; The first conversion interfaces of the remaining linear frequency modulation chips except the last linear frequency modulation chip are cascaded in sequence, so as to receive the signal frequency component output by the previous linear frequency modulation chip and the signal frequency component of the previous linear frequency modulation chip through the first conversion interface and send them to the next linear frequency modulation chip; The input end of the signal merging module of the last linear frequency modulation chip is connected to the first conversion interface of the previous linear frequency modulation chip to receive the signal frequency components sent by the previous linear frequency modulation chip and its own signal frequency components for merging and processing to obtain a linear frequency modulation signal with the preset signal-to-noise ratio.

3. The multi-antenna signal cascade device according to claim 2, characterized in that: It also includes a control chip, which is connected to each of the linear frequency modulation chips respectively, and the output end of the signal processing module of each of the linear frequency modulation chips is connected to the first conversion interface through a first switch, and is connected to the signal merging module through a second switch; The control chip includes a control unit, which is used to control the first switch of the last linear frequency modulation chip to be opened and the second switch to be closed, and to control the first switch of each of the remaining linear frequency modulation chips to be closed and the second switch to be opened, so as to realize the sequential cascading of each of the linear frequency modulation chips.

4. The multi-antenna signal cascade device according to claim 3, characterized in that: The control chip further includes a calculation unit connected to the control unit, configured to calculate the number of cascaded chips according to the required signal-to-noise ratio and the single signal signal-to-noise ratio of each linear frequency modulation chip acquired in advance, and determine the last linear frequency modulation chip according to the number of cascaded chips; The control unit is further used for controlling the first switch of the last linear frequency modulation chip to be opened and the second switch to be closed, and controlling the first switch of the remaining linear frequency modulation chips before the chip number to be closed and the second switch to be opened.

5. The multi-antenna signal cascade device according to claim 4, characterized in that: The control chip further comprises a storage unit connected to the calculation unit and used to store the chip numbers of the linear frequency modulation chips, wherein the chip numbers are arranged in sequence according to the cascade order; The calculation unit determines the chip number of the last linear frequency modulation chip according to the number of the cascaded chips and sends the chip number to the control unit.

6. The multi-antenna signal cascade device according to claim 4, characterized in that: The calculation unit calculates the number of cascade chips according to the following calculation formula: in, Among them, m is used to represent the number of cascade chips, SNR1 is used to represent the requirement Signal-to-noise ratio, SNR2 is used to represent the single signal signal-to-noise ratio, s is used to represent the signal frequency component, and n is used to represent the single signal noise of the linear frequency modulation chip.

7. The multi-antenna signal cascade device according to claim 2, characterized in that: The signal processing module includes a radio frequency front end, an analog-to-digital converter, a digital filter, a digital intermediate frequency mixer and a Fourier transform unit connected in sequence. The radio frequency front end is connected to the corresponding receiving antenna as the input end of the signal processing module, and the output end of the Fourier transform unit is the output end of the signal processing module.

8. The multi-antenna signal cascade device according to claim 2, characterized in that: The signal combining module comprises a maximum ratio combining unit and a digital demodulator which are connected in sequence, and an input end of the maximum ratio combining unit is connected to an output end of the signal processing module.

9. The multi-antenna signal cascade device according to claim 2, characterized in that: It also includes multiple second conversion interfaces, and the input end of the signal merging module of the last linear frequency modulation chip in the cascade is connected to the first conversion interface of the previous linear frequency modulation chip through the corresponding second conversion interface, and the first conversion interfaces of the remaining linear frequency modulation chips are respectively connected to the first conversion interfaces of adjacent linear frequency modulation chips through the corresponding second conversion interfaces.

10. The multi-antenna signal cascade device according to claim 9, characterized in that: The first conversion interface is a parallel-to-serial conversion interface, and the second conversion interface is a parallel-to-serial conversion interface.

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