High-frequency signal generating device

Abstract

A high-frequency signal generation device according to the present invention comprises: (A) a clock signal generating unit that generates a clock signal using a harmonic component that is generated by a non-linear amplifier; (B) a DDS (direct digital synthesizer) that uses the clock signal as a system clock for operating internal processing and generates a frequency signal having a frequency that is set by frequency setting data; and (C) a high-frequency unit that is composed of a non-active frequency multiplier that does not use an active element and that increases the frequency of the frequency signal generated by the DDS. The clock signal is generated by using the harmonic component that is generated by the non-linear amplifier, an increase in speed is handled by shortening a delay time in a variable function of the frequency, and a high C / N ratio is handled by suppressing spurious emission and phase noise.

Description

High-frequency signal generator

[0001] The present invention relates to a high frequency signal generator with a variable output frequency.

[0002] A high frequency signal (RF signal) in the VHF to UHF band (100 MHz to 1 GHz) is supplied to a linear amplifier type high frequency power supply used in semiconductor manufacturing equipment, liquid crystal panel manufacturing equipment, etc. The high frequency power supply is equipped with a high frequency signal generator and generates a high frequency signal (RF signal) with a variable frequency.

[0003] 2. Description of the Related Art Known high-frequency signal generators that generate high-frequency signals (RF signals) with variable frequencies include frequency synthesizers that use a DDS (Direct Digital Synthesizer) (see Patent Documents 1 and 2).

[0004] [Amendment under Rule 91 11.04.2024] These frequency synthesizers are equipped with a frequency mixer and a PLL circuit as peripheral equipment for DDS that increase the frequency of the DDS signal.

[0005] 4A shows an example of the configuration of a high-frequency signal generator including a frequency mixer. High-frequency signal generator 100 includes reference signal oscillator 101 that generates a periodic signal having a specific frequency, DDS 102 that uses the output of reference signal oscillator 101 as a clock signal and generates a signal with a frequency specified by frequency setting data, local oscillator 103 that outputs a local oscillator wave, mixer 104 that mixes the output signal of DDS 102 with the local oscillator wave, multiplier 105 that multiplies the signal mixed by mixer 104, and frequency divider 106 that divides the output signal of multiplier 105. The output frequency can be varied by changing the division ratio of frequency divider 106 based on the frequency setting data.

[0006] [Correction based on Rule 91, 11.04.2024] Figure 4B shows an example of the configuration of a high-frequency signal generator including a PLL circuit. High-frequency signal generator 110 includes clock signal source 111, which outputs a clock signal; DDS 112, which generates a signal with a frequency specified by frequency setting data based on the clock signal; PLL circuit 113, which outputs an oscillation signal with a set frequency based on the frequency of the DDS signal; and control unit 114, which outputs the frequency setting data. PLL circuit 113 includes phase comparator 113a, loop filter 113b, voltage-controlled oscillator (VOC) 113c, and frequency divider 113d.

[0007] JP 2000-124740 A JP 2022-113497 A

[0008] Conventional frequency synthesizer high-frequency signal generators that use DDS to generate variable frequency signals have problems such as delay times that occur within the PLL circuit, and a decrease in the carrier-to-noise ratio (C / N ratio) due to spurious and phase noise that occur in peripheral devices of the DDS and in the PLL circuit.

[0009] When the frequency is made variable, a delay occurs in the output signal due to the response characteristics of the frequency mixer and the voltage-controlled oscillator (VOC) of the PLL circuit, and the lock-up time required for the PLL output to lock to a predetermined frequency within the PLL loop is approximately 1 ms to several ms.

[0010] 5 shows an example of the delay time of a high-frequency signal generator equipped with a PLL circuit. When switching the frequency from f1 to f2, a process of writing PLL frequency data to the DDS is performed. For example, this requires 1.72 ms of write time. The time required for the frequency to stabilize through repeated processing within the PLL loop is, for example, 38.67 ms when switching from 450 MHz to 460 MHz, and 34.67 ms when switching from 460 MHz to 450 MHz.

[0011] Furthermore, spurious and phase noise caused by circuit elements such as a frequency mixer and a voltage-controlled oscillator (VCO) in a PLL circuit will reduce the carrier-to-noise ratio (C / N ratio) of the frequency signal generated by the high-frequency signal generator.

[0012] 6 is a schematic diagram for explaining spurious and phase noise. When the modulation signal that phase-modulates the carrier signal is a periodic signal, harmonic spurious occurs at frequencies that are integer multiples of the fundamental wave. Phase noise occurs in both sidebands of the carrier and is expressed as the carrier-to-noise ratio (C / N ratio).

[0013] When a high frequency signal generator is required to have a variable frequency at high speed and to produce an output signal with a high C / N ratio, conventional high frequency signal generators have the problem that it is difficult to achieve high speeds and a high C / N ratio due to delays in lock-up time, spurious signals, and phase noise.

[0014] The present invention aims to solve the above-mentioned conventional problems, and to shorten the delay time in the variable frequency function to accommodate higher speeds, and to suppress spurious and phase noise to accommodate a high C / N ratio.

[0015] The high frequency signal generator of the present invention comprises: (A) a clock signal generating unit that generates a clock signal using harmonic components generated by a nonlinear amplifier; (B) a DDS (direct digital synthesizer) that uses the clock signal as a system clock for operating internal processing and generates a frequency signal having a frequency set by frequency setting data; and (C) a high frequency increasing unit that is composed of a non-active frequency multiplier that does not use active elements and that increases the frequency of the frequency signal generated by the DDS.

[0016] (A: Clock Signal Generator) The high-frequency signal generator of the present invention uses a clock signal generated by a clock signal generator as a system clock for operating the internal processing of the DDS. The clock signal generator includes a nonlinear amplifier, which generates harmonic components relative to the fundamental wave due to the nonlinearity. The high-frequency signal generator of the present invention generates a high-frequency signal using the harmonic components generated by the amplifier, and uses this high-frequency signal as a clock signal for the system clock of the DDS.

[0017] The clock signal generating section can generate a clock signal with a high C / N ratio (carrier-to-noise ratio) and low spurious by using harmonic components generated by the nonlinear amplifier.

[0018] The clock signal generating unit of the present invention comprises: (a) a reference signal oscillator that generates a periodic signal of a specific frequency as a reference signal; (b) a nonlinear amplifier that generates harmonic components of the fundamental wave of the reference signal; (c) a narrow-band harmonic filter (first BPF) that passes only harmonic components; and (d) a high-frequency amplifier that amplifies the harmonic components that have passed through the narrow-band harmonic filter, and (e) generates an output signal of the high-frequency amplifier as a clock signal.

[0019] A nonlinear amplifier generates harmonic components in addition to the fundamental frequency due to its nonlinearity. The present invention generates a high-frequency signal to be used as a clock signal by utilizing the harmonic components generated by the nonlinear amplifier. Since the harmonic components are integer multiples of the fundamental frequency, if the fundamental frequency of the reference signal of the reference signal oscillator is highly accurate, the accuracy of the obtained high-frequency signal will also be highly accurate. A buffer amplifier or a class C amplifier can be used as the nonlinear amplifier.

[0020] (B: DDS) A DDS (Direct Digital Synthesizer) generates a frequency signal having a frequency set by frequency setting data. The control unit sets the frequency setting data for the DDS, and the DDS generates a frequency signal having the frequency set by the frequency setting data. By changing the frequency setting data, the frequency of the frequency signal can be made variable.

[0021] The DDS of the present invention performs processing using the clock signal generated by the clock signal generator as the system clock. Since the DDS operates with a clock signal with a high C / N ratio (carrier-to-noise ratio) and low spurious, the C / N ratio of the output frequency is increased.

[0022] (C: High Frequency Increasing Unit) The high frequency increasing unit increases the frequency of the frequency signal generated by the DDS to generate a high frequency signal. The high frequency increasing unit is composed of a non-active frequency multiplier that does not use active elements. In active multipliers, spurious emissions and phase noise occur in frequency bands other than the fundamental frequency due to the non-linearity of the active elements. In contrast, the non-active frequency multiplier included in the high frequency signal generating device of the present invention is configured without active elements, and therefore can suppress the generation of spurious emissions and phase noise caused by the non-linearity of the active elements.

[0023] The high frequency conversion unit includes: (f) a differential output unit that generates a differential signal of the DDS frequency signal; (g) a non-active frequency multiplier that multiplies the frequency of the differential signal; and (h) a target frequency band filter that passes a target frequency component from the multiplied signal, and (i) outputs the frequency component that has passed through the target frequency band filter (second BPF) as an output signal.

[0024] The differential output section (f) generates a signal with an inverted polarity relative to the DDS frequency signal, and uses the difference between these signals as a differential output signal, thereby improving noise resistance without reducing the potential difference.A differential amplifier or a harmonic transformer can be used as the differential output section.

[0025] The non-active frequency multiplier (g) does not have the non-linearity of active elements, and therefore can suppress spurious and phase noise. As the non-active frequency multiplier (g), a rectifying multiplier composed of a Schottky diode or a rectifying diode can be applied.

[0026] The frequency converter of the present invention generates a differential signal from the DDS frequency signal and multiplies the frequency of the generated differential signal using a non-active frequency multiplier, thereby achieving a stepwise frequency increase. This stepwise frequency increase allows for a high frequency signal with a high C / N ratio and low spurious emissions compared to when the frequency is increased at the DDS stage.

[0027] As described above, according to the high frequency signal generator of the present invention, the variable frequency function can shorten the delay time to accommodate higher speeds, and suppress spurious and phase noise to accommodate a high C / N ratio.

[0028] [Correction based on Rule 91 11.04.2024] A diagram for explaining an example of the configuration of a high frequency signal generator of the present invention. A diagram for explaining the processing time in a DDS. A diagram comparing an example using a DDS of the present invention with an example using a PLL circuit. A diagram showing an example of phase noise. A configuration example of a high frequency signal generator including a frequency mixer (mixer). A configuration example of a high frequency signal generator including a PLL circuit. A diagram showing an example of the delay time of a high frequency signal generator including a PLL circuit. A schematic diagram for explaining spurious and phase noise.

[0029] (1) Schematic Configuration of the High-Frequency Signal Generator of the Present Invention The schematic configuration of the high-frequency signal generator of the present invention will now be described with reference to Fig. 1. The high-frequency signal generator 10 comprises a control unit 1, a DDS 2, a clock signal generating unit 3, and a high-frequency generating unit 4.

[0030] The control unit 1 determines frequency setting data that sets the frequency of the high frequency signal output by the high frequency signal generator 10. The frequency of the high frequency signal can be made variable by changing the frequency setting data.

[0031] (DDS) The DDS (Direct Digital Synthesizer) 2 receives the frequency setting data set by the control unit 1 and generates a frequency signal having the frequency set by the frequency setting data.

[0032] The DDS2 is a digitally synthesized frequency synthesizer that generates a series of digital states that are linearly incremented to form a periodic numerical ramp representing the instantaneous phase of the output waveform. This is then digitally input into a lookup table that calculates the amplitude of a sine wave from the phase data, converting the numerical ramp into a sine wave. A digital-to-analog converter is applied to the DDS2, which then outputs the desired analog output after filtering. The digital processing of the DDS is based on a system clock generated from an external reference clock.

[0033] The clock signal generating unit 3 generates a clock signal to be used as a system clock in the DDS 2. The high frequency increasing unit 4 increases the frequency of the frequency signal generated by the DDS 2 to a predetermined high frequency.

[0034] (Clock Signal Generator) The clock signal generated by the clock signal generator 3 is used as a system clock for operating the internal processing of the DDS 2.

[0035] The clock signal generating unit 3 of the present invention includes a nonlinear amplifier. This amplifier generates harmonic components relative to the fundamental wave due to the nonlinearity. The high-frequency signal generating device 10 of the present invention generates a high-frequency signal using the harmonic components generated by the amplifier, and uses this high-frequency signal as a clock signal for the system clock of the DDS2.

[0036] The clock signal generator 3 uses the amplifier not as a means for amplifying a signal but as a means for generating a high frequency signal. The DDS 2 operates with a clock signal having a high C / N ratio (carrier to noise ratio) and low spurious, so the C / N ratio of the output frequency is increased.

[0037] Therefore, the high frequency signal generator 10 of the present invention generates a clock signal with a high C / N ratio (carrier to noise ratio) and low spurious by using the harmonic components generated by the nonlinear amplifier.

[0038] The clock signal generating unit 3 includes: (a) a reference signal oscillator 3a that generates a periodic signal of a specific frequency as a reference signal; (b) a nonlinear amplifier 3b that generates harmonic components of the fundamental wave of the reference signal of the reference signal oscillator 3a; (c) a narrow-band harmonic filter (first BPF) 3c that passes only the harmonic components generated by the nonlinear amplifier 3b; and (d) a high-frequency amplifier 3d that amplifies the harmonic components that have passed through the narrow-band harmonic filter 3c, and (e) an output signal of the high-frequency amplifier 3d is generated as a clock signal.

[0039] The nonlinear amplifier 3b generates harmonic components in addition to the fundamental frequency due to its nonlinearity. The harmonic components generated by the nonlinear amplifier 3b are used to generate a high-frequency signal used as a clock signal. Since the harmonic components are integer multiples of the fundamental frequency, if the fundamental frequency of the reference signal from the reference signal oscillator 3a is highly accurate, the high-frequency signal obtained by the high-frequency amplifier 3d will also be highly accurate. As an example, a buffer amplifier or a class C amplifier can be used as the nonlinear amplifier 3b.

[0040] An example of the clock signal generator 3 is shown below. For example, a 60 MHz crystal oscillator or TCXO is used as the reference signal oscillator 3a. The nonlinear amplifier 3b generates harmonic components with frequencies that are integer multiples of the fundamental wave by passing the 60 MHz reference signal through it. The TCXO is a temperature-compensated crystal oscillator that adds a temperature compensation circuit to a crystal oscillator to suppress frequency fluctuations caused by changes in the ambient temperature.

[0041] For example, the narrow-band harmonic filter 3c may be an LC ladder filter, a SAW surface acoustic wave filter, an MCF monolithic crystal filter, etc. When a clock signal is generated using a tenth harmonic component, a band-pass filter BPF with a center frequency of 600 MHz and a bandwidth of ±1 MHz is used as the narrow-band harmonic filter 3c.

[0042] The high frequency signal having a center frequency of 600 MHz that has passed through the narrow band harmonic filter 3c is output as the clock signal Sysclk to be used as the system clock in the DDS2.

[0043] The sampling theorem dictates that the relationship between the output frequency fo of the DDS2 and the clock signal Sysclk is Sysclk > 2fo. Furthermore, the phase noise component is expressed as 20 log (fo / f_sysclk) dB, and the greater the frequency f_sysclk of the clock signal Sysclk is than twice the output frequency fo, the more phase noise and spurious signals are reduced. Furthermore, because the DDS2 generates the output frequency fo by writing frequency data and does not include a PLL circuit, delays due to lockup time are suppressed.

[0044] FIG. 2A is a diagram illustrating the processing time in the DDS2. In the example shown in FIG. 2A, the period required to write frequency data is 32 μs (32×10 -６ sec), and the shift interval for switching the frequency based on the frequency data is 16 μs (16×10 -６ sec).

[0045] Figure 2B compares an example using the DDS of the present invention with an example using a PLL circuit. The upper graph in Figure 2B is an example using a DDS, and the lower graph in Figure 2B is an example using a PLL circuit. The upper graph in Figure 2B and Figure 2A show the same example, but the time scale in the upper graph in Figure 2B has been reduced to match the time scale of the PLL circuit.

[0046] In an example using a PLL circuit, the interval required to write the PLL frequency data is 1.72 ms, and the shift interval for switching the frequency based on the PLL frequency data is 38.67 ms when switching from 450 MHz to 460 MHz, and 34.67 ms when switching from 460 MHz to 450 MHz.

[0047] (High Frequency Increasing Section) The high frequency increasing section 4 is configured by a non-active frequency multiplier that does not use an active element, and increases the frequency of the frequency signal generated by the DDS 2.

[0048] The high frequency converter 4 generates a high frequency signal by increasing the frequency of the frequency signal generated by the DDS 2. The high frequency converter 4 is configured by a non-active frequency multiplier that does not use an active element.

[0049] In active frequency multipliers, spurious emissions and phase noise occur in frequency bands other than the fundamental frequency due to the nonlinearity of the active elements. In contrast, the nonactive frequency multiplier included in the high-frequency signal generator of the present invention is configured without active elements. Because it is configured without active elements, the generation of spurious emissions and phase noise caused by the nonlinearity of the active elements is suppressed.

[0050] The high frequency unit 4 comprises: (f) a differential output unit 4a that generates a differential signal of the frequency signal of the DDS2; (g) an inactive frequency multiplier 4b that multiplies the frequency of the differential signal of the differential output unit 4a; and (h) a target frequency band filter 4c that passes a target frequency component from the multiplied signal multiplied by the inactive frequency multiplier 4b, and (i) the frequency component that has passed through the target frequency band filter (second BPF) 4c is output as an output signal.

[0051] The differential output unit 4a generates a signal with an inverted polarity relative to the frequency signal of the DDS2, and the difference between these signals is used as a differential output signal. By using a differential output signal, common-mode noise can be suppressed and noise resistance can be improved without reducing the potential difference. For example, a differential amplifier or a harmonic transformer can be used as the differential output unit. FIG. 1 shows an example configuration using a harmonic transformer as the differential output unit 4a.

[0052] The non-active frequency multiplier 4b does not have the non-linearity of active elements, and therefore can suppress spurious and phase noise. A rectifying multiplier configured with a Schottky diode or a rectifying diode can be used as the non-active frequency multiplier 4b.

[0053] For example, an LC ladder filter, a SAW surface acoustic wave filter, or the like can be applied to the target frequency band filter 4c.

[0054] The following shows an example of the frequency in the high frequency converter 4. An example is shown in which a high frequency signal with a target frequency of 450 MHz is output using a frequency f_sysclk of the system clock Sysclk of the DDS2 device of 1 GSPS (giga samples per second).

[0055] The control unit 1 sends 225 MHz frequency data to the DDS 2, which then outputs a 225 MHz sine wave signal in response to the frequency data. The differential output unit 4a converts the 225 MHz sine wave signal into a differential signal. The target frequency band filter 4c multiplies the 225 MHz differential signal. When multiplied by 2, a high-frequency signal of 450 MHz is output.

[0056] The frequency converter 4 of the present invention generates a differential signal from the frequency signal of the DDS 2 and multiplies the frequency of the generated differential signal by the inactive frequency multiplier 4 b, thereby increasing the frequency in stages. This stepwise increase in frequency makes it possible to obtain a high-frequency signal with a high C / N ratio and low spurious emissions compared to when the frequency is increased at the DDS stage.

[0057] An example of phase noise is shown in Fig. 3. Fig. 3 shows the phase noise level at ±1 kHz relative to the output frequency fo.

[0058] In a configuration using a PLL circuit, the phase noise level at ±1 kHz when the output frequency fo is 400 MHz is -62.3 dB. In contrast, in the case of the present invention, the phase noise level at ±1 kHz when the output frequency fo is 220 MHz is -75.8 dB, and the phase noise level at ±1 kHz when the output frequency fo is 450 MHz is -76.8 dB. This example shows that the phase noise level of the high frequency signal generator of the present invention is improved in terms of phase noise suppression compared to a configuration using a PLL circuit.

[0059] The high frequency signal generator of the present invention can be applied to a high frequency power source (RF generator) used in semiconductor manufacturing equipment, liquid crystal panel manufacturing equipment, and the like.

[0060] REFERENCE SIGNS LIST 1 Control unit 2 DDS (Direct Digital Synthesizer) 3 Clock signal generating unit 3a Reference signal oscillator 3b Nonlinear amplifier 3c Narrow-band harmonic filter 3d High-frequency amplifier 4 High-frequency unit 4a Differential output unit 4b Inactive frequency multiplier 4c Target frequency band filter 10 High-frequency signal generating device 100 High-frequency signal generating device 101 Reference signal oscillator 102 DDS 103 Local oscillator 104 Mixer 105 Multiplier 106 Frequency divider 110 High-frequency signal generating device 111 Clock signal source 112 DDS 113 PLL circuit 113a Phase comparator 113b Loop filter 113c Voltage-controlled oscillator (VOC) 113d Frequency divider 114 Control unit

Claims

1. A high frequency signal generator comprising: a clock signal generating unit which generates a clock signal using harmonic components generated by a non-linear amplifier; a DDS (Direct Digital Synthesizer) which uses the clock signal as a system clock for operating internal processing and generates a frequency signal having a frequency set by frequency setting data; and a high frequency increasing unit which is composed of a non-active frequency multiplier which does not use active elements and which increases the frequency of the frequency signal generated by the DDS.

2. The high frequency signal generating device of claim 1, wherein the clock signal generating unit comprises: a reference signal oscillator that generates a periodic signal of a specific frequency as a reference signal; a non-linear amplifier that generates harmonic components of the fundamental wave of the reference signal; a narrow-band harmonic filter that passes only the harmonic components; and a high frequency amplifier that amplifies the harmonic components that have passed through the narrow-band harmonic filter, and generates an output signal of the high frequency amplifier as a clock signal.

3. The high frequency signal generating device according to claim 1, wherein the high frequency conversion unit comprises: a differential output unit that generates a differential signal of the DDS frequency signal; a non-active frequency multiplier that multiplies the frequency of the differential signal; and a target frequency band filter that passes a target frequency component from the multiplied signal, and the frequency component that has passed through the target frequency band filter is used as an output signal.

4. The high frequency signal generating device of claim 1, wherein the clock signal generating unit comprises: a reference signal oscillator that generates a periodic signal of a specific frequency as a reference signal; a non-linear amplifier that generates harmonic components of the fundamental wave of the reference signal; a narrow-band harmonic filter that passes only the harmonic components; and a high frequency amplifier that amplifies the harmonic components that have passed through the narrow-band harmonic filter, and generates an output signal of the high frequency amplifier as a clock signal; and the high frequency increasing unit comprises: a differential output unit that generates a differential signal of the DDS frequency signal; a non-active frequency multiplier that multiplies the frequency of the differential signal; and a target frequency band filter that passes a target frequency component from the multiplied signal, and the frequency component that has passed through the target frequency band filter is used as an output signal.

5. The high frequency signal generating device according to claim 2 or 4, wherein the nonlinear amplifier is a buffer amplifier or a class C amplifier.

6. The high frequency signal generator according to claim 3 or 4, wherein the differential output section is a differential amplifier or a harmonic transformer, and the non-active type frequency multiplier is a rectifier type multiplier constituted by a Schottky diode or a rectifier diode.

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