Semiconductor device

Abstract

According to the present invention, a substrate has a P wiring line (421) and an N wiring line (422), which are disposed on one surface of an insulating base material. A P terminal (611) is connected to the P wiring line, and an N terminal (612) is connected to the N wiring line. A semiconductor element (30H) is electrically connected to the P wiring line. A snubber circuit (70) comprises a capacitor (71), and electrically bridges the P wiring line and the N wiring line. The substrate has a signal wiring line (425) which is disposed between the semiconductor element and the snubber circuit, and electrically relays a signal terminal and the semiconductor element.

Description

Semiconductor Devices CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Patent Application No. 2023-110769 filed in Japan on July 5, 2023, and Patent Application No. 2024-071968 filed in Japan on April 25, 2024, and the contents of the base applications are incorporated by reference in their entirety.

[0002] TECHNICAL FIELD The disclosure herein relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device having a built-in snubber circuit. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification.

[0004] Japanese Patent Application Laid-Open No. 2021-182575

[0005] In Patent Document 1, a snubber circuit including a capacitor is connected in parallel to a series circuit of two switching elements that constitute upper and lower arm circuits. The electrode on the lower surface of the switching element and the connection terminal at the lower end of the capacitor are connected to a common wiring on the substrate. The capacitor is disposed near the switching element and is affected by the heat generated by the switching element. In terms of the above and other aspects not mentioned, further improvements are required in semiconductor devices.

[0006] One disclosed object is to provide a semiconductor device that can reduce the influence of heat from a semiconductor element on a capacitor.

[0007] One aspect of the disclosure is a semiconductor device that constitutes a power conversion circuit, comprising: a substrate having a first main terminal, a second main terminal, a signal terminal, an insulating substrate, a first wiring arranged on one surface of the insulating substrate and electrically connected to the first main terminal, and a second wiring arranged on one surface and electrically connected to the second main terminal; a semiconductor element electrically connected to the first wiring; and a snubber circuit including a capacitor and electrically bridging the first wiring and the second wiring, wherein the substrate has a signal wiring arranged between the semiconductor element and the snubber circuit and electrically relaying the signal terminal and the semiconductor element.

[0008] According to the disclosed semiconductor device, intentional patterning of wiring on a substrate provides signal wiring that electrically connects a signal terminal and a semiconductor element, and the signal wiring is arranged between the semiconductor element and the snubber circuit. The capacitor that constitutes the snubber circuit is spaced apart from the semiconductor element by the amount of the signal wiring, thereby reducing the effect of heat from the semiconductor element on the capacitor.

[0009] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings.

[0010] 18 is a diagram illustrating a circuit configuration of a power conversion device to which the semiconductor device according to the first embodiment is applied; FIG. 20 is a perspective view illustrating an example of a semiconductor module; FIG. 21 is a plan view of a semiconductor module; FIG. 22 is a cross-sectional view taken along line IV-IV in FIG. 3; FIG. 23 is a plan view illustrating an example of a semiconductor device; FIG. 24 is a plan view illustrating a wiring pattern of a substrate; FIG. 25 is a cross-sectional view taken along line VII-VII in FIG. 5; FIG. 26 is a cross-sectional view illustrating another example of a connection structure between a capacitor and a substrate; FIG. 27 is a cross-sectional view illustrating another example of a connection structure between a capacitor and a substrate; FIG. 28 is a circuit diagram illustrating a verification model; FIG. 29 is a diagram illustrating verification results; FIG. 30 is a diagram illustrating temperature distribution; FIG. 31 is a diagram illustrating an arrangement of a current path using a snubber circuit; FIG. 32 is a plan view illustrating a modified example; FIG. 33 is a plan view illustrating a modified example; FIG. 34 is a plan view illustrating a semiconductor element in a semiconductor device according to a second embodiment; FIG. 35 is a cross-sectional view taken along line XIX-XIX in FIG. 18; 29 is a plan view showing another example of a clip. FIG. 29 is a plan view showing another example of a clip. FIG. 30 is a cross-sectional view showing another example of a clip. FIG. 31 is a plan view showing another example of a clip. FIG. 32 is a cross-sectional view showing another example of a clip. FIG. 33 is a plan view showing another example of a connection structure between a clip and a semiconductor element. FIG. 34 is a cross-sectional view taken along line XXX-XXX of FIG. 29. FIG. 35 is a plan view showing another example of a clip. FIG. 36 is a plan view showing another example of a clip. FIG. 37 is a plan view showing another example of a clip. FIG. 38 is a plan view showing another example of a clip. FIG. 39 is a plan view showing another example of a clip. FIG. 39 is a plan view showing another example of a clip. FIG. 39 is a plan view showing an example of a clip.62. A diagram showing a current path on the upper arm side. A plan view showing an example of a substrate. A diagram showing another example of a substrate. A plan view showing an example of a semiconductor module according to a fifth embodiment. A plan view showing a state in which a housing is removed in a semiconductor module. A cross-sectional view taken along line LV-LV of FIG. 53. A cross-sectional view showing the periphery of a collar. A diagram showing the relationship between the thickness of a sealing material and thermal resistance. A cross-sectional view showing a reference example of a semiconductor module. A cross-sectional view taken along line LIX-LIX of FIG. 53. A cross-sectional view showing another example of a semiconductor module. A cross-sectional view showing an example of a semiconductor module according to a sixth embodiment. A plan view showing an example of a semiconductor device. A cross-sectional view taken along line LXIII-LXIII of FIG. 62. A cross-sectional view showing warping of a substrate in a semiconductor module. A plan view showing another example of a semiconductor module. A diagram for explaining oscillation in a parallel circuit. A plan view showing an example of a semiconductor device according to a seventh embodiment. A diagram showing an equivalent circuit diagram of upper and lower arm circuits provided by a semiconductor device. A plan view showing another example of a semiconductor device. A plan view showing another example of a semiconductor device. A plan view showing another example of a semiconductor device. A cross-sectional view showing another example of a semiconductor device. A cross-sectional view showing another example of a semiconductor device. 79 is an enlarged view of region LXXIII shown in FIG. 72. FIG. 80 is a plan view showing another example of a semiconductor device. FIG. 81 is a plan view showing another example of a semiconductor device. FIG. 82 is a plan view showing another example of a semiconductor device. FIG. 83 is a plan view showing another example of a semiconductor device. FIG. 84 is a plan view showing an example of a semiconductor device according to an eighth embodiment. FIG. 85 is an enlarged view of FIG. 79. FIG. 86 is a schematic view showing the positional relationship between a substrate and an interposer substrate when viewed in the Y direction of FIG. 79. FIG. 87 is a schematic view showing another example of an interposer substrate. FIG. 88 is a plan view showing an example of a semiconductor device according to a ninth embodiment. FIG. 89 is a schematic view showing the positional relationship between a bonding tool and a semiconductor device when viewed in the X direction of FIG. 83. FIG. 89 is a schematic view showing a path of a current loop according to a tenth embodiment.

[0011] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment described previously can be applied to the remaining portions of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments can also be partially combined together even if not explicitly stated, as long as there is no particular problem with the combination. Note that the term "A and / or B" means at least one of A and B. In other words, it may include only A, only B, or both A and B.

[0012] The semiconductor device and the semiconductor module including the semiconductor device according to the present embodiment are applied to, for example, a power conversion device for a mobile body using a rotating electric machine as a drive source. The mobile body may be, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, construction machinery, or agricultural machinery. An example of application to a vehicle will be described below.

[0013] First Embodiment First, a schematic configuration of a vehicle drive system will be described with reference to FIG.

[0014] <Vehicle Drive System> As shown in FIG. 1 , a vehicle drive system 1 includes a DC power supply 2 , a motor generator 3 , and a power conversion device 4 .

[0015] The DC power supply 2 is a DC voltage source formed by a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power supply 2 and the motor generator 3.

[0016] <Power Conversion Device> Next, the circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6, which is a power conversion circuit.

[0017] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power supply line on the high potential side, and an N line 8, which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0018] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts DC voltage into three-phase AC voltage under switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into DC voltage under switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.

[0019] The inverter 6 is configured to include upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side.

[0020] The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. Of the upper and lower arm circuits 9, the U-phase upper and lower arm circuit 9U is connected to the U-phase winding 3a via a corresponding output line 10. The V-phase upper and lower arm circuit 9V is connected to the V-phase winding 3a via a corresponding output line 10. The W-phase upper and lower arm circuit 9W is connected to the W-phase winding 3a via a corresponding output line 10. At least a portion of each of the P line 7, the N line 8, and the output lines 10 is formed of a conductive member such as a bus bar.

[0021] The inverter 6 has six arms. Each arm is configured with a switching element. The number of switching elements constituting each arm is not particularly limited. It may be one or more. When there are more than one switching elements, the multiple switching elements connected in parallel with each other are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0022] In this embodiment, an n-channel MOSFET 11 is used as the switching element constituting each arm. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are connected to each other.

[0023] A freewheeling diode 12 is connected in antiparallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0024] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is also connected in antiparallel.

[0025] The inverter 6 includes a snubber circuit 13 in addition to the upper and lower arm circuits 9 described above. The snubber circuit 13 absorbs a transient high voltage that occurs during switching, a so-called switching surge. This enables high-speed switching. The snubber circuit 13 may be provided individually for the upper and lower arm circuits 9 and connected in parallel to the corresponding upper and lower arm circuits 9. The snubber circuit 13 may be provided individually for each arm 9H, 9L and connected in parallel to the corresponding arm 9H, 9L. As an example, the snubber circuit 13 in this embodiment is connected in parallel to the upper and lower arm circuits 9.

[0026] The snubber circuit 13 has at least a capacitor 131. The snubber circuit 13 may be, for example, a C snubber circuit having the capacitor 131, or an RC snubber circuit having the capacitor 131 and a resistor 132 as shown in Fig. 1. It may also be an RCD snubber circuit having the capacitor 131, the resistor 132, and a diode.

[0027] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage, for example, into a DC voltage of a different value. The converter is provided between the DC power source 2 and the smoothing capacitor 5. The converter is configured with, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage step-up and step-down. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power source 2. The filter capacitor is provided between the DC power source 2 and the converter.

[0028] The power conversion device 4 may include a drive circuit for the switching elements that constitute the inverter 6 and the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0029] The power conversion device 4 may include a control circuit for the switching elements. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a host ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0030] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured with, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0031] <Semiconductor Module> Fig. 2 is a perspective view showing an example of a semiconductor module. Fig. 3 is a top plan view of the semiconductor module shown in Fig. 2. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 3. Fig. 4 shows a simplified structure of the semiconductor module. The housing is omitted from Fig. 4.

[0032] In the following, the thickness direction of the substrate is referred to as the Z direction, and one direction perpendicular to the Z direction is referred to as the Y direction. The direction perpendicular to both the Z direction and the Y direction is referred to as the X direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, the planar view from the Z direction may be simply referred to as the planar view.

[0033] 2, 3, and 4, the semiconductor module 20 may include a semiconductor device 21, a housing 22, and a cooler 23. The semiconductor module 20, together with a capacitor device that provides the smoothing capacitor 5, an input terminal block, an output terminal block, and the like, constitutes the power conversion device 4. The semiconductor module 20 may be housed in a case of the power conversion device 4 together with other elements such as the capacitor device.

[0034] The semiconductor device 21 is arranged on one surface of the cooler 23 in the Z direction. The semiconductor device 21 provides at least one arm of the inverter 6, which is a power conversion circuit. Each of the semiconductor devices 21 illustrated in FIG. 2 provides the upper and lower arm circuits 9 for one phase. The semiconductor module 20 includes three semiconductor devices 21 to provide the inverter 6. The three semiconductor devices 21 are arranged on the same surface of the cooler 23 and are lined up in the X direction. Each of the semiconductor devices 21 is fixed to the cooler 23.

[0035] One of the semiconductor devices 21, semiconductor device 21U, provides the U-phase upper and lower arm circuit 9U. Another of the semiconductor devices 21, semiconductor device 21V, provides the V-phase upper and lower arm circuit 9V. Another of the semiconductor devices 21, semiconductor device 21W, provides the W-phase upper and lower arm circuit 9W. In other words, the semiconductor module 20 provides the inverter 6. Details of the semiconductor device 21 will be described later.

[0036] The housing 22 is formed using an electrically insulating material such as resin. The housing 22 may be, for example, a resin molded body. The housing 22 may hold some of the components of the semiconductor device 21. Some of the components of the semiconductor device 21 may be integrally molded with the housing 22 as an insert part. The housing 22 may be fixed to the cooler 23. The housing 22 may be fixed to the case of the power conversion device 4 together with the cooler 23. The housing 22 may be arranged on one side of the cooler 23 and, together with the cooler 23, provide an accommodation space for the semiconductor device 21. A sealant that seals the semiconductor element 30 and the like may be arranged in the accommodation space formed by the housing 22 and the cooler 23. The sealant is, for example, a gel or a potting resin.

[0037] 2 and 3 , the housing 22 may include a frame 221 and a partition wall 222. The frame 221 has a predetermined height in the Z direction and is annular so as to surround the semiconductor device 21 in a plan view in the Z direction. The frame 221 may be referred to as an annular wall portion. The frame 221 may have a substantially rectangular annular shape. The rectangular annular frame 221 has four walls 221a, 221b, 221c, and 221d.

[0038] The walls 221a and 221b extend in the X direction. The walls 221a and 221b are arranged opposite each other with a predetermined gap in the Y direction. The wall 221a is arranged on one end side of the semiconductor device 21 in the Y direction, and the wall 221b is arranged on the other end side of the semiconductor device 21. The walls 221a and 221b include walls that define an area and extensions that extend outward from the walls in the Y direction. The walls 221c and 221d extend in the Y direction. The wall 221c is continuous with the walls 221a and 221b at one end side in the X direction. The wall 221d is continuous with the walls 221a and 221b at the other end side in the X direction.

[0039] The partition wall 222 has a predetermined height in the Z direction and is continuous with the frame body 221. The partition wall 222 divides the area defined by the frame body 221 into a plurality of areas. The partition wall 222 may divide the area into areas corresponding to the number of semiconductor devices 21, for example. The partition wall 222 is sometimes referred to as a partition wall. The partition wall 222 may extend in a predetermined direction, and both ends thereof may be continuous with the frame body 221. As illustrated in FIGS. 2 and 3 , the housing 22 may have two partition walls 222a and 222b as the partition wall 222. The partition walls 222a and 222b extend in the Y direction, similar to the walls 221c and 221d. One end of each of the partition walls 222a and 222b is continuous with the wall portion 221a, and the other end is continuous with the wall portion 221b. The partition walls 222a and 222b and the wall portions 221c and 221d are aligned in the X direction at a predetermined interval. The partition walls 222 divide the opposing area of ​​the frame body 221 into three areas. A semiconductor device 21 is housed in each of the three divided areas.

[0040] The cooler 23 cools the semiconductor devices 21. The cooler 23 is made of a metal material such as aluminum or copper. As shown in FIG. 4, the cooler 23 may have a flow path 231 therein. The flow path 231 is provided so as to overlap at least a portion of the semiconductor device 21 in a plan view so as to effectively cool the semiconductor device 21. The flow path 231 may be provided so as to encompass most of each semiconductor device 21 in a plan view.

[0041] A refrigerant 232 is supplied to the flow path 231 via an inlet pipe (not shown). The refrigerant 232 that has flowed through the flow path 231 is discharged to the outside of the cooler 23 via an outlet pipe (not shown). As the refrigerant 232, a refrigerant that changes phase, such as water or ammonia, or a refrigerant that does not change phase, such as an ethylene glycol-based refrigerant, can be used.

[0042] The cooler 23 is not limited to the above-described configuration having the flow path 231. A heat dissipation member such as a heat sink may be used as the cooler 23. A heat sink is sometimes referred to as a cooling plate. The heat dissipation member may include heat dissipation fins. If insulation is not required, a bonding material may be disposed between the semiconductor device 21 and the cooler 23. In the example shown in FIG. 4 , a bonding material 24 is interposed between the semiconductor device 21 and the cooler 23. Examples of the bonding material 24 include solder and sintered Ag. The semiconductor module 20 includes the bonding material 24 disposed between the semiconductor device 21 and the cooler 23. The semiconductor device 21 is fixed to the cooler 23 by bonding. If insulation is required, an electrically insulating material may be disposed between the semiconductor device 21 and the cooler 23. Examples of the insulating material include a ceramic plate and a resin sheet. To improve thermal conductivity, a thermal insulating material (TIM) such as silicone gel may be used. TIM stands for Thermal Interface Material.

[0043] The semiconductor module 20 may include a circuit board (not shown). The drive circuit described above is formed on the circuit board. The circuit board is arranged above the semiconductor devices 21 in the Z direction. The semiconductor module 20 may also include a cover that provides a housing together with the housing 22 and the cooler 23. The cover is arranged on the opposite side of the semiconductor devices 21 from the cooler 23. The cover may be arranged to cover the three semiconductor devices 21 as a whole.

[0044] <Semiconductor Device> Fig. 5 is a top plan view showing an example of a semiconductor device. Fig. 5 is an enlarged view of one semiconductor device from Fig. 3. Fig. 5 also shows a part of the housing. Fig. 6 is a plan view showing the wiring pattern of the substrate in the semiconductor device shown in Fig. 5.

[0045] As described above, the semiconductor device 21 may provide one phase of the upper and lower arm circuits 9. As illustrated in Fig. 5, the semiconductor device 21 may include a semiconductor element 30, a substrate 40, a clip 50, an external connection terminal 60, and a snubber circuit 70.

[0046] The semiconductor element 30 is a vertical element formed on a semiconductor substrate made of silicon (Si) or a wide bandgap semiconductor having a wider bandgap than silicon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO). ２ O ３ ), diamond. The semiconductor element 30 may be called a power element, a semiconductor chip, or the like.

[0047] The vertical element is configured to pass a main current in the thickness direction of the semiconductor element 30 (semiconductor substrate). The semiconductor element 30 is disposed so that its thickness direction is substantially parallel to the Z direction. The semiconductor element 30 has main electrodes on both sides in the thickness direction. The semiconductor element 30 of this embodiment is formed by forming an n-channel MOSFET 11 as a vertical element on a semiconductor substrate made of SiC. As shown in FIGS. 4 and 5 , the semiconductor element 30 has a drain electrode 31 on its bottom surface facing the substrate 40 and a source electrode 32 on its top surface opposite the bottom surface, as main electrodes.

[0048] When the MOSFET 11 is turned on, a current (main current) flows between the main electrodes, that is, between the drain electrode 31 and the source electrode 32. If the diode 12 is a parasitic diode, the source electrode 32 also serves as the anode electrode, and the drain electrode 31 also serves as the cathode electrode. The diode 12 may be formed on a chip separate from the MOSFET 11. The drain electrode 31 is the main electrode on the high potential side, and the source electrode 32 is the main electrode on the low potential side. The drain electrode 31 is formed over almost the entire bottom surface. The source electrode 32 is formed on a portion of the top surface.

[0049] The semiconductor element 30 has a generally rectangular shape in plan view. The semiconductor element 30 has, on its upper surface, pads 33 that are electrodes for signals. The pads 33 are formed at positions on the upper surface that are different from the source electrodes 32. The pads 33 include at least a gate pad.

[0050] The multiple semiconductor elements 30 include a semiconductor element 30H that constitutes the upper arm 9H and a semiconductor element 30L that constitutes the lower arm 9L. The semiconductor element 30H is sometimes referred to as an upper arm element. The semiconductor element 30L is sometimes referred to as a lower arm element. For example, the semiconductor elements 30H and 30L may have a common configuration. In this embodiment, the semiconductor element 30H corresponds to a first element, and the semiconductor element 30L corresponds to a second element.

[0051] The semiconductor elements 30H and 30L are aligned in the Y direction. The pad 33 of the semiconductor element 30H is provided near the end on the P terminal 611 and N terminal 612 side in the Y direction. The pad 33 of the semiconductor element 30L is provided near the end on the O terminal 613 side in the Y direction. The pads 33 are provided near the outer ends, not the inner ends facing each other. The semiconductor elements 30H and 30L are arranged at approximately the same position as each other in the Z direction. The semiconductor elements 30H and 30L are arranged in the same orientation so that the drain electrodes 31 are on the substrate 40 side.

[0052] The number of each of the semiconductor elements 30H, 30L is not particularly limited. There may be one of each, or multiple of each. In the examples shown in Figures 2, 3, and 5, the semiconductor element 30 includes four of each of the semiconductor elements 30H, 30L. Four semiconductor elements 30H are connected in parallel to provide the MOSFET 11 of the upper arm 9H of one phase. Four semiconductor elements 30L are connected in parallel to provide the MOSFET 11 of the lower arm 9L of one phase. The four semiconductor elements 30H are lined up in the X direction. The four semiconductor elements 30L are lined up in the X direction.

[0053] The substrate 40 contains all of the semiconductor elements 30 (30H, 30L) in a plan view. The substrate 40 is disposed on the drain electrode 31 side of the semiconductor elements 30. As will be described later, the substrate 40 is electrically connected to the drain electrode 31 and provides a wiring function. The substrate 40 may also be referred to as a wiring board, a printed circuit board, or the like.

[0054] The substrate 40 has an insulating base material 41 and a conductor disposed on the insulating base material 41. The insulating base material 41 is formed using an electrically insulating material such as ceramic or resin. As shown in Fig. 4, the insulating base material 41 has one surface 41a that faces the semiconductor element 30 and a back surface 41b that is the surface opposite to the one surface 41a in the Z direction. The substrate 40 may be divided into units of semiconductor devices 21, or may be integrated into units of semiconductor modules 20.

[0055] The conductor is formed from a metal such as Cu or Al that has good electrical and thermal conductivity. The conductor may have a plating film of Ni-based metal or Au-based metal on its surface. The conductor may be disposed on only one surface 41a of the insulating substrate 41, or on both the one surface 41a and the back surface 41b. The conductor may be disposed inside the insulating substrate 41. In other words, the substrate 40 may be a single-sided substrate, a double-sided substrate, or a multilayer substrate having three or more layers of conductors. The conductor may include a via conductor. The via conductor is formed by disposing a conductor such as a plating in a through hole (via) formed in an insulating layer that constitutes the insulating substrate 41. The via conductor electrically connects conductors disposed on different layers.

[0056] The substrate 40 has conductors 42 arranged on one surface 41a. The conductors 42 are patterned. The patterned conductors 42 provide wiring, i.e., circuits. The conductors 42 include P wiring 421, N wiring 422, O wiring 423, relay wiring 424, and signal wiring 425, 426. Each wiring is electrically separated by a predetermined interval (gap). The substrate 40 has a conductor 43 arranged on the back surface 41b.

[0057] The P wiring 421 is connected to the drain electrode 31 of the semiconductor element 30H. The P wiring 421 is connected to a P terminal 611, which will be described later. The P wiring 421 electrically connects the drain electrode 31 of the semiconductor element 30H and the P terminal 611. The P wiring 421 may be referred to as a positive wiring, a high-potential power supply wiring, or the like. In this embodiment, the P wiring 421 corresponds to the first wiring.

[0058] The P wiring 421 has a base 421a and an extension 421b. The base 421a extends in the direction in which the semiconductor elements 30H are arranged, i.e., in the X direction. The semiconductor element 30H is disposed on the base 421a. The base 421a and the drain electrode 31 of the semiconductor element 30H are connected via a bonding material.

[0059] The extension portion 421b is connected to the base portion 421a and extends from the base portion 421a in the Y direction. The extension portion 421b is connected to the base portion 421a near the longitudinal center. The extension portion 421b extends in a direction away from the semiconductor element 30H. The P wiring 421 is generally T-shaped in plan view. The P wiring 421 is disposed approximately symmetrically with respect to the center line CL of the substrate 40, which is indicated by a two-dot chain line in FIG. 6. The center line CL is an imaginary line that bisects the substrate 40 in the X direction. The extension portion 421b of the substrate 40 has a terminal connection portion 421c at the end opposite the connection end with the base portion 421a. The P terminal 611 is connected to the terminal connection portion 421c. A capacitor 71 of a snubber circuit 70 is connected to the extension portion 421b between the end connected to the base portion 421a and the terminal connection portion 421c.

[0060] The N wiring 422 is connected to the N terminal 612. The source electrode 32 of the semiconductor element 30L is electrically connected to the N wiring 422 via the clip 50L. The N wiring 422 electrically connects the source electrode 32 of the semiconductor element 30L and the N terminal 612. The N wiring 422 may be referred to as a negative wiring, a low potential power supply wiring, or the like. The N wiring 422 corresponds to the second wiring.

[0061] The N wiring 422 has a base 422a and an extension 422b. The base 422a extends in the X direction. The base 422a is disposed adjacent to the base 421a of the P wiring 421 in the Y direction. The base 421a is disposed between the base 421a of the P wiring 421 and the base 423a of the O wiring 423. The base 422a extends from near one end to near the other end of the substrate 40 in the X direction. A clip 50L is connected to the base 422a.

[0062] The extension portion 422b is connected to the base portion 422a and extends from the base portion 422a generally in the Y direction. The extension portion 422b extends in a direction away from the semiconductor element 30L. The N wiring 422 has two extension portions 422b. The extension portions 422b are connected to both ends of the base portion 422a in the X direction. The vicinity of each tip of the extension portions 422b extends toward the terminal connection portion 421c of the P wiring 421. The N wiring 422 is generally C-shaped in plan view. The N wiring 422 is arranged generally symmetrically with respect to the center line CL of the substrate 40.

[0063] Each of the extension portions 422b has a terminal connection portion 422c at the end opposite the connection end with the base portion 422a. The two terminal connection portions 422c are arranged next to the terminal connection portion 421c. The two terminal connection portions 422c and one terminal connection portion 421c are lined up in the X direction. The two terminal connection portions 422c sandwich the terminal connection portion 421c. The N terminal 612 is connected to the terminal connection portion 422c. A resistor 72 of the snubber circuit 70 is connected to the extension portion 422b between the connection end with the base portion 422a and the terminal connection portion 422c. The resistor 72 is connected to the portion of the extension portion 422b extending in the Y direction.

[0064] The O wiring 423 is connected to the drain electrode 31 of the semiconductor element 30L. The O wiring 423 is connected to an O terminal 613, which will be described later. The source electrode 32 of the semiconductor element 30H is electrically connected to the O wiring 423 via a clip 50H. The O wiring 423 electrically connects the source electrode 32 of the semiconductor element 30H, the drain electrode 31 of the semiconductor element 30L, and the O terminal 613. The O wiring 423 is sometimes referred to as an output wiring, etc.

[0065] The O wiring 423 has a base 423a and an extension 423b. The base 423a extends in the X direction. The base 423a is disposed adjacent to the base 422a of the N wiring 422 in the Y direction. The base 423a extends from near one end of the substrate 40 to near the other end in the Y direction. The semiconductor element 30L is disposed on the base 423a. The base 423a and the drain electrode 31 of the semiconductor element 30L are connected via a bonding material. A clip 50H is connected to the base 423a.

[0066] The extension portion 423b is connected to the base portion 423a and extends from the base portion 423a in the Y direction. The extension portion 423b is connected to the base portion 423a near the center of the longitudinal direction. The extension portion 423b extends in a direction away from the semiconductor elements 30H, 30L. The O wiring 423 is generally T-shaped in plan view. The O wiring 423 is arranged symmetrically with respect to the center line CL of the substrate 40. The extension portion 422b has a terminal connection portion 423c. The O terminal 613 is connected to the terminal connection portion 423c. In the Y direction, the length of the extension portion 423b is shorter than the length of the extension portion 421b. As an example, the entire extension portion 422b forms the terminal connection portion 423c.

[0067] The relay wiring 424, together with electronic components described below, provides the snubber circuit 70. The relay wiring 424, together with the electronic components of the snubber circuit 70, electrically bridges the P wiring 421 and the N wiring 422. One or more relay wirings 424 may be provided in one current path of the snubber circuit 70. The relay wiring 424 illustrated in FIGS. 5 and 6 has two relay wirings 424a and 424b in one current path. The relay wirings 424a and 424b are arranged between the two extension portions 422b and the extension portion 421b, respectively. The substrate 40 has two sets of relay wirings 424a and 424b.

[0068] The relay wirings 424a and 424b are aligned in the X direction between the extension portion 421b of the P wiring 421 and the extension portion 422b of the N wiring 422. Both relay wirings 424a and 424b have a generally rectangular shape in plan view. The relay wiring 424a is arranged next to the extension portion 421b, and the relay wiring 424b is arranged next to the extension portion 422b. The relay wirings 424 are arranged symmetrically with respect to the center line CL of the substrate 40. The relay wirings 424a and 424b have generally the same length in the Y direction. The relay wiring 424a has a longer length in the X direction than the relay wiring 424b. A capacitor 71 and a resistor 72 are connected to the relay wiring 424a. A resistor 72 is connected to the relay wiring 424b.

[0069] The signal wiring 425 electrically connects the pad 33 of the semiconductor element 30H to the corresponding signal terminal 62. The signal wiring 425 is connected to the pad 33 via a bonding wire 80. The signal wiring 425 is connected to the signal terminal 62 via a bonding wire 80. The signal wiring 425 extends in the X direction. The signal wiring 425 is disposed between the base 421a of the P wiring 421 and the relay wiring 424 in the Y direction. In other words, the signal wiring 425 is disposed between the semiconductor element 30H and the snubber circuit 70. The signal wiring 425 is disposed between the extension portion 421b of the P wiring 421 and the extension portion 422b of the N wiring 422 in the X direction.

[0070] The signal wiring 425 is arranged between each of the two extension portions 422b and the extension portion 421b. The signal wiring 425 is arranged on both sides of the extension portion 421b in the X direction. The signal wiring 425 arranged on one side of the extension portion 421b is connected to the pads 33 of the two semiconductor elements 30H. The signal wiring 425 arranged on the other side of the extension portion 421b is connected to the pads 33 of the remaining two semiconductor elements 30H. The signal wiring 425 separated by the extension portion 421b may be electrically connected via bonding wires. If the substrate 40 is a printed circuit board, the signal wiring 425 separated by the extension portion 421b may be electrically connected to each other via wiring inside the substrate (not shown). The number of signal wirings 425 is not particularly limited. The substrate 40 has a number of signal wirings 425 depending on the type of signal and the division structure. The signal wirings 425 are arranged symmetrically with respect to the center line CL of the substrate 40.

[0071] The signal wiring 426 electrically connects the pad 33 of the semiconductor element 30L to the corresponding signal terminal 62. The signal wiring 426 is connected to the pad 33 via a bonding wire 80. The signal wiring 426 is connected to the signal terminal 62 via a bonding wire 80. The signal wiring 426 extends in the X direction. The signal wiring 426 is arranged between the end of the substrate 40 and the base 423a of the O wiring 423 in the Y direction. The signal wiring 426 is arranged between the end of the substrate 40 and the extension portion 423b of the O wiring 423 in the X direction. The signal wiring 426 is arranged on both sides of the extension portion 423b in the X direction.

[0072] The signal wiring 426 arranged on one side of the extension portion 423b is connected to the pads 33 of two semiconductor elements 30L. The signal wiring 426 arranged on the other side of the extension portion 423b is connected to the pads 33 of the remaining two semiconductor elements 30L. The signal wiring 426 separated by the extension portion 423b may be electrically connected via bonding wires. The signal wiring 426 separated by the extension portion 423b may be electrically connected to each other by wiring inside the substrate (not shown). The signal terminals 62 corresponding to the separated signal wiring 426 may be integrally connected to each other. The number of signal wirings 426 is not particularly limited. The substrate 40 has a number of signal wirings 426 according to the type of signal and the division structure.

[0073] The clip 50 may also be referred to as a bridging member, relay member, metal bridge, etc. The clip 50 is a metal plate material whose base material is a metal with good conductivity, such as Cu or a Cu alloy. The clip 50 may be formed by punching and pressing a metal plate of a predetermined thickness. The clip 50 may also be formed using a profiled material with a different thickness in parts. The clip 50 may have a film applied to the surface of the base material by surface treatment. The clip 50 may have a plated film of Ni, Au, or the like on its surface. The clip 50 may have a Ni plated film containing P formed on the base material. The NiP film is formed by electroless plating. Instead of Cu, Ag, Au, Al, Mg, etc. may be used as the base material. Instead of Ni or Au, Sn, Ag, etc. may be used as the film applied to the base material.

[0074] The clips 50 include a clip 50H connected to the semiconductor element 30H and a clip 50L connected to the semiconductor element 30L. The clip 50H electrically connects the source electrode 32 of the semiconductor element 30H to the base 423a of the O wiring 423. The clips 50H extend in the Y direction. The clips 50H may be provided individually for each semiconductor element 30H, or may be provided collectively for multiple semiconductor elements 30H. As shown in FIG. 5 and other figures, one clip 50H may be provided for two semiconductor elements 30H. The semiconductor device 21 includes two clips 50H. Each of the clips 50H is substantially Y-shaped in plan view.

[0075] The clip 50L electrically connects the source electrode 32 of the semiconductor element 30L and the base 422a of the N wiring 422. The clip 50L extends in the Y direction. The clip 50L may be provided individually for each semiconductor element 30L, or may be provided collectively for multiple semiconductor elements 30L. In the example shown in FIG. 5 and other figures, the clip 50L is provided individually for each semiconductor element 30L. The semiconductor device 21 includes four clips 50L.

[0076] The external connection terminals 60 are terminals for electrically connecting the semiconductor device 21 to external devices. The external connection terminals 60 are formed using a metal material with good conductivity, such as copper. The external connection terminals 60 are, for example, a plate material. The external connection terminals 60 include a main terminal 61 and a signal terminal 62. The main terminal 61 is a terminal electrically connected to a main electrode of the semiconductor element 30. The signal terminal 62 is a terminal electrically connected to a pad 33 of the semiconductor element 30. The main terminal 61 includes a P terminal 611 and an N terminal 612, which are power supply terminals, and an O terminal 613.

[0077] The P terminal 611 is the external connection terminal 60 electrically connected to the P line 7 described above. The P terminal 611 is electrically connected to the positive terminal of the smoothing capacitor 5. The P terminal 611 may also be referred to as a positive terminal, a high-potential power supply terminal, or the like. The P terminal 611 is connected to the terminal connection portion 421c of the P wiring 421. The P terminal 611 is electrically connected via the P wiring 421 to the drain electrode 31 of the semiconductor element 30H that constitutes the upper arm 9H.

[0078] As shown in FIG. 2 and other figures, the P terminal 611 has a connection portion 611a for connecting to an external device and a connection portion 611b for connecting to the circuit board 40. The P terminal 611 generally extends in the Y direction. One of the Y-direction ends of the P terminal 611 forms the connection portion 611a, and the other Y-direction end forms the connection portion 611b. In the example shown in FIG. 2 and other figures, a portion of the P terminal 611 is held by the frame 221 of the housing 22. The connection portion 611a of the P terminal 611 protrudes outward from the wall portion 221a of the frame 221, and the connection portion 611b protrudes inward from the wall portion 221a, i.e., toward the partitioned area. The P terminal 611 has one connection portion 611a and one connection portion 611b. The connection portion 611b is connected to the terminal connection portion 421c of the P wiring 421. A capacitor device providing the smoothing capacitor 5 is connected to the connection portion 611a, for example, via a bus bar or the like.

[0079] The N terminal 612 is an external connection terminal 60 electrically connected to the above-described N line 8. The N terminal 612 is electrically connected to the negative terminal of the smoothing capacitor 5. The N terminal 612 may also be referred to as a negative terminal, a low-potential power supply terminal, or the like. The N terminal 612 is connected to the terminal connection portion 422c of the N wiring 422. The N terminal 612 is electrically connected to the source electrode 32 of the semiconductor element 30L constituting the lower arm 9L via the N wiring 422 and a clip 50L.

[0080] The N terminal 612 has a connection portion 612a for connecting to an external device and a connection portion 612b for connecting to the circuit board 40. The N terminal 612 extends generally in the Y direction. One of the Y-direction ends of the N terminal 612 forms the connection portion 612a, and the other Y-direction end forms the connection portion 612b. In this embodiment, as an example, a portion of the N terminal 612 is held by the frame 221 of the housing 22. The connection portion 612a of the N terminal 612 protrudes outward from the wall portion 221a of the frame 221, and the connection portion 612b protrudes inward from the wall portion 221a. The N terminal 612 has one connection portion 612a and two connection portions 612b. One of the connection portions 612b is connected to one of the terminal connection portions 421c of the N wiring 422, and the other connection portion 612b is connected to the other one of the terminal connection portions 421c. The smoothing capacitor 5 is connected to the connection portion 612a via, for example, a bus bar.

[0081] The O terminal 613 is an external connection terminal 60 electrically connected to the output line 10. The O terminal 613 is electrically connected to the winding 3a of the opposing phase of the motor generator 3. The O terminal 613 may also be referred to as an output terminal, an AC terminal, or the like. The semiconductor module 20 includes, as the O terminals 613, a U-phase O terminal 613U, a V-phase O terminal 613V, and a W-phase O terminal 613W.

[0082] The O terminal 613 is connected to the terminal connection portion 423c of the O wiring 423. The O terminal 613 is electrically connected to the drain electrode 31 of the semiconductor element 30L constituting the lower arm 9L via the O wiring 423. The O terminal 613 is electrically connected to the source electrode 32 of the semiconductor element 30H constituting the upper arm 9H via the O wiring 423 and the clip 50H.

[0083] The O terminal 613 has a connection portion 613a for connecting to an external device and a connection portion 613b for connecting to the circuit board 40. The O terminal 613 extends generally in the Y direction. One of the Y-direction ends of the O terminal 613 forms the connection portion 613a, and the other Y-direction end forms the connection portion 613b. In this embodiment, as an example, a portion of the O terminal 613 is held by the frame 221 of the housing 22. The connection portion 613a of the O terminal 613 protrudes outward from the wall portion 221b of the frame 221, and the connection portion 613b protrudes inward from the wall portion 221b. The O terminal 613 has one connection portion 613a and one connection portion 613b. The connection portion 613b is connected to the terminal connection portion 423c of the O wiring 423. The motor generator 3 is connected to the connection portion 613a via, for example, a bus bar or the like.

[0084] The signal terminals 62 electrically connect the semiconductor element 30 to a circuit board (not shown). The signal terminals 62 are electrically connected to the pads 33 of the semiconductor element 30 via connecting members such as bonding wires 80. The number of signal terminals 62 is not particularly limited. The signal terminals 62 only need to include at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element 30. The signal terminals 62 may include a terminal for detecting the source potential of the semiconductor element 30. The signal terminals 62 may include a terminal for detecting the drain potential of the semiconductor element 30. The signal terminals 62 may include a terminal for detecting the temperature of the semiconductor element 30.

[0085] The signal terminal 62 has a connection portion 621 with the circuit board and a connection portion 622 with the signal wiring 425, 426. One end of the signal terminal 62 in the extension direction forms the connection portion 621, and the other end forms the connection portion 622. In the example shown in FIG. 2 and other figures, a portion of the signal terminal 62 is held by the walls 221b, 221c and the partition walls 222a, 222b of the frame body 221. The signal terminal 62 on the upper arm 9H side is held by the frame body 221 and the partition wall 222. For example, the U-phase signal terminal 62 is held by the wall 221c of the frame body 221. The V-phase signal terminal 62 is held by the partition wall 222a, and the W-phase signal terminal 62 is held by the partition wall 222b. The signal terminal 62 on the lower arm 9L is held by the wall 221b of the frame body 221.

[0086] The connection portion 621 of the signal terminal 62 protrudes upward from the upper end of the housing 22. The connection portion 622 protrudes inward from the housing 22. Each signal terminal 62 has a bent portion. The signal terminal 62 is, for example, substantially L-shaped. The connection portion 622 of the upper arm 9H is connected to the corresponding signal wiring 425 via a bonding wire 80. The connection portion 622 of the lower arm 9L is connected to the corresponding signal wiring 426 via a bonding wire 80. The connection portion 621 of the signal terminal 62 is connected to the above-mentioned circuit board.

[0087] The snubber circuit 70 includes at least a capacitor 71 as an electronic component. The snubber circuit 70 illustrated in FIG. 5 and other figures is an RC snubber circuit. In addition to the capacitor 71, the snubber circuit 70 includes a plurality of resistors 72. The snubber circuit 70 functions as the snubber circuit 13 shown in FIG. 1. The capacitor 71 provides the capacitor 131, and the resistor 72 provides the resistor 132. As described above, the snubber circuit 70 is connected in parallel with the upper and lower arm circuits 9. The snubber circuit 70 electrically bridges the P wiring 421 and the N wiring 422. The snubber circuit 70 includes the relay wiring 424 (424a, 424b) described above in addition to the capacitor 71 and the resistor 72.

[0088] The capacitor 71 is connected to the extension portion 421b of the P wiring 421 and the relay wiring 424a. The capacitor 71 electrically bridges the extension portion 421b and the relay wiring 424a. Some of the multiple resistors 72 are connected to the relay wiring 424a and the relay wiring 424b. Some of the resistors 72 electrically bridge the relay wirings 424a and 424b. Another part of the resistors 72 is connected to the relay wiring 424b and the extension portion 422b of the N wiring 422. Another part of the resistors 72 electrically bridges the relay wiring 424b and the extension portion 422b.

[0089] <Connection Structure Between Capacitor and Substrate> Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5. Fig. 7 shows an example of a connection structure between a capacitor constituting a snubber circuit and a substrate. Figs. 8, 9, and 10 each show other examples of the connection structure between a capacitor and a substrate.

[0090] 7, the capacitor 71 may be mounted on the substrate 40 via a bonding material such as solder 73. The terminals of the capacitor 71 are bonded to a P wiring 421 and a relay wiring 424.

[0091] As shown in FIG. 8 , the capacitor 71 may be sealed by a sealant 74. The sealant 74 may seal only the capacitor 71 among the components mounted on the substrate 40, or may seal the capacitor 71 and other components together. The sealant 74 is formed using an electrically insulating material such as resin or gel. The sealant 74 has a higher thermal conductivity than air. A filler may be added to the sealant 74 to increase the thermal conductivity. The sealant 74 is a thermally conductive member that thermally connects the capacitor 71 to the substrate 40 except for the joint portion with the capacitor 71.

[0092] As shown in Figure 9, a configuration may be adopted in which dummy wiring 44 is provided on the substrate 40, and heat from the capacitor 71 is dissipated to the substrate 40 side through the dummy wiring 44. The dummy wiring 44 is provided on the substrate 40 between the extension portion 421b of the P wiring 421 and the relay wiring 424 (424a). The dummy wiring 44 is electrically isolated from the other conductors 42 arranged on one surface 41a of the insulating base material 41, and does not provide a wiring function. The bottom surface of the main body of the capacitor 71 is in contact with the dummy wiring 44. The dummy wiring 44 is a thermally conductive member that thermally connects the capacitor 71 to a portion of the substrate 40 excluding the junction with the capacitor 71.

[0093] 10 , an adhesive 75 may be disposed between the capacitor 71 and the dummy wiring 44. The adhesive 75 may be a material with excellent thermal conductivity, such as TIM. The adhesive 75 is a thermally conductive member that is interposed between the capacitor 71 and the dummy wiring 44 and thermally connects the capacitor 71 to the portion of the substrate 40 excluding the joint portion with the capacitor 71.

[0094] <Capacitor Capacitance> The required capacitance C of a capacitor that constitutes a snubber circuit depends on the parasitic inductance Ldc of the main circuit outside the capacitor. Therefore, we investigated whether the required capacitance C could be specified using C / Ldc as a parameter.

[0095] FIG. 11 is a circuit diagram showing a verification model. In FIG. 11, the capacitance of the capacitor 131 of the snubber circuit 13 is indicated as C. In addition, in the main circuit connecting the smoothing capacitor 5 and the upper and lower arm circuits 9 (MOSFET 11), the parasitic inductance of the portion connecting the smoothing capacitor 5 and the snubber circuit 13 is indicated as Ldc. The parasitic inductance Ldc is the parasitic inductance of the portion of the main circuit from the connection point of the snubber circuit 13 to the smoothing capacitor 5. An inductive load 16 is connected to the midpoint of the upper and lower arm circuits 9. The inductive load 16 is sometimes referred to as an L load.

[0096] In the verification, the circuit constants were set as follows: In the main circuit, the parasitic inductance from the connection point of the snubber circuit 13 to the MOSFET 11 was set to 5 nH. The resistance value of the resistor 132 of the snubber circuit 13 was set to 0.1 Ω. The resistance value of the gate resistor 15 provided in the wiring connecting the gate driver (GD) 14 and the gate of the MOSFET 11 was set to 1 Ω. Vdd was set to 800 V, and the drain current Id flowing through the MOSFET 11 of the upper arm 9H was set to 400 A.

[0097] FIG. 12 is a diagram showing the verification results. In FIG. 12, the horizontal axis represents C / Ldc, and the vertical axis represents the ΔVds ratio. The ΔVds ratio is the ratio of the voltage Vds at each value of C / Ldc to the voltage Vds when C / Ldc is 0 (zero). The voltage Vds is the drain-source voltage. As shown in FIG. 12, the ΔVds ratio decreases as C / Ldc increases. The intersection of the two imaginary lines shown in FIG. 12 corresponds to the inflection point. The intersection is where C / Ldc = 0.004. The ΔVds ratio converges (saturates) in the range where C / Ldc exceeds 0.004.

[0098] Summary of First Embodiment According to the semiconductor device 21 and semiconductor module 20 of this embodiment, the signal wiring 425 that electrically connects the signal terminal 62 and the semiconductor element 30 (30H) is provided by intentional wiring patterning of the substrate 40. Furthermore, the signal wiring 425 is disposed between the semiconductor element 30 and the snubber circuit 70, as illustrated in FIGS. 5 and 6 . The capacitor 71 that constitutes the snubber circuit 70 is spaced apart from the semiconductor element 30 by the distance corresponding to the signal wiring 425. This allows the snubber circuit 70 to enable high-speed switching while reducing the effect of heat from the semiconductor element 30 on the capacitor 71. The placement of the signal wiring 425, which is the conductor 42, can suppress heat absorption by the capacitor 71.

[0099] Since the heat received by the capacitor 71 can be suppressed, the margin up to the upper limit temperature of the heat resistance of the capacitor 71 is increased. This allows the size of the capacitor 71 to be reduced. Furthermore, in a configuration in which a plurality of capacitors 71 are provided and connected in parallel for heat resistance purposes, the number of capacitors 71 can be reduced by suppressing heat reception. As a result, the size of the semiconductor device 21 can be reduced. Furthermore, the manufacturing cost can be reduced.

[0100] 13 shows the results of a simulation showing the temperature distribution caused by heat generation from the semiconductor element 30. In FIG. 13, the temperature distribution is indicated by the density of dots. The denser the dots, the higher the temperature, and the sparser the dots, the lower the temperature. It is clear from the simulation results shown in FIG. 13 that providing the signal wiring 425 as described above can reduce the temperature of the capacitor 71 that constitutes the snubber circuit 70.

[0101] The semiconductor device 21 may provide one phase of the upper and lower arm circuits 9. The semiconductor device 21 includes a semiconductor element 30H as a first element and a semiconductor element 30L as a second element. The first main terminal is a P terminal 611, and the second main terminal is an N terminal 612. The first wiring is a P wiring 421, and the second wiring is an N wiring 422. The drain electrode 31 of the semiconductor element 30H is electrically connected to the P wiring 421, and the source electrode 32 of the semiconductor element 30L is electrically connected to the N wiring 422. In this configuration, the signal wiring 425 may be disposed between the semiconductor element 30H and the snubber circuit 70. In a configuration in which the snubber circuit 70 (13) is connected in parallel to the upper and lower arm circuits 9, the effect of heat from the semiconductor element 30 on the capacitor 71 can be reduced.

[0102] The number of capacitors 71 is not particularly limited. It may be one or more. In order to achieve high-speed switching, it is effective to arrange multiple capacitors 71 near the semiconductor element 30 and increase the capacitance. Increasing the capacitance by using multiple capacitors 71 is also effective in suppressing a voltage increase due to LC resonance between the inductance (L) of the wiring connecting the snubber circuit 70 and the smoothing capacitor 5 and the capacitor 71 (C).

[0103] In this way, in a configuration in which the snubber circuit 70 includes multiple capacitors 71, it is preferable to arrange the multiple current paths so that the impedances of the multiple current paths including the capacitors 71 are equal to each other. This makes it possible to suppress current imbalance in the multiple current paths, i.e., the multiple capacitors 71. It is possible to suppress the uneven flow of current and the temperature rise of some of the capacitors 71. By suppressing current imbalance, the margin up to the upper limit temperature of the heat resistance of the capacitors 71 is increased. Therefore, the size of the capacitors 71 can be reduced. Furthermore, the number of capacitors 71 connected in parallel can be reduced. As a result, the size of the semiconductor device 21 can be reduced. Furthermore, manufacturing costs can be reduced.

[0104] The multiple current paths may be arranged symmetrically with respect to each other, thereby achieving a configuration in which the impedances are equal to each other. Note that the line-symmetric arrangement is not limited to a line symmetry in which the left and right sides of the symmetry axis (e.g., center line CL) are perfectly aligned. A roughly line-symmetric relationship is also possible. For example, the mounting positions of the capacitors 71 may be slightly offset from each other. The wiring patterns may be perfectly aligned with each other, while the arrangement of the capacitors 71 and resistors 72 may be the same on both sides. For example, in the example shown in FIG. 5 , the resistor 72 of one current path may be positioned next to the capacitor 71 of another current path. The roughly line-symmetric relationship allows the impedances of the multiple current paths to be roughly equal to each other, thereby suppressing power imbalances. Although not line-symmetric, multiple current paths may be arranged so that the impedances are equal.

[0105] The semiconductor device 21 may have the configuration illustrated in FIG. 5 . The semiconductor device 21 illustrated in FIG. 5 includes one P terminal 611, which is a first main terminal, and two N terminals 612, which are second main terminals. The P terminal 611 and the N terminal 612 are arranged side by side in the X direction, with the P terminal 611 being arranged between the N terminals 612. Furthermore, a semiconductor element 30H, which is a first element, and a semiconductor element 30L, which is a second element, are arranged side by side in the Y direction. The N wiring 422, which is a second wiring, is arranged to sandwich the P wiring 421, which is a first wiring, in the X direction. In other words, the P wiring 421 is arranged between two extension portions 422b of the N wiring 422.

[0106] 14, the semiconductor device 21 having such a configuration has two current paths including a P terminal 611 (first main terminal), a P wiring 421 (first wiring), a capacitor 71, an N wiring 422 (second wiring), and an N terminal 612 (second main terminal). The two current paths are arranged symmetrically with respect to the center line CL of the substrate 40. Therefore, the above-mentioned effects can be achieved.

[0107] If the capacitance of the capacitor 131 (71) constituting the snubber circuit 13 (70) is C and the parasitic inductance of the main circuit portion connecting the snubber circuit 13 and the smoothing capacitor 5 is Ldc, the capacitance C should be set so that C / Ldc>0.004. By setting the C value that satisfies the above relationship, the ΔVds ratio, that is, the surge voltage, can be effectively suppressed, as shown in Figure 12.

[0108] The capacitor 71 constituting the snubber circuit 70 may be joined to at least one of the P wiring 421 and the N wiring 422. That is, the capacitor 71 may be mounted on the substrate 40. Compared to a configuration using a separate substrate for the snubber circuit, the thermal resistance between the capacitor 71 and the substrate 40 can be reduced. This allows the heat of the capacitor 71 to be effectively dissipated through the substrate 40. The heat of the capacitor 71 can be effectively dissipated to the conductor 43 on the rear surface 41b side and further to the cooler 23. This allows the size of the capacitor 71 to be reduced. Furthermore, in a parallel-connected configuration, the number of capacitors 71 can be reduced.

[0109] The semiconductor device 21 may include a thermally conductive member that thermally connects the capacitor 71 to a portion of the substrate 40 other than the junction with the capacitor 71. The thermally conductive member may include, for example, a seal 74 or dummy wiring 44. An adhesive 75 may be interposed between the capacitor 71 and the dummy wiring 44. By including the thermally conductive member, heat from the capacitor 71 can be more effectively dissipated through the substrate 40. This improves the heat dissipation of the capacitor 71. This allows the size of the capacitor 71 to be reduced. Furthermore, in a parallel-connected configuration, the number of capacitors 71 can be reduced. By improving the heat dissipation of the capacitor 71, the switching speed can be further increased. The seal 74 and dummy wiring 44 may be combined. The seal 74, dummy wiring 44, and adhesive 75 may be combined.

[0110] <Modifications> In the configuration having one P terminal 611 and two N terminals 612, the current paths including the capacitors 71 of the snubber circuit 70 are arranged symmetrically about an axis, but this is not limiting. As shown in Fig. 15 , the current paths may be arranged symmetrically about an axis in a configuration having two P terminals 611 and one N terminal 612. For convenience, the source electrode 32, pad 33, O terminal 613, signal terminal 62, and bonding wire 80 are omitted from Fig. 15 .

[0111] The P terminal 611 and the N terminal 612 are arranged side by side in the X direction, and the N terminal 612 is arranged between the P terminals 611. Furthermore, the semiconductor element 30H and the semiconductor element 30L are arranged side by side in the Y direction, with the semiconductor element 30L on the P terminal 611 and N terminal 612 side. The P wiring 421 is arranged to sandwich the N wiring 422 in the X direction.

[0112] The P wiring 421 has a generally C-shape in plan view. P terminals 611 are connected to both ends of the C shape. Four semiconductor elements 30H are mounted on the base of the P wiring 421. The N wiring 422 has a generally T-shape in plan view. An N terminal 612 is connected to the tip of an extended portion of the N wiring 422. In the X direction, relay wiring 424 is disposed between both ends of the base of the N wiring 422 and the two extended portions of the P wiring 421. A capacitor 71 constituting a snubber circuit 70 bridges the P wiring 421 and the relay wiring 424, and a resistor 72 bridges the relay wiring 424 and the N wiring 422. The O wiring 423 is divided into two. One of the O wirings 423 is disposed between the base of the P wiring 421 and the base of the N wiring 422 in the Y direction. A semiconductor element 30L is mounted on this O wiring 423. The other O wiring 423 is provided at the end of the substrate 40 opposite to the P terminal 611 and the N terminal 612 .

[0113] The source electrode 32 of the semiconductor element 30H is connected to the O wiring 423 between the P wiring 421 and the N wiring 422 via a clip 50H. The source electrode 32 of the semiconductor element 30L is connected to the base of the N wiring 422 via a clip 50L. The two O wirings 423 are connected to each other via a clip 50M. The signal wiring 425 is arranged between the base of the P wiring 421 and the O wiring 423 provided at the edge of the substrate in the Y direction. The signal wiring 426 is arranged between the O wiring 423 surrounded by the P wiring 421 and the base of the N wiring 422. The signal wiring 426 extends in the X direction to a position facing the snubber circuit 70.

[0114] As described above, in the configuration shown in FIG. 15 , the signal wiring 426 is disposed between the semiconductor element 30L and the snubber circuit 70. This reduces the thermal effect of the semiconductor element 30L on the capacitor 71. Furthermore, the semiconductor device 21 includes two current paths, each including the N terminal 612 (first main terminal), the N wiring 422 (first wiring), the capacitor 71, the P wiring 421 (second wiring), and the P terminal 611 (second main terminal). The two current paths are arranged symmetrically with respect to the center line CL of the substrate 40, as shown in FIG. 15 . This reduces current imbalances in the multiple current paths, i.e., the multiple capacitors 71, as described above.

[0115] Although an example in which the semiconductor element 30H on the upper arm 9H side and the semiconductor element 30L on the lower arm 9L are aligned in the Y direction has been shown, this is not limiting. As shown in FIG. 16 , the semiconductor element 30H and the semiconductor element 30L may be aligned in the X direction. For convenience, the source electrode 32, pad 33, signal terminal 62, and bonding wire 80 are omitted from FIG. 16 . The semiconductor device 21 includes one P terminal 611 and one N terminal 612. The P terminal 611 and the N terminal 612 are aligned in the X direction. Furthermore, the semiconductor element 30H and the semiconductor element 30L are aligned in the X direction.

[0116] The P wiring 421 has a substantially L-shape in plan view. The semiconductor element 30H is mounted on the base of the P wiring 421. The extension portion of the P wiring 421 extends from the base in the Y direction. A P-terminal 611 is connected near the tip of the extension portion of the P wiring 421. The O wiring 423 has a substantially L-shape in plan view. The semiconductor element 30L is mounted on the base of the O wiring 423. The extension portion of the O wiring 423 extends from the base in the Y direction, in the same direction as the extension portion of the P wiring 421. An O-terminal 613 is connected near the tip of the extension portion of the O wiring 423. The N wiring 422 extends in the Y direction. The N wiring 422 is aligned with the base of the O wiring 423 in the Y direction. The N wiring 422 is arranged between the extension portions of the P wiring 421 and the O wiring 423 in the X direction. An N terminal 612 is connected to the vicinity of the end of the N wiring 422 .

[0117] The source electrode 32 of the semiconductor element 30H is connected to the base of the O wiring 423 via a clip 50H. The source electrode 32 of the semiconductor element 30L is connected to the N wiring 422 via a clip 50L. The relay wiring 424 is disposed between the extended portion of the P wiring 421 and the N wiring 422 in the X direction. The capacitor 71 constituting the snubber circuit 70 bridges the extended portion of the P wiring 421 and the relay wiring 424. The resistor 72 bridges the relay wiring 424 and the N wiring 422. The signal wiring 425 is disposed between the base of the P wiring 421 and the snubber circuit 70 in the Y direction. In other words, the signal wiring 425 is disposed between the semiconductor element 30H and the snubber circuit 70. This reduces the effect of heat from the semiconductor element 30H on the capacitor 71.

[0118] Although an example in which the snubber circuits 70 (13) are provided in parallel with the upper and lower arm circuits 9 has been shown, this is not limiting. As shown in FIG. 17 , the snubber circuits 70 may be provided in parallel with the arms. For convenience, the source electrodes 32, pads 33, signal terminals 62, and bonding wires 80 are omitted from FIG. 17 . The semiconductor device 21 shown in FIG. 17 includes one drain terminal 614 and one source terminal 615 as main terminals 61. The drain terminal 614 and the source terminal 615 are arranged side by side in the X direction.

[0119] The substrate 40 includes a drain wiring 427, a source wiring 428, and a signal wiring 429 as the conductors 42. The drain wiring 427 is substantially L-shaped in plan view. The semiconductor element 30 is mounted on the base of the drain wiring 427. The extension portion of the drain wiring 427 extends in the Y direction from the base. A drain terminal 614 is connected to the vicinity of the tip of the extension portion of the drain wiring 427. The source wiring 428 extends in the Y direction. The source wiring 428 is aligned with the base portion of the drain wiring 427 in the Y direction. The source wiring 428 is aligned with the extension portion of the drain wiring 427 in the X direction. A source terminal 615 is connected to the vicinity of the end of the source wiring 428.

[0120] The source electrode 32 of the semiconductor element 30 is connected to the source wiring 428 via the clip 50. The relay wiring 424 is arranged between the extended portion of the drain wiring 427 and the source wiring 428 in the X direction. The capacitor 71 that constitutes the snubber circuit 70 bridges the extended portion of the drain wiring 427 and the relay wiring 424. The resistor 72 bridges the relay wiring 424 and the source wiring 428. The signal wiring 429 is arranged between the base of the drain wiring 427 and the snubber circuit 70 in the Y direction. In other words, the signal wiring 429 is arranged between the semiconductor element 30 and the snubber circuit 70. Therefore, the effect of heat from the semiconductor element 30 on the capacitor 71 can be reduced.

[0121] Second Embodiment This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0122] <Semiconductor Element> FIG. 18 is a plan view showing an example of a semiconductor element 30 in a semiconductor device 21 according to this embodiment. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. Similar to the configurations shown in the preceding embodiments, the semiconductor element 30 includes a drain electrode 31, a source electrode 32, and pads 33. As shown in FIG. 18, the pads 33 include at least a gate pad 33G. The pads 33 may also include an anode pad 33A and a cathode pad 33C. The anode pad 33A and the cathode pad 33C are temperature detection pads connected to temperature-sensitive diodes. The pads 33 may also include a Kelvin source pad 33KS. The Kelvin source pad 33KS is a pad for detecting the potential of the source electrode 32. The semiconductor element 30 shown in FIG. 18 includes four pads 33. All of the pads 33 may be electrically connected to the signal terminals 62, or only some of the pads 33, including the gate pad 33G, may be electrically connected to the signal terminals 62.

[0123] The semiconductor element 30 includes a semiconductor substrate 34. The semiconductor substrate 34 has, for example, a substantially rectangular shape in plan view. The semiconductor substrate 34 has an element region 341 and a peripheral region 342. The element region 341 is located inside the two-dot chain line shown in FIG. 18 , and the peripheral region 342 is located outside it. The element region 341 is a region where a vertical element is formed. The MOSFET 11 is formed in the element region 341. The element region 341 may also be referred to as an active region, a main region, a cell region, or the like. The peripheral region 342 surrounds the element region 341 in plan view. A voltage-withstanding structure (not shown), such as a guard ring, is formed in the peripheral region 342.

[0124] The semiconductor substrate 34 has one surface 34a and a back surface 34b. The back surface 34b is the surface opposite to the one surface 34a in the thickness direction of the semiconductor substrate 34 (semiconductor element 30). The semiconductor element 30 includes an insulating film 35 disposed on the one surface 34a of the semiconductor substrate 34. The insulating film 35 is disposed on the peripheral region 342. The insulating film 35 is also disposed on a portion of the element region 341. The insulating film 35 may include, for example, polyimide. The insulating film 35 is sometimes referred to as a protective film.

[0125] The drain electrode 31 is disposed over almost the entire back surface 34b. The source electrode 32 is disposed on the first surface 34a, mainly on the element region 341. The pad 33 is disposed on the first surface 34a on the outer periphery region 342. The source electrode 32 has a multi-layer structure. The source electrode 32 has a lower layer 321 and an upper layer 322. The lower layer 321 may be formed using a material mainly composed of Al (aluminum), for example. The lower layer 321 may be formed using an Al alloy such as AlSi or AlSiCu. The lower layer 321 may also be referred to as an underlying electrode, wiring electrode, underlying layer, etc. The lower layer 321 is connected to the first surface 34a of the semiconductor substrate 34. The lower layer 321 is connected to the source and anode of the vertical element. The lower layer 321 extends from above the element region 341 to above the outer periphery region 342, and the outer periphery of the lower layer 321 is covered with an insulating film 35.

[0126] The upper layer 322 is laminated on the lower layer 321 for the purposes of improving the bonding strength with the solder and improving the wettability with the solder. The upper layer 322 may be formed, for example, using a material whose main component is Ni (nickel). The upper layer 322 may be a Ni-plated film containing P. A NiP film is formed by electroless plating. The upper layer 322 may also be referred to as an upper electrode, connection electrode, upper layer, plating layer, etc. An Au layer may be formed on the upper layer 322 during the manufacturing process. Au, for example, suppresses oxidation of Ni and improves the wettability with the solder. Since Au diffuses into the solder during soldering, it exists in the pre-bonded state, but not in the bonded state. The pad 33 has a configuration similar to that of the source electrode 32.

[0127] The semiconductor element 30 includes signal wiring. At least a portion of the signal wiring is disposed on the element region 341 of the first surface 34a. The signal wiring is disposed alongside the source electrode 32 in a plan view. The signal wiring may be disposed on the same surface as the lower layer 321 of the source electrode 32. The signal wiring may include, for example, a gate wiring 36 shown by a dashed line in FIG. 18. The gate wiring 36 electrically connects the gate of the MOSFET 11 formed in the element region 341 to a gate pad 33G. The signal wiring may include, for example, an anode wiring and a cathode wiring. The anode wiring electrically connects the anode of the temperature-sensitive diode to the anode pad 33A. The cathode wiring electrically connects the cathode of the temperature-sensitive diode to the cathode pad 33C. The signal wiring may include the gate wiring 36, the anode wiring, and the cathode wiring. For convenience, only the gate wiring 36 is shown in FIG. 18.

[0128] The insulating film 35 has openings 351 and 352. The opening 351 defines the junction region of the source electrode 32. The upper layer 322 is stacked on a portion of the lower layer 321 that faces the opening 351. The upper layer 322 is stacked on the upper layer 322 within the opening 351. The outer contour of the opening 351, i.e., the junction region (exposed portion) of the source electrode 32, substantially coincides with the outer contour of the element region 341 in a plan view in the plate thickness direction. The opening 352 defines the junction region of the pad 33.

[0129] The insulating film 35 has a peripheral portion 353 disposed on the peripheral region 342 and an upper element portion 354 disposed on the element region 341. The upper element portion 354 is continuous with the peripheral portion 353. The upper element portion 354 is disposed on the one surface 34a and covers the signal wiring disposed on the element region 341. The upper element portion 354 electrically isolates the signal wiring from the source electrode 32. The upper element portion 354 extends along the signal wiring. In a plan view, the upper element portion 354 is sandwiched between the source electrode 32. The upper element portion 354 and the peripheral portion 353 provide the wall surfaces of the opening 351. The source electrode 32 is in contact with the side surface of the upper element portion 354. The upper end of the upper element portion 354 is located above the upper surface of the source electrode 32, i.e., the surface exposed from the opening 351.

[0130] 18 , the upper element portion 354 covers the signal wiring including the gate wiring 36. The gate wiring 36 is disposed approximately at the center of the element region 341 in the X direction, and extends in the Y direction so as to divide the element region 341 approximately in half. The upper element portion 354 extends along the gate wiring 36, and divides the source electrode 32 approximately in half. The source electrode 32 is divided (compartmented) by the upper element portion 354. The upper element portion 354 is connected to the outer periphery 353 at both ends in the Y direction.

[0131] The pattern of the signal wiring including the gate wiring 36, i.e., the pattern of the element upper portion 354, is not limited to the example shown in Fig. 18. For example, it may have a cross shape in plan view. The element upper portion 354 may be connected to the outer periphery portion 353 only on the pad 33 side.

[0132] <Semiconductor Device and Semiconductor Module> The semiconductor device 21 of this embodiment includes at least the semiconductor element 30, metal plate, and solder illustrated in FIGS. 18 and 19 . The metal plate is solder-bonded to the main electrode. The metal plate may be the clip 50 described in the preceding embodiment, or may be a member other than the clip 50, such as a lead. The semiconductor device 21 may include a substrate having wiring. The semiconductor element 30 is mounted on the substrate. The clip 50, which is a metal plate, is bonded to the wiring as well as the main electrode. The semiconductor device 21 may include a sintered member. The semiconductor element 30 is connected to the metal member via the sintered member. The metal member may be wiring on the substrate or a metal plate such as a heat sink. The semiconductor device 21 may include a sealant that seals the semiconductor element 30 and the metal plate. A gel may be used as the sealant.

[0133] FIG. 20 shows an example of a semiconductor device 21 and a semiconductor module 20. FIG. 20 is a partial cross-sectional view showing the periphery of a semiconductor element 30L and a clip 50L in the semiconductor device 21 and the semiconductor module 20. The basic configurations of the semiconductor device 21 and the semiconductor module 20 are similar to those described in the preceding embodiment. The semiconductor module 20 includes a semiconductor device 21, a housing 22, and a cooler 23. The semiconductor device 21 includes a semiconductor element 30, a substrate 40, a clip 50, and an external connection terminal 60. The semiconductor device 21 may include a snubber circuit 70, as in the preceding embodiment. The semiconductor device 21 includes a solder 81 and a sintered member 82 as bonding materials. The semiconductor device 21 includes a sealing body 90.

[0134] The clip 50L (50) corresponds to a metal plate. The clip 50L has a joint 51 with the source electrode 32 of the semiconductor element 30L and a joint 52 with the N wiring 422. In this embodiment, the joint 51 corresponds to the first joint, and the joint 52 corresponds to the second joint. Solder 81 is interposed between the source electrode 32 and the joint 51. The solder 81 joins the source electrode 32 to the clip 50L. The solder 81 is interposed between the N wiring 422 and the joint 52. The solder 81 joins the N wiring 422 to the clip 50L. The clip 50L has a connecting portion 53. The connecting portion 53 is continuous with the joints 51 and 52. The connecting portion 53 connects the joints 51 and 52 to form a continuous, integrated body. The connecting portion 53 may connect joints 51 connected to different semiconductor elements 30.

[0135] The connecting portion 53 has inclined portions 531 and 532 and an intermediate portion 533. The inclined portion 531 rises obliquely upward from the joint portion 51. The inclined portion 531 has an inclination such that the further away from the joint portion 51 in the Y direction the inclined portion 531 is, the further away from the joint portion 51 (semiconductor element 30L) in the Z direction. The inclined portion 532 rises obliquely upward from the joint portion 52. The further away from the joint portion 52 in the Y direction the inclined portion 532 is, the further away from the joint portion 52 (substrate 40) in the Z direction. The inclined portions 531 and 532 are inclined with respect to the Y direction, which is the arrangement direction of the joint portions 51 and 52. The intermediate portion 533 connects the inclined portions 531 and 532. The intermediate portion 533 may be approximately parallel to the joint portions 51 and 52 in the mounted state.

[0136] Although not shown, clip 50H has the same configuration as clip 50L. Clip 50H has a joint 51 with source electrode 32 of semiconductor element 30H, a joint 52 with O wiring 423, and a connecting portion 53. Solder 81 is interposed between source electrode 32 and joint 51. Solder 81 joins source electrode 32 to clip 50H. Solder 81 is interposed between O 423 and joint 52. Solder 81 joins O wiring 423 to clip 50H.

[0137] The sintered member 82 is interposed between the drain electrode 31 of the semiconductor element 30L and the O wiring 423. The sintered member 82 joins the drain electrode 31 and the O wiring 423. Although not shown, the sintered member 82 is interposed between the drain electrode 31 of the semiconductor element 30H and the P wiring 421. The sintered member 82 joins the drain electrode 31 and the P wiring 421. The sintered member 82 is disposed below the semiconductor element 30, and the solder 81 is disposed above the semiconductor element 30.

[0138] The sintered member 82 is made of Ag or Cu. The sintered member 82 is a sintered body made of Ag particles or Cu particles. The sintered member 82 can be bonded at a lower temperature than solder. Ideally, the sintered member 82 is arranged so that it approximately coincides with the bonding surface of the drain electrode 31 in a planar view. The sintered member 82 is provided, for example, as a sintered sheet. The sintered sheet is sometimes called a sintered film. Before being pressed, the sintered sheet is smaller than the drain electrode 31 in a planar view. The sintered sheet is placed between the drain electrode 31 and the target wiring to form a laminate, and the laminate is pressed from the semiconductor element 30 side while being heated. As a result, the sintered sheet is expanded between the opposing surfaces of the drain electrode 31 and the wiring, reducing its thickness, and is sintered to form the sintered member 82.

[0139] The sealing body 90 seals the elements of the semiconductor device 21. The sealing body 90 integrally seals a portion of each of the semiconductor element 30, the substrate 40, the clip 50, and the external connection terminal 60. The sealing body 90 also seals the bonding wire 80 that electrically connects the pad 33 of the semiconductor element 30 to the signal terminal 62. In the example shown in FIG. 20 , a gel 91 is used as the sealing body 90. A potting resin may be used instead of the gel 91. The sealing body 90 fills the space formed by the housing 22 and the cooler 23. The sealing body 90 may be a resin molded body. The sealing body 90 may be provided in the semiconductor device 21 or in the semiconductor module 20.

[0140] <Clip> Figures 21, 22, 23, and 24 show an example of a clip 50 that can be used with the semiconductor element 30 shown in Figures 18 and 19. Figures 21 and 22 show an example of a clip 50L. Figure 22 is a cross-sectional view taken along line XXII-XXII in Figure 21. Figures 23 and 24 show an example of a clip 50H. Figures 21, 22, and 23 show a connection structure between the clip 50 and the semiconductor element 30. The clip 50 shown in Figures 21 to 24 has the same configuration as that shown in the preceding embodiment.

[0141] As shown in FIGS. 21 and 22 , the clip 50L is connected to a single semiconductor element 30L. The joint 51 with the source electrode 32 is arranged to avoid the signal lines, including the gate wiring 36, arranged on the element region 341. In plan view, the joint 51 is arranged so as not to overlap the signal lines over the entire length of the signal lines. As exemplified in FIGS. 21 and 22 , the joint 51 may be arranged to avoid the element upper portion 354 that covers the signal lines. By avoiding overlap with the element upper portion 354, overlap with the signal lines covered by the element upper portion 354 is also avoided. The joint 51 may be arranged so as to overlap the element upper portion 354 but not the signal lines in plan view.

[0142] The clip 50L has two joints 51 corresponding to the two divided source electrodes 32. The joints 51 are branched into the same number as the source electrodes 32. A facing space 54, indicated by a dashed line in FIG. 22 , is formed between the opposing side surfaces of adjacent joints 51. The facing space 54 is sometimes referred to as a facing region. In a plan view, one of the joints 51 overlaps one of the source electrodes 32, and the other of the joints 51 overlaps the other of the source electrodes 32. One of the joints 51 is solder-bonded to one of the source electrodes 32, and the other of the joints 51 is solder-bonded to the other of the source electrodes 32. The facing space 54 is located above the signal lines and the upper element portions 354. In a plan view, the joints 51 do not overlap the signal lines and the upper element portions 354.

[0143] The clip 50L extends in the Y direction. The joints 51 and 52 are aligned in the Y direction. The two joints 51 are aligned in the X direction. Each joint 51 has a generally rectangular shape in plan view, with the Y direction as the longitudinal direction and the X direction as the lateral direction. In plan view, the area of ​​each joint 51 is smaller than the area of ​​the corresponding source electrode 32. The clip 50L has a connecting portion 53. As illustrated in FIG. 20 , the connecting portion 53 has inclined portions 531 and 532 and an intermediate portion 533.

[0144] 23 , the clip 50H is connected to two semiconductor elements 30H. The joints 51 with the source electrodes 32 are arranged to avoid the signal lines including the gate wiring 36 arranged on the element region 341. In a plan view, the joints 51 are arranged so as not to overlap the signal lines over the entire length of the signal lines. As illustrated in FIG. 23 , the joints 51 are preferably arranged to avoid the upper part 354 of the element that covers the signal lines.

[0145] The clip 50H has four joints 51 corresponding to the two halves of the source electrodes 32 of each of the two semiconductor elements 30H. Two of the joints 51 are connected to one of the semiconductor elements 30H, and the other two are connected to the other of the semiconductor elements 30H. A facing space 54 is formed between the side surfaces of the joints 51 that are connected to the common semiconductor element 30H. The distance between the joints 51 connected to different semiconductor elements 30H, i.e., the distance between the second and third joints 51 in the X direction, is longer than the facing space 54 in the X direction. In a plan view, each joint 51 overlaps the corresponding source electrode 32. The joints 51 are solder-bonded to the corresponding source electrode 32. The facing space 54 is located above the signal lines and the upper element portions 354. In a plan view, none of the joints 51 overlaps the signal lines or the upper element portions 354.

[0146] The clip 50H extends in the Y direction. The joints 51 and 52 are aligned in the Y direction. The four joints 51 are aligned in the X direction. Each joint 51 has a generally rectangular shape in plan view, with the Y direction as the longitudinal direction and the X direction as the lateral direction. Each joint 51 is smaller in area than the corresponding source electrode 32 in plan view. The clip 50H has a connecting portion 53. The connecting portion 53 connects the joints 51 and 52. The connecting portion 53 connects the joints 51 connected to different semiconductor elements 30H. Like the clip 50L, the connecting portion 53 has inclined portions 531 and 532 and an intermediate portion 533.

[0147] The intermediate portion 533 includes a first intermediate portion 533a and a second intermediate portion 533b. The first intermediate portion 533a extends in the arrangement direction of the joint portions 51, i.e., in the X direction. The first intermediate portion 533a connects the four joint portions 51 via the inclined portions 531. In FIG. 24 , an inclined portion 531 is provided for each joint portion 51, but a configuration in which multiple joint portions 51 are connected to a common inclined portion 531 is also possible. The second intermediate portion 533b extends in the arrangement direction of the joint portions 51 and 52, i.e., in the Y direction. The second intermediate portion 533b connects the joint portion 52 and the first intermediate portion 533a. The clip 50H has a tapered portion 534 at the end of the first intermediate portion 533a on the joint portion 52 side. The tapered portion 534 has an inclination such that the length of the first intermediate portion 533a in the X direction increases as the tapered portion 534 becomes farther away from the joint portion 52 in the Y direction. The tapered portion 534 is inclined with respect to the Y direction, which is the arrangement direction of the joint portions 51 and 52.

[0148] The clip 50 is not limited to the above-described shape. Various shapes can be employed. For example, as shown in FIG. 25 , a tapered portion 535 may be added to the configuration shown in FIG. 24 . The tapered portion 535 is provided at the end of the first intermediate portion 533 a on the joint 51 side. Clip 50H has a shape in which the end of the first intermediate portion 533 a on the joint 51 side is cut out at a position between the second and third joints 51. The cutout space is approximately triangular in plan view, and the length in the X direction increases as it moves away from the joint 52 in the Y direction. The tapered portion 535 is an end face that defines the cutout space. The tapered portion 535 is inclined with respect to the Y direction, which is the arrangement direction of the joints 51 and 52.

[0149] 26 , the clip 50L may have a tapered portion 536. The tapered portion 534 is inclined such that the length of the connecting portion 53 in the X direction increases with increasing distance from the joint portion 52 in the Y direction. The tapered portion 536 is inclined with respect to the Y direction, which is the arrangement direction of the joint portions 51 and 52.

[0150] As shown in Figure 27, clip 50L may have inclined portions 531 and 532 but no intermediate portion 533. Inclined portion 531 is connected to inclined portion 532 without intermediate portion 533. Without intermediate portion 533, inclined portions 531 and 532 have a gentler slope. Clip 50H may have a similar structure. Inclined portions 531 and 532 are inclined with respect to the Y direction, which is the arrangement direction of joint portions 51 and 52.

[0151] As shown in Figure 28, clip 50L may have a through hole 55. The through hole 55 penetrates connecting portion 53 in the plate thickness direction. The planar shape of through hole 55 is not particularly limited. It may be circular as shown in the figure, or a polygonal shape such as a triangle or a rectangle. It may be a cross shape or an L shape in plan. It may also be an elongated hole that is long in one direction. The number of through holes 55 is not particularly limited. It may be one or multiple. The position of through hole 55 is also not particularly limited. Clip 50H may have a similar structure.

[0152] As shown in Figures 29 and 30, the clip 50L may have a bridge portion 56. Figure 30 is a cross-sectional view taken along line XXX-XXX in Figure 29. The bridge portion 56 is continuous with a plurality of joint portions 51 connected to a common semiconductor element 30L. The bridge portion 56 bridges adjacent joint portions 51 at a position farther away from the semiconductor element 30L than the joint portions 51. The facing space 54 is formed directly below the bridge portion 56. The bridge portion 56 is provided so as to overlap the facing space 54 in a plan view. The clip 50H may have a similar structure.

[0153] As shown in Fig. 31 , the clip 50H may be substantially L-shaped in plan view. The clip 50H has a connecting portion 57 and an extending portion 58. The connecting portion 57 is connected to the source electrodes 32 of the two semiconductor elements 30H and electrically connects the source electrodes 32 to each other. The extending portion 58 is continuous with the connecting portion 57 and electrically connects the source electrodes 32 to the O wiring 423. In Fig. 31 , the connecting portion 57 extends in the X direction in plan view and is disposed so as to overlap the source electrodes 32. The extending portion 58 extends in the Y direction.

[0154] For convenience, clip 50H is shown in a simplified form in Figure 31. Although omitted from Figure 31, connecting portion 57 includes joint portion 51. Joint portion 51 branches in accordance with the divided structure of source electrode 32. Extension portion 58 includes joint portion 52. Connecting portion 57 and extension portion 58 each include connecting portion 53. Connecting portion 57 may include bridge portion 56. Connecting portion 53 may have a through-hole 55. The same applies to Figures 32 to 37 shown below.

[0155] As shown in Fig. 32, the clip 50H may have a generally U-shaped planar shape. As in Fig. 31, the connecting portion 57 extends in the X direction and electrically connects the source electrodes 32 of the two semiconductor elements 30H. The clip 50H has two extension portions 58. The two extension portions 58 are connected to the O wiring 423. One of the extension portions 58 is connected to one end of the connecting portion 57, and the other extension portion 58 is connected to the other end of the connecting portion 57.

[0156] As shown in Figure 33, the clip 50H may have a generally Y-shaped planar configuration. The connecting portion 57 of the clip 50H has a generally U-shaped planar configuration. One end of the connecting portion 57 is connected to one of the semiconductor elements 30H, and the other end is connected to the other one of the semiconductor elements 30H. The extension portion 58 is continuous with the connecting portion 57 at a position offset toward one of the semiconductor elements 30H in the X direction. The extension portion 58 extends in the Y direction and is connected to the O wiring 423.

[0157] As shown in Figure 34, the clip 50H may have a generally H-shaped planar shape. As in Figure 34, the connecting portion 57 has a generally U-shaped planar shape. The clip 50H has two extension portions 58. One of the extension portions 58 is connected to the connecting portion 57 at a position offset to one side of the semiconductor element 30H. The other extension portion 58 is connected to the connecting portion 57 at a position offset to the other side of the semiconductor element 30H. Both extension portions 58 extend in the Y direction and are connected to the O wiring 423.

[0158] As shown in Fig. 35, the clip 50H may be substantially T-shaped. As in Fig. 31, the connecting portion 57 extends in the X direction and electrically connects the source electrodes 32 of the two semiconductor elements 30H. The extension portion 58 is continuous with the connecting portion 57 near the center in the X direction. The extension portion 58 extends in the Y direction and is connected to the O wiring 423.

[0159] 31 to 35, two clips 50H are used for four semiconductor elements 30H. Alternatively, as shown in FIG. 36, one clip 50H may be used for four semiconductor elements 30H. As in FIG. 31, the connecting portion 57 extends in the X direction and electrically connects the source electrodes 32 of the four semiconductor elements 30H. The clip 50H has four extension portions 58. The extension portions 58 are arranged side by side in the X direction at intervals corresponding to the semiconductor elements 30H. All of the extension portions 58 extend in the Y direction and are connected to the O wiring 423.

[0160] A clip 50H shown in FIG. 37 may also be used. The connecting portion 57 has a structure in which two planar, approximately U-shaped portions are connected together. The connecting portion 57 electrically connects the source electrodes 32 of the four semiconductor elements 30H. The clip 50H has four extension portions 58. The extension portions 58 are arranged side by side in the X direction with a spacing corresponding to the semiconductor elements 30H. All of the extension portions 58 extend in the Y direction and are connected to the O wiring 423.

[0161] As shown in FIG. 38 , a clip 50 may be provided for each semiconductor element 30. In other words, one clip 50 may be used for each semiconductor element 30. Clips 50H and 50L have a common structure. Clip 50 is generally L-shaped in plan view. Clip 50 has an expanded width portion 59a, which is a wide portion having a length in the X direction in plan view, and a narrowed width portion 59b, which is a narrowed width portion. Expanded width portion 59a includes joint portion 51 and a portion of connecting portion 53. Reduced width portion 59b includes joint portion 52 and a portion of connecting portion 53.

[0162] In this way, the clips 50H and 50L share a common, generally L-shaped structure, with the clip 50L rotated 180 degrees relative to the clip 50H. Therefore, even if the number of semiconductor elements 30H and 30L is the same, the clips 50H and 50L can be positioned to interlock with each other. This allows for a reduction in the size of the clips in the X direction. Note that "interlocking with each other" refers to a positional relationship in which at least a portion of the reduced width portion 59b of the clip 50H faces the expanded width portion 59a of the clip 50L in the Y direction, and at least a portion of the reduced width portion 59b of the clip 50L faces the expanded width portion 59a of the clip 50H in the Y direction.

[0163] For convenience, the clip 50 is also shown in a simplified form in Figure 38. Although not shown, the joint portion 51 is branched in accordance with the divided structure of the source electrode 32. The clip 50 may have a bridge portion 56 or a through hole 55. The same applies to Figures 39 and 40 shown below.

[0164] As shown in FIG. 39 , the width of the narrowed portion 59b may be increased while being offset in the X direction. The clip 50 has an expanded portion 59a including the joint portion 51 and a narrowed portion 59b including the joint portion 52. The narrowed portion 59b is offset in the X direction relative to the expanded portion 59a. This offset creates a step in the connecting portion 53. The width of the narrowed portion 59b is wider than in the example shown in FIG. 38 . The joint portion 52 is not pulled straight out from the joint portion 51, but is offset in the X direction. The clip 50L has the same structure as the clip 50H, but is rotated 180 degrees relative to the clip 50H. Therefore, even if the width of the narrowed portion 59b is increased, the clips 50H and 50L can be positioned to interlock with each other. This allows for a smaller size in the X direction.

[0165] As shown in FIG. 40 , the narrowed portion 59b may extend diagonally. The clip 50 has a widened portion 59a including the joint 51 and a narrowed portion 59b including the joint 52. The narrowed portion 59b extends from the widened portion 59a in a direction oblique to the X and Y directions. The width of the narrowed portion 59b is wider than that of the example shown in FIG. 38 . The joint 52 is pulled out diagonally rather than straight from the joint 51. The clip 50L has a common structure with the clip 50H, but is rotated 180 degrees relative to the clip 50H. Therefore, even if the narrowed portion 59b is wider, the clips 50H and 50L can be positioned to interlock with each other. This allows for a smaller size in the X direction.

[0166] Summary of the Second Embodiment According to this embodiment, the semiconductor device 21 includes a semiconductor element 30, a clip 50 made of a metal plate, and solder 81 connecting the semiconductor element 30 and the clip 50. As described above, the semiconductor element 30 includes signal lines including the source electrode 32 and gate wiring 36 arranged on one surface of the semiconductor substrate 34 and in the element region 341. The semiconductor element 30 also includes an upper element portion 354 of the insulating film 35 covering the signal lines. As shown in FIG. 22 and other figures, the joint portion 51 of the clip 50 is provided to avoid the signal lines. This prevents the solder 81 from flowing into scratches on the upper element portion 354 caused during the manufacturing process. This prevents signal line leakage, such as gate leakage. This also prevents leakage current (leakage current) from occurring in the signal lines.

[0167] The clip 50 preferably has multiple joints 51 for the common semiconductor element 30. This makes it possible to suppress leakage of signal lines while ensuring a sufficient joint area. In particular, it is preferable that the joints 51 for the common semiconductor element 30 are branched into multiple branches. By employing joints 51 with a multiple-branch structure, it is easy to ensure a sufficient joint area while avoiding signal lines. Due to the branched structure, the opposing spaces 54 between adjacent joints 51 function as injection ports for the sealing material when forming the sealing body 90 and as outlets for air. This makes it possible to suppress the sealing body 90 from being left unfilled and the formation of air pockets within the sealing body 90.

[0168] The clip 50 may have a bridge portion 56 that connects to adjacent joint portions 51 at a position farther away from the one surface 34a of the semiconductor substrate 34 than the joint portions 51. By having the bridge portion 56, the heat dissipation area and the current-carrying area can be increased. As shown in Figure 30, the bridge portion 56 is located above the joint portions 51, so that the solder 81 can be prevented from wetting and spreading over the surface of the bridge portion 56 and flowing onto the upper portion 354 of the element.

[0169] The clip 50 preferably has a plurality of joints 51 and 52. In other words, it is preferable to have a total of three or more joints 51, 52. The clip 50 is supported at three or more points, stabilizing its position. This makes it possible to prevent misalignment, including tilting, of the clip 50. The joints 52 are preferably connected to the wiring of the substrate 40 on which the semiconductor element 30 is mounted. For example, this can simplify the configuration. Because the semiconductor element 30 and the clip 50 are connected to the substrate 40, it is easy to determine the positions of the semiconductor element 30, the wiring of the substrate 40, and the clip 50.

[0170] The drain electrode 31 of the semiconductor element 30 may be connected to the metal member to be connected via a sintered member 82. That is, the sintered member 82 may be disposed directly below the drain electrode 31 of the semiconductor element 30, and the solder 81 may be disposed directly above the source electrode 32 of the semiconductor element 30. By using the sintered member 82, the thermal resistance of the path that primarily contributes to heat dissipation can be reduced. When applying pressure to form the sintered member 82, there is a risk that the pressure device may scratch the upper element portion 354 of the insulating film 35. However, even if a scratch does occur, the positioning of the joint 51 to avoid the signal line can prevent the solder 81 from flowing into the scratch on the upper element portion 354.

[0171] The semiconductor element 30 having the pad 33, the clip 50, a portion of the signal terminal 62, and the bonding wire 80 connecting the pad 33 and the signal terminal 62 may be integrally sealed with the gel 91. In such a sealing structure, a through hole 55 may be provided in the connecting portion 53 of the clip 50. The gel 91 located above the clip 50 and the gel 91 located below the clip 50 are continuously connected through the gel 91 disposed in the through hole 55. Even if vibrations of the moving body are transmitted to the gel 91, the vibrations of the gel 91 are limited by the through hole 55 (clip 50). The gel 91 is fixed by the through hole 55. Therefore, breakage of the bonding wire 80 due to vibrations of the gel 91 can be suppressed.

[0172] The semiconductor element 30 and the clip 50 may be integrally sealed with a sealant 90 such as a gel 91 or potting resin. In such a sealing structure, the connecting portion 53 of the clip 50 may be formed with a shape that is inclined relative to the alignment direction of the joint portions 51 and 52. As shown in FIGS. 20 and 27 , the inclined portions 531 and 532 are inclined relative to the Y direction, which is the alignment direction of the joint portions 51 and 52. As shown in FIGS. 23 , 25 , and 26 , the tapered portions 534, 535, and 536 are all inclined relative to the Y direction, which is the alignment direction of the joint portions 51 and 52. This prevents the connecting portion 53 from interfering with the flow of the sealant along the clip 50 when filling the sealant 90 to form the sealant 90. The sealant flows along the inclination. This enhances the fluidity of the sealant. This prevents the sealant 90 from being left unfilled and prevents air pockets from forming within the sealant 90.

[0173] The configuration described in this embodiment can be combined with the configuration described in the preceding embodiment.

[0174] Third Embodiment This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0175] The semiconductor device 21 of this embodiment includes at least a resin housing, a substrate having wiring, a plurality of semiconductor elements joined to the wiring and connected in parallel, and a signal terminal. The signal terminal includes a branch terminal. The branch terminal has a single first connection portion connected to an external device, a plurality of second connection portions electrically connected to pads of the semiconductor elements, and a link portion connecting the first connection portion and the second connection portion.

[0176] FIG. 41 is a diagram illustrating an example of a semiconductor device 21 and a semiconductor module 20 according to this embodiment. FIG. 41 illustrates a portion of the semiconductor device 21. FIG. 42 is an enlarged perspective view of the periphery of an O terminal 613 of the semiconductor device 21 illustrated in FIG. 41. In FIGS. 41 and 42, the housing 22 is shown in a see-through manner. The basic configurations of the semiconductor device 21 and the semiconductor module 20 illustrated in FIGS. 41 and 42 are similar to those described in the preceding embodiment. The semiconductor module 20 includes the semiconductor device 21, a housing 22, and a cooler 23. The semiconductor device 21 includes a semiconductor element 30, a substrate 40, a clip 50, and external connection terminals 60. The semiconductor device 21 may include a snubber circuit 70, as in the preceding embodiment. The semiconductor device 21 may include a sealing body 90.

[0177] As shown in FIG. 5 , the semiconductor device 21 of this embodiment includes a plurality of semiconductor elements 30H and a plurality of semiconductor elements 30L. The configuration of the semiconductor elements 30 is similar to that shown in, for example, FIGS. 18 and 19 . The semiconductor elements 30H are aligned in the X direction. The drain electrodes 31 of the semiconductor elements 30H are bonded to the P wiring 421 of the substrate 40. The semiconductor elements 30L are aligned in the X direction. The drain electrodes 31 of the semiconductor elements 30L are bonded to the O wiring 423. The semiconductor elements 30H and 30L are aligned in the Y direction.

[0178] The pads 33 of the semiconductor element 30H are electrically connected to the corresponding signal terminals 62 via signal wiring 425. The pads 33 of the semiconductor element 30L are electrically connected to the corresponding signal terminals 62 via signal wiring 426. The pads 33 are connected to the corresponding signal terminals 62 via bonding wires 80.

[0179] The main terminals 61, i.e., P terminal 611, N terminal 612, and O terminal 613, and the signal terminal 62 are inserted into the housing 22. The main terminals 61 and the signal terminals 62 are integrally molded with the housing 22. Each of the main terminals 61 and the signal terminals 62 is held by the housing 22. Portions 611a, 612a, and 613a of the P terminal 611, N terminal 612, and O terminal 613 that connect to external devices protrude from the housing 22. Portions 611b, 612b, and 613b that connect to wiring on the board 40 protrude from the housing 22. Of the signal terminal 62, a portion 621 that connects to external devices and a portion 622 that connects to the pad 33 protrude from the housing 22.

[0180] <Arrangement of Output Terminals> As shown in Figures 41 and 5, the O terminal 613 is aligned with the semiconductor element 30L in the Y direction. The O terminal 613 is connected to the central region of the O wiring 423 in the arrangement direction (X direction) of the semiconductor elements 30L. The O terminal 613 is connected near the center of the O wiring 423 in the X direction. The O terminal 613 is joined to the O wiring 423 near the center of the arrangement area of ​​the multiple semiconductor elements 30L in the X direction. The arrangement area of ​​the multiple semiconductor elements 30L is a virtual rectangular area connecting the outer contours of the multiple semiconductor elements 30L in a plan view in the Z direction. The O terminal 613 is arranged so as to overlap the center position between the second semiconductor element 30L and the third semiconductor element 30L. The O terminal 613 is joined to the terminal connection portion 423c of the extension portion 423b of the O wiring 423, which is continuous with the base portion 423a on which the semiconductor element 30L is mounted.

[0181] <Signal Wiring> The signal wiring 426 corresponding to the semiconductor element 30L is disposed between the semiconductor element 30L and the signal terminal 62 in the Y direction. The signal wiring 426 extends in the X direction. The signal wiring 426 includes a gate wiring 426G, a Kelvin source wiring 426KS, an anode wiring 426A, and a cathode wiring 426C.

[0182] The signal wiring 426 includes wiring that is divided (segmented) into multiple pieces by the O terminal 613 and the O wiring 423 (extension portion 423b), i.e., split wiring. In the example shown in FIGS. 41 and 42 , the gate wiring 426G and the Kelvin source wiring 426KS are split wirings. The gate wiring 426G and the Kelvin source wiring 426KS are split into two by the O terminal 613 and the O wiring 423. The two gate wirings 426G and the two Kelvin source wirings 426KS are arranged to sandwich the O terminal 613 and the O wiring 423 in the X direction.

[0183] The gate pad 33G is connected to the gate wiring 426G that is closer to the two gate wirings 426G. The gate pads 33G of two semiconductor elements 30L are connected to one of the gate wirings 426G, and the gate pads 33G of the other two semiconductor elements 30L are connected to the other one of the gate wirings 426G. The Kelvin source pad 33KS is connected to the Kelvin source wiring 426KS that is closer to the two Kelvin source wirings 426KS. The Kelvin source pads 33KS of two semiconductor elements 30L are connected to one of the Kelvin source wirings 426KS, and the Kelvin source pads 33KS of the other two semiconductor elements 30L are connected to the other one of the Kelvin source wirings 426KS.

[0184] In the example shown in Figures 41 and 42, the temperature of only one of the four semiconductor elements 30L at its end in the X direction is monitored. Therefore, the anode wiring 426A and the cathode wiring 426C are arranged near the semiconductor element 30L whose temperature is being monitored. The anode wiring 426A and the cathode wiring 426C are arranged on one side in the X direction relative to the O terminal 613. The anode wiring 426A and the cathode wiring 426C are arranged alongside the split wiring. In the example shown in Figure 41, the anode wiring 426A is aligned with one of the Kelvin source wirings 426KS in the X direction. The cathode wiring 426C is aligned with one of the gate wirings 426G in the X direction.

[0185] The anode pad 33A of the semiconductor element 30L arranged at the edge is connected to the anode wiring 426A via a bonding wire 80. The cathode pad 33C is connected to the cathode wiring 426C via a bonding wire 80. The anode pads 33A and cathode pads 33C of the other three semiconductor elements 30L are not connected to the anode wiring 426A and the cathode wiring 426C. At least one of the anode pad 33A and the cathode pad 33C is connected to a nearby Kelvin source wiring 426KS to ground the temperature-sensitive diode to the source potential. In the example shown in FIG. 41 , the anode pad 33A is connected to the nearby Kelvin source wiring 426KS.

[0186] <Signal Terminals> The signal terminals 62 corresponding to the semiconductor element 30L are held by the frame 221 of the housing 22. As shown in FIG. 3, the signal terminals 62 are held by the wall portion 221b of the frame 221. The signal terminals 62 include a gate terminal 62G, a Kelvin source terminal 62KS, an anode terminal 62A, and a cathode terminal 62C. The semiconductor device 21 includes one each of the gate terminal 62G, the Kelvin source terminal 62KS, the anode terminal 62A, and the cathode terminal 62C as the signal terminals 62 corresponding to the semiconductor element 30L.

[0187] The gate terminal 62G is connected to the gate wiring 426G via a bonding wire 80. The Kelvin source terminal 62KS is connected to the Kelvin source wiring 426KS via a bonding wire 80. The anode terminal 62A is connected to the anode wiring 426A via a bonding wire 80. The cathode terminal 62C is connected to the cathode wiring 426C via a bonding wire 80.

[0188] The connection portions 621 of the four signal terminals 62 are arranged together on one side in the X direction with respect to the O terminal 613. The four connection portions 621 are arranged on the side where the anode wiring 426A and the cathode wiring 426C are arranged with respect to the O terminal 613. The signal terminals 62 include branch terminals in which the connection portion 622 is divided (segmented) into multiple parts by the O terminal 613. In the examples shown in FIGS. 41 and 42 , the gate terminal 62G and the Kelvin source terminal 62KS are branch terminals.

[0189] The gate terminal 62G has a single connection portion 621, two connection portions 622, and a linking portion 623. In this embodiment, the connection portion 621 corresponds to the first connection portion, and the connection portion 622 corresponds to the second connection portion. The two connection portions 622 are arranged to sandwich the O terminal 613 in a plan view. The two connection portions 622 are arranged approximately symmetrically with respect to the center of the O terminal 613 in the X direction. One of the connection portions 622 is connected to one of the gate wirings 426G, and the other connection portion 622 is connected to the other of the gate wirings 426G.

[0190] The coupling portion 623 electrically connects the single connection portion 621 and the multiple connection portions 622. The coupling portion 623 is disposed within the frame 221 of the housing 22. As shown in Fig. 42 , the coupling portion 623 may include a coupling portion 623a that connects one of the connection portions 622 to the connection portion 621, and a coupling portion 623b that connects another of the connection portions 622 to the coupling portion 623a. The coupling portion 623a includes a portion that extends in the Z direction. The coupling portion 623b includes a portion that extends in the X direction.

[0191] 43 and 44 show an example of the arrangement of the O terminal 613 and the gate terminal 62G, which is a branch terminal. FIG. 43 is a plan view seen from the X direction. FIG. 44 is a plan view seen from the Y direction. For convenience, the O wiring 423 and the housing 22 are omitted from FIG. 44. As shown in FIGS. 43 and 44, the coupling portion 623 (coupling portion 623b) that electrically connects the two connection portions 622 may be arranged below the O terminal 613 and may straddle the O terminal 613.

[0192] 45 and 46 show other examples of the arrangement of the O terminal 613 and the gate terminal 62G, which is a branch terminal. Fig. 45 corresponds to Fig. 43. Fig. 46 corresponds to Fig. 44. As shown in Fig. 45 and 46, the linking portion 623 (linking portion 623b) that electrically connects two connection portions 622 may be arranged above the O terminal 613 and may straddle the O terminal 613.

[0193] 42, the Kelvin source terminal 62KS has a configuration similar to that of the gate terminal 62G. The Kelvin source terminal 62KS has a single connection portion 621, two connection portions 622, and a coupling portion 623. The coupling portion 623 may include a coupling portion 623a and a coupling portion 623b.

[0194] <Current Sense Integrated Structure> As shown in FIG. 47 , a shunt resistor 613d for detecting current may be provided in a portion of the O terminal 613. The length, width, and thickness of the shunt resistor 613d in the extension direction are controlled to achieve a predetermined resistance value. The signal wiring 426 includes two sense wirings 426S. The signal terminal 62 includes two sense terminals 62S. One end of the shunt resistor 613d is connected to one of the sense terminals 62S via a bonding wire 80 and one of the sense wirings 426S. The other end of the shunt resistor 613d is connected to the other of the sense terminals 62S via a bonding wire 80 and the other of the sense wirings 426S. With this configuration, the potential difference across the shunt resistor 613d, i.e., the current flowing through the shunt resistor 613d, can be detected.

[0195] 48 , the semiconductor device 21 may include a core 63 that constitutes a current sensor. The core 63 is held in the housing 22. The core 63 is inserted into the housing 22. The core 63 is disposed around a connecting portion 613c of the O-terminal 613. The current can be detected by measuring the magnitude of the magnetic field generated in the core 63 by the current flowing through the O-terminal 613.

[0196] Summary of Third Embodiment The semiconductor device 21 of this embodiment includes a resin housing 22, a substrate 40, a plurality of semiconductor elements 30 (30L) joined to wiring on the substrate 40 and connected in parallel, and a signal terminal 62. The signal terminal 62 is inserted into the housing 22. The signal terminal 62 includes a branch terminal. The branch terminal is, for example, a gate terminal 62G or a Kelvin source terminal 62KS. The branch terminal has a single connection portion 621 connected to an external device, a plurality of connection portions 622 individually connected to pads 33 having the same function of different semiconductor elements 30L, and a linking portion 623.

[0197] In this way, the multiple connection portions 622 (second connection portions) and the single connection portion 621 (first connection portion) are electrically connected inside the housing 22. Therefore, in a configuration in which multiple semiconductor elements 30L are connected in parallel, contact and breakage of the bonding wires 80 can be suppressed while suppressing an increase in the physical size.

[0198] The semiconductor device 21 may include a main terminal 61 (613) connected to the wiring on which the semiconductor element 30 (30L) is mounted. The main terminal 61 is aligned with the semiconductor element 30 in the Y direction (second direction) perpendicular to the X direction (first direction) in which the semiconductor elements 30 (30L) are aligned, and is connected to a central region of the wiring in the X direction. In this configuration, multiple connection portions 622 may be arranged to sandwich the main terminal 61 in the X direction. Because the main terminal 61 is connected to the central region of the wiring, it is possible to prevent current from flowing unevenly through some of the semiconductor elements 30. In other words, it is possible to prevent current imbalance.

[0199] When the main terminal 61 is connected to the central region of the wiring, the connecting portions 622, which have the same function, are inevitably separated by the main terminal 61. As described above, the separated connecting portions 622 are connected to the single connecting portion 621 inside the housing 22. Therefore, it is possible to suppress current imbalance while suppressing an increase in the physical size.

[0200] The substrate 40 may have signal wiring 426 that relays the pads 33 and the signal terminals 62. In a configuration having the signal wiring 426, the signal wiring 426 may include a plurality of split wirings that are provided according to the connection portions 622 and individually connected to pads 33 that have the same function on different semiconductor elements 30 (30L). The branch terminals are, for example, gate wiring 426G and Kelvin source wiring 426KS. The plurality of split wirings may be positioned between the semiconductor element 30 and the connection portions 622 in the Y direction and may be arranged to sandwich the main terminal 61 (613) in the X direction.

[0201] This makes it possible to prevent contact and breakage of the bonding wires 80 in a configuration in which more semiconductor elements 30 are connected in parallel in order to increase the output of the semiconductor device 21, and ultimately the semiconductor module 20. Furthermore, even if signal wiring having the same function is divided, it is electrically connected within the housing 22 via the connection portion 622. This makes it possible to prevent an increase in the physical size.

[0202] In a configuration in which the semiconductor device 21 provides the upper and lower arm circuits 9 and a plurality of semiconductor elements 30H and a plurality of semiconductor elements 30L are arranged side by side in the Y direction, the O terminal 613 may serve as the main terminal 61 that separates the connection portion 622 and the signal wiring 426. The P terminal 611 and the N terminal 612 can be drawn from one end side in the Y direction, and the O terminal 613 can be drawn from the other end side. Furthermore, because the O terminal 613 is connected to the central region of the O wiring 423, it is possible to suppress current imbalance and an increase in physical size.

[0203] The O terminal 613 may be inserted into the housing 22. The O terminal 613 is held in the housing 22 together with the signal terminal 62. This simplifies the configuration. Furthermore, the accuracy of the relative positions of the O terminal 613 and the signal terminal 62 can be improved.

[0204] The O terminal 613 may have a shunt resistor portion 613d for current detection. By providing the O terminal 613 with a shunt resistor function, the size can be made smaller than in a configuration in which a separate current sensor is provided.

[0205] The semiconductor device 21 may include a core 63 that is inserted into the housing 22 and arranged around the O terminal 613. By providing the core 63 of the current sensor in the housing 22, the size of the semiconductor device 21 can be made smaller than in a configuration in which the current sensor is provided separately. In addition, the accuracy of the relative positions of the O terminal 613 and the core 63 can be improved.

[0206] In the example shown, a branch terminal is applied to the signal terminal 62 corresponding to the semiconductor element 30L, and divided wiring is applied to the signal wiring 426. However, a branch terminal may be applied to the signal terminal 62 corresponding to the semiconductor element 30H, or divided wiring may be applied to the signal wiring 425. For example, in a configuration without the snubber circuit 70, the signal terminal 62 corresponding to the semiconductor element 30H may be provided on the wall portion 221a of the frame body 221, and the signal terminal 62 corresponding to the semiconductor element 30H may include a branch terminal.

[0207] The configuration described in this embodiment can be combined with the configuration described in the preceding embodiment.

[0208] (Fourth Embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0209] <Semiconductor Device> FIG. 49 is a plan view showing an example of a semiconductor device 21 according to this embodiment. In FIG. 49, the semiconductor device 21 is illustrated in a simplified form. For convenience, the signal terminals 62 are omitted from FIG. 49. The configurations of the semiconductor device 21 and the semiconductor module 20 are similar to those of the preceding embodiment (see, for example, FIGS. 2 to 6). The semiconductor device 21 includes a plurality of semiconductor elements 30, a substrate 40, a clip 50, external connection terminals 60, and a snubber circuit 70. The semiconductor device 21 may also include the sealing body 90 shown in the preceding embodiment.

[0210] The semiconductor device 21 provides one phase of the upper and lower arm circuits 9. The multiple semiconductor elements 30 include multiple semiconductor elements 30H that provide the upper arm 9H and multiple semiconductor elements 30L that provide the lower arm 9L. The multiple semiconductor elements 30H are arranged on a common wiring and connected in parallel. The multiple semiconductor elements 30L are arranged on a common wiring and connected in parallel. The numbers of the semiconductor elements 30H and 30L may be the same or different. In the example shown in FIG. 49 , the semiconductor device 21 includes four semiconductor elements 30H and four semiconductor elements 30L. The semiconductor elements 30H are arranged side by side in the X direction. The semiconductor elements 30L are also arranged side by side in the X direction. The semiconductor elements 30H and 30L are arranged side by side in the Y direction. The semiconductor elements 30H and 30L are arranged at a common interval (pitch).

[0211] As in the previous embodiment (see FIGS. 3 and 5 ), the external connection terminal 60 includes a main terminal 61 and a signal terminal 62 (not shown). The main terminal 61 includes a P terminal 611, an N terminal 612, and an O terminal 613. The P terminal 611 and the N terminal 612 are connected to corresponding conductors 42 at one of the Y-direction ends of the substrate 40, and the O terminal 613 is connected to corresponding conductors 42 at another of the Y-direction ends. The semiconductor device 21 has one P terminal 611 and one O terminal 613, and two N terminals 612. The P terminal 611 and the O terminal 613 are each connected at a position including approximately the center of the substrate 40 in the X direction. The N terminals 612 are arranged to sandwich the P terminal 611.

[0212] The substrate 40 has a conductor 42 on one surface. The conductor 42 is patterned to have multiple wirings. The conductor 42 is patterned in the same manner as in the previous embodiment (see FIG. 6 ). The conductor 42 has a P wiring 421, an N wiring 422, an O wiring 423, a relay wiring 424, and signal wirings 425 and 426. The P wiring 421 has a generally T-shape in plan view. The P wiring 421 extends in the X direction and has a base 421a on which multiple semiconductor elements 30H are mounted, and an extension 421b extending in the Y direction from near the center of the base 421a. A terminal connection 421c is provided at the end of the extension 421b.

[0213] The N wiring 422 has a substantially C-shape (or U-shape) in plan view. The N wiring 422 has a base 422a extending in the X direction and two extension portions 422b extending generally in the Y direction from both ends of the base 422a. The extension portions 422b are arranged to bypass the multiple semiconductor elements 30H. The extension portions 422b are disposed near the X-direction end of the substrate 40. The P wiring 421, relay wiring 424, and signal wiring 425 are disposed between the two extension portions 422b. Terminal connection portions 422c are provided at the ends of the extension portions 422b. The O wiring 423 has a substantially T-shape in plan view. The O wiring 423 has a base 423a extending in the X direction and on which multiple semiconductor elements 30L are mounted, and an extension portion 423b extending in the Y direction from near the center of the base 423a. A terminal connection portion 423c is provided at the end of the extension portion 423b.

[0214] The relay wiring 424, together with electronic components such as the capacitor 71, provides the snubber circuit 70. The relay wiring 424, together with the electronic components of the snubber circuit 70, electrically bridges the P wiring 421 and the N wiring 422. The relay wiring 424 is arranged to sandwich the extension portion 421b of the P wiring 421 in the X direction. The relay wiring 424 includes relay wirings 424a and 424b. The relay wirings 424a and 424b are aligned in the X direction between the extension portion 421b of the P wiring 421 and the extension portion 422b of the N wiring 422.

[0215] The signal wiring 425 electrically connects the pad 33 of the semiconductor element 30H to the signal terminal 62. The signal wiring 425 extends in the X direction. The signal wiring 425 is disposed between the extension portion 421b of the P wiring 421 and the extension portion 422b of the N wiring 422 in the X direction. The signal wiring 425 is disposed between the base portion 421a of the P wiring 421 and the relay wiring 424 in the Y direction. The signal wiring 426 electrically connects the pad 33 of the semiconductor element 30L to the signal terminal 62. The signal wiring 426 extends in the X direction. The signal wiring 426 is disposed so as to sandwich the extension portion 422b of the O wiring in the X direction. The signal wiring 426 is disposed at one of the ends of the substrate 40 in the Y direction.

[0216] The clips 50 electrically connect the source electrode 32 of the semiconductor element 30 to the wiring of the substrate 40. The clips 50 include a clip 50H connected to the source electrode 32 of the semiconductor element 30H and a clip 50L connected to the source electrode 32 of the semiconductor element 30L. The semiconductor device 21 includes two clips 50H and four clips 50L. One clip 50H is provided for each of two adjacent semiconductor elements 30H. The clips 50H have the same configuration as the preceding embodiment (see FIGS. 23 and 24). The clips 50H are generally Y-shaped in plan view, with both ends branching into two. The clips 50L are individually provided for each semiconductor element 30L. The clips 50L have the same configuration as the preceding embodiment (see FIGS. 21 to 23). The clips 50L are generally I-shaped in plan view, with one end branching into two.

[0217] The snubber circuit 70 includes a capacitor 71 and a resistor 72. The capacitor 71 bridges the extension portion 421b of the P wiring 421 and the relay wiring 424a. A part of the resistor 72 bridges the relay wiring 424a and the relay wiring 424b. Another part of the resistor 72 bridges the relay wiring 424b and the extension portion 422b of the N wiring 422.

[0218] <Heat Reception and Heat Generation> In Figure 49, the four semiconductor elements 30L are shown as semiconductor element 30L1, semiconductor element 30L2, semiconductor element 30L3, and semiconductor element 30L4 from one end in the X direction. Semiconductor element 30L1 is located at the end and is adjacent to one semiconductor element 30L. Semiconductor element 30L2 is located in the central region and is adjacent to two semiconductor elements 30L. Like semiconductor element 30L2, semiconductor element 30L3 is adjacent to two semiconductor elements 30L. Like semiconductor element 30L1, semiconductor element 30L4 is adjacent to one semiconductor element 30L.

[0219] The semiconductor element 30L is affected by the heat generated by the adjacent semiconductor elements 30L. Therefore, the greater the number of adjacent semiconductor elements 30L, the greater the amount of heat received. The amount of heat received by the semiconductor elements 30L1 and 30L4 is smaller than that of the semiconductor elements 30L2 and 30L3. The amount of heat received by the semiconductor elements 30L2 and 30L3 is greater than that of the semiconductor elements 30L1 and 30L4.

[0220] In the semiconductor device 21 described above, the parallel-connected semiconductor elements 30L are turned on and off at the same timing. When the semiconductor element 30L is turned on, a current flows through the O-terminal 613, the terminal connection portion 423c of the O-wiring 423, the extension portion 423b, the base portion 423a, the semiconductor element 30L, the clip 50L, the base portion 422a of the N-wiring 422, the extension portion 422b, the terminal connection portion 422c, and the N-terminal 612.

[0221] When the semiconductor element 30L1 is turned on, current flows along the path indicated by the dashed line in the figure. When the semiconductor element 30L2 is turned on, current flows along the path indicated by the two-dot chain line in the figure. The source electrode 32 of the semiconductor element 30L is connected to the base 422a of the N wiring 422 via the clip 50L. The source electrode 32 of the semiconductor element 30L1 is connected to the base 422a at a position closer to the extension portion 422b in the X direction. The source electrode 32 of the semiconductor element 30L2 is connected to the base 422a at a position farther from the extension portion 422b than the semiconductor element 30L1. Therefore, the current path of the semiconductor element 30L1 (dashed line) is shorter than the current path of the semiconductor element 30L2 (dash-dotted line). The current path of the semiconductor element 30L2 is longer than the current path of the semiconductor element 30L1.

[0222] The two current paths have different lengths at the base 422a, where the line width is narrow. The path length at the base 422a of the semiconductor element 30L2 is longer than that of the semiconductor element 30L1. As a result, the wiring resistance between the main terminals 612, 613 is greater for the semiconductor element 30L2 than for the semiconductor element L1. The current path length is longer for the semiconductor element 30L2 than for the semiconductor element L1. A current flows more easily through the semiconductor element 30L1 than through the semiconductor element L2. A current flows less easily through the semiconductor element 30L2 than through the semiconductor element 30L1. In other words, the amount of heat generated by current flow is greater for the semiconductor element 30L1 than for the semiconductor element 30L2.

[0223] The semiconductor element 30L4 is similar to the semiconductor element 30L1, and the semiconductor element 30L3 is similar to the semiconductor element 30L2.

[0224] FIG. 50 shows the current path on the semiconductor element 30H side. In FIG. 50, the four semiconductor elements 30H are shown as semiconductor element 30H1, semiconductor element 30H2, semiconductor element 30H3, and semiconductor element 30H4, starting from one end in the X direction. Semiconductor elements 30H1 and 30H4 are located at the ends and are adjacent to one semiconductor element 30H. Semiconductor elements 30H2 and 30H3 are located in the central region and are adjacent to two semiconductor elements 30H. The semiconductor element 30H is also affected by the heat generated by the adjacent semiconductor elements 30H. Therefore, the greater the number of adjacent semiconductor elements 30H, the greater the amount of heat received. The amount of heat received by semiconductor elements 30H1 and 30H4 is smaller than that of semiconductor elements 30H2 and 30H3. The amount of heat received by semiconductor elements 30H2 and 30H3 is greater than that of semiconductor elements 30H1 and 30H4.

[0225] In the semiconductor device 21 described above, the multiple semiconductor elements 30H connected in parallel are turned on and off at the same timing. When the semiconductor element 30H is turned on, a current flows through the P terminal 611, the terminal connection portion 421c of the P wiring 421, the extension portion 421b, the base portion 421a, the semiconductor element 30H, the clip 50H, the base portion 423a of the O wiring 423, the extension portion 423b, the terminal connection portion 423c, and the O terminal 613.

[0226] When the semiconductor element 30H2 is turned on, current flows through the path indicated by the dashed line in the figure. When the semiconductor element 30H1 is turned on, current flows through the path indicated by the two-dot chain line in the figure. The source electrode 32 of the semiconductor element 30H is connected to the base 423a of the O wiring 423 via the clip 50H. The drain electrode 31 of the semiconductor element 30H2 is connected to the base 421a at a position closer to the connection between the extension portion 421b and the base 421a. The drain electrode 31 of the semiconductor element 30H1 is connected to the base 421a at a position farther from the connection than the semiconductor element 30H2. The current path of the semiconductor element 30H2 (dashed line) is shorter than the current path of the semiconductor element 30H1 (dash-dot line). The current path of the semiconductor element 30H1 is longer than the current path of the semiconductor element 30H2.

[0227] In the base 421a, current flows through the region between the mounting position of the semiconductor element 30H and the end on the P terminal 611 side. This region is narrow. The two current paths have different path lengths in the base 421a. The path length in the base 421a of the semiconductor element 30H1 is longer than that of the semiconductor element 30H2. As a result, the wiring resistance between the main terminals 611, 613 is greater in the semiconductor element 30H1 than in the semiconductor element H2. The current path length in the semiconductor element 30H1 is longer than that in the semiconductor element H2. Current flows more easily in the semiconductor element 30H2 than in the semiconductor element H1. Current flows less easily in the semiconductor element 30H1 than in the semiconductor element 30H2. In other words, the amount of heat generated by current flow is greater in the semiconductor element 30H2 than in the semiconductor element 30H1.

[0228] The semiconductor element 30H4 is similar to the semiconductor element 30H1, and the semiconductor element 30H3 is similar to the semiconductor element 30H2.

[0229] As described above, current tends to flow through the semiconductor elements 30L1 and 30L4 located at both ends of the semiconductor element 30L, and current tends to flow through the semiconductor elements 30H2 and 30H3 located in the central region of the semiconductor element 30H.

[0230] <Clip> Adjacent semiconductor elements having different numbers of semiconductor elements and / or semiconductor elements having different current path lengths between main electrodes and main terminals may be electrically connected by a metal plate material.

[0231] 50, semiconductor elements 30H1 and 30H2 are electrically connected by a common clip 50H, and semiconductor elements 30H3 and 30H4 are electrically connected by a common clip 50H.

[0232] As described above, the semiconductor elements 30H1 and 30H4 are adjacent to one another, whereas the semiconductor elements 30H2 and 30H3 are adjacent to two another. This causes the semiconductor elements 30H1 and 30H4 and the semiconductor elements 30H2 and 30H3 to receive different amounts of heat.

[0233] 50, the source electrode 32 of one semiconductor element 30H1 of adjacent semiconductor elements 30H is connected to the source electrode 32 of two semiconductor elements 30H2 of adjacent semiconductor elements 30 by a common clip 50H. The source electrode 32 of two semiconductor elements 30H3 of adjacent semiconductor elements 30H is connected to the source electrode 32 of one semiconductor element 30H1 of adjacent semiconductor elements 30 by a common clip 50H.

[0234] The semiconductor elements 30H1 and 30H4 have a long current path length from the P terminal 611 to the drain electrode 31. The semiconductor elements 30H2 and 30H3 have a short current path length from the P terminal 611 to the drain electrode 31. The semiconductor elements 30H1 and 30H4 and the semiconductor elements 30H2 and 30H3 have different current path lengths. The semiconductor elements 30H1 and 30H4 and the semiconductor elements 30H2 and 30H3 differ in the ease with which current flows, and therefore in the amount of heat generated.

[0235] 50, the source electrode 32 of the semiconductor element 30H1 having a long current path length and the source electrode 32 of the semiconductor element 30H2 having a short current path length are connected by a common clip 50H. The source electrode 32 of the semiconductor element 30H3 having a short current path length and the source electrode 32 of the semiconductor element 30H1 having a long current path length are connected by a common clip 50H.

[0236] <Substrate> In the substrate 40, the conductor 42 can have various patterns. The area of ​​the first conductor, which is the mounting portion on which the semiconductor element 30 is mounted, may be different between the semiconductor element 30H, which is the upper arm element, and the semiconductor element 30L, which is the lower arm element. In such a configuration in which the areas of the first conductors are different, the second conductor, on which the semiconductor element 30 is not mounted, may be disposed near the first conductor, which has a smaller area.

[0237] FIG. 51 shows an example of a substrate 40 in a semiconductor device 21. The conductor pattern is shown in a simplified form in FIG. 51. The conductor 42 shown in FIG. 51 has a configuration similar to that shown in the preceding embodiment (see FIG. 6) and the configuration shown in FIG. 49. The P wiring 421 has a base 421a on which multiple semiconductor elements 30H are arranged. The O wiring 423 has a base 423a on which multiple semiconductor elements 30L are arranged. The bases 421a and 423a correspond to the first conductor. The relay wiring 424 is a conductor on which the semiconductor elements 30, which are heat-generating bodies, are not mounted. The relay wiring 424 corresponds to the second conductor. The relay wiring 424 is provided with electronic components, such as a capacitor 71 and a resistor 72, that constitute a snubber circuit 70.

[0238] The base 421a has a smaller area than the base 423a. The length LX1 of the base 421a in the X direction is shorter than the length LX2 of the base 423a in the X direction. The length LY1 of the base 421a in the Y direction is shorter than the length LY2 of the base 423a in the Y direction. The relay wiring 424 is disposed closer to the base 421a, which has the smaller area, of the bases 421a and 423a. The base 421a is disposed between the relay wiring 424 and the base 423a in the Y direction.

[0239] As described above, the semiconductor element 30, which is a heat generating element, is mounted on the first conductor. For this reason, the first conductor may be formed using a highly thermally conductive material that has better thermal conductivity than the other portions of the conductor 42, including the second conductor.

[0240] FIG. 52 shows another example of the substrate 40. The pattern of the conductor 42 is the same as the pattern shown in FIG. 51. The base 421a of the P wiring 421 is formed using a highly thermally conductive material. The base 423a of the O wiring 423 is also formed using a highly thermally conductive material. The highly thermally conductive material is, for example, copper graphite (CuGr). The other wiring, including the relay wiring 424, is formed using a material with lower thermal conductivity than the highly thermally conductive material, for example, Cu. In FIG. 52, the bases 421a and 423a are hatched for distinction. The Cu material and CuGr material are arranged on a common insulating base material 41.

[0241] The high thermal conductivity material may be anisotropic. The high thermal conductivity material may be arranged so that the high thermal conductivity direction is approximately aligned with the arrangement direction of the semiconductor elements 30. Figure 52 shows the high thermal conductivity (HD) direction and low thermal conductivity (LD) direction of the high thermal conductivity material. The high thermal conductivity material is arranged so that the HD direction is approximately parallel to the X direction and the LD direction is approximately parallel to the Y direction.

[0242] <Temperature Monitor> As described above, in a configuration in which the semiconductor device 21 includes multiple semiconductor elements 30, the temperature of only one of the semiconductor elements 30 may be output. For example, as shown in FIG. 49, the temperature of only the semiconductor element 30L1 may be output. As shown in the previous embodiment (see FIG. 18), the semiconductor element 30 includes a gate pad 33G, a Kelvin source pad 33KS, an anode pad 33A, and a cathode pad 33C. The anode pad 33A and the cathode pad 33C are connected to the temperature-sensitive diodes included in the semiconductor element 30.

[0243] The anode pad 33A of the semiconductor element 30L1 is connected to the anode signal wiring 426. The cathode pad 33C of the semiconductor element 30L1 is connected to the cathode signal wiring 426. As in the preceding embodiment (see FIGS. 41 and 42), the anode pad 33A and the cathode pad 33C of the semiconductor element 30L1 are connected to the corresponding signal terminals 62 via the signal wiring 426. The anode pad 33A and the cathode pad 33C of the other semiconductor elements 30 are not connected to the signal terminals 62. For example, the anode pad 33A is connected to the Kelvin source signal wirings 425 and 426.

[0244] In Figure 49, the configuration is such that the temperature of semiconductor element 30L1, which is located at the end in the X direction and the end in the Y direction, is output. Alternatively, the configuration may be such that the temperature of semiconductor element 30L4 is output. Alternatively, the configuration may be such that the temperature of either semiconductor element 30L2 or 30L3 is output. Of the multiple semiconductor elements 30H, semiconductor elements 30H2 and 30H3 located in the central region receive a large amount of heat and allow current to flow easily. Therefore, the configuration may be such that the temperature of either semiconductor element 30H2 or 30H3 is output. Alternatively, the configuration may be such that the temperature of either semiconductor element 30H1 or 30H4, which is located at the end in the X direction, is output.

[0245] Summary of Fourth Embodiment The semiconductor device 21 may include a substrate 40, a plurality of semiconductor elements 30 arranged on one surface of the substrate 40 and connected in parallel to one another, and a main terminal 61 that is common to the main electrodes of the plurality of semiconductor elements 30. The wiring resistance between the main terminal 61 and the main electrode may vary depending on the number of adjacent semiconductor elements 30, and the wiring resistance may be greater as the number of adjacent semiconductor elements 30 increases.

[0246] As described above, among the multiple semiconductor elements 30 connected in parallel, the semiconductor elements 30 with a larger number of adjacent semiconductor elements 30 receive a larger amount of heat. A semiconductor element 30 with a large wiring resistance between the main terminal 61 and the main electrode has a smaller amount of heat generated by current flow because current does not flow easily through the semiconductor element 30. By configuring the semiconductor elements 30 with a larger number of adjacent semiconductor elements 30 so that the wiring resistance increases with the number of adjacent semiconductor elements 30, heat generation in the semiconductor elements 30 with a larger number of adjacent semiconductor elements 30 can be suppressed. This allows the total amounts of heat received and generated in the multiple semiconductor elements 30 to be closer to each other. Therefore, heat variations in the multiple semiconductor elements 30 can be suppressed. In other words, temperature bias can be suppressed.

[0247] Since local temperature increases can be suppressed, it is possible to prevent the temperature of some of the semiconductor elements 30 from exceeding the allowable upper limit temperature and reducing the output of the semiconductor device 21. Furthermore, since the arrangement of the multiple semiconductor elements 30 connected in parallel is not limited to a staggered pattern, it is possible to improve the degree of freedom in arrangement. Since the staggered arrangement is not required, it is possible to suppress an increase in the physical size.

[0248] The substrate 40 may have a common wiring to which the main terminals 61 are bonded and to which the main electrodes of the multiple semiconductor elements 30 are connected. This wiring may be arranged so that the length from the bonding portion of the main terminals 61 to the electrical connection portion of the main electrodes increases as the number of adjacent semiconductor elements 30 increases. By using a common wiring in this way and varying the positions of the main electrode connection portions on the wiring, it is possible to vary the current path length, that is, the wiring resistance. Heat variation can be suppressed with a simple configuration.

[0249] The semiconductor device 21 may provide the upper and lower arm circuits 9. The semiconductor device 21 may include a plurality of semiconductor elements 30H (second semiconductor elements) arranged side by side in the X direction (first direction) and connected in parallel to each other, and a plurality of semiconductor elements 30L (first semiconductor elements) arranged side by side in the X direction and connected in parallel to each other. The semiconductor element 30H may be arranged between the N terminal 612 (main terminal 61) and the semiconductor element 30L in the Y direction (second direction), and the N wiring 422 may be routed to bypass the plurality of semiconductor elements 30H. This can increase the wiring resistance of the semiconductor elements 30L2 and 30L3, which have a large number of adjacent semiconductor elements 30L, among the plurality of semiconductor elements 30L arranged side by side in the X direction. It can also reduce the wiring resistance of the semiconductor elements 30L1 and 30L4, which have a small number of adjacent semiconductor elements 30L. Therefore, thermal variations can be suppressed with a simple configuration.

[0250] The semiconductor elements 30H, 30L may be provided in equal numbers. The positions of the semiconductor elements 30L1, 30L4, through which current flows easily among the plurality of semiconductor elements 30L (first semiconductor elements), and the positions of the semiconductor elements 30H2, 30H3, through which current flows easily among the plurality of semiconductor elements 30H (second semiconductor elements), may be offset from each other in the X direction (first direction). Among the plurality of semiconductor elements 30 constituting the upper and lower arm circuits 9, the semiconductor elements 30 that generate a large amount of heat when current is applied are dispersedly arranged. This makes it possible to suppress thermal variations among the plurality of semiconductor elements 30 constituting the upper and lower arm circuits 9.

[0251] As shown in Figure 49, in a semiconductor element 30L that provides a lower arm 9L, the wiring resistance may be configured to increase as the number of adjacent semiconductor elements 30L increases. Although not shown, in a semiconductor element 30H that provides an upper arm 9H, the wiring resistance may be configured to increase as the number of adjacent semiconductor elements 30H increases. The semiconductor device 21 is not limited to a configuration that provides an upper or lower arm circuit 9. It can also be applied to a semiconductor device 21 that provides one of the arms. In a plurality of semiconductor elements 30 that are connected in parallel and provide one of the arms, the wiring resistance may be configured to increase as the number of adjacent semiconductor elements 30 increases.

[0252] The semiconductor device 21 may include a substrate 40, a plurality of semiconductor elements 30 arranged on one surface of the substrate 40 and connected in parallel, a main terminal 61 that is a common connection target for the main electrodes of the plurality of semiconductor elements 30, and a metal plate clip 50. The clip 50 may electrically connect semiconductor elements 30 having different numbers of adjacent semiconductor elements 30 and / or semiconductor elements 30 having different current path lengths between the main electrodes and the main terminals 61.

[0253] 50 , for example, among multiple semiconductor elements 30H connected in parallel, the source electrodes 32 of semiconductor elements 30H1 and 30H2 having different numbers of adjacent semiconductor elements 30H may be connected by clips 50H. The source electrodes 32 of semiconductor elements 30H3 and 30H4 having different numbers of adjacent semiconductor elements 30H may be connected by clips 50H. Among multiple semiconductor elements 30H connected in parallel, the source electrodes 32 of semiconductor elements 30H1 and 30H2 having different current path lengths may be connected by clips 50H. The source electrodes 32 of semiconductor elements 30H3 and 30H4 having different current path lengths may be connected by clips 50H.

[0254] As described above, semiconductor elements 30 with a large number of adjacent semiconductor elements 30 receive a large amount of heat, while semiconductor elements 30 with a small number of adjacent semiconductor elements 30 receive a small amount of heat. Current flows less easily through semiconductor elements 30 with long current paths between the main electrodes and main terminals 61, while current flows more easily through semiconductor elements 30 with short current paths. Therefore, by connecting semiconductor elements 30 with different numbers of adjacent semiconductor elements 30 and therefore differing amounts of heat received, using clips 50, heat transfer via the clips 50 can suppress thermal variations. Furthermore, by connecting semiconductor elements 30 with different current path lengths and therefore differing amounts of heat generated, using metal plates, thermal variations can be suppressed. Therefore, thermal variations among multiple semiconductor elements 30 can be suppressed. For example, a decrease in output can be suppressed.

[0255] The metal plate material connecting the source electrodes to each other is not limited to the clip 50. It may also be a lead. The semiconductor element 30 is not limited to the semiconductor element 30H. Although not shown, it may also be applied to multiple semiconductor elements 30L connected in parallel. The semiconductor device 21 is not limited to a configuration that provides upper and lower arm circuits 9. It may also be applied to a semiconductor device 21 that provides one of the arms. In multiple semiconductor elements 30 connected in parallel and providing one of the arms, the source electrodes 32 may be electrically connected by the clip 50.

[0256] The semiconductor device 21 may include a substrate 40 and a plurality of semiconductor elements 30 arranged on one surface of the substrate 40, and the semiconductor elements 30 may include a semiconductor element 30H that is an upper arm element and a semiconductor element 30L that is a lower arm element. The conductor 42 of the substrate 40 may include base portions 421a, 423a (first conductors) on which the semiconductor elements 30 are mounted, and a relay wiring 424 (second conductor) on which no semiconductor element 30 is mounted. The relay wiring 424 may be arranged near the base portion 421a, which has a smaller area than the base portion 423a.

[0257] Because the small-area base 421a is located near the relay wiring 424, heat from the semiconductor element 30H mounted on the small-area base 421a can be dissipated toward the relay wiring 424. Even though the area of ​​the base 421a is small, heat from the semiconductor element 30H can be dissipated by using the relay wiring 424. The base 423a, which is located farther from the relay wiring 424, has a larger area, so it functions as a thermal mass better than the base 421a and has a larger heat dissipation area. Heat from the semiconductor element 30L can be dissipated via the base 423a. This makes it possible to suppress thermal variations among the multiple semiconductor elements 30 that make up the upper and lower arm circuits 9. For example, it is possible to suppress a decrease in output.

[0258] Although the semiconductor element 30, which is a heat generating element, is not mounted, the relay wiring 424 that provides the wiring function is used, and the base 421a is made smaller accordingly, thereby making it possible to reduce the size of the substrate 40 and, ultimately, the size of the semiconductor device 21.

[0259] A configuration may be adopted in which a snubber circuit 70 including a capacitor 71 is provided, and the capacitor 71 is disposed on the relay wiring 424. The wiring that constitutes the snubber circuit 70, particularly the wiring on which the capacitor 71 is disposed, requires a relatively large area. While utilizing the second conductor (relay wiring 424) as a mounting conductor for the capacitor 71, it is possible to dissipate heat from the semiconductor element 30 mounted on the base 421a, which has a small area.

[0260] The bases 421a and 423a, which are the first conductors, may be formed using a highly thermally conductive material that has better thermal conductivity than the material forming the other conductors 42, including the second conductors. By using a highly thermally conductive material only for the bases 421a and 423a, on which the semiconductor element 30, which is a heat generating element, is mounted, it is possible to improve heat dissipation while suppressing an increase in costs.

[0261] The semiconductor device 21 may include a plurality of semiconductor elements 30H arranged side by side in the X direction and a plurality of semiconductor elements 30L also arranged side by side in the X direction. A highly thermally conductive material having anisotropic thermal conductivity may be used as the highly thermally conductive material. The highly thermally conductive material may be disposed so that its high thermal conductivity direction coincides with the X direction, which is the arrangement direction of the semiconductor elements 30H and 30L. Heat from the semiconductor elements 30H and 30L is primarily conducted in the X direction in the bases 421a and 423a, and is less likely to be conducted in the Y direction. Heat dissipation can be ensured even if the length of the bases 421a and 423a in the Y direction is shortened. This allows the size of the substrate 40, and therefore the semiconductor device 21, to be reduced.

[0262] In a configuration in which the semiconductor device 21 includes multiple semiconductor elements 30, the temperature of only one of the multiple semiconductor elements 30 may be output. Deterioration of the semiconductor device 21 can be detected with a minimum number of temperature monitors. Deterioration can be detected while reducing costs. For example, as shown in FIG. 49 , the temperature of only the semiconductor element 30L1 may be output. The semiconductor element 30L1 is located near the edge of the substrate 40 in the X and Y directions. The bonding material 24 (solder) that bonds the substrate 40 to the cooler 23 cracks from the outer periphery of the substrate 40 and deteriorates. As described above, current easily flows through the semiconductor element 30L1. The semiconductor element 30L1 easily generates heat. By detecting the temperature of the semiconductor element 30L1, deterioration of the semiconductor device 21 can be more effectively detected with a minimum number of temperature monitors.

[0263] The configuration described in this embodiment can be combined with the configuration described in the preceding embodiment.

[0264] Fifth Embodiment This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0265] <Semiconductor Module> Fig. 53 is a plan view showing an example of a semiconductor module 20 according to this embodiment. Fig. 54 is a plan view showing a configuration of the semiconductor module 20 excluding the housing 22, that is, a state in which the semiconductor device 21 is arranged on the cooler 23. For convenience, the sealing body is omitted in Figs. 53 and 54. Fig. 55 is a cross-sectional view taken along the line LV-LV shown in Fig. 53. Fig. 55 shows a simplified version of the semiconductor module 20.

[0266] 53 to 55, the basic configurations of the semiconductor module 20 and the semiconductor device 21 are similar to those shown in the preceding embodiments (see FIGS. 2 to 6). The semiconductor module 20 includes a semiconductor device 21, a housing 22, and a cooler 23. The semiconductor device 21 and the housing 22 are disposed on one surface 23a of the cooler 23.

[0267] Similar to the configuration shown in the preceding embodiment, the semiconductor device 21 includes a semiconductor element 30, a substrate 40, and external connection terminals 60. The external connection terminals 60 include a main terminal 61 and a signal terminal 62. The external connection terminals 60 are inserted into the housing 22. The main terminals 61, which include a P terminal 611, an N terminal 612, and an O terminal 613, are joined to corresponding wiring of the conductor 42, similar to the preceding embodiment.

[0268] The semiconductor device 21 includes a sealing body 90, similar to the configuration shown in the preceding embodiment (see FIG. 20 ). The sealing body 90 seals other elements of the semiconductor device 21. The sealing body 90 seals the portion of the semiconductor device 21 that is exposed to the accommodation space. The sealing body 90 is filled up to a predetermined position that is lower than the upper end of the housing 22. The sealing body 90 may be included in the semiconductor device 21 or in the semiconductor module 20. As shown in FIG. 55 , the sealing body 90 may include a gel 91, or may be a sealing body made of resin.

[0269] The semiconductor device 21 may further include a clip 50. The semiconductor device 21 may further include a snubber circuit 70. As shown in Figures 53 to 55, the semiconductor device 21 may further include a clip 50 and a snubber circuit 70.

[0270] The semiconductor device 21 constitutes a power converter. The semiconductor device 21 may provide one arm. As shown in FIGS. 53 to 55 , the semiconductor device 21 may provide the upper and lower arm circuits 9 for one phase. The semiconductor module 20 may include three semiconductor devices 21 each providing the upper and lower arm circuits 9 for one phase. The three semiconductor devices 21, i.e., the three substrates 40, may be arranged side by side in the X direction. The substrates 40 may be fixed to the cooler 23 via a bonding material 24 such as solder.

[0271] The cooler 23 may have a flow path 231, as shown in the preceding embodiment (see FIG. 4 ). The cooler 23 may be a heat dissipation member such as a heat sink. The heat dissipation member may include heat dissipation fins. The semiconductor module 20 may include fastening holes 233 penetrating the cooler 23, as illustrated in FIG. 54 . The semiconductor module 20 may include a collar 234 that provides the fastening holes 233, and the collar 234 is integral with the cooler 23. The collar 234 is a cylindrical surface pressure buffer member formed using a highly rigid material. The collar 234 is a metal member. The cooler 23 may be provided with multiple fastening holes 233. As shown in FIG. 54 , the collar 234 may be provided on the outer periphery of one surface 23 a that is substantially rectangular in plan view. Parts of the collar 234 may be provided at the four corners, and other parts of the collar 234 may be provided between the substrates 40 in the arrangement direction (X direction) of the substrates 40.

[0272] <Housing> The housing 22 includes a frame 221. The frame 221 is fixed to the cooler 23. The frame 221, together with the cooler 23, provides a storage space. The frame 221 has walls 221a, 221b, 221c, and 221d. The wall 221a holds a P terminal 611 and an N terminal 612. The wall 221b holds an O terminal 613 (613U, 613V, 613W). The semiconductor device 21 is disposed in the storage space. The storage space is filled with a sealing body 90.

[0273] The frame 221 is fixed to the cooler 23. The frame 221, together with the cooler 23, provides a storage space. The frame 221 has walls 221a, 221b, 221c, and 221d. The P terminal 611 and the N terminal 612 are held on the wall 221a. The O terminal 613 (613U, 613V, 613W) is held on the wall 221b. The semiconductor device 21 is disposed in the storage space. The storage space is filled with a sealing body 90.

[0274] 53 , the semiconductor module 20 may include fastening holes 223 that penetrate the housing 22. The fastening holes 223 are provided to correspond to the fastening holes 233. For example, the housing 22 and the cooler 23, and therefore the semiconductor device 21, are fastened to a case of a power converter (not shown) by bolts that are inserted through the fastening holes 223 and 233.

[0275] The semiconductor module 20 may include a collar 224 that provides the fastening hole 223, and is integral with the housing 22. The collar 224 is a metal member. The collar 224 is a cylindrical surface pressure buffer member formed using a highly rigid material. The collar 224 is inserted into the housing 22. The semiconductor module 20 may include a plurality of fastening holes 223. As shown in FIG. 53 , the collar 224 may be provided on a frame 221 that has a substantially rectangular ring shape in plan view. Parts of the collar 224 may be provided at the four corners of the frame 221, and other parts of the collar 224 may be provided at positions between the substrates 40 in the arrangement direction (X direction) of the substrates 40.

[0276] Figure 56 is a cross-sectional view showing the periphery of the collar 224. Figure 56 shows the connection structure between the housing 22 and the cooler 23. For convenience, the collar 234 on the cooler 23 side is omitted from Figure 56. As shown in Figure 56, the collar 224 may protrude a predetermined amount from the lower surface 22a of the housing 22 toward the cooler 23 and come into contact with the one surface 23a. In other words, the collar 224 may come into contact with the one surface 23a of the cooler 23, while the housing 22 (for example, the frame 221) does not come into contact with the one surface 23a. The lower surface 22a is the surface facing the one surface 23a of the cooler 23.

[0277] The collar 224 ensures a gap (space) of a predetermined height H10 between the lower surface 22a of the housing 22 and the first surface 23a of the cooler 23. A sealant 25 is disposed in this gap. The sealant 25 is interposed between the lower surface 22a of the housing 22 and the first surface 23a of the cooler 23. The sealant 25 has an adhesive function. The sealant 25 fixes the housing 22 to the cooler 23. The sealant 25 has a sealing function. The sealant 25 provides a liquid-tight seal between the lower surface 22a and the first surface 23a. The sealant 25 prevents the sealed body 90 from leaking from the housing space. The thickness of the sealant 25 is controlled by the amount of protrusion of the collar 224. The thickness of the sealant 25 is approximately equal to the height H10.

[0278] FIG. 57 is a diagram showing the relationship between the sealant 25 and thermal resistance. As shown in FIG. 57, the thicker the sealant 25, the greater the thermal resistance. If the thickness of the sealant 25 is less than 0.1 mm, the amount of protrusion of the collar 224 is small, and there is a risk that the sealing body 90 will rest on the seating surface. In addition, the manufacturing tolerance is ±0.1 mm. Based on the above, it is recommended that the thickness of the sealant 25, i.e., the amount of protrusion of the collar 224 from the lower surface 22a, be set within the range of 0.1 mm or more and 0.3 mm or less.

[0279] As illustrated in Fig. 53 , the housing 22 may include a partition wall 222 in addition to a frame body 221. The partition wall 222 divides the storage space according to the number of boards 40. In the example shown in Fig. 53 , the housing 22 includes two partition walls 222 that divide the storage space into three sections. The partition walls 222 divide the storage space into the same number of sections as the number of boards 40 in the X direction, which is the direction in which the boards 40 are arranged. The partition wall 222 extends in the Y direction, which is perpendicular to the direction in which the boards 40 are arranged, and both ends of the partition wall 222 are connected to the wall portions 221a, 221b of the frame body 221.

[0280] The partition walls 222 are provided at positions between adjacent substrates 40 in the direction in which the substrates 40 are arranged. The partition wall 222a is provided between the substrate 40 that constitutes the U-phase semiconductor device 21 and the substrate 40 that constitutes the V-phase semiconductor device 21. The partition wall 222b is provided between the substrate 40 that constitutes the V-phase semiconductor device 21 and the substrate 40 that constitutes the W-phase semiconductor device 21. The substrates 40, i.e., the semiconductor devices 21 for each phase, are arranged individually in the three divided storage spaces.

[0281] The partition walls 222a and 222b may hold at least some of the signal terminals 62. As shown in Fig. 53, some of the signal terminals 62 may be held by the partition walls 222a and 222b, and other parts of the signal terminals may be held by the walls 221b and 221c. Fig. 58 shows a cross-sectional view of a reference example. Fig. 58 corresponds to Fig. 59. In the reference example, the letter "r" is added to the end of the reference numerals of elements related to the configuration of this embodiment.

[0282] In the reference example shown in FIG. 58 , a partition wall 222r of a housing 22r has a protrusion 225r. The protrusion 225r is located on the partition wall 222r below the connection portion 622r of the signal terminal 62r. ​​The protrusion 225r supports the connection portion 622r. The connection portion 622r is disposed on an upper surface 225ar of the protrusion 225r. The protrusion 225r is provided between the connection portion 622r and one surface 23ar of the cooler 23r. In the partition wall 222r, the protrusion 225r is an expanded portion having a large length (width) in the X direction, and the portion above the protrusion 225r is a reduced width portion having a narrower width than the protrusion 225r. The connection portion 621r of the signal terminal 62r protrudes from the upper surface of the reduced width portion.

[0283] Between the partition wall 222r and the substrate 40r, there is nothing blocking the sealing body 90r from the surface 23ar to the top surface of the sealing body 90r. Therefore, if the sealing body 90r is a gel 91r, for example, when vibrations of the moving body are transmitted to the gel 91r, the gel 91r can vibrate over a wide range from the surface 23ar to the top surface of the sealing body 90r. In other words, the gel 91r deforms significantly. This may result in breakage of the bonding wire 80r. If the sealing body 90r is made of resin, the resin expands and contracts significantly with temperature changes, which may result in peeling of the sealing body 90r.

[0284] FIG. 59 is a cross-sectional view taken along line LIX-LIX in FIG. 53. FIG. 59 shows an example of the structure of the semiconductor module 20 around the partition wall 222. As shown in FIG. 59, a recess 226 may be provided in the partition wall 222. The partition wall 222 has an inner surface that contacts the sealing body 90, and the portion that contacts the sealing body 90 has an uneven shape. The connection portion 622 of the signal terminal 62 is disposed on the upper surface 225a of the partition wall 222. The protrusion 225 is sometimes referred to as a support portion that supports the connection portion 622. The bonding wire 80 electrically connects the connection portion 622 and the signal wiring 425.

[0285] The recess 226 is provided directly below the protrusion 225. The recess 226 is sometimes referred to as a hollow. The recess 226 is provided between the protrusion 225 and one surface 23a of the cooler 23. The partition wall 222 is recessed from the lower surface 22a to the protrusion 225. The area above the protrusion 225 is also recessed relative to the protrusion 225. The protrusion 225 protrudes toward the substrate 40. In the example shown in Figure 59, a portion of the substrate 40 is recessed directly below the protrusion 225. The substrate 40 is recessed into the area recessed by the recess 226. In a plan view in the Z direction, a portion of the substrate 40 overlaps the protrusion 225.

[0286] Fig. 60 is a cross-sectional view showing another example of the structure around the partition wall 222. Fig. 60 corresponds to Fig. 59. In the example shown in Fig. 60, the substrate 40 does not overlap the convex portion 225 in plan view. Except for this point, the configuration is the same as that shown in Fig. 59. The partition wall 222 has a convex portion 225 and a concave portion 226.

[0287] The above-described uneven structure may be provided on at least one of the partition walls 222a and 222b. The uneven structure may be provided on at least one of the wall portions 221a, 221b, 221c, and 221d of the frame body 221. It is particularly effective to provide the uneven structure on the wall portions 221b and 221c that hold the signal terminals 62 and on the partition walls 222a and 222b. In the example shown in Figure 53, the uneven structure is provided on the partition walls 222a and 222b and the wall portions 221b, 221c, and 221d. In all cases, the substrate 40 overlaps the protrusions 225.

[0288] Summary of Fifth Embodiment The semiconductor module 20 may include a cooler 23, a housing 22, a substrate 40, a semiconductor element 30, a main terminal 61, a sealant 90, a sealant 25, and a metal member having a fastening hole 223. The substrate 40 is disposed in an accommodation space formed by the cooler 23 and the housing 22, which is disposed on one surface 23a of the cooler 23, and the semiconductor element 30 is joined to the conductor 42 of the substrate 40. The main terminal 61 inserted into the housing 22 is joined to the conductor 42. The sealant 90 fills the accommodation space. The sealant 25 is interposed between the one surface 23a of the cooler 23 and the lower surface 22a of the housing 22. The metal member is integrated with the housing 22. In the above configuration, the metal member may protrude from the housing 22 toward the one surface 23a and contact the one surface 23a so as to ensure a gap of a predetermined height H10 between the one surface 23a of the cooler 23 and the lower surface 22a of the housing 22.

[0289] The sealant 25 is disposed in a gap of a predetermined height H10 secured by the metal member. This ensures sealing performance and prevents leakage of the sealing body 90. Furthermore, the metal member is in contact with the cooler 23, but the resin housing 22 is not in contact with the cooler 23. This prevents the housing 22 from pressing strongly against the cooler 23 when fastening the housing 22. In other words, stress generated in the housing 22 due to the pressing can be prevented from acting on the joint between the main terminal 61 inserted into the housing 22 and the conductor 42, and ultimately on the circuit board 40. This prevents distortion of the joint and the circuit board 40.

[0290] 53 and 56 may be used as the metal member that provides the fastening hole 223. The collar 224 is inserted into the housing 22. With this simple configuration, distortion of the joint and the substrate 40 can be suppressed.

[0291] The amount of protrusion of the metal member from the housing 22 should be set within the range of 0.1 mm to 0.3 mm. In other words, the thickness of the sealant 25 should be set within the range of 0.1 mm to 0.3 mm. This prevents the sealing body 90 from resting on the seating surface, i.e., prevents deterioration of the fastening due to resin creep. It also reduces thermal resistance.

[0292] The semiconductor module 20 may include only one substrate 40 or multiple substrates 40. Multiple substrates 40 may be arranged side by side in a predetermined direction (X direction), and the fastening holes 223 may be provided at positions between adjacent substrates 40 in the arrangement direction. Even if the cooler 23 (e.g., a cooling plate) warps due to a difference in the linear expansion coefficients between the cooler 23 and the substrates 40, providing fixing points between the substrates 40 in the arrangement direction can reduce stress acting on the substrates 40 and the bonding material 24 due to fastening.

[0293] The semiconductor element 30 and the signal terminal 62 may be electrically connected via bonding wires 80, and the bonding wires 80 may be sealed with gel 91 as a sealant 90 filled in the storage space. In this configuration, the housing 22 may be provided with partition walls 222 that divide the storage space according to the arrangement of the multiple substrates 40. Even if vibrations of the moving body are transmitted to the gel 91, the partition walls 222 narrow the range in which the gel 91 can deform, thereby reducing the amount of deformation of the gel 91. This makes it possible to prevent the bonding wires 80 from breaking.

[0294] The semiconductor module 20 may include three substrates 40 that provide the upper and lower arm circuits 9 for one phase together with the semiconductor elements 30. In this configuration, partition walls 222 (222a, 222b) may be provided between adjacent substrates 40 to divide the accommodation space into three spaces, and the substrates 40 may be individually arranged in the divided spaces. This makes it possible to prevent breakage of the bonding wires 80 in all of the semiconductor devices 21 in the semiconductor module 20 that provides the inverter 6.

[0295] The partition wall 222 may be used in combination with the above-described configuration in which a gap of the predetermined height H10 is secured using a metal member, or may be used alone. For example, the partition wall 222 may be provided in a configuration in which the collar 224 is not used.

[0296] The housing 22 may have a protrusion 225 as a portion with which the sealing body 90 comes into contact, and a recess 226 provided between the protrusion 225 and the one surface 23a of the cooler 23. When the sealing body 90 is made of resin, the anchor effect can suppress interfacial peeling of the resin. Furthermore, the protruding protrusion 225 limits the area in which the resin expands and contracts, thereby suppressing resin peeling. When the sealing body 90 is made of gel 91, the protruding protrusion 225 limits deformation of the gel 91 due to vibration transmission, thereby reducing the amount of deformation and ultimately suppressing breakage of the bonding wire 80.

[0297] In a configuration in which the housing 22 has a protrusion 225 and a recess 226, a portion of the substrate 40 may be arranged to overlap the protrusion 225 in a plan view. In other words, the substrate 40 may be configured to extend directly below the protrusion 225. When the sealing body 90 is made of resin, the anchor effect can be enhanced. Furthermore, since the substrate 40 is positioned directly below the protrusion 225, the region in which the resin expands and contracts can be further limited. Therefore, resin peeling can be effectively suppressed. For example, peeling of the sealing body 90 from the substrate 40 can be suppressed. When the sealing body 90 is made of gel 91, the substrate 40 being positioned directly below the protrusion 225 can further suppress deformation of the gel 91. Therefore, breakage of the bonding wire 80 can be effectively suppressed. Furthermore, since the substrate 40 extends directly below the protrusion 225, the size of the sealing body 90 can be reduced in a direction perpendicular to the Z direction.

[0298] In a configuration in which the housing 22 has a protrusion 225 and a recess 226, the signal terminal 62 may be held by the housing 22, and the connection portion 622 may be disposed on the upper surface 225a of the protrusion 225. This can prevent breakage of the bonding wire 80 connected to the connection portion 622. Because the upper surface 225a of the protrusion 225 is used to connect the bonding wire 80, the anchor effect can prevent resin peeling while miniaturizing the device. In addition, it can prevent breakage of the bonding wire 80 connected to the connection portion 622.

[0299] The configuration having the convex portion 225 and the concave portion 226 may be combined with the above-described configuration in which a gap of the predetermined height H10 is secured using a metal member, or may be used alone without being combined. The configuration having the convex portion 225 and the concave portion 226 may be combined with the partition wall 222, or may be used alone without being combined. For example, in a configuration in which the housing 22 does not have the partition wall 222, the convex portion 225 and the concave portion 226 may be provided on the frame body 221.

[0300] The configuration described in this embodiment can be combined with the configuration described in the preceding embodiment.

[0301] Sixth Embodiment This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0302] <Semiconductor Module> FIG. 61 is a cross-sectional view showing an example of a semiconductor module 20 according to this embodiment. Similar to the configuration shown in the preceding embodiment (see FIGS. 2 to 4), the semiconductor module 20 includes a semiconductor device 21, a cooler 23, and a bonding material 24. The semiconductor device 21 is disposed on one surface 23a of the cooler 23. The cooler 23 may have a flow path 231 as shown in the preceding embodiment (see FIG. 4), or may be a heat dissipation member such as a heat sink. The bonding material 24 is interposed between the semiconductor device 21 and the cooler 23. The thermally conductive member interposed between the semiconductor device 21 and the cooler 23 is not limited to the bonding material 24. A TIM or the like may also be used. Although not shown, the semiconductor module 20 may also include a housing 22.

[0303] Fig. 62 is a plan view showing an example of a semiconductor device 21. Fig. 62 shows a substrate 40 and electronic components mounted on the substrate 40. The semiconductor device 21 includes a semiconductor element 30 and a substrate 40, similar to the configuration shown in the preceding embodiment (see Figs. 5 and 6). Fig. 62 shows a simplified view of the semiconductor element 30.

[0304] As shown in Fig. 62, the semiconductor device 21 may include a snubber circuit 70. Although not shown, the semiconductor device 21 may include a clip 50. The semiconductor device 21 may include an external connection terminal 60. The semiconductor device 21 may include a sealing body 90, similar to the configuration shown in the preceding embodiment (see Fig. 20). The sealing body 90 may be included in the semiconductor device 21 or in the semiconductor module 20. The sealing body 90 may include a gel 91, or may be a sealing body made of resin.

[0305] The semiconductor device 21 constitutes a power converter. The semiconductor device 21 includes a plurality of semiconductor elements 30. The configuration of the semiconductor elements 30 is the same as that shown in the preceding embodiment (see FIGS. 5 and 18). The semiconductor device 21 includes a plurality of semiconductor elements 30 connected in parallel to each other. The parallel-connected semiconductor elements 30 provide one arm. The semiconductor device 21 may provide only one arm. As shown in FIGS. 61 and 62, the semiconductor device 21 provides the upper and lower arm circuits 9 for one phase. The semiconductor device 21 providing the upper and lower arm circuits 9 includes a plurality of semiconductor elements 30H that provide the upper arm 9H and a plurality of semiconductor elements 30L that provide the lower arm 9L. The semiconductor elements 30H correspond to the upper arm elements, and the semiconductor elements 30L correspond to the lower arm elements.

[0306] A plurality of semiconductor elements 30H are lined up in the X direction. A plurality of semiconductor elements 30L are lined up in the X direction. The semiconductor elements 30H and the semiconductor elements 30L are lined up in the Y direction. The number of semiconductor elements 30H and 30L may be the same or different. In the example shown in FIG. 62 , the semiconductor elements 30H and 30L have the same configuration, and the number of semiconductor elements 30H and 30L is the same.

[0307] Similar to the configuration shown in the preceding embodiment, the semiconductor module 20 may include three semiconductor devices 21 each providing one phase of upper and lower arm circuits 9. The three semiconductor devices 21, i.e., the three substrates 40, may be arranged side by side in the X direction.

[0308] <Semiconductor Element and Substrate> Figure 63 is a cross-sectional view taken along line LXIII-LXIII in Figure 62. Similar to the configuration shown in the preceding embodiment (see Figure 4), the substrate 40 includes an insulating base material 41 and conductors 42 and 43. The conductor 42 corresponds to the surface conductor, and the conductor 43 corresponds to the back conductor. The conductor 42 is patterned and has multiple wiring patterns. The conductor 43 may be, for example, an unpatterned, so-called solid conductor, as shown in Figure 63. The conductor 43 may also be patterned.

[0309] The conductor 42 includes an element mounting portion as a wiring pattern. The conductor 42 includes at least one element mounting portion. The drain electrodes 31 of the multiple semiconductor elements 30 arranged in the X direction are connected to the element mounting portion. As shown in FIGS. 62 and 63 , the conductor 42 may have, as the element mounting portion, a base 421a on which multiple semiconductor elements 30H are mounted and a base 423a on which multiple semiconductor elements 30L are mounted. The base 421a corresponds to the upper arm mounting portion, and the base 423a corresponds to the lower arm mounting portion.

[0310] The base 421a extends in the X direction. The multiple semiconductor elements 30H are arranged on the base 421a and lined up in the X direction. The source electrodes 32 of the multiple semiconductor elements 30H are bonded to the common base 421a. As a result, the multiple semiconductor elements 30H are connected in parallel to one another. The base 423a extends in the X direction. The multiple semiconductor elements 30L are arranged on the base 423a and lined up in the X direction. The source electrodes 32 of the multiple semiconductor elements 30L are bonded to the common base 423a. As a result, the multiple semiconductor elements 30L are connected in parallel to one another.

[0311] One of the element mounting portions is disposed in the central region of the substrate 40 in the Y direction. The central region is a region of a predetermined range centered on the central position of the substrate 40 in the Y direction. As shown in Figures 62 and 63, in a configuration including two base portions 421a, 423a, the base portion 421a may be disposed in the central region of the substrate 40. That is, multiple semiconductor elements 30H may be mounted in the central region of the substrate 40 in the Y direction. In this configuration, the base portion 423a is disposed outside the central region in the Y direction. Multiple semiconductor elements 30L are mounted on the substrate 40 outside the central region in the Y direction.

[0312] The conductor 42 may be divided into a plurality of wiring patterns in the Y direction. For example, in the portion indicated by the dashed dotted line in Fig. 62 , the conductor 42 is divided into an N wiring 422, a relay wiring 424, a signal wiring 425, a base 421a, an N wiring 422, a base 423a, and a signal wiring 426. The conductor 42 is laid out in such a manner that the bases 421a and 423a, which are mounting portions for the semiconductor element 30, and the relay wiring 424 and signal wirings 425 and 426, which are mounting portions for the capacitor 71 and resistor 72, which are passive components, are separately included.

[0313] As shown in Figure 62, the substrate 40 may have a non-placement region 411 in which the conductor 42 is not placed, and which is provided so as to cross the conductor 42 in the X direction. The non-placement region 411 is a region in which the conductor 42 is not placed on the insulating base material 41, and extends from one end to the other end of the substrate 40 in the X direction. The non-placement region 411 separates the conductor 42 in the Y direction. The number of non-placement regions 411 is not particularly limited. The substrate 40 may have only one non-placement region 411 as shown in Figure 62, or may have multiple non-placement regions 411.

[0314] The conductor 42 may have an extension portion 421b and an N wiring 422 as main wiring portions. The extension portion 421b electrically connects the drain electrode 31 of the semiconductor element 30H to the P terminal 611 via the base portion 421a. The N wiring 422 electrically connects the source electrode 32 of the semiconductor element 30L to the N terminal 612. As shown in FIGS. 62 and 63 , the N wiring 422, which is a main wiring electrically isolated from the semiconductor element 30H arranged in the central region, may be arranged between the base portions 421a and 423a. In other words, the main wiring may be arranged between the base portions 421a and 423a in the Y direction.

[0315] The wiring pattern of the conductor 42 shown in FIG. 62 is similar to that of the preceding embodiment (see FIGS. 5 and 6 ). The N wiring 422 has a base 422a located between the bases 421a and 423a and an extension 422b connecting the main terminal 612 and the base 422a. A terminal connection 422c provided at the end of the extension 422b is aligned with the terminal connection 421c of the P wiring 421 in the X direction. The N wiring 422 has two extensions 422b extending from both ends of the base 422a. The N wiring 422 has a generally C-shape in plan view, and the two extensions 422b sandwich the P wiring 421, the relay wiring 424, and the signal wiring 425 in the X direction.

[0316] The area relationship between the bases 421a and 423a in plan view from the Z direction is not particularly limited. For example, they may be equal in area. The area of ​​the element mounting portion arranged in the central region may be smaller than the area of ​​the element mounting portion arranged outside the central region. In the example shown in FIG. 62 , the area of ​​the base 421a arranged in the central region is smaller than the area of ​​the base 423a arranged outside the central region.

[0317] The spacing between the semiconductor elements 30 mounted on the bases 421a and 423a is not particularly limited. For example, as shown in FIG. 62 , the spacing between the semiconductor elements 30H and the spacing between the semiconductor elements 30L may be substantially equal. The spacing between the semiconductor elements 30H may be narrower than the spacing between the semiconductor elements 30L. For example, the spacing between the semiconductor elements 30H on the base 421a with a small area located in the central region may be narrower than the spacing between the semiconductor elements 30L on the base 423a with a large area located outside the central region.

[0318] The thickness of the conductor 42 may be substantially equal to the thickness of the conductor 43. As shown in FIG.

[0319] Summary of Sixth Embodiment A semiconductor module 20 may include a cooler 23, a substrate 40, a bonding material 24, and a plurality of semiconductor elements 30. The substrate 40 is disposed on one surface 23a of the cooler 23, and a bonding material 24 (thermal conductive member) is interposed between a conductor 43 (rear surface conductor) of the substrate and the cooler 23. Drain electrodes 31 (first main electrodes) of the plurality of semiconductor elements 30 are bonded to conductors 42 (surface conductors) of the substrate 40. In the above configuration, one of the element mounting portions, to which the drain electrodes 31 of the plurality of semiconductor elements 30 arranged in the X direction are commonly connected, may be disposed in a central region of the substrate 40 in the Y direction (orthogonal direction).

[0320] According to the above configuration, the substrate 40 has a convex warp toward the cooler 23 due to the difference in expansion and contraction between the patterned conductors 42 and 43. The substrate 40 warps due to heat generated during the manufacturing process. The substrate 40 warps in the Y direction, with the central region serving as the apex of the convex. The warp of the substrate 40 is greater in the Y direction than in the X direction, in which multiple semiconductor elements 30 are arranged. As illustrated in FIG. 64 , the substrate 40 is fixed to the cooler 23 in a warped state via a thermally conductive member. For example, heat generated during soldering (reflow) causes the substrate 40 to warp toward the cooler 23, and the substrate 40 is fixed (soldered) to the cooler 23 in a warped state. The thickness of the bonding material 24 is thin near the apex of the convex, i.e., directly below the central region. By locating the element mounting portion in the central region, thermal resistance can be reduced in a configuration in which multiple semiconductor elements 30 are connected in parallel. Heat from the semiconductor elements 30, which are heat-generating elements, can be effectively dissipated toward the cooler 23.

[0321] 63, the conductor 42 may be divided into multiple wiring patterns in the Y direction. By dividing the wiring patterns into multiple patterns and narrowing the areas that expand and contract, the substrate 40 is more likely to warp in the Y direction. This effectively reduces the thermal resistance between the substrate 40 and the cooler 23 directly below the multiple semiconductor elements 30 located in the central region.

[0322] 62 , the substrate 40 may be provided with a no-placement area 411 that crosses the conductor 42 in the X direction. By providing the no-placement area 411, the substrate 40 is more likely to warp in the Y direction. Therefore, the thermal resistance between the substrate 40 and the cooler 23 directly below the multiple semiconductor elements 30 located in the central region can be effectively reduced.

[0323] The multiple semiconductor elements 30 may include multiple semiconductor elements 30H (upper arm elements) aligned in the X direction and multiple semiconductor elements 30L (lower arm elements) aligned in the X direction. The element mounting portion may include a base 421a (upper arm element portion) to which the drain electrodes 31 of the semiconductor elements 30H are commonly connected, and a base 423a (lower arm element portion) to which the drain electrodes 31 of the semiconductor elements 30L are commonly connected. In the above configuration, one of the bases 421a, 423a may be disposed in a central region of the substrate 40 in the Y direction, and the other of the bases 421a, 423a may be disposed outside the central region. In other words, this configuration may be applied to a configuration providing upper and lower arm circuits 9.

[0324] 62, for example, when the base 421a is disposed in the central region, it is possible to effectively reduce the thermal resistance between the substrate 40 and the cooler 23 directly below the plurality of semiconductor elements 30H. Although not shown, when the base 423a is disposed in the central region, it is possible to effectively reduce the thermal resistance between the substrate 40 and the cooler 23 directly below the plurality of semiconductor elements 30L.

[0325] In a configuration that provides upper and lower arm circuits 9, a main wiring section that is electrically isolated from the semiconductor elements 30 arranged in the central region may be arranged between the bases 421a and 423a. By arranging the main wiring section, the conductor 42 is divided into more wiring patterns in the Y direction. This makes the substrate 40 more likely to warp in the Y direction. This effectively reduces the thermal resistance between the substrate 40 and the cooler 23 directly below the multiple semiconductor elements 30 located in the central region.

[0326] The area of ​​the bases 421a, 423a in the central region may be smaller than that of the bases located outside the central region in a plan view in the Z direction. The semiconductor elements 30 in the central region can reduce the thermal resistance directly below them as described above, so heat can be effectively dissipated even if the bases are small. The semiconductor elements 30 outside the central region have larger base areas, so heat can be effectively dissipated even if the thermal resistance directly below them is greater than that of the semiconductor elements 30H, 30L in the central arm circuit 9. In other words, heat can be effectively dissipated from both the semiconductor elements 30H, 30L that constitute the upper and lower arm circuits 9.

[0327] In a configuration in which one of the element mounting portions is disposed in the central region of the substrate 40 in the Y direction, the conductor 42 may be thicker than the conductor 43. By making the conductor 42 thicker, the amount of warping of the substrate 40 can be reduced. In other words, the increase in thermal resistance associated with warping can be suppressed outside the central region. Note that the substrate 40 will warp convexly toward the cooler 23 when the volume of the conductor 43 is greater than or equal to the volume of the conductor 42. The conductor 42 is patterned to warp convexly toward the cooler 23 when the volume of the conductor 43 is greater than or equal to the volume of the conductor 42. Even if the conductor 42 is thicker, the substrate 40 will warp convexly toward the cooler 23 as long as the relationship of the volume of the conductor 43 is satisfied.

[0328] 65 , in a semiconductor device 21 that provides one arm, one of the element mounting portions may be disposed in the central region of the substrate 40 in the Y direction. Multiple semiconductor elements 30 are mounted on base portions 427a (element mounting portions) of drain wiring 427. The base portions 427a are disposed in the central region of the substrate 40 in the Y direction, which is perpendicular to the arrangement direction (X direction) of the multiple semiconductor elements 30. The base portions 427a and the source wiring 428 are aligned in the Y direction. The source electrode 32 of the semiconductor element 30 is electrically connected to the source wiring 428 via a clip 50.

[0329] The configuration described in this embodiment can be combined with the configuration described in the preceding embodiment.

[0330] Seventh Embodiment This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0331] <Oscillation in Parallel Connection> Figure 66 is an equivalent circuit diagram showing an example of the upper arm 9H. In Figure 66, two MOSFETs 11 are connected in parallel to form the upper arm 9H. The MOSFETs 11 have parasitic capacitances between the gate and source, between the gate and drain, and between the drain and source. The gate electrodes of the two MOSFETs 11 are connected to each other. A gate drive signal is input to each gate electrode from a common gate driver (GD) 14. The gate wiring connecting the gate driver 14 to each gate electrode has resistance Rg and parasitic inductance Lg. The source electrodes of the two MOSFETs 11 are connected to each other. The wiring connecting the source electrodes has parasitic inductance Ls.

[0332] In a parallel circuit of multiple MOSFETs 11, an oscillation circuit is formed by the parasitic capacitance of the MOSFETs 11, the parasitic inductance of the wiring, etc. Oscillation occurs when the input signal input from the gate driver 14 to the gate electrode and the feedback signal on the path via the parasitic capacitance, parasitic inductance, etc. are in phase and the gain is 0 dB or more, that is, when the feedback signal is amplified. Oscillation occurs when the resonance condition is met.

[0333] The parasitic inductance Ls between the source electrodes is large, while the parasitic inductance Lg of the gate wiring is small. To suppress oscillation, it is effective to reduce the parasitic inductance Ls between the source electrodes and / or increase the gate impedance.

[0334] <Reduction of Parasitic Inductance Between Source Electrodes> Figure 67 shows an example of a semiconductor device 21 according to this embodiment. The basic configuration of the semiconductor device 21 is similar to the configuration described in the preceding embodiments (see Figures 2 to 6 and 18). The semiconductor device 21 includes a plurality of semiconductor elements 30 and a substrate 40. As shown in Figure 67, the semiconductor device 21 may include a clip 50. The semiconductor device 21 may include an external connection terminal 60. The semiconductor device 21 may include a snubber circuit 70.

[0335] As described above, the semiconductor element 30 has a source electrode 32 and a pad 33 arranged on one surface 34a of the semiconductor substrate 34, and a drain electrode 31 arranged on the back surface 34b. Multiple semiconductor elements 30 may provide only one arm. As shown in FIG. 67, a semiconductor device 21 may provide upper and lower arm circuits 9 for one phase. The semiconductor device 21 providing the upper and lower arm circuits 9 includes multiple semiconductor elements 30H that provide upper arms 9H and multiple semiconductor elements 30L that provide lower arms 9L. The multiple semiconductor elements 30H are aligned in the X direction. The multiple semiconductor elements 30L are aligned in the X direction. The semiconductor elements 30H and the semiconductor elements 30L are aligned in the Y direction.

[0336] Similar to the configuration shown in the preceding embodiment, the semiconductor module 20 may include three semiconductor devices 21 each providing one phase of upper and lower arm circuits 9. The three semiconductor devices 21, i.e., the three substrates 40, may be arranged side by side in the X direction.

[0337] Similar to the configuration described in the preceding embodiment, the substrate 40 has an insulating base material 41 and a conductor 42 disposed on the insulating base material 41. The conductor 42 corresponds to wiring. The substrate 40 may have a conductor 43 on the surface opposite the conductor 42. The conductor 42 is patterned. The conductor 42 has a P wiring 421, an N wiring 422, and an O wiring 423 to provide the upper and lower arm circuits 9. As shown in FIG. 67 , the conductor 42 may have a relay wiring 424. The conductor 42 may have signal wirings 425 and 426.

[0338] A plurality of semiconductor elements 30H are mounted on the base 421a of the P wiring 421. The drain electrodes 31 of the plurality of semiconductor elements 30H are bonded to the base 421a. The plurality of semiconductor elements 30H are connected in parallel to one another. A plurality of semiconductor elements 30L are mounted on the base 423a of the O wiring 423. The drain electrodes 31 of the plurality of semiconductor elements 30L are bonded to the base 423a. The plurality of semiconductor elements 30L are connected in parallel to one another. The source electrodes 32 of the plurality of semiconductor elements 30H are electrically connected to the base 423a of the O wiring 423 via clips 50H. The source electrodes 32 of the plurality of semiconductor elements 30L are electrically connected to the base 422a of the N wiring 422 via clips 50L.

[0339] As shown in FIG. 67 , the semiconductor device 21 may include a metal plate 100. The metal plate 100 is a plate formed using a metal material with good conductivity, such as copper. The metal plate 100 may be, for example, flat. The metal plate 100 shorts the source electrodes 32 of multiple semiconductor elements 30 connected in parallel. The metal plate 100 electrically connects the multiple source electrodes 32 with low impedance. The metal plate 100 may be joined to the source electrodes 32 or may be connected to the source electrodes 32 via another metal member. The metal plate 100 bridges the multiple source electrodes 32. The metal plate 100 may be arranged so as to be enclosed in a planar view by wiring on which the multiple semiconductor elements 30 to be connected are mounted.

[0340] 67 , the metal plate 100 may include a metal plate 100H and a metal plate 100L. The metal plate 100H short-circuits the source electrodes 32 of multiple semiconductor elements 30H. The metal plate 100L short-circuits the source electrodes 32 of multiple semiconductor elements 30L. The metal plate 100H is joined to a clip 50H. The metal plate 100L is joined to a clip 50L. Although not shown, the clip 50 may also function as the metal plate 100.

[0341] Fig. 68 shows an equivalent circuit of the upper and lower arm circuits 9 provided by the semiconductor device 21 illustrated in Fig. 67. The short-circuit portion formed by the metal plate material 100H shorts the source electrodes 32 of the multiple MOSFETs 11 that constitute the upper arm 9H. The short-circuit portion formed by the metal plate material 100L shorts the source electrodes 32 of the multiple MOSFETs 11 that constitute the lower arm 9L.

[0342] The configuration for short-circuiting the source electrodes 32 is not limited to the above example. For example, as shown in FIG. 69 , bonding wires 80 may be used instead of the metal plate 100. The bonding wires 80 electrically connect adjacent joints 51 in the X direction. As shown in FIG. 69 , the bonding wires 80 may electrically connect adjacent joints 51 joined to the source electrodes 32 of different semiconductor elements 30H. The bonding wires 80 may also electrically connect adjacent joints 51 joined to the source electrodes 32 of different semiconductor elements 30L. The number of bonding wires 80 connecting adjacent joints 51 is not particularly limited. As shown in FIG. 69 , multiple bonding wires 80 may be connected.

[0343] As shown in Figure 70, a configuration without using the clip 50 may be used. The metal plate 100H is joined to the source electrode 32 of the semiconductor element 30H. The metal plate 100H bridges four semiconductor elements 30H. A plurality of bonding wires 80 are connected to the metal plate 100H. The bonding wires 80 extend in the Y direction in a plan view. One end of the bonding wire 80 is connected to the metal plate 100H, and the other end is connected to the base 423a of the O wiring 423. The plurality of bonding wires 80 are arranged in the X direction in a plan view.

[0344] Similarly, the metal plate 100L is bonded to the source electrode 32 of the semiconductor element 30L. The metal plate 100L bridges the four semiconductor elements 30L. A plurality of bonding wires 80 are connected to the metal plate 100L. The bonding wires 80 extend in the Y direction in a plan view. One end of the bonding wire 80 is connected to the metal plate 100L, and the other end is connected to the base 422a of the N wiring 422. The plurality of bonding wires 80 are arranged in the X direction in a plan view. The bonding wires 80 connected to the metal plate 100H and the bonding wires 80 connected to the metal plate 100L are arranged alternately in the X direction.

[0345] As shown in Figures 71, 72, and 73, a metal block 101 of a predetermined height may be interposed between the source electrode 32 of the semiconductor element 30 and the metal plate 100. Figure 71 shows the periphery of the semiconductor elements 30H and 30L in the semiconductor device 21. Figure 72 is a cross-sectional view taken along line LXXII-LXXII in Figure 71. Figure 73 is an enlarged view of the region LXXIII indicated by the dashed dotted line in Figure 72. The metal block 101 may also be referred to as a terminal, a conductive spacer, or the like. The metal block 101 is provided separately for each semiconductor element 30. The metal block 101 is connected to the source electrode 32 via a bonding material such as solder 81. The metal block 101 is connected to the metal plate 100 via a bonding material 83 such as solder.

[0346] As shown in FIG. 73 , the metal block 101 may have an oxide film 102. The oxide film 102 is provided on the surface facing the semiconductor element 30, on the portion of the insulating film 35 facing the element upper portion 354 (see FIGS. 18 and 19 ). The metal block 101 may have a base material made of a highly conductive metal such as copper, and a plating film formed on the base material. The plating film contains, for example, Ni as its main component. The oxide film 102 is formed, for example, by irradiating the plating film with laser light. The oxide film 102 has low wettability with respect to solder. The oxide film 102 can prevent the solder 81 from being positioned above the element upper portion 354.

[0347] <Increase in Gate Impedance> Fig. 74 shows another example of the semiconductor device 21. Similar to the configuration shown in Fig. 67, the semiconductor device 21 includes a plurality of semiconductor elements 30 and a substrate 40. As shown in Fig. 74, the semiconductor device 21 may include a clip 50. The semiconductor device 21 may include an external connection terminal 60. The semiconductor device 21 may include a snubber circuit 70.

[0348] The semiconductor device 21 may include a passive component 103. The passive component 103 includes a ferrite bead or a balancing resistor. The passive component 103 is disposed in the gate wiring (signal path) connecting the gate electrode of the MOSFET 11, i.e., the gate pad 33G of the semiconductor element 30, to the gate driver 14, and increases the impedance of the gate wiring. As shown in FIG. 74 , in a configuration in which the substrate 40 includes signal wirings 425 and 426, the passive component 103 may be mounted on the gate wirings 425G and 426G.

[0349] In the example shown in Figure 74, the semiconductor device 21 includes a signal terminal 62. For convenience, Figure 74 shows only a gate terminal 62G as the signal terminal 62. The arrangement and connection structure of the signal wirings 425, 426 including gate wirings 425G, 426G, and the signal terminal 62 including the gate terminal 62G are similar to the configurations described in the preceding embodiment (see Figures 5 and 42). The signal wirings 425, which are divided by the P wiring 421 and have the same function, are electrically connected by bonding wires 80.

[0350] The passive component 103 is mounted on the gate wiring 425G so as to electrically relay between a portion electrically connected to the gate terminal 62G and a portion electrically connected to the gate pad 33G. The passive component 103 is mounted on the gate wiring 426G so as to electrically relay between a portion electrically connected to the gate terminal 62G and a portion electrically connected to the gate pad 33G.

[0351] The parallel-connected semiconductor elements 30 are divided into groups with a number smaller than the number of elements. The parallel-connected semiconductor elements 30 are grouped together based on their similar layout. In the example shown in FIG. 74 , the semiconductor elements 30H are divided into two groups 301H and 302H. Of the four semiconductor elements 30H aligned in the X direction, the two semiconductor elements 30H at one end belong to group 301H, and the two semiconductor elements 30H at the other end belong to group 302H. Similarly, the semiconductor elements 30L are divided into two groups 301L and 302L. Of the four semiconductor elements 30L aligned in the X direction, the two semiconductor elements 30L at one end belong to group 301L, and the two semiconductor elements 30L at the other end belong to group 302L.

[0352] The above-mentioned passive components 103 are provided for each group, not for each semiconductor element 30. As shown in FIG. 74 , the gate pad 33G of the semiconductor element 30H belonging to group 301H is electrically connected via a bonding wire 80 to a gate wiring 425G located on the group 301H side in the X direction. A passive component 103 is mounted on the gate wiring 425G corresponding to group 301H. The gate pad 33G of the semiconductor element 30H belonging to group 302H is electrically connected via a bonding wire 80 to a gate wiring 425G located on the group 302H side in the X direction. A passive component 103 is mounted on the gate wiring 425G corresponding to group 302H.

[0353] Similarly, the gate pad 33G of the semiconductor element 30L belonging to group 301L is electrically connected to a gate wiring 426G located on the group 301L side in the X direction via a bonding wire 80. A passive component 103 is mounted on the gate wiring 426G corresponding to group 301L. The gate pad 33G of the semiconductor element 30L belonging to group 302L is electrically connected to a gate wiring 426G located on the group 302L side in the X direction via a bonding wire 80. A passive component 103 is mounted on the gate wiring 426G corresponding to group 302L.

[0354] 75, the passive components 103 are arranged outside the semiconductor device 21. As described above, the passive components 103 are provided in the signal path between the gate driver 14 and the gate pad 33G. The passive components 103 may be mounted on a circuit board (not shown) on which the gate driver 14 is formed, for example. The gate terminals 62G are provided for each group. The semiconductor device 21 includes a gate terminal 62G corresponding to the group 301H, a gate terminal 62G corresponding to the group 302H, a gate terminal 62G corresponding to the group 301L, and a gate terminal 62G corresponding to the group 302L.

[0355] A configuration that reduces the inductance between source electrodes 32 may be combined with a configuration that increases the impedance of the gate wiring. For example, as shown in Fig. 76, a configuration in which source electrodes 32 are short-circuited by a metal plate 100 may be combined with a configuration in which passive components 103 are provided for each group. In Fig. 76, a metal plate 100 is provided for each group. The metal plate 100 short-circuits the source electrodes 32 of two semiconductor elements 30 that belong to the same group.

[0356] Although an example in which the passive components 103 are mounted on the substrate 40 has been shown, this is not limiting. A printed circuit board may be prepared separately from the insulating substrate serving as the substrate 40, and the passive components 103 may be mounted on the printed circuit board. The insulating base material of the printed circuit board contains resin. The insulating base material of the insulating substrate does not contain resin and is made of, for example, ceramic. Printed circuit boards allow for finer wiring patterns than insulating substrates.

[0357] The semiconductor device 21 shown in FIG. 77 includes an interconnection board 104. The interconnection board 104 is a printed circuit board. Passive components 103 are mounted on the interconnection board 104. The substrate 40 shown in FIG. 77 is an insulating substrate. As shown in FIG. 77, the interconnection board 104 may be mounted on the substrate 40. The interconnection board 104 is disposed on an insulating substrate 41 made of ceramic. The interconnection board 104 is fixed to the substrate 40 by adhesive, for example. In the example shown in FIG. 77, the semiconductor device 21 includes three semiconductor elements 30H. A separate interconnection board 104 is provided for each semiconductor element 30H. Passive components 103 are mounted on each of the interconnection boards 104. The semiconductor elements 30H are arranged in the X direction, and the interconnection boards 104 are also arranged in the X direction. The interconnection boards 104 are arranged to avoid the P wiring 421 and the N wiring 422.

[0358] The pad 33 is connected to the corresponding wiring on the relay board 104 via a bonding wire 80. The passive component 103 is provided on a signal path connecting the gate pad 33G of the semiconductor element 30H corresponding to the mounted relay board 104 and the gate terminal 62G. Wires having the same function on adjacent relay boards 104 are electrically connected via a bonding wire 80. One of the relay boards 104 at the end in the X direction is electrically connected to the gate terminal 62G via a bonding wire 80.

[0359] The relay substrate 104 may be disposed on a metal member bonded to the source electrodes 32 of the semiconductor elements 30. For example, as shown in FIG. 78 , the relay substrate 104 may be disposed on a metal plate 100. The metal plate 100 is bonded to a clip 50H, similar to the configuration shown in FIG. 67 . The metal plate 100 extends in the X direction so as to overlap with three semiconductor elements 30H in a plan view. The metal plate 100 short-circuits the source electrodes 32 of the three semiconductor elements 30H via the clip 50H. The relay substrate 104 is adhesively fixed to the metal plate 100.

[0360] The relay substrates 104 are arranged so as to overlap the corresponding semiconductor elements 30H in a plan view. The pads 33 are connected to the corresponding wiring of the relay substrates 104 via bonding wires 80. Wires having the same function on adjacent relay substrates 104 are electrically connected via bonding wires 80. One of the relay substrates 104 at the end in the X direction is electrically connected to the gate terminal 62G via the bonding wire 80.

[0361] 77 and 78 show an example of semiconductor element 30H, but a similar structure can also be adopted for semiconductor element 30L. While FIGS. 77 and 78 show an example in which relay substrates 104 are provided individually for semiconductor elements 30, this is not limiting. In a configuration in which relay substrates 104 are mounted on substrate 40, relay substrates 104 may be provided for multiple semiconductor elements 30. For example, a common relay substrate 104 may be provided for two semiconductor elements 30, and the passive components 103 provided for each semiconductor element 30 may be mounted on the common relay substrate 104. A relay substrate 104 may also be provided for each of the above-mentioned groups. Passive components 103 common to the group are mounted on the relay substrate 104.

[0362] In a configuration in which the relay board 104 is disposed on the metal plate 100, the relay board 104 may be provided for each of the plurality of semiconductor elements 30. For example, a common relay board 104 may be provided for two semiconductor elements 30, and the passive components 103 provided for each semiconductor element 30 may be mounted on the common relay board 104. A relay board 104 may be provided for each of the above-mentioned groups. Passive components 103 common to the group are mounted on the relay board 104. A common relay board 104 may be provided for all of the semiconductor elements 30 connected in parallel. In this case, the passive components 103 provided for each semiconductor element 30 may be mounted on the common relay board 104. The passive components 103 provided for each group may be mounted on the common relay board 104.

[0363] 78 shows an example in which the relay substrate 104 is disposed on the metal plate 100, but the present invention is not limited to this. The relay substrate 104 may be disposed on the clip 50. In a configuration that does not include the clip 50, the relay substrate 104 may be disposed on the metal plate 100.

[0364] Summary of Seventh Embodiment The semiconductor device 21 may include a substrate 40 having a conductor 42 (wiring), and a plurality of semiconductor elements 30 connected in parallel with each other by having their drain electrodes 31 (first main electrodes) joined to a common wiring. The source electrodes 32 (second main electrodes) of the plurality of parallel-connected semiconductor elements 30 may be short-circuited by a metal member.

[0365] Since the source electrodes 32 are short-circuited by the metal member, the parasitic inductance Ls between the source electrodes 32 is small, and therefore, it is possible to suppress oscillation between the semiconductor elements 30, that is, in the parallel circuit.

[0366] The metal member may be a metal plate 100 or a bonding wire 80. Using the metal plate 100 can further reduce the parasitic inductance Ls between the source electrodes 32. Using the bonding wire 80 can short-circuit the source electrodes 32 in the wire connection process that electrically connects the pad 33 and the signal terminal 62. Therefore, the process can be simplified and the parasitic inductance Ls between the source electrodes 32 can be reduced.

[0367] The semiconductor device 21 may include a substrate 40 having a conductor 42 (wiring) and a plurality of semiconductor elements 30 connected in parallel with each other by having their drain electrodes 31 (first main electrodes) joined to a common wiring. In addition to the substrate 40 and the semiconductor elements 30, the semiconductor device 21 may include a passive component 103 including a ferrite bead or a balancing resistor, which is provided on the gate wiring electrically connected to the gate pad 33G. The plurality of semiconductor elements 30 may be grouped together with those arranged in close proximity and divided into groups with a number of groups smaller than the number of semiconductor elements 30 connected in parallel, and a passive component 103 may be provided for each group.

[0368] By providing the gate wiring with a passive component 103, such as a ferrite bead or balance resistor, the impedance of the gate wiring can be increased. Therefore, oscillation between semiconductor elements 30, i.e., in a parallel circuit, can be suppressed. In parallel-connected semiconductor elements 30, the greater the distance between the semiconductor elements 30, the greater the parasitic inductance between the source electrodes 32, making oscillation more likely to occur. In other words, oscillation is less likely to occur between semiconductor elements 30 that are located close to each other. By grouping semiconductor elements 30 that are located close to each other and less likely to experience oscillation, and providing a passive component 103 for each group, oscillation between groups can be suppressed. By providing a passive component 103 for each group, oscillation in a parallel circuit can be suppressed while reducing the number of passive components 103.

[0369] The semiconductor device 21 may include a gate terminal 62G as the signal terminal 62. The passive component 103 may be mounted on the gate wiring 425G, 426G that electrically connects the gate pad 33G and the gate terminal 62G on the substrate 40. This makes it possible to adjust the impedance of the gate wiring within the semiconductor device 21. Since the passive component 103 can be mounted using the manufacturing process of the semiconductor device 21, the manufacturing process can be simplified.

[0370] An insulating substrate may be used as the substrate 40. The semiconductor device 21 may include a substrate 40 (insulating substrate) having a conductor 42 (wiring) and a plurality of semiconductor elements 30 whose drain electrodes 31 (first main electrodes) are joined to a common wiring and connected in parallel. In addition to the substrate 40 and the semiconductor elements 30, the semiconductor device 21 may include a gate terminal 62G and an interconnection substrate 104 (printed circuit board) on which passive components 103 are mounted. The passive components 103 include ferrite beads or balancing resistors and adjust the impedance of the gate wiring provided on the interconnection substrate 104.

[0371] Since the gate wiring of the relay substrate 104 is provided with a passive component 103, which is a ferrite bead or a balance resistor, the impedance of the gate wiring can be increased. This can suppress oscillation between the semiconductor elements 30, i.e., in a parallel circuit. A printed circuit board allows for finer wiring than an insulating substrate such as an AMB substrate. AMB is an abbreviation for Active Metal Brazing. Since the gate wiring is provided on the relay substrate 104, which can be finely processed, rather than on the substrate 40, the size of the semiconductor device 21 can be reduced in a configuration including the passive component 103.

[0372] The relay substrate 104 may be mounted on the substrate 40, or may be disposed on a metal member bonded to the source electrode 32 (second main electrode). When disposed on the substrate 40, the wiring can be made finer as described above, thereby enabling the size of the semiconductor device 21 to be reduced. When disposed on a metal member, there is no need to provide space for the relay substrate 104 on the substrate 40, enabling the size of the semiconductor device 21 to be further reduced. The metal member may be a metal plate 100 that short-circuits the source electrode 32, as illustrated in FIG. 78 .

[0373] The configuration described in this embodiment can be combined with the configuration described in the preceding embodiment.

[0374] Eighth Embodiment This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In particular, this embodiment is a modification of the semiconductor device 21 shown in FIG.

[0375] As shown in Figure 79, the semiconductor device 21 according to this embodiment includes an interconnection board 104, similar to that of Figure 77 described above. A plurality of interconnection boards 104 are provided for one semiconductor device 21. A plurality of interconnection boards 104 are provided for one upper arm 9H. The number of interconnection boards 104 provided for one upper arm 9H is the same as the number of semiconductor elements 30H that constitute one upper arm 9H. For example, in the example of Figure 79, three semiconductor elements 30H are connected in parallel to provide one upper arm 9H,

[0376] The lower arm 9L is similar to the upper arm 9H, and each lower arm 9L is provided with a plurality of relay boards 104. In the example of Fig. 79, the number of relay boards 104 is three. The plurality of relay boards 104 are electrically connected by bonding wires 80.

[0377] The relay substrate 104 provides a portion of the signal wiring that electrically relays the signal terminals 62 and the semiconductor element 30. The signal terminals 62 include a gate terminal 62G, a Kelvin source terminal 62KS, an anode terminal 62A, and a cathode terminal 62C. As described above with reference to Figures 2 and 3, the signal terminals 62 are held by the frame body 221. The gate terminal 62G corresponds to a drive command terminal. The Kelvin source terminal 62KS corresponds to a potential detection terminal.

[0378] In this embodiment, as in the preceding embodiment, the relay board 104 that provides signal wiring is disposed between the semiconductor element 30 and the snubber circuit 13. The semiconductor elements 30 of each arm are disposed side by side in a predetermined direction (X direction). The positions of these semiconductor elements 30 in the Y direction are the same. Similar to the semiconductor elements 30, the multiple relay boards 104 are also disposed side by side in the above-mentioned predetermined direction (X direction). The relay board 104 has a rectangular shape with the X direction as its longitudinal axis.

[0379] The relay board 104 for the upper arm 9H is disposed between the semiconductor element 30H and the snubber circuit 13. The relay board 104 for the lower arm 9L is disposed on the opposite side of the snubber circuit 13 with respect to the semiconductor element 30L. In other words, the snubber circuit 13, the relay board 104 for the upper arm 9H, the semiconductor element 30H, the semiconductor element 30L, and the relay board 104 for the lower arm 9L are arranged in this order in the direction perpendicular to the predetermined direction (Y direction).

[0380] The relay substrate 104 has an insulating base material and a conductor disposed on the insulating base material. The relay substrate 104 is fixed to one surface 41 a of the substrate 40. For example, the relay substrate 104 is mounted on the substrate 40 via a bonding material such as solder.

[0381] 80, a passive component 103 is mounted on an interconnect substrate 104. A ferrite bead is used for the passive component 103 according to this embodiment. This ferrite bead suppresses parasitic oscillation that occurs when multiple semiconductor elements 30H are connected in parallel.

[0382] Furthermore, a plurality of bonding pads are provided on the relay substrate 104. Of the bonding pads, pads 1G, 2G, and 3G are electrically connected to a gate pad 33G of the semiconductor element 30. The three pads 1G, 2G, and 3G are connected to each other by conductors (printed wiring) on ​​the relay substrate 104. The gate pad 33G corresponds to a drive command pad that commands the flow of electricity to the main electrodes, namely the drain electrode 31 and the source electrode 32.

[0383] Among the bonding pads of the relay board 104, pads 1KS, 2KS, and 3KS are electrically connected to the Kelvin source pad 33KS. The three pads 1KS, 2KS, and 3KS are connected to each other by conductors (printed wiring) of the relay board 104. The Kelvin source pad 33KS corresponds to a potential detection pad that outputs a signal for detecting the potential of the source electrode 32, which is the main electrode.

[0384] Bonding wire 10G connects gate pad 33G to pad 1G. Bonding wire 10KS connects Kelvin source pad 33KS to pad 1KS. Bonding wire 10A connects anode pad 33A to pad 1G. Pad 2G is connected to pad 3G or gate terminal 62G of another relay substrate 104. Bonding wire 80 connected to pad 2G and pad 3G will be referred to as bonding wire 80G in the following description. Pad 2KS is connected to pad 3KS or Kelvin source terminal 62KS of another relay substrate 104. Bonding wire 80 connected to pad 2KS and pad 3KS will be referred to as bonding wire 80KS in the following description. Bonding wire 80G corresponds to connecting wiring that electrically connects multiple relay substrates 104.

[0385] Pad 1G and pad 1KS are arranged side by side in the X direction. Three pads 1G, 2G, and 3G are arranged side by side in the X direction. Three pads 1KS, 2KS, and 3KS are arranged side by side in the X direction. Kelvin source pad 33KS, gate pad 33G, anode pad 33A, and cathode pad 33C are arranged side by side in the X direction. These four pads 33 are arranged to face the relay substrate 104. In other words, the orientation of the semiconductor element 30 is set so that the gate pad 33G is located on the relay substrate 104 side with respect to the main electrode.

[0386] <Clip Arrangement> The clip 50H corresponds to the upper arm metal plate material, and the clip 50L corresponds to the lower arm metal plate material. The clip 50H and the clip 50L are arranged to face each other in the Y direction. The clip 50H and the clip 50L are arranged offset so as to be in different positions in the X direction.

[0387] The portion of the intermediate portion 533 that is connected to the joint portion 52 corresponds to the adjacent portion 533p. The adjacent portion 533p has a shape that extends in the Y direction. The adjacent portion 533p of the clip 50H and the adjacent portion 533p of the clip 50L are arranged so as to be adjacent to each other in the X direction. As shown by the arrows in FIG. 79 , the direction of the current flowing through the adjacent portion 533p of the clip 50H is opposite to the direction of the current flowing through the adjacent portion 533p of the clip 50L.

[0388] <Summary of Eighth Embodiment> In this embodiment as well, the relay substrate 104 (signal wiring) is disposed between the semiconductor element 30H and the snubber circuit 70. Therefore, the capacitor 71 constituting the snubber circuit 70 is spaced apart from the semiconductor element 30 by the distance of the relay substrate 104. This makes it possible to suppress heat reception by the capacitor 71.

[0389] Here, when a multi-parallel configuration is adopted in which one upper arm 9H or one lower arm 9L is configured with multiple semiconductor elements 30 connected in parallel to one another, the following problem arises. That is, it becomes necessary to turn on and off the multiple semiconductor elements 30 at the same timing. Therefore, it is necessary to transmit a common gate drive signal to each semiconductor element 30. As a result, the transmission path for transmitting the gate drive signal becomes complicated, which hinders effective use of the space on the substrate 40 and leads to an increase in the size of the semiconductor device 21.

[0390] In consideration of this point, in this embodiment, the multiple semiconductor elements 30H are arranged side by side in a predetermined direction (X direction). These multiple semiconductor elements 30H are arranged in an orientation such that the gate pads 33G are located on the relay substrate 104 side with respect to the main electrodes. This makes it possible to shorten the distance between the signal wiring provided by the relay substrate 104 and the gate pads 33G. Furthermore, the length of the signal wiring can also be shortened. This shortens the transmission path described above, promotes effective use of space on the substrate 40, and enables the miniaturization of the semiconductor device 21.

[0391] Furthermore, in this embodiment, the lower arm 9L is also miniaturized as follows. That is, the multiple semiconductor elements 30L are arranged side by side in a predetermined direction (X direction). These multiple semiconductor elements 30L are arranged so that the gate pads 33G are located on the relay substrate 104 side with respect to the main electrodes. This allows for a shorter distance between the relay substrate 104 (signal wiring) and the gate pads 33G, and also allows for a shorter length of the signal wiring. This shortens the transmission path described above, allowing for more efficient use of space on the substrate 40 to achieve miniaturization.

[0392] Furthermore, in this embodiment, the transmission path can be shortened in both the upper arm 9H and the lower arm 9L as described above, which also has the effect of shortening the length of the bonding wire 80. This reduces the risk of the bonding wire 80 breaking due to vibration.

[0393] As shown in FIG. 81 , the substrate 40 may be warped due to heat applied during the manufacturing process. In this case, if signal wiring is provided using a single relay substrate 104, contrary to the present embodiment, the following problem occurs. That is, since a long relay substrate 104 is mounted on the warped substrate 40, the gap between the relay substrate 104 and the substrate 40 in the Z direction becomes large. This makes it difficult to mount the relay substrate 104 on the substrate 40. Furthermore, the positional accuracy of the pads 1G, 2G, 3G, 1KS, 2KS, and 3KS relative to the substrate 40 deteriorates. This reduces the workability of bonding the bonding wires 10G, 10KS, and 10A using a tool.

[0394] To address the above-described problem, in this embodiment, multiple relay substrates 104 are provided for each upper arm 9H. That is, the signal wiring that electrically connects the signal terminals 62 and the semiconductor element 30 is provided by multiple relay substrates 104 and bonding wires 80G (connecting wiring). This allows each relay substrate 104 to be short. This reduces the gap between the relay substrate 104 and the substrate 40 in the Z direction. This facilitates mounting the relay substrate 104 on the substrate 40. This also improves the positional accuracy of the pads 1G, 2G, 3G, 1KS, 2KS, and 3KS relative to the substrate 40. This improves the workability of bonding the bonding wires 10G, 10KS, and 10A using a tool.

[0395] Furthermore, in this embodiment, the number of relay substrates 104 is the same as the number of semiconductor elements 30H constituting one upper arm 9H. This allows the distance between the gate pad 33G and the pad 1G to be shortened. This also allows the bonding wire 10G to be shortened. This reduces the risk of the bonding wire 10G being broken due to vibration.

[0396] In the present embodiment shown in Fig. 81, the number of the relay substrates 104 is three, but it may be two as shown in Fig. 82. In other words, the number of the relay substrates 104 may be less than the number of semiconductor elements 30H that constitute one upper arm 9H.

[0397] 79, the signal wiring is provided by the relay substrate 104 and the bonding wires 80. Alternatively, the relay substrate 104 may be replaced with the conductor 42 patterned on the substrate 40 (see FIG. 5).

[0398] Furthermore, in this embodiment, the clip 50H and the clip 50L have adjacent portions 533p adjacent to each other. The direction of current flowing through the adjacent portion 533p of the clip 50H is opposite to the direction of current flowing through the adjacent portion 533p of the clip 50L. Therefore, the direction of the magnetic field formed around the adjacent portion 533p of the clip 50H is opposite to the direction of the magnetic field formed around the adjacent portion 533p of the clip 50L. As a result, the magnetic fields cancel each other out, reducing the inductance of the clip 50H and the clip 50L.

[0399] Ninth Embodiment This embodiment is a modification of the preceding embodiment, and the description of the preceding embodiment can be used. In particular, this embodiment is a modification of the semiconductor device 21 shown in FIG.

[0400] 83, similarly to Fig. 15, the relay substrate 104 (signal wiring) is disposed between the semiconductor element 30H and the snubber circuit 70. The resistor 72 of the snubber circuit 70 is disposed closer to the center 40c of the substrate 40 than the passive component 103. The center 40c is the center in both the Y direction and the X direction.

[0401] The semiconductor device 21 shown in Fig. 15 has two P terminals 611 and one N terminal 612. In contrast to this, the semiconductor device 21 shown in Fig. 83 has one P terminal 611 and two N terminals 612. The N terminal 612 and the P terminal 611 are arranged adjacent to each other in the X direction.

[0402] The semiconductor device 21 has two current paths each including a P terminal 611, a P wiring 421, a capacitor 71, a resistor 72, an N wiring 422, and an N terminal 612. The two current paths are arranged symmetrically with respect to the center line CL of the substrate 40. The center line CL is a straight line that passes through the center 40c and extends in the Y direction. In the following explanation, one of the current paths arranged symmetrically with respect to the center line CL will be explained.

[0403] Each current path includes a plurality of capacitors 71 and a plurality of resistors 72. The plurality of capacitors 71 electrically bridge the N wiring 422 and the relay wiring 424. The plurality of capacitors 71 are connected in parallel to each other. The plurality of capacitors 71 are arranged in a line in the Y direction.

[0404] The plurality of resistors 72 electrically bridge the relay wiring 424 and the P wiring 421. Some of the plurality of resistors 72 form parallel groups connected in parallel to each other. A plurality of parallel groups are provided. In the example of FIG. 83 , two parallel groups of three resistors are provided. The two parallel groups are connected in series to each other via the relay wiring 424p. The three resistors 72 forming the parallel group are arranged in a row in the Y direction. The two parallel groups are arranged in a row in the X direction. These six resistors 72 are arranged on the side of the center line CL with respect to the four capacitors 71.

[0405] 84 , bonding wires 10G, 10KS that bridge pads 1G, 1KS of an interconnect substrate 104 and pads 33 of a semiconductor element 30 are formed by a bonding tool TL. The bonding tool TL has a nozzle TLa that leads out the wires. The TL semiconductor element 30 bonds the wires to the interconnect substrate 104 after bonding the wires to the semiconductor element 30.

[0406] That is, as shown by the dashed line in FIG. 84 , first, the bonding tool TL positions the nozzle TLa over the pad 33, and leads out the wire to bond it. Then, the nozzle TLa is moved in the direction of the arrow TL1 toward the relay board 104. This movement direction is linear when viewed in the Z direction. When forming the bonding wire 10G, the nozzle TLa moves in the direction of the straight line connecting the pad 33G and the pad 1G. When forming the bonding wire 10KS, the nozzle TLa moves in the direction of the straight line connecting the Kelvin source pad 33KS and the pad 1KS.

[0407] The bonding tool TL then positions the nozzle TLa over the pads 1G and 1KS, leading out the wire for bonding. Then, to cut the wire, the nozzle TLa is further moved in the direction of the arrow TL2 (see the two-dot chain line). The direction of the arrow TL2 coincides with the direction of the arrow TL1 when viewed in the Z direction.

[0408] In the Z direction, the height of the capacitor 71 is higher than the height of the resistor 72. Furthermore, the upper end position of the capacitor 71 in the Z direction is located higher than the nozzle TLa position during cutting, as shown by the two-dot chain line. The upper end position of the capacitor 71 in the Z direction is located higher than the nozzle TLa position during bonding, as shown by the solid line. The upper end position of the resistor 72 in the Z direction is located lower than the nozzle TLa position during cutting, as shown by the two-dot chain line. The upper end position of the resistor 72 in the Z direction is located lower than the nozzle TLa position during bonding, as shown by the solid line. In the Z direction, the upper end position of the resistor 72 is set at a position lower than the surface positions of the pads 1G and 1KS.

[0409] The dashed line in Fig. 83 indicates an extension line 33ex along which the bonding wire 10KS extends on a projection plane perpendicular to the Z direction. The passive component 103 is disposed at a position off the extension line 33ex. In other words, the extension line 33ex corresponds to an extension line of the movement locus of the nozzle TLa along the arrows TL1 and TL2 in Fig. 84.

[0410] Summary of the Ninth Embodiment According to this embodiment, the resistor 72 of the snubber circuit 70 is arranged closer to the center 40c of the substrate 40 than the passive components 103. In general, the height of the resistor 72 in the Z direction is lower than the passive components 103. Therefore, in a layout in which the relay substrate 104 is arranged between the snubber circuit 70 and the semiconductor element 30, it is possible to easily avoid interference of the nozzle TLa with the passive components 103 when forming the bonding wires 10G and 10KS.

[0411] Furthermore, the area of ​​the substrate 40 occupied by the six resistors 72 is shorter in the Y direction than the area occupied by the four capacitors 71. Therefore, according to this embodiment in which the resistors 72 are arranged closer to the center 40c than the passive components 103, a larger area can be secured in the Y direction for the portion of the N wiring 422 that is joined to the N terminal 612, as shown in Fig. 83. This allows the limited area of ​​the substrate 40 to be used effectively.

[0412] Furthermore, in this embodiment, the height position of the resistor 72 is set lower in the Z direction than the surface positions of the pads 1G and 1KS. This makes it easier to avoid the nozzle TLa interfering with the resistor 72 when moving the nozzle TLa from the solid line position to the two-dot chain line position in Figure 84. In other words, it is possible to realize a layout design for the relay board 104 in which interference between the nozzle TLa and the resistor 72 does not need to be taken into consideration.

[0413] Furthermore, in this embodiment, the passive component 103 is disposed at a position that is off the extension line 33ex of the bonding wire 10KS connected to the pad 1KS on the projection plane perpendicular to the Z direction. This makes it easier to avoid the nozzle TLa from interfering with the passive component 103 when moving the nozzle TLa from the solid line position to the two-dot chain line position in FIG.

[0414] Tenth Embodiment This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0415] In the semiconductor device 21 according to this embodiment, as shown in FIG. 85 , a first current loop IR1 and a second current loop IR2 are formed. When current is applied to the main terminal 61 to energize the main circuit, a magnetic field is generated. In the first current loop IR1 and the second current loop IR2, a potential is generated in a direction that opposes the change in the magnetic field. The first current loop IR1 is shown as a path indicated by a dotted line in FIG. 85 , and the dotted arrow indicates the direction of the current that opposes the magnetic field generated by the main circuit current. The second current loop IR2 is shown as a path indicated by a solid line in FIG. 85 , and the solid arrow indicates the direction of the current that opposes the magnetic field generated by the main circuit current. In the example shown in FIG. 85 , one first current loop IR1 and multiple second current loops IR2 are formed. The number of second current loops IR2 is the same as the number of semiconductor elements 30. Note that passive components 103 and wire bonding are not shown in FIG. 85 .

[0416] The current path of the first current loop IR1 is formed to include at least the Kelvin source terminal 62KS (potential detection terminal), the plurality of relay boards 104, and the gate terminal 62G (drive command terminal). The current path of the second current loop IR2 is formed to include at least the gate pad 33G (drive command pad), the Kelvin source pad 33KS (potential detection pad), and the plurality of relay boards 104 (signal wiring).

[0417] In either the first current loop IR1 or the second current loop IR2, a current flows in a direction that removes charge from the gate pad 33G. In the other of the first current loop IR1 or the second current loop IR2, a current flows in a direction that injects charge into the gate pad 33G. In other words, when viewed in the Z direction, a current flows clockwise in either the current loop IR1 or the second current loop IR2, and counterclockwise in the other. The gate terminal 62G, the Kelvin source terminal 62KS, the gate pad 33G, the Kelvin source pad 33KS, and the like are arranged so that the current directions are opposite to each other.

[0418] When viewed in the Z direction, the first current loop IR1 and the second current loop IR2 intersect with each other at an intersection IRp. The number of intersections IRp appearing in one second current loop IR2 is odd, and in the example of FIG. 85, the number of intersections IRp is one.

[0419] Summary of the Tenth Embodiment According to this embodiment, a first current loop IR1 and a second current loop IR2 are formed on a plane perpendicular to the Z direction, and the currents flowing in the first current loop IR1 and the second current loop IR2 have different directions that interfere with the magnetic field generated by the main circuit current. Therefore, the direction of the current generated in the first current loop IR1 is opposite to the direction of the current generated in the second current loop IR2. Therefore, the currents cancel each other out. This allows for stable on / off operation of the multiple semiconductor elements 30 connected in parallel with each other using gate signals.

[0420] (Other Embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0421] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0422] When an element or layer is referred to as being "on," "coupled," "connected," or "coupled," it may be directly on, coupled, connected, or coupled to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly coupled" to another element or layer, there are no intervening elements or layers present. Other language used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0423] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may also be oriented in other ways (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0424] The vehicle drive system 1 is not limited to the above-described configuration. For example, although an example has been shown in which one motor generator 3 is provided, this is not limiting. Multiple motor generators may be provided. Although an example has been shown in which the power conversion device 4 is provided with an inverter 6 as a power conversion unit, this is not limiting. For example, a configuration may be provided with multiple inverters. A configuration may be provided with at least one inverter and a converter. Or only a converter may be provided.

[0425] (Disclosure of Technical Ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be described in a multiple dependent form, with the subsequent clause alternatively referring to the preceding clause. Furthermore, some clauses may be described in a multiple dependent form, with the subsequent clause referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0426] <Technical Idea 1> A semiconductor device constituting a power conversion circuit (6), comprising: a first main terminal (611); a second main terminal (612); a signal terminal (62); an insulating base (41); a substrate (40) having a first wiring (421) arranged on one surface of the insulating base and electrically connected to the first main terminal; and a second wiring (422) arranged on the one surface and electrically connected to the second main terminal; a semiconductor element (30, 30H) electrically connected to the first wiring; and a snubber circuit (70) including a capacitor (71) and electrically bridging the first wiring and the second wiring, wherein the substrate has a signal wiring (425) arranged between the semiconductor element and the snubber circuit and electrically relaying the signal terminal and the semiconductor element.

[0427] <Technical Idea 2> The semiconductor device according to Technical Idea 1, further comprising: a second element (30L) connected in series to the first element, which is the semiconductor element, and providing an upper and lower arm circuit (9) together with the first element; one of the first main terminal and the second main terminal is a positive terminal, and the other is a negative terminal; the second element is electrically connected to the second wiring; and the snubber circuit is connected in parallel to the upper and lower arm circuits.

[0428] <Technical Idea 3> The semiconductor device according to Technical Idea 2, wherein the snubber circuit includes a plurality of the capacitors, and includes a plurality of current paths including the first main terminal, the first wiring, the capacitors, the second wiring, and the second main terminal, and the impedances of the plurality of current paths are equal to each other.

[0429] <Technical Concept 4> The semiconductor device according to Technical Concept 3, wherein the plurality of current-carrying paths are arranged in line symmetry.

[0430] <Technical Idea 5> A semiconductor device according to Technical Idea 4, comprising one first main terminal and two second main terminals arranged side by side with the first main terminal in a first direction perpendicular to the thickness direction of the substrate, the two second main terminals arranged so as to sandwich the first main terminal in the first direction, the first element and the second element arranged side by side in a second direction perpendicular to the thickness direction and the first direction, and the second wiring arranged so as to sandwich the first wiring in the first direction.

[0431] <Technical Idea 6> The semiconductor device according to any one of Technical Ideas 1 to 5, wherein the capacitance is set so as to satisfy C / Ldc>0.004, where C is the capacitance of the capacitor and Ldc is the parasitic inductance of a main circuit portion connecting the snubber circuit and the smoothing capacitor.

[0432] <Technical Concept 7> The semiconductor device according to any one of Technical Concepts 1 to 6, wherein the capacitor is connected to at least one of the first wiring and the second wiring.

[0433] <Technical Concept 8> The semiconductor device according to any one of Technical Concepts 1 to 7, further comprising a thermally conductive member (44, 74, 75) that thermally connects the capacitor to a portion of the substrate other than the joint with the capacitor.

[0434] (Technical Idea 9) A semiconductor device according to any one of Technical Ideas 1 to 8, wherein the semiconductor elements are arranged in a line in a predetermined direction and each have a main electrode (31, 32) and a drive command pad (33G) that commands the flow of current to the main electrode, and the semiconductor elements are arranged in an orientation such that the drive command pad is located on the signal wiring side of the main electrode.

[0435] (Technical Idea 10) A semiconductor device according to any one of Technical Ideas 1 to 9, comprising: an upper arm element (30H) providing an upper arm (9H) of an upper and lower arm circuit; a lower arm element (30L) providing a lower arm (9L) of the upper and lower arm circuit; an upper arm metal plate (50H) joined to a main electrode of the upper arm element; and a lower arm metal plate (50L) joined to a main electrode of the lower arm element, wherein the semiconductor element is either the upper arm element or the lower arm element, wherein the upper arm metal plate and the lower arm metal plate each have adjacent portions (533p) adjacent to each other, and wherein the direction of current flowing through the adjacent portion of the upper arm metal plate is opposite to the direction of current flowing through the adjacent portion of the lower arm metal plate.

[0436] (Technical Idea 11) A semiconductor device according to any one of Technical Ideas 1 to 10, comprising: an interconnection substrate (104) on which passive components (103) for suppressing parasitic oscillation are mounted; and interconnection wiring (80G) for electrically connecting a plurality of the interconnection substrates, wherein the signal wiring includes a plurality of the interconnection substrates and the interconnection wiring.

[0437] (Technical Idea 12) The semiconductor device according to any one of Technical Ideas 1 to 11, wherein the snubber circuit includes a resistor (72) connected in series with the capacitor, and the resistor is arranged closer to the center of the substrate than the capacitor.

[0438] (Technical Idea 13) A semiconductor device according to Technical Idea 12, comprising an interconnection substrate (104) that provides the signal wiring, wherein the interconnection substrate is mounted with passive components (103) that suppress parasitic oscillation and pads (G1, KS1) that are connected to the semiconductor element by wires, and wherein the height position of the resistor is set lower than the surface position of the pad in the thickness direction of the substrate.

[0439] (Technical Idea 14) A semiconductor device according to any one of Technical Ideas 1 to 13, comprising an interposer (104) that provides the signal wiring, wherein the interposer is mounted with passive components (103) that suppress parasitic oscillation and pads (G1, KS1) that are connected to the semiconductor element by wires, and the passive components are arranged in a projection plane perpendicular to the thickness direction of the substrate at a position that is off the extension line of the wires connected to the pads.

[0440] (Technical Idea 15) The semiconductor element has main electrodes (31, 32), a drive command pad (33G) that commands the flow of current to the main electrodes, and a potential detection pad (33KS) that outputs a signal for detecting the potential of the main electrodes, and the signal terminals include a drive command terminal (62G) electrically connected to the drive command pad via the signal wiring, and a potential detection terminal (62KS) electrically connected to the potential detection pad via the signal wiring, and a first current loop (IR1) is formed by the drive command terminal, the signal wiring, and the potential detection terminal, and a second current loop (IR2) is formed by the drive command pad, the potential detection pad, and the signal wiring, and in either the first current loop or the second current loop, a current flows in a direction that draws charge from the drive command pad with respect to a magnetic field generated by the main circuit current flow, A semiconductor device described in any one of technical ideas 1 to 14, wherein the other of the first current loop and the second current loop flows current in a direction that injects charge into the drive command pad relative to the magnetic field caused by the main circuit current flow.

Claims

1. A semiconductor device constituting a power conversion circuit (6), comprising: a substrate (40) having a first main terminal (611), a second main terminal (612), a signal terminal (62), an insulating base material (41), a first wiring (421) arranged on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring (422) arranged on the one surface and electrically connected to the second main terminal, a semiconductor element (30, 30H) electrically connected to the first wiring, and a snubber circuit (70) including a capacitor (71) and electrically bridging the first wiring and the second wiring, wherein the substrate has a signal wiring (425) arranged between the semiconductor element and the snubber circuit and electrically relaying the signal terminal and the semiconductor element.

2. The semiconductor device according to claim 1, further comprising a second element (30L) connected in series to the first element which is a semiconductor element and providing an upper and lower arm circuit (9) together with the first element, one of the first main terminal and the second main terminal being a positive terminal and the other being a negative terminal, the second element being electrically connected to the second wiring, and the snubber circuit being connected in parallel to the upper and lower arm circuits.

3. The semiconductor device according to claim 2, wherein the snubber circuit includes a plurality of the capacitors, and has a plurality of current paths including the first main terminal, the first wiring, the capacitors, the second wiring, and the second main terminal, and the impedances of the respective current paths are equal to each other.

4. The semiconductor device according to claim 3, wherein the plurality of current paths are arranged in line symmetry.

5. The semiconductor device described in claim 4, comprising one first main terminal and two second main terminals arranged side by side with the first main terminal in a first direction perpendicular to the thickness direction of the substrate, the two second main terminals arranged so as to sandwich the first main terminal in the first direction, the first element and the second element arranged side by side in a second direction perpendicular to the thickness direction and the first direction, and the second wiring arranged so as to sandwich the first wiring in the first direction.

6. A semiconductor device according to any one of claims 1 to 5, wherein the capacitance of the capacitor is set so as to satisfy C / Ldc>0.004, where C is the capacitance of the capacitor and Ldc is the parasitic inductance of a main circuit portion connecting the snubber circuit and the smoothing capacitor.

7. The semiconductor device according to claim 1, wherein the capacitor is joined to at least one of the first wiring and the second wiring.

8. The semiconductor device according to claim 7, further comprising a thermally conductive member (44, 74, 75) that thermally connects said capacitor to a portion of said substrate other than the portion where said capacitor is joined.

9. A semiconductor device as claimed in any one of claims 1 to 5, wherein the semiconductor elements are arranged in a row in a predetermined direction and have main electrodes (31, 32) and drive command pads (33G) that command the flow of electricity to the main electrodes, and the semiconductor elements are arranged in an orientation such that the drive command pad is located on the signal wiring side of the main electrodes.

10. A semiconductor device as claimed in any one of claims 1 to 5, comprising: an upper arm element (30H) providing an upper arm (9H) of an upper and lower arm circuit; a lower arm element (30L) providing a lower arm (9L) of the upper and lower arm circuit; an upper arm metal plate material (50H) joined to a main electrode of the upper arm element; and a lower arm metal plate material (50L) joined to a main electrode of the lower arm element, wherein the semiconductor element is either the upper arm element or the lower arm element, each of the upper arm metal plate material and the lower arm metal plate material having adjacent portions (533p) adjacent to each other, and a direction of current flowing through the adjacent portion of the upper arm metal plate material is opposite to a direction of current flowing through the adjacent portion of the lower arm metal plate material.

11. A semiconductor device according to any one of claims 1 to 5, comprising: an intermediate substrate (104) on which passive components (103) for suppressing parasitic oscillation are mounted; and interconnection wiring (80G) for electrically connecting a plurality of the intermediate substrates, wherein the signal wiring includes a plurality of the intermediate substrates and the interconnection wiring.

12. A semiconductor device according to any one of claims 1 to 5, wherein the snubber circuit includes a resistor (72) connected in series with the capacitor, the resistor being positioned closer to the center of the substrate than the capacitor.

13. The semiconductor device according to claim 12, further comprising an intermediate substrate (104) that provides the signal wiring, the intermediate substrate having mounted thereon passive components (103) that suppress parasitic oscillation and pads (G1, KS1) that are connected to the semiconductor element by wires, and the height position of the resistor in the thickness direction of the substrate is set lower than the surface position of the pad.

14. A semiconductor device as claimed in any one of claims 1 to 5, further comprising an intermediate substrate (104) that provides the signal wiring, wherein the intermediate substrate is mounted with passive components (103) that suppress parasitic oscillation and pads (G1, KS1) that are connected to the semiconductor element by wires, and wherein the passive components are disposed in a projection plane perpendicular to the thickness direction of the substrate, at a position that is off the extension line of the wires connected to the pads.

15. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor element has main electrodes (31, 32), a drive command pad (33G) that commands the flow of current to the main electrodes, and a potential detection pad (33KS) that outputs a signal to detect the potential of the main electrodes, and the signal terminals include a drive command terminal (62G) electrically connected to the drive command pad via the signal wiring, and a potential detection terminal (62KS) electrically connected to the potential detection pad via the signal wiring, a first current loop (IR1) is formed by the drive command terminal, the signal wiring, and the potential detection terminal, and a second current loop (IR2) is formed by the drive command pad, the potential detection pad, and the signal wiring, and in one of the first current loop and the second current loop, a current flows in a direction that extracts charge from the drive command pad with respect to a magnetic field generated by main circuit current flow, and in the other of the first current loop and the second current loop, a current flows in a direction that injects charge into the drive command pad with respect to the magnetic field generated by main circuit current flow.

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