System and method for basic block vector system-on-chip performance optimization

Abstract

According to one aspect of the present disclosure, a system-on-chip (SoC) is provided. The SoC may identify a first set of instructions associated with parallel processing by a plurality of computational units. The SoC may input the first set of instructions associated with the parallel processing by the plurality of computational units into a Gaussian mixture model (GMM). The SoC may identify a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM. The second set of instructions may include a subset of the first set of instructions.

Description

SYSTEM AND METHOD FOR BASIC BLOCK VECTOR SYSTEM-ON- CHIP PERFORMANCE OPTIMIZATIONBACKGROUND

[0001] Embodiments of the present disclosure relate to a system and method of data processing.

[0002] Smart phones, wearable devices, and smart surveillance are hotspots in today’s market. Due to the rapid increase in the amount of data generated by terminal devices, and in order to achieve rapid response and parallel big data processing in the cloud, manufacturers are turning their attention to parallel processing by various computational components in a system-on-chip (SoC).SUMMARY

[0003] According to one aspect of the present disclosure, a system-on-chip (SoC) is provided. The SoC may include at least one processor. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to identify a first set of instructions associated with parallel processing by a plurality of computational units. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to input the first set of instructions associated with the parallel processing by the plurality of computational units into a Gaussian mixture model (GMM). The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to identify a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM. The second set of instructions may include a subset of the first set of instructions.

[0004] According to another aspect of the present disclosure, an apparatus for parallel processing is provided. The apparatus may include an SoC. The SoC may include at least one processor. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to identify a first set of instructions associated with parallel processing by a plurality of computational units. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to input the first set of instructions associated with the parallel processing by the plurality of computational units into a GMM. The SoC may include memory storing instructions, which whenexecuted by the at least one processor, cause the at least one processor to identify a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM. The second set of instructions may include a subset of the first set of instructions.

[0005] According to a further aspect of the present disclosure, a method of parallel processing by an SoC is provided. The method may include identifying, by at least one processor, a first set of instructions associated with parallel processing by a plurality of computational units. The method may include inputting, by the at least one processor, the first set of instructions associated with the parallel processing by the plurality of computational units into a GMM. The method may include identifying, by the at least one processor, a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM. The second set of instructions may include a subset of the first set of instructions.

[0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 illustrates a block diagram of an exemplary system-on-chip (SoC), according to some embodiments of the present disclosure.

[0009] FIG. 2A illustrates an exemplary diagram of a basic block made up of a sequence of statements, according to some embodiments of the present disclosure.

[0010] FIG. 2B illustrates an exemplary diagram of the basic block of FIG. 2A, according to some embodiments of the present disclosure.

[0011] FIG. 3A illustrates an exemplary source code, according to some embodiments of the present disclosure.

[0012] FIG. 3B illustrates an exemplary three-address code for the source code of FIG. 3 A, according to some embodiments of the present disclosure.

[0013] FIG. 4 illustrates an exemplary flow diagram for a program, according to some embodiments of the present disclosure.

[0014] FIG. 5 illustrates a diagram of an exemplary parallel processing sample point technique, according to some embodiments of the present disclosure.

[0015] FIG. 6 illustrates a diagram of exemplary basic block vector (BBV) combinations for parallel processing by an SoC, according to some embodiments of the present disclosure.

[0016] FIG. 7 illustrates a flowchart of a first exemplary method of SoC performance evaluation for parallel processing, according to some embodiments of the present disclosure.

[0017] FIG. 8 illustrates a diagram of exemplary BBV combinations for parallel processing by an SoC, according to some embodiments of the present disclosure.

[0018] FIG. 9 illustrates a graphical representation of the exemplary performance feature capture, evaluation, and validation achieved using an exemplary parallel processing technique of an SoC, according to some embodiments of the present disclosure.

[0019] FIG. 10 illustrates a flowchart of a second exemplary method of SoC performance evaluation for parallel processing, according to some embodiments of the present disclosure.

[0020] FIG. 11 illustrates a wireless network, according to certain embodiments of the present disclosure.

[0021] FIG. 12 illustrates a block diagram of a node, according to certain embodiments of the present disclosure.DETAILED DESCRIPTION

[0022] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0023] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that one or more embodiments described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitlydescribed.

[0024] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the terms “based on,” “based upon,” and terms with similar meaning may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0025] Various aspects of the present disclosure will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0026] In addition, various aspects of the exemplary parallel processing performance evaluation technique(s) of the present disclosure may be described in connection with an SoC, one or more subsystems of the SoC, one or more pipelines of the subsystem, or a set of functional blocks (also referred to herein as “computational units”) associated with the pipeline. It is understood that the exemplary power management technique described below may be applied at the functional block level, pipeline level, or subsystem level to other types of circuits, computing devices and / or electronic devices, other than an SoC, without departing from the scope of the present disclosure.

[0027] A SoC is an integrated circuit that integrates subsystems, each having a different function, in a computing system or other electronic device. The subsystems integrated by an SoC may include, without limitation, one or more of the following: central processing units (CPUs), graphics processing units (GPUs), microcontrollers, microprocessors, multiprocessors, digital signal processor (DSP) cores, other types of cores, a memory unit, read-only memory7(ROM), random-access memory (RAM), clock signal generators, input / output (I / O) interfaces, analoginterfaces, voltage regulators and power management circuits, an advanced peripheral unit(s), wireless communication unit(s) (e.g., Wi-Fi module, cellular module, 5G new radio (NR) module, Bluetooth® module, etc ), or coprocessors, just to name a few.

[0028] Building more powerful system-on-chips (SoCs) requires an intense and expensive production process. Some computational problems take years to solve, even with the benefit of a more powerful microprocessor. Partly because of these factors, computer scientists sometimes use a different approach, e.g., namely, parallel processing.

[0029] In general, parallel processing means that at least two computational units (e.g., central processing unit (CPU), graphics processing unit (GPU), DSP, etc.) of the SoC handle parts of an overall task. The concept is pretty simple: a program designer divides a complex problem into basic blocks using special software specifically designed for the task. Each basic block may then be assigned a dedicated computational unit. Each computational unit solves its part of the overall computational problem. The software reassembles the data to reach the end conclusion of the original complex problem. To identify which basic block of a program is performed by which computational unit, various techniques have been proposed to evaluate SoC performance. These techniques include, e.g., structure-preserving transformations, common subexpression elimination, dead-code elimination, re-naming temporary variables, interchange-of-statements, and algebraic transformations, just to name a few.

[0030] Each of the above-mentioned SoC performance evaluation techniques has various drawbacks. Using structure-preserving transformations, the basic block can be transformed by substituting the same expressions in the assemble code. However, the same expressions need to be predicted, and there is no interrupt handling. Using dead-code elimination, the basic block is transformed by removing the “dead” expressions in the assemble code. However, using this technique, dead expressions must be searched, and here, again, there is no interrupt handling. In the re-naming temporary variables method, the basic block is transformed by renaming the temporary expressions in the assemble code. However, here, the temporary expressions must be located, and there is no interrupt handling. Using interchange-of-statements, the basic block can be transformed by interchanging two statements without affecting the value of the block in the assemble code. However, the interchangeable expressions need to be located, and there is no interrupt handling. Algebraic transformations use algebraic computing to obtain a basic block with an algebraically equivalent set. Unfortunately, this technique requires power and time-consuming algebraic transformations, and interrupt handling is unavailable.

[0031] To overcome these and other challenges, the present disclosure provides an exemplary SoC load characteristic modeling and evaluation technique for parallel processing. The exemplary SoC load characteristic modeling and evaluation technique described below captures the basic blocks from the parallel assembly code of the overall system architecture. The main point is to provide a heterogeneous computing framework clustered with a plurality of computational components (e.g., CPU, a GPU, and a DSP), which combine the multi-function processing of the CPU, the highly parallel computing of the GPU, and the data of the DSP. Combining processing capabilities to improve data calculation speed and data processing capabilities. The code for parallel processing of all computational units in the heterogeneous architecture is input into a Gaussian mixture model (GMM), which is used to identify the most basic and representative code as the judgment of the overall SoC load characteristics. The exemplary SoC load characteristic modeling and evaluation technique incorporates physical power characteristics into the GMM design, which enables the design feature values to be obtained in the early programming stage. This increases processing speed, while limiting power consumption to a minimum.

[0032] The exemplary SoC load characteristic modeling and evaluation technique for parallel processing may include the following operations. For example, the technique described herein may estimate the power consumption sum of the CPU, GPU, DSP, and other components of large matrix multiplication by using a pre-detection program. To that end the present technique may determine the power unit of a processing element by combining the basic blocks of each component (e.g., CPU, GPU, DSP, memory, microcontroller (MCU), etc.) of the PE involved in the calculation. Then, a GMM may be used to cluster all different BBV combinations. Find the weight of each category may be determined, and code cloning may be performed. The binary code may be extracted as a benchmark for performance and energy efficiency. The estimated execution time is the total workload divided by the calculation speed that the PE processing unit can support. The estimated energy consumption is the steady-state power multiplied by the execution time. Additional details of the exemplary SoC load characteristics modeling and evaluation technique are provided below in connection with FIGs. 1-12.

[0033] FIG. 1 illustrates a system 100 including an exemplary system-on-chip (SoC) 102, according to some embodiments of the present disclosure. System 100 can include any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such asany member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (loT) node. As shown in FIG. 1, SoC 102 may include a first central processing unit (CPU) 104a, a second CPU 104b, a graphics processing unit (GPU) 106, a system link 108 (e.g., a system bus), memory controllers 110, a display and video subsystem 112, a main memory 114, and peripheral devices that include a DSP 116, among others. The computational units (e.g., CPUs 104a, 104b, GPU 106, DSP 116, etc.) of SoC 102 may form a heterogeneous architecture in which the computational units use more than one instruction set, all of which share a single memory. Using this architecture, programs may be written differently for each of the dissimilar instruction sets.

[0034] Still referring to FIG. 1, SoC 102 achieves above-mentioned technical solutions using a heterogeneous computing framework based on first CPU 104a and / or second CPU 104b, GPU 106, and DSP 116, application processor (AP) / host, and a device-side computational component. The AP / host may include one or more of, e.g., first CPU 104a, second CPU 104b, GPU 106, DSP 116, and main memory 114 (e.g., a dynamic random access memory (DRAM)). First CPU 104a and second CPU 104b may be responsible for performing operating system and system software operations. At the same time, first CPU 104a and / or second CPU 104b, may perform general processing and simple calculation tasks with complex instruction scheduling, looping, branching, logical judgment, and general application programs, and data exchange and storage with main memory 114.

[0035] DSP 116 may include a storage unit, a control unit, and an arithmetic unit. The control unit may issue an instruction to the storage unit to read data from the DSP memory and store it in, e.g., main memory 114. At the same time, the control unit issues an instruction to the arithmetic unit to make the arithmetic unit read data from the DSP storage unit and perform operations. After the arithmetic unit completes the operation, it may send an operation completion signal to the control unit. After receiving the operation completion signal, the control unit issues an instruction to the DSP storage unit to receive the data returned by the operation unit. The deviceside includes, e.g., main memory 114 and GPU 106. GPU 168 may include multiple processing cores. GPU 106 may be used for highly parallel computing and processing of large-scale non- logical relational data.

[0036] As mentioned above, first CPU 104a and / or second CPU 104b may support the operating system. The operating system with first CPU 104a and / or second CPU 104b as the core facilitates human-computer interaction and communication with standard interface devices, whichis very convenient for viewing. No hardware development is required, but the peripheral interface circuit of first CPU 104a and second CPU 104b is complicated. On the other hand, DSP 116 may be used in embedded signal processing systems, does not emphasize human-computer interaction, and generally does not require many communication interfaces. The structure of DSP 116 may be simple and easy to develop, so the respective advantages and disadvantages of first CPU 104a, second CPU 104b, GPU 106, and DSP 116 make up for each other. This enables the full utilization of the respective strengths of these computational units, while concealing their weaknesses are concealed. For example, DSP 116 is a branch of the development direction of first CPU 104a and / or second CPU 104b. DSP 116 is programmable, and its real-time running speed can reach tens of millions of complex instruction programs per second, which exceeds general -purpose CPUs. Moreover, DSP 116 has strong computing power, fast speed, and a small size. Using software programming has high flexibility. Thus, combining DSP 116 with first CPU 104a and / or second CPU 104b for parallel processing can effectively share the data calculation load of first CPU 104a and / or second CPU 104b, while at the same time increasing the speed of calculation.

[0037] Further, DSP 116 and main memory 114 are connected by a data bus and an address bus (e.g., part of system link 108). DSP 116 separates the data bus from the address bus, so that the program and data are stored in two separate spaces. This allows the fetching and execution of instructions to completely overlap. Furthermore, host / AP and the device-side components are connected by a high-speed serial bus (e.g., part of system link 108). The high-speed serial bus has the advantages of convenient use, fast speed, flexible connection, and independent power supply. Further, the multiprocessor in GPU 106 includes registers and shared memory, and AP / host may include at least one DSP or other computation units. Compared with existing SoCs, SoC has the following advantages and beneficial effects: 1) it combines the multifunctional processing of first CPU 102a and / or second CPU 102b, the highly parallel computing of GPU 106, and the data processing capability of DSP 116, 2) it shares the data processing burden of first CPU 104a and / or second CPU 104b, 3) it improves the speed of data calculation and data processing, and 4) it reduces power consumption.

[0038] For end-to-end simulation of SoC workloads, including workloads with acceleration functions handled by fixed-function hardware blocks, a designer can study the complex behaviors and interactions between general -purpose CPUs and hardware accelerators, e.g., such as cache consistency and memory consistency in heterogeneous platforms, data movement, and communication, shared resource contention, and how all these have system-level effects willaffect overall application performance and acceleration.

[0039] Sharing the CPU workload(s) between first CPU 104a, second CPU 104a, GPU 106, and DSP 116 is a form of parallel processing. As previously mentioned, parallel processing means that at least two computational units (e.g., first CPU 104a, second CPU 104b, GPU 106, DSP 116etc.) of the SoC 102 handle parts of an overall CPU task. For example, a complex CPU problem may be divided into basic blocks using special software specifically designed for the task. Each basic block may then be assigned a dedicated computational unit. Each computational unit solves its part of the overall computational problem. The software reassembles the data to reach the end conclusion of the original complex problem. To identify which basic block of a program is performed by which computational unit, various techniques have been proposed to evaluate the performance of SoC 102. Examples of basic blocks are depicted in FIGs. 2A and 2B.

[0040] FIG. 2A illustrates an exemplary diagram of a basic block 200 made up of a sequence of statements, according to some embodiments of the present disclosure. FIG. 2B illustrates an exemplary diagram 250 of the basic block of FIG. 2A, according to some embodiments of the present disclosure. FIG. 3A illustrates an exemplary source code 300 of basic block 200 of FIG. 2A, according to some embodiments of the present disclosure. FIG. 3B illustrates an exemplary three-address code 350 for the source code of FIG. 3 A, according to some embodiments of the present disclosure. FIGs. 2A, 2B, 3 A, and 3B will be described together.

[0041] Referring to FIGs. 2A and 2B, basic block 200 is a linear code segment with an entry point and an exit point. For instance, basic block 200 may be a sequence of consecutive statements in which the flow of control enters at the beginning and leaves at the end without any halt or possibility of branching except at the end. The sequence of three-address statements illustrated in FIG. 2A forms basic block 200. A basic block vector (BBV) is a list of all basic blocks entered during program execution and a count of the number of times each basic block has been run. BBV is a tool that generates basic block vectors for use with simulation analysis tools, e.g., as a simulation point (SimPoint). The SimPoint approach may speed up architecture simulations by running only a small part of the program and then inferring the overall behaviour from this small part. As indicated by its name, the BBV is a vector. Each dimension of this vector represents the number of times the program enters the basic block while it is running. BBV represents the characteristics of fragments. For example, if a fragment always calls a function, then the dimension value corresponding to the first basic block of this function will be relatively large. If a branch always jumps, then the value of the basic block that always jumps will be greater.If two fragments have similar values on the same branch or function call, their execution paths will be similar, and intuitively, their behaviour will be similar. The one-dimensional similarity is extended to the multi-dimensional similarity. That is, the Euclidean distance is close. Therefore, SimPoint uses k-means as a clustering algorithm to cluster BBV and find “representative” segments.

[0042] Still referring to FIGs. 2A and 2B, most programs exhibit stage-based behaviour. This means that at different times during execution, the program will encounter time intervals where the code behaviour is similar to the previous time interval. If these intervals can be identified and combined, an approximation of the overall program behaviour may be identified by simulating only the minimum number of intervals and then scaling the result. In computer architecture research, running a benchmark test on a cycle-accurate simulator may result in a 1,000-time slowdown, which may require days, weeks, or even longer to run a complete benchmark test. By using SimPoint, this can be reduced significantly, e.g., usually by 90-95%, while still maintaining reasonable accuracy.

[0043] Referring to FIG. 3 A, the algorithm for identifying basic blocks is shown. The input to the algorithm may include a sequence of three-address statements. The algorithm’s output may include a lot of basic blocks with each of the three-address statement in exactly one block, d’hen the algorithm may determine the set of leaders, the first statements of basic blocks. The rules applied by the algorithm include the following: 1 ) the first statement is a leader, 2) any statement that is the target of a conditional or unconditional goto is a leader, and 3) any statement that immediately follows a goto or conditional goto statement is a leader. For each leader, its basic block is made up of the leader and all statements up to but not including the next leader or the end of the program. The source program code depicted in FIG. 3 A is for a dot product of two vectors, and the three-address code for the source program code of FIG. 3A is depicted in FIG. 3B. Referring to FIG. 3B, a first basic block includes statements (1) to (2), and a second basic block includes statements (3) to (12).

[0044] FIG. 4 illustrates an exemplary flow graph 400 for a program, according to some embodiments of the present disclosure. Flow graph 400 is a directed graph containing the flow- of-control information for the set of basic blocks making up a program. Flow graph 400 depicts a program for a vector dot product. The nodes of the flow graph are basic blocks, and it has a distinguished initial node.

[0045] Basic block 1 is the initial node. Basic block 2 immediately follows basic block 1,so there is an edge from basic block 1 to basic block 2. The target jumps from the last statement of Bl is the first statement B2, so there is an edge from basic block 1 (e.g., last statement) to basic block 2 (e.g., first statement). A loop is a collection of nodes in flow graph 400 such that all nodes in the collection are strongly connected. The collection of nodes has a unique entry. A loop that contains no other loops is called an inner loop. For example, basic block 1 is the predecessor of basic block 2, and basic block 2 is a successor of basic block 1.

[0046] FIG. 5 illustrates a diagram 500 of an exemplary parallel processing sample point technique, according to some embodiments of the present disclosure. The parallel processing sample point technique depicted in FIG. 1 may be implemented using an exemplary synchronous parallel computing model, e.g., such as a bulk synchronous parallel (BSP) model.

[0047] The synchronous parallel computing model mainly has the following characteristics. The model takes into account the concept of a super step. Each super step represents a complete parallel calculation process in the BSP model. The entire calculation process includes several serial super steps. A super step includes, e.g., a local calculation process, a communication process between computing nodes, and a synchronization process. The three stages in the super step are strictly serial. In other words, after the local calculations of all processors are completed, the communication process is carried out uniformly, and the synchronization stage is finally executed. In addition, each arithmetic unit can only transmit or receive data once in a super step. In the realization of this model, all computational units (e.g., CPU, GPU, DSP, etc.) are coordinated by a master node (e.g., a CPU) to complete the above three stages. BSP abandons the principle of program locality, thereby simplifying the design of the program and implementation. This is an ideal feature in parallel computing.

[0048] A selector may use point-to-point communication to route communications between computational units, thereby effectively avoiding congestion. The BSP model separates the computational units from the router. In other words, the exemplary technique separates the calculation task from the communication task. The router only completes point-to-point message transfer, and does not provide functions such as combining, copying, and broadcasting. This not only covers the specific topology of the Internet, but also simplifies the communication protocol. The global synchronization achieved by roadblock synchronization is implemented using a controllable coarse-grained level, thus providing an effective way to execute tightly integrated synchronous parallel algorithms.

[0049] FIG. 6 illustrates a diagram 600 of exemplary BBV combinations for parallelprocessing by an SoC, according to some embodiments of the present disclosure.

[0050] The clustering method is used for basic block classification. X-means is a popular clustering method. The general idea is to divide the data into multiple heaps, and each heap is a category. Each heap has a cluster center (the result of learning is to obtain these k cluster centers), this center is the mean value of all data in this class, and all points in this heap to the cluster center of this class are less than to the cluster centers of other classes (the process of classification is the process of comparing the unknown data to these k cluster centers, whoever is closest to it). The k- means principle is to group the most similar data together, and the definition of “like” is done by people, such as the smallest Euclidean distance, and so on.

[0051] To identify the exemplary BBV combinations for parallel processing and / or performance evaluation, the present technique uses a GMM, which introduces probability. There are two types of statistical learning models, one is a probabilistic model, and the other is a non- probabilistic model. The probability model P(Y|X), so that in the process of classification, identifies a probability distribution of the value of Y through the unknown data X. In other words, the output of the GMM after training is not a specific value, but a series of values. These values represent a probability. Corresponding to the classification problem, they are the probability corresponding to each different class. Then, the class with the highest probability can be selected as the decision object (e.g., soft assignment). Rather than a probabilistic model, it means that the learning model is a decision function Y=f(X), and the input data X can be projected to get only one Y, which is the judgment result (hard assignment).

[0052] Referring again to GMM, the learning process trains several probability distributions. The GMM refers to the estimation of the probability density distribution of the sample, and the estimated model is the weighted sum of several Gaussian models, which may be established prior to training. Each Gaussian model represents a class (also referred to as a “cluster”). The data in the sample may be projected onto several Gaussian models to obtain the probabilities for each class. Then, the class with the highest probability can be selected as the decision result.

[0053] After obtaining the probability, each combination of the “binary executable segment” will be used to make judgments and analyses on the weight of the software. From the perspective of the central limit theorem, it is reasonable to assume that the mixture model is Gaussian. Of course, it can also be defined as a Mixture Model of any distribution based on actual data. Finally, the probability distribution of each code combination can be modelled by the GMM.

[0054] Where K is the number of models, 7tk is the weight of the k-th Gaussian, which isthe probability density function of the k-th Gaussian, with the mean value of pk and the variance of ok. The estimation of this probability density requires various variables of 7tk, pk, and ok. After the expression is calculated, the result of each item of the summation formula respectively represents the probability that sample x belongs to each class.

[0055] When performing parameter estimation, the maximum likelihood method may be used. The maximum likelihood method maximizes the probability value of the sample point on the estimated probability density function. Since the probability value is generally very small, the result of this continuous multiplication is very small when N is large, which may easily cause floating-point numbers to underflow.

[0056] FIG. 7 illustrates a flowchart of a first exemplary method 700 (referred to hereinafter as “method 700”) of SoC performance evaluation, according to some embodiments of the present disclosure. Method 700 may be performed by an apparatus, e.g., SoC 102, first CPU 104a, second CPU 104b, GPU 106, DSP 116, etc. Method 700 may include operations 702-712 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 7. FIG. 8 illustrates a diagram of exemplary BBV combinations 800 for parallel processing by an SoC, according to some embodiments of the present disclosure. The exemplary BBV combinations 800 may be identified using method 700, for example. FIGs. 7 and 8 will be described together.

[0057] Referring to FIG. 7, at 702, the apparatus may obtain a combination of basic blocks. The basic blocks may be associated with a set of instructions that originate from one or more of a CPU, GPU, or DSP. At 704, the apparatus may normalize the combination of basic blocks. At 706, the apparatus may initialize a mean vector, covariance coefficient, and mixing coefficient for the GMM. At 706, the apparatus may determine whether the number of iterations of the output from the GMM meets a threshold number. If “Yes” at 706, the operations may move to 710; otherwise, if “No” at 706, the operations may move to 708, where the apparatus applies an expectation-maximization (EM) algorithm. From operation 708, the operations may return to 706. At 710, the apparatus may apply the maximum mixing coefficient to each sample (BBV combination) output from the GMM. At 712, the apparatus may output a weighted BBV combination 800, as depicted in FIG. 8. The weights may be used to indicate which BBV combination achieves the best performance in terms of processing time and power consumption. The power consumption information associated with one or more of the BBV combinations may be maintained at a power control unit (PCU) and / or power policy unit (PPU).

[0058] FIG. 9 illustrates a graphical representation 900 of the exemplary performance feature capture, evaluation, and validation achieved using an exemplary parallel processing technique of an SoC, according to some embodiments of the present disclosure.

[0059] Referring to FIG. 9, SoC workloads are executed on heterogeneous platforms including CPU, GPU, DSP, memory, and other components. The performance and energy efficiency of parallel cores depend on the parallel algorithm and execution environment. The code running on all modules expresses the characteristics of the overall load. The most likely occurrence of code running in parallel on all modules expresses the representativeness of these loads. This is a building block in a large-scale multi-processing system, which allows efficient implementation of CPU, GPU, DSP, microcontroller (MCU), system bus, and memory components. The load can be a computationally intensive task or a memory-intensive task.

[0060] For example, CPU and GPU, multi-core, and GPU provide a collaborative architecture, in which single instruction multiple data (SIMD) and single program multiple data (SPMD) programming models can coexist and complement each other. The kernel is started by the host CPU and has a specified number of basic blocks and threads. A basic block represents a specific number of threads, and all basic blocks in the kernel start have the same number of threads. The threads in the warp are executed in SIMD, and the warps in the basic block are executed concurrently in the SPMD. The power of a complementary metal-oxide-semiconductor (CMOS) chip can be theoretically estimated by expression (1).Power=Dynamic Power + Short Circuit Power + Leakage Power (1).

[0061] Referring to equation (1), Short Circuit Power is the power that expands momentarily and flows between the supply voltage and ground. Leakage Power is the power due to current leakage. Among the three terms on the righthand-side of equation (1), dynamic power can be identified by the capacitance switches / clock, the operating voltage, the clock frequency, and the chip’s temperature. In the SIMD computation, if a computational unit’s frequency and temperature are constant, its power only changes with the number of executions. Thus, the design of algorithms may impact the amount of power consumption for a given SIMD computing problem. Power dissipation of a compute unified device architecture (CUD A) program originates from each power-consuming component when the executable code runs on it. The power consumption of a CPU-GPU processing element (PE) includes the power of the CPU and GPU, as well as the power for memory operations and data transfers along different levels of memory hierarchy. The CUDAPE’s power can be modeled according to expression (2).where P, PCPIJ-. PDSP > PGPU-. PMCuan^ Pdevtces represent the power of the PE, CPU, DSP, GPU, MCU, and all components. N, M, Q, and H represent the total number of each of the above components, respectively.

[0062] FIG. 10 illustrates a flowchart of a second exemplary method 1000 (referred to hereinafter as “method 1000”) of SoC performance evaluation for parallel processing, according to some embodiments of the present disclosure. Method 1000 may be performed by an apparatus, e.g., SoC 102, first CPU 104a, second CPU 104b, GPU 106, DSP 116, etc. Method 1000 may include operations 1002-1006 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 10.

[0063] Referring to FIG. 10, at 1002, the apparatus may identify a first set of instructions associated with parallel processing by a plurality of computational units. The first set of instructions may include the combination of all basic blocks associated with the plurality of computational units (e.g., CPU(s), GPU(s), DSP(s), memory, MCU(s)).

[0064] At 704, the apparatus may input the first set of instructions associated with the parallel processing by the plurality of computational units into a GMM. For example, the combination of all basic blocks may be input into the GMM.

[0065] At 706, the apparatus may identify a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM. The second set of instructions may include the weighted combination of BBVs.

[0066] The hardware and software data processing technology disclosed herein, such as system 100 in FIG. 1 and methods 700, 1000 in FIGs. 7 and 10, may be implemented by any suitable computing device such as, e.g., a personal computer (PC), a laptop computer, a digital signal processor, a tablet device, a digital camera, a merchant terminal, a vehicle, or any suitable nodes in a wireless network, just to name a few. For example, FIG. 11 illustrates a wireless network 1100, in which certain aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0067] As shown in FIG. 11, wireless network 1100 may include a network of nodes, such as a user equipment (UE) 1102, an access node 1104, and a core network element 1106. User equipment 1102 may be any terminal device, such as a mobile phone, a desktop computer, a laptopcomputer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that user equipment 1102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0068] Access node 1104 may be a device that communicates with user equipment 1102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 1104 may have a wired connection to user equipment 1102, a wireless connection to user equipment 1102, or any combination thereof. Access node 1104 may be connected to user equipment 1102 by multiple connections, and user equipment 1102 may be connected to other access nodes in addition to access node 1104. Access node 1104 may also be connected to other UEs. It is understood that access node 1104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0069] Core network element 1106 may serve access node 1104 and user equipment 1102 to provide core network services. Examples of core network element 1106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the Long-Term Evolution (LTE) system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 1106 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the new radio (NR.) system. It is understood that core network element 1106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0070] Core network element 1106 may connect with a large network, such as the Internet 1108, or another internet protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 1102 may be communicated to other UEs connected to other access points, including, for example, a computer 1110 connected to Internet 1108, for example, using a wired connection or a wireless connection, or to a tablet 1112 wirelessly connected to Internet 1108 via a router 1114. Thus, computer 1110 and tablet 1112 provide additional examples of possible UEs, and router 1114 provides an example of another possible access node.

[0071] A generic example of a rack-mounted server is provided as an illustration of core network element 1106. However, there may be multiple elements in the core network including database servers, such as a database 1116, and security and authentication servers, such as an authentication server 1118. Database 1116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 1118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 1106, authentication server 1118, and database 1116, may be local connections within a single rack.

[0072] Each element in FIG. 11 may be considered a node of wireless network 1100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 1200 in FIG. 12. Node 1200 may be configured as user equipment 1102, access node 1104, or core network element 1106 in FIG. 11. Similarly, node 1200 may also be configured as computer 1110, router 1114, tablet 1112, database 1116, or authentication server 1118 in FIG. 11. As shown in FIG. 12, node 1200 may include a processor 1202, a memory 1204, and a transceiver 1206. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 1200 is user equipment 1102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 1200 may be implemented as a blade in a server system when node 1200 is configured as core network element 1106. Other implementations are also possible.

[0073] Transceiver 1206 may include any suitable device for sending and / or receiving data. Node 1200 may include one or more transceivers, although only one transceiver 1206 is shown for simplicity of illustration. An antenna 1208 is shown as a possible communication mechanism for node 1200. Multiple antennas and / or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 1200 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 1104 may communicate wirelessly to user equipment 1102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 1106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0074] As shown in FIG. 12, node 1200 may include processor 1202. Although only oneprocessor is shown, it is understood that multiple processors can be included. Processor 1202 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 1202 may be a hardware device having one or more processing cores. Processor 1202 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software.

[0075] As shown in FIG. 12, node 1200 may also include memory 1204. Although only one memory is shown, it is understood that multiple memories can be included. Memory 1204 can broadly include both memory and storage. For example, memory 1204 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 1202. Broadly, memory 1204 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0076] Processor 1202, memory 1204, and transceiver 1206 may be implemented in various forms in node 1200 for performing wireless communication functions. In some embodiments, processor 1202, memory 1204, and transceiver 1206 of node 1200 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 1202 and memory 1204 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 1202 and memory 1204 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g.,from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 1202 and transceiver 1206 (and memory 1204 in some cases) may be integrated on a radio frequency (RF) SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 1208. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. In particular, processor 1202 may be implemented as system 100 as described above to provide low latency, high precision stack overflow prevention.

[0077] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 1200 in FIG. 12. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0078] According to one aspect of the present disclosure, a SoC is provided. The SoC may include at least one processor. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to identify a first set of instructions associated with parallel processing by a plurality of computational units. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to input the first set of instructions associated with the parallel processing by the plurality of computational units into a GMM. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to identify a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM. The second set of instructions may include a subset of the first set of instructions.

[0079] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to identify one or more power profile characteristics for with the first set of instructions associated with the parallel processing by the plurality of computational units.

[0080] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to input the one or more power profile characteristics for the first set of instructions associated with the parallel processing by the plurality of computational units into the GMM. In some embodiments, the second set of instructions may be identified based at least in part on the one or more power profile characteristics input into the GMM.

[0081] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to identify power consumption information associated with the second set of instructions based on the output from the GMM.

[0082] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to cause the power consumption information to be maintained at one or more of a power control unit (PCU) or power policy unit (PPU).

[0083] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to cause a first computational unit of the plurality of computational units to execute a first basic block of the second set of instructions. In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to cause a second computational unit of the plurality of computational units to execute a second basic block of the second set of instructions. In some embodiments, the first basic block and the second basic block may originate from the first computational unit.

[0084] In some embodiments, the plurality of computational units may form a heterogeneous computational architecture.

[0085] According to another aspect of the present disclosure, an apparatus for parallel processing is provided. The apparatus may include an SoC. The SoC may include at least one processor. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to identify a first set of instructions associated withparallel processing by a plurality of computational units. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to input the first set of instructions associated with the parallel processing by the plurality of computational units into a GMM. The SoC may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to identify a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM. The second set of instructions may include a subset of the first set of instructions.

[0086] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to identify one or more power profile characteristics for the first set of instructions associated with the parallel processing by the plurality of computational units.

[0087] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to input the one or more power profile characteristics for the first set of instructions associated with the parallel processing by the plurality of computational units into the GMM. In some embodiments, the second set of instructions may be identified based at least in part on the one or more power profile characteristics input into the GMM.

[0088] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to identify power consumption information associated with the second set of instructions based on the output from the GMM.

[0089] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to cause the power consumption information to be maintained at one or more of a PCU or PPU.

[0090] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to cause a first computational unit of the plurality of computational units to execute a first basic block of the second set of instructions. In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to cause a second computational unit of the plurality of computational units to execute a second basic block of the second set of instructions. In some embodiments, the first basic block and the second basic block may originate from the first computational unit.

[0091] In some embodiments, the plurality of computational units may form a heterogeneous computational architecture.

[0092] According to a further aspect of the present disclosure, a method of parallel processing by an SoC is provided. The method may include identifying, by at least one processor, a first set of instructions associated with parallel processing by a plurality of computational units. The method may include inputting, by the at least one processor, the first set of instructions associated with the parallel processing by the plurality of computational units into a GMM. The method may include identifying, by the at least one processor, a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM. The second set of instructions may include a subset of the first set of instructions.

[0093] In some embodiments, the method may include identifying, by the at least one processor, one or more power profile characteristics for with the first set of instructions associated with the parallel processing by the plurality of computational units.

[0094] In some embodiments, the method may include inputting, by the at least one processor, the one or more power profile characteristics for the first set of instructions associated with the parallel processing by the plurality of computational units into the GMM. In some embodiments, the second set of instructions may be identified based at least in part on the one or more power profile characteristics input into the GMM.

[0095] In some embodiments, the method may include identifying, by the at least one processor, power consumption information associated with the second set of instructions based on the output from the GMM.

[0096] In some embodiments, the method may include causing, by the at least one processor, the power consumption information to be maintained at one or more of a PCU or PPU.

[0097] In some embodiments, the method may include causing, by the at least one processor, a first computational unit of the plurality of computational units to execute a first basic block of the second set of instructions. In some embodiments, the method may include causing, by the at least one processor, a second computational unit of the plurality of computational units to execute a second basic block of the second set of instructions. In some embodiments, the first basic block and the second basic block may originate from the first computational unit. In some embodiments, the plurality of computational units may form a heterogeneous computational architecture.

[0098] The foregoing description of the specific embodiments will so reveal the generalnature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and / or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0099] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0100] The Summary and Abstract sections may set forth one or more but not all embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0101] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0102] The breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A system-on-chip (SoC), comprising: at least one processor; and memory storing instructions, which when executed by the at least one processor, cause the at least one processor to: identify a first set of instructions associated with parallel processing by a plurality of computational units; input the first set of instructions associated with the parallel processing by the plurality of computational units into a Gaussian mixture model (GMM); and identify a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM, wherein the second set of instructions includes a subset of the first set of instructions.

2. The SoC of claim 1, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: identify one or more power profile characteristics for with the first set of instructions associated with the parallel processing by the plurality of computational units.

3. The SoC of claim 2, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: input the one or more power profile characteristics for the first set of instructions associated with the parallel processing by the plurality of computational units into the GMM, wherein the second set of instructions are identified based at least in part on the one or more power profile characteristics input into the GMM.

4. The SoC of claim 1, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: identify power consumption information associated with the second set of instructions based on the output from the GMM.

5. The SoC of claim 4, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: cause the power consumption information to be maintained at one or more of a power control unit (PCU) or power profile unit (PPU).

6. The SoC of claim 1, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: cause a first computational unit of the plurality of computational units to execute a first basic block of the second set of instructions; and cause a second computational unit of the plurality of computational units to execute a second basic block of the second set of instructions, wherein the first basic block and the second basic block originate from the first computational unit.

7. The SoC of claim 1, wherein the plurality of computational units form a heterogeneous computational architecture.

8. An apparatus for parallel processing, comprising: a system-on-chip (SoC), comprising: at least one processor; and memory storing instructions, which when executed by the at least one processor, cause the at least one processor to: identify a first set of instructions associated with parallel processing by a plurality of computational units; input the first set of instructions associated with the parallel processing by the plurality of computational units into a Gaussian mixture model (GMM); and identify a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM, wherein the second set of instructions includes a subset of the first set of instructions.

9. The apparatus of claim 8, wherein the memory storing instructions, which when executedby the at least one processor, further cause the at least one processor to: identify one or more power profile characteristics for the first set of instructions associated with the parallel processing by the plurality of computational units.

10. The apparatus of claim 9, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: input the one or more power profile characteristics for the first set of instructions associated with the parallel processing by the plurality of computational units into the GMM, wherein the second set of instructions are identified based at least in part on the one or more power profile characteristics input into the GMM.

11. The apparatus of claim 8, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: identify power consumption information associated with the second set of instructions based on the output from the GMM.

12. The apparatus of claim 11, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: cause the power consumption information to be maintained at one or more of a power control unit (PCU) or power profile unit (PPU).

13. The apparatus of claim 8, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: cause a first computational unit of the plurality of computational units to execute a first basic block of the second set of instructions; and cause a second computational unit of the plurality of computational units to execute a second basic block of the second set of instructions, wherein the first basic block and the second basic block originate from the first computational unit.

14. The apparatus of claim 8, wherein the plurality of computational units form a heterogeneous computational architecture.

15. A method of parallel processing by a system-on-chip (SoC), comprising: identifying, by at least one processor, a first set of instructions associated with parallel processing by a plurality of computational units; inputting, by the at least one processor, the first set of instructions associated with the parallel processing by the plurality of computational units into a Gaussian mixture model (GMM); and identifying, by the at least one processor, a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM, wherein the second set of instructions includes a subset of the first set of instructions.

16. The method of claim 15, further comprising: identifying, by the at least one processor, one or more power profile characteristics for with the first set of instructions associated with the parallel processing by the plurality of computational units.

17. The method of claim 16, further comprising: inputting, by the at least one processor, the one or more power profile characteristics for the first set of instructions associated with the parallel processing by the plurality of computational units into the GMM, wherein the second set of instructions are identified based at least in part on the one or more power profile characteristics input into the GMM.

18. The method of claim 15, further comprising: identifying, by the at least one processor, power consumption information associated with the second set of instructions based on the output from the GMM.

19. The method of claim 18, further comprising: causing, by the at least one processor, the power consumption information to be maintained at one or more of a power control unit (PCU) or power profile unit (PPU).

20. The method of claim 15, further comprising: causing, by the at least one processor, a first computational unit of the plurality of computational units to execute a first basic block of the second set of instructions; and causing, by the at least one processor, a second computational unit of the plurality of computational units to execute a second basic block of the second set of instructions, wherein the first basic block and the second basic block originate from the first computational unit, and wherein the plurality of computational units form a heterogeneous computational architecture.

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