Image-sensor forming method, and image sensor

Abstract

An image-sensor forming method, comprising: before forming a gate electrode, etching a semiconductor substrate (100) according to a preset first mask layer (200), so as to form semiconductor island structures (110) which are arranged in an array, wherein upper portions of at least some of the semiconductor island structures (110) are connected to upper portions of adjacent semiconductor island structures (110) by means of cantilever beam structures (120), and an intercommunicated first trench (130) is formed between the semiconductor island structures (110); and forming a gate dielectric layer (131) in the intercommunicated first trench (130), so as to reduce photoelectric crosstalk between the semiconductor island structures (110). Compared with an existing image-sensor forming solution, the present solution can significantly reduce the requirements of pixels on process quality, without the need for additionally providing a photomask, and the present solution can increase the production yield while greatly reducing the level of dark currents, and provide a better pixel reading capability.

Description

Image sensor forming method and image sensor Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an image sensor forming method and an image sensor. Background Art

[0002] With the advancement of semiconductor process nodes and the market's demand for image sensor performance, sensor pixel size is being forced to shrink. At the same time, pixel signal-to-noise ratio requirements are gradually increasing. This conflicting demand forces the photodiode size to increase as a percentage of the pixel volume to improve signal strength, while also requiring good pinning at each silicon interface to reduce pixel dark current. Limited by the resolution of photoresist, ion implantation is difficult to achieve both of these requirements simultaneously, necessitating the use of epitaxial growth methods to fabricate photodiodes.

[0003] Currently, a scheme exists for forming discrete photodiodes using an N-type substrate through etching and secondary epitaxial growth. In this scheme, the photodiode structure is defined by photolithography, resulting in complete and uniform inter-diode isolation across the entire depth of the photodiode. Because the epitaxial growth steps occur simultaneously across the entire depth of the photodiode, the photodiodes fabricated using this scheme offer high capacitance across the entire depth, significantly improving the full well capacity of the resulting photosensor. However, due to the layout of the surface transistors, the epitaxial growth step requires a complete silicon substrate structure. The epitaxial growth process closes the isolation trenches, causing stress in the silicon crystal, which can introduce lattice defects and rapidly expand at high epitaxial temperatures. Secondary epitaxial growth also carries the risk of introducing silicon defects, which can significantly affect the dark current level of the photodiode. Furthermore, as pixel size decreases, the volume share of the photodiode increases, but the area of ​​the heavily P-type doped isolation region decreases rapidly, exacerbating the already severe dark current and causing the depletion voltage of the photodiode to continue to rise, compromising the complete readout of the photoelectron signal.

[0004] Summary of the Invention

[0005] The present invention provides a method for forming an image sensor, comprising: before forming a gate, etching a semiconductor substrate according to a preset first mask layer to form an array of semiconductor island structures, wherein the upper portions of at least some of the semiconductor island structures are connected to the upper portions of adjacent semiconductor island structures via a cantilever structure, and first trenches interconnecting the semiconductor island structures are formed;

[0006] A gate dielectric layer is formed in the interconnected first trenches to reduce photoelectric crosstalk of the semiconductor island structure.

[0007] Furthermore, after forming the first trench, the width of the bottom of the first trench is reduced by at least one epitaxial process to improve the sensitivity of the image sensor.

[0008] Furthermore, it also includes:

[0009] The first mask layer is etched again in a self-aligned manner to increase the width of the upper portion of the first trench, thereby optimizing the subsequent process of filling polysilicon.

[0010] Furthermore, after forming the gate dielectric layer in the interconnected first trenches, the method further includes: filling polysilicon on the surface of the gate dielectric layer to form a polysilicon gate, and further forming a pinning layer in the sidewall of the semiconductor island structure.

[0011] Furthermore, a transistor is formed at at least a portion of the cantilever structure.

[0012] Furthermore, the cantilever structure improves the support strength provided to the semiconductor island structure, thereby avoiding problems caused by the semiconductor island structure tipping over during the process.

[0013] Furthermore, etching the semiconductor substrate to form an array of semiconductor island structures according to the preset first mask layer includes:

[0014] According to the preset first mask layer, etching the semiconductor substrate to form a second trench;

[0015] forming a first dielectric layer on the surface of the second trench;

[0016] Continue etching the bottom of the first dielectric layer and the semiconductor substrate to form a third trench;

[0017] Isotropic etching is used to etch and widen the third trench on both sides to form the semiconductor island structure. The upper part of the semiconductor island structure is protected from being etched by the first dielectric layer, and the first trenches interconnected at the lower part of the semiconductor island structure are formed to form the cantilever structure.

[0018] Furthermore, etching the semiconductor substrate to form an array of semiconductor island structures according to the preset first mask layer includes:

[0019] According to the preset first mask layer, etching the semiconductor substrate to form a second trench;

[0020] forming a first dielectric layer on the surface of the second trench;

[0021] Continue etching the bottom of the first dielectric layer and the semiconductor substrate, and by adjusting the etching process conditions, form the semiconductor island structure. The upper portion of the semiconductor island structure is protected from being etched by the first dielectric layer, and the first trenches interconnected at the lower portion of the semiconductor island structure are formed, thereby forming the cantilever structure.

[0022] Furthermore, etching the semiconductor substrate to form an array of semiconductor island structures according to the preset first mask layer includes:

[0023] The semiconductor substrate is etched according to the preset first mask layer, and the semiconductor island structure is formed by adjusting the etching process conditions. The first trenches interconnected at the bottom of the semiconductor island structure are formed, and the cantilever structure is formed.

[0024] Furthermore, when the semiconductor substrate is etched to form array-arranged semiconductor island structures, at least part of the semiconductor island structures form multiple groups of sub-arrays. In each group of the sub-arrays, adjacent semiconductor island structures are connected to each other through the cantilever structures located in the corresponding corner areas.

[0025] Furthermore, after the surface of the gate dielectric layer is filled with polysilicon to form a polysilicon gate, the method further includes:

[0026] Etching back is performed according to a preset mask pattern so that the area of ​​the polysilicon gate close to the floating diffusion area is lower than the semiconductor substrate, so as to improve the charge-to-voltage conversion gain of the image sensor.

[0027] Furthermore, at least a portion of the boundaries of the metal vias of the semiconductor island structure exceed the boundaries of the active area.

[0028] Furthermore, the method further includes: forming a first epitaxial layer in the first trench through an epitaxial process.

[0029] Furthermore, by designing the width and shape of the first trench in the horizontal and vertical directions between adjacent semiconductor island structures, it is ensured that the width of the first trench in the lower part of the semiconductor island structure is uniform in the horizontal and vertical directions after the first epitaxial layer is formed.

[0030] Furthermore, the width of the first groove around the cantilever structure is at least 5% wider than the width of the first groove in other areas.

[0031] Furthermore, the first epitaxial layer and the semiconductor substrate have opposite doping types, forming a lateral PN junction structure.

[0032] Furthermore, the first epitaxial layer includes at least a sub-epitaxial layer having a doping type opposite to that of the semiconductor substrate;

[0033] The forming of the first epitaxial layer in the first trench by an epitaxial process includes:

[0034] epitaxially growing an intrinsic semiconductor on the surface of the first trench through an epitaxial process to form a first sub-epitaxial layer;

[0035] A semiconductor material having a doping type opposite to that of the semiconductor substrate is epitaxially grown on the surface of the first sub-epitaxial layer to form a second sub-epitaxial layer, thereby forming a lateral PIN junction structure.

[0036] Furthermore, the first epitaxial layer is an intrinsic semiconductor material, and the gate dielectric layer contains a doped semiconductor with a doping type opposite to that of the semiconductor substrate. Through a thermal diffusion process, the doped semiconductor in the gate dielectric layer penetrates into the first epitaxial layer to form a lateral PN junction structure.

[0037] Furthermore, both the first epitaxial layer and the gate dielectric layer have semiconductor doping types opposite to the doping type of the semiconductor substrate. Through a thermal diffusion process, the doped semiconductor in the gate dielectric layer is allowed to penetrate into the first epitaxial layer. By adjusting the thickness and / or doping concentration of the gate dielectric layer, the doping concentration of the first epitaxial layer is further controlled to achieve a preset effect.

[0038] Furthermore, the method further comprises: forming the gate dielectric layer on the surface of the first trench, wherein the gate dielectric layer has a doped semiconductor having a doping type opposite to that of the semiconductor substrate;

[0039] Through a thermal diffusion process, the doped semiconductor in the gate dielectric layer is allowed to penetrate into the semiconductor substrate to form a lateral PN junction structure.

[0040] Furthermore, the transistors are sidewall transistors to improve the performance of the image sensor.

[0041] Furthermore, the sidewall transistor includes at least two sidewall structures perpendicular to the surface of the semiconductor substrate.

[0042] Furthermore, the method further includes: forming a second dielectric layer around the cantilever structure, and etching the second dielectric layer in a self-aligned manner using at least a portion of the first mask layer to form the sidewall transistor at the cantilever structure.

[0043] Furthermore, it also includes: etching the semiconductor island structure according to the second mask layer to form an active area and a shallow trench isolation structure, and forming a vertical transfer gate at the shallow trench isolation structure to reduce the depth and capacitance of the vertical transfer gate.

[0044] Furthermore, the sub-array includes the semiconductor island structures arranged in a 2×2 pattern.

[0045] Furthermore, each group of sub-arrays is independent of each other.

[0046] Furthermore, the semiconductor island structure includes a first protruding structure extending toward the adjacent diagonal sub-array to form a floating diffusion region in a subsequent step.

[0047] Furthermore, the method further includes: forming a sidewall transfer transistor in the first protruding structure region, wherein the sidewall transfer transistor is formed simultaneously with sidewall transistors in other regions.

[0048] Furthermore, in the sub-array, the semiconductor island structure includes a second protruding structure extending toward the semiconductor island structure adjacent to the diagonal side, so as to be subsequently connected to a potential.

[0049] Furthermore, the sub-array includes the semiconductor island structures arranged in a 2×1 pattern.

[0050] Furthermore, each 2×2 sub-arrays share a set of signal control circuits.

[0051] The present invention also provides an image sensor formed by the above-mentioned image sensor forming method.

[0052] Compared with the existing image sensor formation scheme, this scheme can significantly reduce the pixel's requirements for process quality without adding additional masks, improve production yield, and significantly reduce the dark current level, and provide better pixel readout capabilities. During the epitaxial process, this scheme may choose not to pursue the closure of the trench, but to retain the trench and grow a dielectric layer (such as a gate oxide layer) and polysilicon therein, thereby avoiding the interface defects caused by stress and lattice mismatch when the semiconductor substrate is epitaxially closed. Then, by applying a negative voltage to the polysilicon filling the trench, the interface pinning effect is improved with the help of the electric field, thereby reducing the doping concentration requirement of the epitaxial layer, reducing the thickness of the epitaxial layer, and thus increasing the full well capacitance of the photodiode. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments when read with reference to the accompanying drawings.

[0054] 1 to 7 are schematic structural diagrams of image sensor forming methods according to different embodiments of the present invention;

[0055] 8 to 11 are schematic diagrams of layouts of image sensors in different embodiments of the present invention.

[0056] In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout different drawings. DETAILED DESCRIPTION

[0057] The present invention provides a method for forming an image sensor, as shown in FIG1 , comprising: before forming a gate, etching a semiconductor substrate 100 according to a preset first mask layer 200 to form an array of semiconductor island structures 110, wherein at least the upper portions of some of the semiconductor island structures 110 are connected to the upper portions of adjacent semiconductor island structures 110 via a cantilever structure 120, and first trenches 130 are formed between the semiconductor island structures 110;

[0058] Afterwards, a gate dielectric layer 131 (not shown in the figure) is formed in the interconnected first trenches 130 , thereby reducing the photoelectric crosstalk of the semiconductor island structure.

[0059] Preferably, the cantilever structure 120 can improve the support strength provided to the semiconductor island structure, thereby avoiding the problem caused by the semiconductor island structure 110 tipping over during the process. In an optional embodiment, the semiconductor island structure 110 and the cantilever structure 120 can be formed by multiple etching schemes. For example, in a preferred embodiment, they can be formed by the following steps:

[0060] Step S111: etching the semiconductor substrate to form a second trench 140 according to the preset first mask layer 200, as shown in FIG2;

[0061] Step S112: forming a first dielectric layer 141 on the surface of the second trench 140, as shown in FIG3, to play a protective role in the subsequent etching process;

[0062] Step S113: Continue etching the bottom of the first dielectric layer 141 and the semiconductor substrate 100 to form a third trench 150, as shown in FIG4;

[0063] Step S114: Using isotropic etching, the third trench 150 is widened on both sides to form the semiconductor island structure 110, and the upper portion of the semiconductor island structure 110 is protected from being etched by the first dielectric layer 141, and the first trenches 130 interconnected at the lower portion of the semiconductor island structure 110 are formed, and the cantilever structure 120 is formed, as shown in Figure 1.

[0064] After the cantilever structure is formed, the first dielectric layer 141 may be removed.

[0065] Alternatively, in another embodiment, the following steps may be employed:

[0066] Step S121: etching the semiconductor substrate 100 to form a second trench 140 according to the preset first mask layer 200, as shown in FIG2;

[0067] Step S122: forming a first dielectric layer 141 on the surface of the second trench 140 , as shown in FIG3 ;

[0068] Step S123: Continue etching the bottom of the first dielectric layer 141 and the semiconductor substrate 100, and form the semiconductor island structure 110 by adjusting the etching process conditions. The upper portion of the semiconductor island structure 110 is protected from being etched by the first dielectric layer 141, and the first trenches 130 interconnected at the lower portion of the semiconductor island structure 110 are formed, thereby forming the cantilever structure 120, as shown in FIG1 .

[0069] The difference from the first embodiment is that in this embodiment, after the second groove 140 is formed, the third groove 150 is no longer etched, but the first groove 130 and the cantilever structure 120 are directly formed by side excavation during etching.

[0070] Optionally, the above operation process can be further simplified as shown in the following embodiment:

[0071] Step S131: Etching the semiconductor substrate 100 according to the preset first mask layer 200, and adjusting the etching process conditions to form the semiconductor island structure 110, forming the first grooves 130 interconnected at the lower part of the semiconductor island structure 110, and forming the cantilever structure 130.

[0072] Optionally, after forming the first trench 130, the width of the bottom of the first trench 130 can be reduced through at least one epitaxial growth process to improve the sensitivity of the image sensor. Further, after reducing the bottom width of the first trench 130, a self-aligned etching process can be performed again through the first mask layer 200 to increase the width of the upper portion of the first trench 130, thereby optimizing the subsequent polysilicon filling process.

[0073] To form a polysilicon gate, in a preferred embodiment, after forming a gate dielectric layer 131 within the interconnected first trenches 130, further steps may be performed: filling with polysilicon to form a polysilicon gate 300, and further forming a pinning layer within the sidewalls of the semiconductor island structure 110. The polysilicon gate 300 structure can serve as an optical and electrical isolation layer between pixel units and can also be connected to a potential to form a pinning layer.

[0074] Preferably, after forming the polysilicon gate 300, an etch-back process can be performed according to a predetermined mask pattern to lower the area of ​​the polysilicon gate 300 near the floating diffusion region below the semiconductor substrate 100, thereby improving the charge-to-voltage conversion gain of the image sensor. Furthermore, at least a portion of the metal via boundaries of the semiconductor island structure 110 can extend beyond the boundaries of the active region to further form a metal connection structure.

[0075] Furthermore, in an optional embodiment, after forming the first trench 130, a first epitaxial layer 400 may be formed in the first trench 130 through an epitaxial process. Subsequently, a gate dielectric layer 131 and a polysilicon gate 300 may be formed in the first epitaxial layer 400, as shown in FIG7 .

[0076] Preferably, when forming the first epitaxial layer 400, the width and shape of the first trenches 130 between adjacent semiconductor island structures 110 are designed to ensure uniformity in both the horizontal and vertical directions of the width of the first trenches 130 in the lower portion of the semiconductor island structures 110 after the first epitaxial layer 400 is formed. Preferably, during the process, the cross-sectional areas of the trenches on all four sides of the semiconductor island structure 110 can be made similar to ensure uniformity. In an optional embodiment, the width of the first trenches 130 around the cantilever structure 120 can be at least 5% wider than the width of the first trenches 130 in other areas.

[0077] Optionally, in different embodiments, a lateral PN junction structure can be formed by different doping of the first epitaxial layer 400 and the semiconductor substrate 100 in various ways, and the pixel unit of the image sensor can be further realized. For example, in an optional embodiment, the doping type of the first epitaxial layer 400 can be directly made opposite to the doping type of the semiconductor substrate 100, thereby forming a lateral PN junction structure.

[0078] In another embodiment, the first epitaxial layer 400 may include at least a sub-epitaxial layer having a doping type opposite to that of the semiconductor substrate 100. Specifically, a lateral PN junction structure is formed by the following steps:

[0079] Step S221: epitaxially growing an intrinsic semiconductor on the surface of the first trench 130 through an epitaxial process to form a first sub-epitaxial layer 410, as shown in FIG6;

[0080] Step S222: A semiconductor material having a doping type opposite to that of the semiconductor substrate 100 is epitaxially grown on the surface of the first epitaxial sub-layer 410 to form a second epitaxial sub-layer 420, thereby forming a lateral PIN junction structure, as shown in FIG6 . The first epitaxial sub-layer 410 of the intrinsic semiconductor can act as a buffer between the second epitaxial sub-layer 420 and the semiconductor substrate 100.

[0081] In another optional embodiment, the first epitaxial layer 400 can be made of intrinsic semiconductor material. At the same time, the gate dielectric layer 131 (not shown in the figure) can be made of a doped semiconductor with a doping type opposite to that of the semiconductor substrate 100. Through a thermal diffusion process, the doped semiconductor in the gate dielectric layer 131 is allowed to penetrate into the first epitaxial layer 400, thereby forming a lateral PN junction structure.

[0082] In addition, in another embodiment, the first epitaxial layer 400 and the gate dielectric layer 131 (not shown in the figure) can also have semiconductor doping types opposite to the doping type of the semiconductor substrate 100, and then through a thermal diffusion process, the doped semiconductor in the gate dielectric layer 131 can be penetrated into the first epitaxial layer 400. By adjusting the thickness and / or doping concentration of the gate dielectric layer 131, the doping concentration of the first epitaxial layer 400 can be further controlled so that the PN junction structure achieves a preset effect.

[0083] In addition, the first epitaxial layer 400 may not be formed, and a lateral PN junction structure may be formed directly by thermal diffusion of the doped gate dielectric layer 131 (not shown in the figure), as shown in the following steps:

[0084] Step S231 : forming the gate dielectric layer 131 on the surface of the first trench 130 , wherein the gate dielectric layer 131 has a doped semiconductor having a doping type opposite to that of the semiconductor substrate 100 ;

[0085] Step S232 : using a thermal diffusion process, allowing the doped semiconductor in the gate dielectric layer 131 to penetrate into the semiconductor substrate 100 to form a lateral PN junction structure.

[0086] In an optional embodiment of the present invention, to achieve image sensor functionality and save space, a transistor, such as a source follower transistor, may be formed on at least a portion of the cantilever structure 120. Optionally, the transistor may be a sidewall transistor (SWT) to improve image sensor performance. Preferably, the sidewall transistor (SWT) includes at least two sidewall structures perpendicular to the surface of the semiconductor substrate 100.

[0087] In this embodiment, optionally, a second dielectric layer 121 can be formed around the cantilever structure 120, and the second dielectric layer 121 can be self-alignedly etched using at least a portion of the first mask layer 200, thereby forming the sidewall transistor (SWT) at the cantilever structure 120 through a subsequent process flow.

[0088] Furthermore, in an optional embodiment, the semiconductor island structure 110 can be etched according to the second mask layer 500 to form an active area (AA) and a shallow trench isolation structure (STI), and a vertical transfer gate (VTG) is formed at the shallow trench isolation structure (STI) to reduce the depth and capacitance of the vertical transfer gate (VTG).

[0089] In an optional embodiment, when etching the semiconductor substrate 100 according to the preset first mask layer 200 to form an array of semiconductor island structures 110, at least some of the semiconductor island structures form multiple groups of sub-arrays. In each group of the sub-arrays, adjacent semiconductor island structures 110 are interconnected by the cantilever structures located in corresponding corner regions, as shown in the figure. For example, the sub-arrays may include a 2×2 arrangement of the semiconductor island structures 110. In this embodiment, each group of the sub-arrays is independent of each other, and only the cantilever structures 120 exist within the sub-arrays to connect the semiconductor island structures 110 to each other, as shown in Figure 8.

[0090] Preferably, in this embodiment, the semiconductor island structure 110 may include a first protruding structure 111 extending toward the adjacent diagonal sub-array, as shown in FIG9 , to facilitate formation of a floating diffusion region (FD) in a subsequent step. Furthermore, a sidewall transfer transistor (TX) may be formed in the region of the first protruding structure, and the sidewall transfer transistor (TX) may be formed simultaneously with the sidewall transistor (SWT) in other regions.

[0091] Likewise, optionally, in the sub-array, the semiconductor island structure 110 may include a second protruding structure 112 extending toward the semiconductor island structure 110 adjacent to the diagonal side, as shown in FIG10 , for subsequent potential connection.

[0092] In addition to arranging the sub-arrays in the form of 2×2 semiconductor island structures 110, a 2×1 arrangement of semiconductor island structures 110 may also be used in one sub-array, as shown in Figure 11. In this embodiment, each 2×2 sub-arrays share a set of signal control circuits.

[0093] The present invention also provides an image sensor formed by the above-mentioned image sensor forming method.

[0094] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the wording "a" does not exclude pluralities. Multiple elements stated in a device claim may also be implemented by a single element. Terms such as first and second are used to indicate names and do not imply any particular order.

Claims

1. A method for forming an image sensor, characterized in that: include: Before the gate is formed, the semiconductor substrate is etched according to a preset first mask layer to form semiconductor island structures arranged in an array, the upper parts of at least some of the semiconductor island structures are connected to the upper parts of adjacent semiconductor island structures through a cantilever structure, and first trenches interconnected with each other are formed between the semiconductor island structures; A gate dielectric layer is formed in the interconnected first trenches to reduce photoelectric crosstalk of the semiconductor island structure.

2. The method for forming an image sensor according to claim 1, wherein: After forming the first trench, the width of the bottom of the first trench is reduced by at least one epitaxial process to improve the sensitivity of the image sensor.

3. The method for forming an image sensor according to claim 2, wherein: Also includes: The first mask layer is etched again in a self-aligned manner to increase the width of the upper portion of the first trench, so as to optimize subsequent processes.

4. The method for forming an image sensor according to claim 1, wherein: After forming the gate dielectric layer in the interconnected first trenches, the method further includes: filling polysilicon on the surface of the gate dielectric layer to form a polysilicon gate, and further forming a pinning layer in the sidewall of the semiconductor island structure.

5. The method for forming an image sensor according to claim 1, wherein: A transistor is formed at at least a portion of the cantilever structure.

6. The method for forming an image sensor according to claim 1, wherein: The cantilever structure improves the support strength of the semiconductor island structure and avoids the problem caused by the semiconductor island structure tipping over during the process.

7. The method for forming an image sensor according to claim 1, wherein: The etching of the semiconductor substrate to form an array-arranged semiconductor island structure according to the preset first mask layer comprises: According to the preset first mask layer, etching the semiconductor substrate to form a second trench; forming a first dielectric layer on the surface of the second groove; Continue etching the bottom of the first dielectric layer and the semiconductor substrate to form a third trench; Isotropic etching is used to etch and widen the third groove on both sides to form the semiconductor island structure. The upper part of the semiconductor island structure is protected from being etched by the first dielectric layer, and the first grooves interconnected with each other are formed at the lower part of the semiconductor island structure to form the cantilever structure.

8. The method for forming an image sensor according to claim 1, wherein: The etching of the semiconductor substrate to form an array-arranged semiconductor island structure according to the preset first mask layer comprises: According to the preset first mask layer, etching the semiconductor substrate to form a second trench; forming a first dielectric layer on the surface of the second groove; Continue to etch the bottom of the first dielectric layer and the semiconductor substrate, by adjusting The semiconductor island structure is formed by adjusting the etching process conditions, the upper part of the semiconductor island structure is protected from being etched by the first dielectric layer, the first grooves interconnected with each other are formed at the lower part of the semiconductor island structure, and the cantilever structure is formed.

9. The method for forming an image sensor according to claim 1, wherein: The etching of the semiconductor substrate to form an array-arranged semiconductor island structure according to the preset first mask layer comprises: The semiconductor substrate is etched according to the preset first mask layer, and the semiconductor island structure is formed by adjusting the etching process conditions, and the first grooves interconnected with each other are formed at the lower part of the semiconductor island structure, and the cantilever beam structure is formed.

10. The method for forming an image sensor according to claim 1, wherein: When the semiconductor substrate is etched to form array-arranged semiconductor island structures, at least part of the semiconductor island structures form multiple groups of sub-arrays. In each group of the sub-arrays, adjacent semiconductor island structures are connected to each other through the cantilever structures located in corresponding corner areas.

11. The method for forming an image sensor according to claim 4, wherein: After the surface of the gate dielectric layer is filled with polysilicon to form a polysilicon gate, the method further includes: Etching back is performed according to a preset mask pattern so that the area of ​​the polysilicon gate close to the floating diffusion area is lower than the semiconductor substrate, so as to improve the charge-to-voltage conversion gain of the image sensor.

12. The method for forming an image sensor according to claim 11, wherein: At least a portion of the metal via boundaries of the semiconductor island structure exceeds the boundary of the active region.

13. The method for forming an image sensor according to claim 1, wherein: Also includes: A first epitaxial layer is formed in the first trench by an epitaxial process.

14. The method for forming an image sensor according to claim 13, wherein: By designing the width and shape of the first trench in the horizontal and vertical directions between adjacent semiconductor island structures, it is ensured that the width of the first trench in the lower part of the semiconductor island structure is uniform in the horizontal and vertical directions after the first epitaxial layer is formed.

15. The method for forming an image sensor according to claim 14, wherein: The width of the first groove around the cantilever structure is at least 5% wider than the width of the first groove in other areas.

16. The method for forming an image sensor according to claim 13, wherein: The doping type of the first epitaxial layer is opposite to that of the semiconductor substrate, forming a lateral PN junction structure.

17. The method for forming an image sensor according to claim 13, wherein: The first epitaxial layer comprises at least a sub-epitaxial layer having a doping type opposite to that of the semiconductor substrate; The forming of the first epitaxial layer in the first trench by an epitaxial process comprises: epitaxially grow an intrinsic semiconductor on the surface of the first trench through an epitaxial process to form a first sub-epitaxial layer; A semiconductor material having a doping type opposite to that of the semiconductor substrate is epitaxially grown on the surface of the first sub-epitaxial layer to form a second sub-epitaxial layer and a lateral PIN junction structure.

18. The method for forming an image sensor according to claim 13, wherein: The first epitaxial layer is an intrinsic semiconductor material, the gate dielectric layer has a doped semiconductor with a doping type opposite to that of the semiconductor substrate, and through a thermal diffusion process, the doped semiconductor in the gate dielectric layer penetrates into the first epitaxial layer to form a lateral PN junction structure.

19. The method for forming an image sensor according to claim 13, wherein: Both the first epitaxial layer and the gate dielectric layer have semiconductor doping types opposite to the doping type of the semiconductor substrate. Through a thermal diffusion process, the doped semiconductor in the gate dielectric layer penetrates into the first epitaxial layer. By adjusting the thickness and / or doping concentration of the gate dielectric layer, the doping concentration of the first epitaxial layer is further controlled to achieve a preset effect.

20. The method for forming an image sensor according to claim 1, wherein: Also includes: Forming the gate dielectric layer on the surface of the first trench, wherein the gate dielectric layer has a doped semiconductor having a doping type opposite to that of the semiconductor substrate; Through a thermal diffusion process, the doped semiconductor in the gate dielectric layer is infiltrated into the semiconductor substrate to form a lateral PN junction structure.

21. The method for forming an image sensor according to claim 5, wherein: The transistor adopts a sidewall transistor to improve the performance of the image sensor.

22. The method for forming an image sensor according to claim 21, wherein: The sidewall transistor includes at least two sidewall structures perpendicular to the surface of the semiconductor substrate.

23. The method for forming an image sensor according to claim 21, wherein: Also includes: A second dielectric layer is formed around the cantilever structure, and the second dielectric layer is etched in a self-aligned manner using at least a portion of the first mask layer to form the sidewall transistor at the cantilever structure.

24. The method for forming an image sensor according to claim 1, wherein: Also includes: The semiconductor island structure is etched according to the second mask layer to form an active area and a shallow trench isolation structure, and a vertical transfer gate is formed at the shallow trench isolation structure to reduce the depth and capacitance of the vertical transfer gate.

25. The method for forming an image sensor according to claim 10, wherein: The sub-array includes the semiconductor island structures arranged in 2×2.

26. The method for forming an image sensor according to claim 10, wherein: Each group of sub-arrays is independent of each other.

27. The method for forming an image sensor according to claim 25, wherein: The semiconductor island structure includes a first protruding structure extending toward the adjacent diagonal sub-array to form a floating diffusion region in a subsequent step.

28. The method for forming an image sensor according to claim 27, wherein: The invention also includes: forming a sidewall transfer transistor in the first protruding structure region, wherein the sidewall transfer transistor is formed simultaneously with sidewall transistors in other regions.

29. The method for forming an image sensor according to claim 25, wherein: In the sub-array, the semiconductor island structure includes a second protruding structure extending toward the semiconductor island structure adjacent to the diagonal side, so as to be subsequently connected to a potential.

30. The method for forming an image sensor according to claim 10, wherein: The sub-array includes the semiconductor island structures arranged in 2×1.

31. The method for forming an image sensor according to claim 30, wherein: Each 2×2 sub-arrays share a set of signal control circuits.

32. An image sensor, characterized in that: The image sensor is formed by the image sensor forming method according to claims 1 to 31.

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