Repair sharing circuit, repair sharing method and memory

Abstract

Provided in the present disclosure are a repair sharing circuit and method, and a memory. The circuit comprises a mode selection circuit and a repair control circuit, wherein the repair control circuit comprises N control sub-circuits, and M control sub-circuits among the N control sub-circuits serve as shared circuits; the mode selection circuit performs latching processing according to a preset clock signal and an enable signal to generate a start signal; the repair control circuit performs logic processing according to the start signal and N state indication signals, and outputs N repair indication signals by means of the N control sub-circuits; and when the start signal is in an enabled state and a repair indication signal which is output by a first control sub-circuit among the shared circuits is in the enabled state, a first repair operation is executed according to a repair resource corresponding to the first control sub-circuit.

Description

Repair shared circuit, repair shared method and memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202310900826.2, application date July 20, 2023, and invention name “Repairing shared circuit, repairing shared method and memory”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a repair sharing circuit, a repair sharing method, and a memory. Background Art

[0004] In the normal use process of memory, some storage rows and / or columns may fail, in order to prolong the life of memory when storage row and / or column fail, the packaging back repair (Post Package Repair, PPR) method is used to repair storage row and / or column of memory.Concrete, can adopt redundant storage row and / or column to replace the storage row and / or column that fail. The PPR method comprises soft encapsulation back repair (Soft PPR, SPPR) and hard encapsulation back repair (Hard PPR, HPPR), wherein, SPPR is a temporary repair, and HPPR is a permanent repair, and the repair of carrying out after memory is carried out built-in self-test (Memory Built-In Self-Test, MBIST) is called test encapsulation back repair (MBIST Post Package Repair, MPPR).

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a repair sharing circuit, a repair sharing method, and a memory.

[0007] In a first aspect, an embodiment of the present disclosure provides a repair sharing circuit, including a mode selection circuit and a repair control circuit. The repair control circuit includes N control subcircuits, M of the N control subcircuits serving as shared circuits, each of the control subcircuits corresponding to a repair resource, N and M being integers greater than 0, and M being less than N, wherein:

[0008] The mode selection circuit is configured to receive a preset clock signal and an enable signal, perform latching processing according to the preset clock signal and the enable signal, and generate a start signal;

[0009] The repair control circuit is configured to receive the start signal and N status indication signals, perform logic processing based on the start signal and the N status indication signals, and output N repair indication signals through the N control sub-circuits, each of the status indication signals being configured to indicate whether a repair resource corresponding to the corresponding control sub-circuit is available;

[0010] Among them, when the start signal is in an enabled state and the repair indication signal output by the first control sub-circuit in the shared circuit is in an enabled state, a first repair operation is performed according to the repair resources corresponding to the first control sub-circuit, and the first control sub-circuit is any one of the M control sub-circuits.

[0011] In some embodiments, when the start signal is in a non-enabled state and the repair indication signal output by the second control sub-circuit in the repair control circuit is in an enabled state, a second repair operation is performed according to the repair resources corresponding to the second control sub-circuit, and the second control sub-circuit is any one of the N control sub-circuits.

[0012] In some embodiments, the remaining (NM) control sub-circuits of the N control sub-circuits are configured as non-shared circuits, and the mode selection circuit includes a latch, wherein:

[0013] The first input end of the latch is used to receive the enable signal, the second input end of the latch is used to receive the preset clock signal, the output end of the latch is used to output the start signal, and the output end of the latch is respectively connected to each of the control sub-circuits in the non-shared circuit.

[0014] In some embodiments, the latch further includes a reset terminal, the reset terminal being configured to receive a reset signal, wherein:

[0015] The latch is used to control the start signal to be reset to a non-enabled state when the reset signal is in an enabled state.

[0016] In some embodiments, the latch includes a first NAND gate and a second NAND gate, wherein:

[0017] The first input terminal of the first NAND gate serves as the first input terminal of the latch, and is used to receive the enable signal;

[0018] The second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate;

[0019] The output end of the first NAND gate serves as the output end of the latch, and is used to output the start signal. The output end of the first NAND gate is connected to the first input end of the second NAND gate.

[0020] The second input end of the second NAND gate serves as the second input end of the latch, and is used to receive the preset clock signal;

[0021] The third input terminal of the second NAND gate serves as a reset terminal of the latch, and is used to receive the reset signal.

[0022] In some embodiments, the i-th control subcircuit is configured to receive the i-th first control signal, the i-th second control signal, the i-th status indication signal, and the repair command signal; and perform logical processing based on the i-th first control signal, the i-th second control signal, the i-th status indication signal, and the repair command signal to generate the i-th repair indication signal; wherein, i is an integer greater than 0 and less than or equal to N, and when i is greater than 0 and less than N, the output end of the i-th control subcircuit is connected to the i+1-th control subcircuit; if the i-th control subcircuit belongs to the shared circuit, the i-th first control signal is a preset signal; if the i-th control subcircuit belongs to the non-shared circuit, the i-th first control signal is the start signal; when i is equal to 1, the first second control signal is a preset signal; when i is greater than 1 and less than or equal to N, the i-th second control signal is the i-1-th repair indication signal;

[0023] Among them, when the i-th first control signal is in the enabled state and the i-th control sub-circuit belongs to the non-shared circuit, the i-th repair indication signal is in the disabled state; when the i-th first control signal is in the enabled state and the i-th control sub-circuit belongs to the shared circuit, or when the i-th first control signal is in the disabled state, if the i-th status indication signal is in the enabled state, the i-th second control signal is in the disabled state, and the repair command signal is in the enabled state, the i-th repair indication signal is in the enabled state.

[0024] In some embodiments, the i-th control subcircuit includes a sampling circuit, a first logic subcircuit, a second logic subcircuit, and a third logic subcircuit, wherein:

[0025] The sampling circuit is configured to receive the i-th state indication signal and the preset clock signal, sample the i-th state indication signal according to the preset clock signal, and generate an i-th sampling indication signal; the state of the i-th sampling indication signal is opposite to the state of the i-th state indication signal;

[0026] the first logic sub-circuit is configured to receive an i-th sampling indication signal and an i-th first control signal; perform logic processing based on the i-th sampling indication signal and the i-th first control signal to generate an i-th first intermediate signal; when the i-th first control signal is in an enabled state, the i-th first intermediate signal is in an enabled state; and when the i-th first control signal is in a disabled state, a state of the i-th first intermediate signal is the same as a state of the i-th sampling indication signal;

[0027] the second logic sub-circuit is configured to receive an i-th first intermediate signal and an i-th second control signal; perform logic processing on the i-th first intermediate signal and the i-th second control signal to generate an i-th second intermediate signal; and when the i-th first intermediate signal is in an enabled state, the i-th second intermediate signal is in a disabled state; and when the i-th first intermediate signal is in a disabled state, the state of the i-th second intermediate signal is opposite to the state of the i-th second control signal.

[0028] The third logic sub-circuit is configured to receive the i-th second intermediate signal and the repair command signal; perform logic processing based on the i-th second intermediate signal and the repair command signal to generate the i-th repair indication signal; wherein, when the i-th second intermediate signal and the repair command signal are both in an enabled state, the i-th repair indication signal is in an enabled state; otherwise, the i-th repair indication signal is in a disabled state.

[0029] In some embodiments, in the i-th control sub-circuit, the sampling circuit includes a trigger, wherein:

[0030] The input end of the trigger is used to receive the i-th state indication signal;

[0031] The clock terminal of the trigger is used to receive the preset clock signal;

[0032] The output end of the trigger is used to output the i-th sampling indication signal.

[0033] In some embodiments, in the i-th control subcircuit, the first logic subcircuit includes an OR gate, the second logic subcircuit includes a NOR gate, and the third logic subcircuit includes an AND gate, wherein:

[0034] The first input terminal of the OR gate is connected to the output terminal of the sampling circuit, and is used to receive the i-th sampling instruction signal; the second input terminal of the OR gate is used to receive the i-th first control signal; the output terminal of the OR gate is connected to the second input terminal of the NOR gate, and is used to output the i-th first intermediate signal;

[0035] The first input terminal of the NOR gate is used to receive the i-th second control signal; the second input terminal of the NOR gate is used to receive the i-th first intermediate signal; the output terminal of the NOR gate is connected to the second input terminal of the AND gate, and is used to output the i-th second intermediate signal;

[0036] The first input end of the AND gate is used to receive the repair command signal; the second input end of the AND gate is used to receive the i-th second intermediate signal; and the output end of the AND gate is used to output the i-th repair indication signal.

[0037] In some embodiments, N=4, M=1, the N control subcircuits include a first subcircuit, a second subcircuit, a third subcircuit, and a fourth subcircuit, and the first subcircuit serves as the shared circuit, and the second subcircuit, the third subcircuit, and the fourth subcircuit serve as the non-shared circuit; wherein:

[0038] The output end of the mode selection circuit is connected to the second sub-circuit, the third sub-circuit and the fourth sub-circuit respectively, and is used to send the start signal to the second sub-circuit, the third sub-circuit and the fourth sub-circuit.

[0039] In some embodiments, the repair shared circuit further comprises:

[0040] a register circuit, configured to set N of the status indication signals and send the N of the status indication signals to the N of the control sub-circuits respectively;

[0041] When the i-th state indication signal is in an enabled state, it indicates that the repair resource corresponding to the i-th control subcircuit is available, where i is an integer greater than 0 and less than or equal to N.

[0042] In some embodiments, the first repair operation includes test post-packaging repair (MPPR), and the second repair operation includes hard post-packaging repair (HPPR).

[0043] In some embodiments, the preset clock signal is generated according to the repair command signal and the initial clock signal.

[0044] In a second aspect, an embodiment of the present disclosure provides a repair sharing method, which is applied to the repair sharing circuit as described in any one of the first aspects, the method comprising:

[0045] Receiving a preset clock signal and an enable signal through the mode selection circuit, performing latch processing according to the preset clock signal and the enable signal, and generating a start signal;

[0046] The repair control circuit receives the start signal and N status indication signals, performs logic processing according to the start signal and the N status indication signals, and outputs N repair indication signals respectively through the N control subcircuits, each of the status indication signals being used to indicate whether a repair resource corresponding to the corresponding control subcircuit is available;

[0047] Among them, when the start signal is in an enabled state and the repair indication signal output by the first control sub-circuit in the shared circuit is in an enabled state, a first repair operation is performed according to the repair resources corresponding to the first control sub-circuit, and the first control sub-circuit is any one of the M control sub-circuits.

[0048] In a third aspect, an embodiment of the present disclosure provides a memory comprising a repair sharing circuit as described in any one of the first aspects.

[0049] Embodiments of the present disclosure provide a repair sharing circuit, a repair sharing method, and a memory. The repair sharing circuit includes a mode selection circuit and a repair control circuit. The repair control circuit includes N control sub-circuits, M of the N control sub-circuits serving as shared circuits, each control sub-circuit corresponding to a repair resource, N and M being integers greater than 0, and M being less than N. The mode selection circuit is configured to receive a preset clock signal and an enable signal, perform latching processing based on the preset clock signal and the enable signal, and generate a start signal. The repair control circuit is configured to receive the start signal and N status indication signals, perform logical processing based on the start signal and the N status indication signals, and output N repair indication signals through the N control sub-circuits, each status indication signal being configured to indicate whether a repair resource corresponding to its corresponding control sub-circuit is available. When the start signal is in an enabled state and the repair indication signal output by the first control sub-circuit in the shared circuit is in an enabled state, a first repair operation is performed based on the repair resource corresponding to the first control sub-circuit, where the first control sub-circuit is any one of the M control sub-circuits. Thus, in the embodiment of the present disclosure, the mode selection circuit latches the enable signal using a preset clock signal, obtains a start signal and sends it to the repair control circuit. If the start signal is in an enabled state, it indicates that it is necessary to control the execution of the first repair operation, thereby combining the status indication signal, and the first control sub-circuit in the shared circuit will output a repair indication signal in an enabled state to perform the first repair operation using the corresponding repair resources; if the start signal is in a non-enabled state, it indicates that it is necessary to control the execution of the second repair operation, thereby combining the status indication signal, and the second control sub-circuit in the repair control circuit will output a repair indication signal in an enabled state to perform the second repair operation using the corresponding repair resources; thereby, when resources are limited, the control of the enable signal allows the first repair operation and the second repair operation to share the repair resources, which is beneficial to the integration of the memory and saves costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic diagram of the structure of an HPPR circuit provided by an embodiment of the present disclosure;

[0051] FIG2 is a schematic diagram of a structure of a repair sharing circuit according to an embodiment of the present disclosure;

[0052] FIG3 is a second structural diagram of a repair sharing circuit provided by an embodiment of the present disclosure;

[0053] FIG4 is a detailed structural diagram of a repair sharing circuit provided by an embodiment of the present disclosure;

[0054] FIG5 is a detailed structural diagram of a control subcircuit provided in an embodiment of the present disclosure;

[0055] FIG6 is a schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure;

[0056] FIG7 is a schematic diagram of a flow chart of a repair sharing method provided by an embodiment of the present disclosure;

[0057] FIG8 is a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0060] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0061] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0062] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0063] Post Package Repair (PPR)

[0064] Soft Post Package Repair (SPPR);

[0065] Hard Post Package Repair (HPPR);

[0066] Memory Built-In Self-Test (MBIST);

[0067] MBIST Post Package Repair (MPPR);

[0068] Dynamic Random Access Memory (DRAM);

[0069] D flip-flop (DFF);

[0070] Standard (SPEC);

[0071] Activation (ACT);

[0072] Row Address (RA);

[0073] Double Data Rate (DDR);

[0074] Mode Register (MR);

[0075] Bank (BK);

[0076] Bank Group (BG);

[0077] Most Significant Bit (MSB);

[0078] Write w / Auto Pre-charge (WRA);

[0079] Burst Length 16WRA (BL16WRA)

[0080] Data (DQ);

[0081] Row Address Select (RAS);

[0082] Column Address Select (CAS);

[0083] tRCD (RAS to CAS delay time).

[0084] FIG1 is a schematic diagram illustrating the structure of an HPPR circuit provided in an embodiment of the present disclosure. As shown in FIG1 , the HPPR circuit 10 includes four PPR sub-circuits: PPR Info 0, PPR Info 1, PPR Info 2, and PPR Info 3. The output of PPR Info 0 is connected to an input of PPR Info 1, the output of PPR Info 1 is connected to an input of PPR Info 2, and the output of PPR Info 2 is connected to an input of PPR Info 3. The specific components of each PPR Info are shown in the dotted box on the left side of FIG1 .

[0085] As shown in Figure 1, each PPR Info includes a flip-flop DFF, a NOR gate, and an AND gate. The DFF's input terminal D receives the PPR_unused signal, which indicates whether the PPR resource is available. The DFF's clock terminal CK receives the clock signal LatClk. The DFF can sample and latch the PPR_unused signal based on the clock signal LatClk, output the PPR_cur_ok_n signal at its inverting output terminal Qn, and send the PPR_cur_ok_n signal to the NOR gate. The NOR gate also receives the PPR_pre_ok signal. The output of the NOR gate is connected to the AND gate, and the NOR result of the PPR_pre_ok signal and the PPR_cur_ok_n signal is sent to the AND gate. The AND gate also receives the PPR_cmd signal and outputs the PPR_ok signal.

[0086] For PPR Info, the PPR_unused signal is used to indicate whether the PPR resources corresponding to the PPR Info are available, wherein the PPR resources are circuits for performing PPR operations, etc., and the PPR_unused signal can be provided or generated by a mode register; if the PPR_unused signal is logic 1 (high level), it indicates that the PPR resources corresponding to the PPR Info are available; if the PPR_unused signal is logic 0 (low level), it indicates that the PPR resources corresponding to the PPR Info are unavailable; the clock signal LatLck can be generated according to the PPR_cmd signal, wherein when the PPR_cmd signal is 1, the HPPR circuit 10 enters the repair working state, a pulse is generated in the clock signal LatClk, and the trigger DFF samples and latches the PPR_unused signal according to the rising edge of the clock signal LatClk. Since the PPR_cur_ok_n signal is the output signal of the inverting output terminal Qn of the trigger DFF, the level state of the PPR_cur_ok_n signal output after sampling is opposite to the level state of the PPR_unused signal.

[0087] The PPR_ok signal is used to indicate whether the HPPR operation is performed using the corresponding PPR resources. If the PPR_ok signal is logic 1, it indicates that the HPPR operation is performed using the corresponding PPR resources. If the PPR_ok signal is logic 0, it indicates that the HPPR operation is not performed using the corresponding PPR resources. The PPR_pre_ok signal is the PPR_ok signal output by the previous PPR Info. For PPR Info 0, there is no previous PPR Info, and the PPR_pre_ok0 signal it receives is the GND signal (logic 0), that is, the ground connection; in PPR Info1 / 2 / 3, the PPR_pre_ok1 / 2 / 3 signal is the PPR_ok0 / 1 / 2 signal output by the previous PPR Info.

[0088] Thus, for the HPPR circuit 10, the availability of the PPR resources corresponding to each PPR Info is determined sequentially from PPR Info 0 to PPR Info 4. In short, for HPPR, four HPPR resources can be allocated to each half bank (the HPPR resource corresponding to PPR Info 0 is HPPR 0, the HPPR resource corresponding to PPR Info 1 is HPPR 1, the HPPR resource corresponding to PPR Info 2 is HPPR 2, and the HPPR resource corresponding to PPR Info 3 is HPPR 3). In conjunction with FIG1 , when performing a repair, each HPPR resource has the following priority order: HPPR0>HPPR1>HPPR2>HPPR3, which means: first check whether HPPR0 is available? If so, use HPPR0 for repair; otherwise, check whether HPPR1 is available? If so, use HPPR1 for repair...

[0089] MPPR can be used after MBIST to repair faults found during the self-test phase. For HPPR and MPPR, it is possible to completely separate the HPPR / MPPR resources and control to achieve these two functions. However, this will inevitably result in more circuit consumption and control difficulties, resulting in an increase in chip area, which is not conducive to chip integration and is costly.

[0090] Based on this, the embodiment of the present disclosure provides a repair sharing circuit for realizing that when resources are limited, the HPPR and MPPR can share repair resources by controlling the enable signal, thereby facilitating the integration of memory and saving costs.

[0091] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0092] In one embodiment of the present disclosure, referring to FIG2 , a schematic diagram of the structure of a repair sharing circuit provided in an embodiment of the present disclosure is shown. As shown in FIG2 , the repair sharing circuit 20 includes: a mode selection circuit 21 and a repair control circuit 22 . The repair control circuit 22 includes N control subcircuits 23 , M of which serve as shared circuits 24 . Each control subcircuit 23 corresponds to a repair resource, where N and M are both integers greater than 0, and M is less than N.

[0093] The mode selection circuit 21 is used to receive a preset clock signal and an enable signal, perform latching processing according to the preset clock signal and the enable signal, and generate a start signal;

[0094] The repair control circuit 22 is configured to receive a start signal and N status indication signals, perform logic processing based on the start signal and the N status indication signals, and output N repair indication signals through the N control sub-circuits 23. Each status indication signal is configured to indicate whether the repair resource corresponding to the corresponding control sub-circuit 23 is available.

[0095] When the start signal is in an enabled state and the repair indication signal output by the first control subcircuit in the shared circuit 24 is in an enabled state, a first repair operation is performed according to the repair resource corresponding to the first control subcircuit, where the first control subcircuit is any one of the M control subcircuits 23;

[0096] When the start signal is in the disabled state and the repair indication signal output by the second control subcircuit in the repair control circuit 22 is in the enabled state, the second repair operation is performed according to the repair resource corresponding to the second control subcircuit, and the second control subcircuit is any one of the N control subcircuits 23.

[0097] It should be noted that, as shown in Figure 2, the embodiment of the present disclosure provides a repair sharing circuit 20, based on which both the first repair operation and the second repair operation can be implemented. In this embodiment, the mode when performing the first repair operation can be recorded as the first repair mode, and the mode when performing the second repair operation can be recorded as the second repair mode. Taking the first repair operation as MPPR and the second repair operation as HPPR as an example, this scheme is described in detail. The first repair mode is the MPPR mode and the second repair mode is the HPPR mode, but it can also be the opposite, or other repair operations, and there is no specific limitation on this. In this way, the subsequent repair resources (PPR resources) involved can all be HPPR resources.

[0098] Among them, regarding HPPR, the standard stipulates: Using HPPR, DDR5 can correct at least one row address for each BG. The HPPR resource designation (MR54, 55, 56, 57) will indicate the resource availability of HPPR and can be read / checked before implementing the repair. It should be noted that HPPR repair is permanent, and once the fuse is programmed, it cannot be switched back to the unblown state. The controller should prevent accidental entry into HPPR mode to perform repairs (i.e., during command / address training). Entering HPPR is enabled through the register, and the ACT command is used to transmit the BK address and row address of the row to be replaced in the DRAM. For non-binary density, ACT commands with invalid row addresses (both MSB and MSB-1 address bits are "high") are not allowed because it may consume PPR resources. After the tRCD time, the BL16WRA command is used to select a single DRAM through the DQ bit and transmit the repair address to the DRAM.

[0099] Regarding MPPR, the standard states: MBIST-PPR (MPPR) can be used after MBIST to repair faults found during the self-test phase. MPPR can be performed only after reading the MR22 MBIST / MPPR completion level, and the MR22 MBIST / MPPR completion level must be read after MPPR completion to determine whether additional MPPR or MBIST is required. If a failure occurs, it is retained after reading the MR22 completion level.

[0100] It should also be noted that, in this embodiment, M control sub-circuits 23 out of the N control sub-circuits 23 constitute a shared circuit 24 , and the remaining NM control sub-circuits 23 constitute a non-shared circuit 25 . In FIG2 , in order of numbering, the example is taken in which the 1st control subcircuit 23 (control subcircuit 0) to the Mth control subcircuit 23 (control subcircuit M-1) form a shared circuit 24, and the M+1th control subcircuit 23 (control subcircuit M) to the Nth control subcircuit 23 (control subcircuit N-1) form a non-shared circuit 25. In other embodiments, other division methods may be used, for example, the 1st control subcircuit 23 to the NMth control subcircuit 23 form a non-shared circuit 25, and the N-M+1th control subcircuit 23 to the Nth control subcircuit 23 form a shared circuit 24. Alternatively, M control subcircuits 23 may be selected from the N control subcircuits 23 according to a certain rule or randomly to form the shared circuit 24, and the remaining NM control subcircuits 23 form the non-shared circuit 25. There is no specific limitation on this.

[0101] As shown in Figure 2, the mode selection circuit 21 controls whether to execute the first or second repair operation based on the enable signal and the preset clock signal. If the enable signal is in the enabled state, it indicates entering the first repair mode and executing the first repair operation. If the enable signal is in the disabled state, it indicates entering the second repair mode and executing the second repair operation. The preset clock signal is used to control whether to sample the enable signal. This control is meaningful only when the state of the enable signal is sampled and latched.

[0102] The mode selection circuit 21 is a circuit with sampling and latching functions, so that the mode selection circuit 21 can sample and latch the state of the enable signal according to the preset clock signal, obtain the start signal and then pass it to the repair control circuit 22 to perform the corresponding repair operation.

[0103] Each control subcircuit 23 receives a corresponding status indication signal, which is used to indicate whether the repair resource corresponding to the corresponding control subcircuit 23 is available; if the status indication signal is in an enabled state, it means that the repair resource corresponding to the corresponding control subcircuit 23 is available, so that the repair operation can be performed using the repair resource; if the status indication signal is in a disabled state, it means that the repair resource corresponding to the corresponding control subcircuit 23 is unavailable, so that the repair operation cannot be performed using the repair resource.

[0104] The output of the mode selection circuit 21 is connected to each control sub-circuit 23 in the non-shared circuit 25. Specifically, in the repair control circuit 22, a start signal is sent to each of the NM control sub-circuits 23 in the non-shared circuit 25. If the enable signal is in the enabled state, the start signal obtained by sampling and latching is in the enabled state. At this time, the start signal "turns off" these NM control sub-circuits 23 in the non-shared circuit 25. This causes the repair indication signal output by the control sub-circuit 23 in the non-shared circuit 25 to be in the disabled state, regardless of whether the status indication signal is in the enabled or disabled state. Consequently, repair operations are not performed using these control sub-circuits 23 in the non-shared circuit 25. Simultaneously, the M control sub-circuits 23 in the shared circuit 24 do not receive the start signal. Among these M control sub-circuits 23 in the shared circuit 24, one control sub-circuit 23 (referred to as the first control sub-circuit) outputs an enabled repair indication signal, indicating that the first repair operation is to be performed using the repair resources corresponding to the first control sub-circuit.

[0105] If the enable signal is in the disabled state, the start signal obtained by sampling and latching is also in the disabled state. At this time, the start signal will not "turn off" the NM control sub-circuits 23 in the shared circuit 24; in this case, one of the N control sub-circuits 23 (referred to as the second control sub-circuit) will output a repair indication signal in the enabled state, indicating that the second repair operation is performed using the repair resources corresponding to the second control sub-circuit.

[0106] That is, the start signal starts the first repair operation, and its function is to control the control sub-circuit 23 receiving the start signal not to start, so that the control sub-circuit 23 that does not receive the start signal can be used to perform the first repair operation.

[0107] Thus, the disclosed embodiment utilizes a preset clock signal to sample and latch the enable signal, generating a start signal. Based on whether the start signal is enabled and whether the repair resource corresponding to the control sub-circuit 23 is available, if the start signal is enabled, the repair resource corresponding to one of the control sub-circuits 23 in the shared circuit 24 is selected to perform the first repair operation. If the start signal is disabled, the repair resource corresponding to one of the N control sub-circuits 23 is selected to perform the second repair operation. Thus, the M control sub-circuits 23 in the shared circuit 24 can be used for both the first and second repair operations, i.e., they are "shared," while the control sub-circuits 23 in the non-shared circuit 25 are used only to perform the second repair operation, i.e., they are "unshared."

[0108] Based on Figure 2, refer to Figure 3, which shows a schematic diagram of the composition structure of another repair sharing circuit provided by an embodiment of the present disclosure. As shown in Figure 3, in some embodiments, the i-th control subcircuit 23 is used to receive the i-th first control signal, the i-th second control signal, the i-th status indication signal and the repair command signal; perform logical processing based on the i-th first control signal, the i-th second control signal, the i-th status indication signal and the repair command signal to generate the i-th repair indication signal; wherein, i is an integer greater than 0 and less than or equal to N, and when i is greater than 0 and less than N, the output end of the i-th control subcircuit 23 is connected to the i+1-th control subcircuit 23; if the i-th control subcircuit 23 belongs to the shared circuit 24, the i-th first control signal is a preset signal, and if the i-th control subcircuit 23 belongs to the non-shared circuit 25, the i-th first control signal is a start signal; when i is equal to 1, the 1-th second control signal is a preset signal, and when i is greater than 1 and less than or equal to N, the i-th second control signal is the i-1-th repair indication signal;

[0109] Among them, when the i-th first control signal is in the enabled state and the control sub-circuit 23 belongs to the non-shared circuit 25, the i-th repair indication signal is in the disabled state; when the i-th first control signal is in the enabled state and the control sub-circuit 23 belongs to the shared circuit 24, or when the i-th first control signal is in the disabled state, if the i-th state indication signal is in the enabled state, the i-th second control signal is in the disabled state, and the repair command signal is in the enabled state, the i-th repair indication signal is in the enabled state.

[0110] It should be noted that, as shown in FIG3 , the N control subcircuits 23 are connected in series, and the output terminals of control subcircuits 0 to N-2 are all connected to an input terminal of the next control subcircuit 23, thereby transmitting the repair instruction signal as the second control signal of the next control subcircuit 23 to the next control subcircuit 23. In other words, the repair instruction signal output by the previous control subcircuit 23 will affect the next control subcircuit 23. Specifically, this effect can be as follows: only when the (i-1)th repair instruction signal is in the disabled state is it necessary to determine the state of the (i-1)th repair instruction signal; if the (i-1)th repair instruction signal is in the enabled state, the repair operation is directly performed using the repair resources corresponding to the (i-1)th control subcircuit 23.

[0111] As shown in FIG3 , each control subcircuit 23 may include at least four input terminals and one output terminal. The control subcircuit 23 performs logic processing according to the signals it receives to generate corresponding repair indication signals.

[0112] Based on the series relationship between the N control subcircuits 23, for the i-th control subcircuit 23, the i-th second control signal it receives is the i-1-th repair control signal output by the i-1-th control subcircuit 23; for the first control subcircuit 23 (control subcircuit 0 in Figure 3), since there is no previous control subcircuit, the first second control signal received by control subcircuit 0 is a preset signal in a fixed level state, and the state of the preset signal is opposite to the level state of the repair indication signal in the enabled state; for example: if the repair indication signal is in the enabled state at logic 1, the preset signal is fixed to logic 0; if the repair indication signal is in the enabled state at logic 0, the preset signal is fixed to logic 1. The second control signal is used to instruct the control subcircuit 23 whether to determine the availability of its corresponding repair resource. Specifically, if the i-th repair indication signal is in the enabled state, it indicates that the repair resource corresponding to the i-th control subcircuit 23 is used to perform the repair operation, and there is no need to determine whether the repair resources corresponding to subsequent control subcircuits 23 are available. In this case, the (i+1)-th to (N)-th control subcircuits 23 are all configured to output repair indication signals in the disabled state. Alternatively, if one or more of the (i+1)-th to (N)-th control subcircuits 23 output repair indication signals in the enabled state, a shielding mechanism may be provided to shield redundant repair indication signals, thereby ensuring that when performing the first repair operation, the control subcircuit 23 that outputs the repair indication signal in the enabled state earliest is determined as the aforementioned first control subcircuit or second control subcircuit according to the priority order of the first to (M)-th control subcircuits 23, and when performing the second repair operation, the control subcircuit 23 that outputs the repair indication signal in the enabled state earliest is determined as the aforementioned first control subcircuit or second control subcircuit according to the priority order of the first to (N)-th control subcircuits 23, and the repair operation is performed using the corresponding repair resource.

[0113] In the embodiment of the present disclosure, taking the example of the repair indication signal being in an enabled state at logic 1, the preset signal can be a ground signal GND (logic 0), and the input terminal of the control sub-circuit 0 is connected to the ground. Logic 1 can be recorded as a first level state, and logic 0 can be recorded as a second level state.

[0114] It should also be noted that the status indication signal is used to indicate the availability of the repair resources corresponding to the corresponding control subcircuit 23; the enabled state of the status indication signal can be logic 1 or logic 0, with logic 1 being used as an example here. When the status indication signal is in the enabled state, it indicates that the repair resources corresponding to the corresponding control subcircuit 23 are available; when the status indication signal is in the disabled state, it indicates that the repair resources corresponding to the corresponding control subcircuit 23 are unavailable.

[0115] The first control signal indicates whether the corresponding control subcircuit 23 needs to perform a repair operation. The enable state of the first control signal can be logic 1 or logic 0, with logic 1 being taken as an example here. When the first control signal is in a non-enabled state, it indicates that the repair resource corresponding to the corresponding control subcircuit 23 needs to perform a repair operation (whether to perform it specifically needs to be determined in combination with other signals). When the first control signal is in an enabled state, it indicates that the repair resource corresponding to the corresponding control subcircuit 23 does not need to perform a repair operation. In the shared circuit 24, whether for the first repair operation or the second repair operation, the repair resource corresponding to each control subcircuit 23 needs to be used as a backup resource for performing the first repair operation. Therefore, the first control signal received by each control subcircuit 23 in the shared circuit 24 is always in a non-enabled state. Since in the embodiment of the present disclosure, taking the first control signal as an enabled state when logic 1 as an example, the first control signal received by the control subcircuit 23 in the shared circuit 24 can be a ground signal GND, so that the input end of the control subcircuit 0 to the control subcircuit M-1 is grounded. In the non-shared circuit 25, the first control signal received by each control sub-circuit 23 is the aforementioned start signal. Based on the state of the start signal and in combination with the states of other signals, it is determined whether the repair resources corresponding to each control sub-circuit 23 in the non-shared circuit 25 are used to perform the repair operation; in this way, if the start signal received by the control sub-circuit 23 in the non-shared circuit 25 is in the enabled state, it means that the repair resources corresponding to the control sub-circuit 23 are not used to perform the repair operation, and a repair indication signal in a disabled state is output; if the start signal received by the control sub-circuit 23 in the non-shared circuit 25 is in the disabled state, it means that the repair resources corresponding to the control sub-circuit 23 are used as backup resources for performing the repair operation, and it is necessary to output a repair indication signal in combination with other signals.

[0116] The repair command signal is used to indicate whether the repair shared circuit 20 is currently in a repair state. Only when the repair command signal is in an enabled state does it indicate that the repair shared circuit 20 is in a repair state, and only then will the repair operation be performed in combination with other signals; otherwise, if the repair command signal is in a disabled state, the N repair indication signals are all in a disabled state.

[0117] Thus, when the start signal is in the enabled state, corresponding to the first repair mode for executing the first repair operation, the control subcircuits 23 in the non-shared circuit 25 are all turned off by the first control signal (start signal), while in the shared circuit 24, the first control signal (preset signal GND) is always in the disabled state. If, among the signals received by the i-th control subcircuit 23, the second control signal (i-1th repair indication signal) is in the disabled state (indicating that the repair resource corresponding to the i-1th control subcircuit 23 is not used to perform the repair operation), the status indication signal is in the enabled state (indicating that the repair resource corresponding to the i-th control subcircuit 23 is available), and the repair command signal is in the enabled state (indicating that the repair shared circuit 20 is in the repair working state), when all these conditions are met, it means that the repair resource corresponding to the i-th control subcircuit 23 can be used to perform the repair operation, and thus the i-th control subcircuit 23 outputs the i-th repair indication signal in the enabled state. The same applies when the start signal is in the disabled state, which will not be elaborated here.

[0118] The disclosed embodiment utilizes the status indication signal, the first control signal, the second control signal, and the repair command signal to cause the control subcircuit 23 to output a repair indication signal to execute a repair operation. Depending on the status of the initiation signal, the first repair operation is executed using the repair resources corresponding to the shared circuit 24, or the second repair operation is executed using the repair resources corresponding to the repair control circuit 22, thereby enabling resource sharing for both the first and second repair operations.

[0119] As shown in FIG3 , the repair sharing circuit 20 may further include:

[0120] The register circuit 26 is used to set N status indication signals and send the N status indication signals to the N control sub-circuits 23 respectively;

[0121] When the i-th state indication signal is in the enabled state, it indicates that the repair resource corresponding to the i-th control subcircuit 23 is available, where i is an integer greater than 0 and less than or equal to N.

[0122] It should be noted that, as shown in FIG3 , register circuit 26 can be configured to provide status indication signals indicating the availability of various repair resources. Here, register circuit 26 can include MR54, 55, 56, and 57 in the DRAM. For example, Table 1 shows the corresponding information between the operands (OP[0]-OP[7]) of MR54 and the repair resources (HPPR Resource), and Table 2 shows the register definition of MR54.

[0123] Table 1

[0124] Table 2

[0125] In this way, the register circuit 26 can convert the data shown in Table 2 to obtain a corresponding status indication signal, thereby controlling the operation performed by the repair sharing circuit 20 .

[0126] It should also be noted that in order to ensure the reliability of the repair control circuit 22, in the first operating mode, the register circuit 26 can set only one of the M status indication signals corresponding to the shared circuit 24 to be in an enabled state. In the second operating mode, the register circuit 26 can set only one of the N status indication signals to be in an enabled state, so that among the available alternative resources, only the repair resource corresponding to one control sub-circuit 23 is in an available state. In this way, it is avoided that multiple control sub-circuits 23 output repair indication signals in an enabled state, causing errors.

[0127] Below, taking N=4 and M=1 as an example, refer to Figure 4, which shows a detailed structural diagram of a repair shared circuit provided by an embodiment of the present disclosure. As shown in Figure 4, the N control subcircuits include a first subcircuit (PPR Info 0), a second subcircuit (PPR Info 1), a third subcircuit (PPR Info 2), and a fourth subcircuit (PPR Info 3), and the first subcircuit (PPR Info 0) serves as a shared circuit, and the second subcircuit (PPR Info 1), the third subcircuit (PPR Info 2), and the fourth subcircuit (PPR Info 3) serve as non-shared circuits; wherein:

[0128] The output end of the mode selection circuit 21 is respectively connected to the second sub-circuit (PPR Info 1), the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3), and is used to send a start signal to the second sub-circuit (PPR Info 1), the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3).

[0129] As shown in FIG4 , the mode selection circuit 21 includes a latch LAT, wherein:

[0130] The first input terminal of the latch LAT is used to receive the enable signal mppr_n, the second input terminal of the latch LAT is used to receive the preset clock signal LatClk, the output terminal of the latch LAT is used to output the start signal mppr_on, and the output terminal of the latch LAT is respectively connected to each control sub-circuit in the non-shared circuit.

[0131] As shown in FIG4 , the latch LAT further includes a reset terminal, which is used to receive a reset signal Reset_n, wherein:

[0132] The latch LAT is used for controlling the start signal mppr_on to be reset to a non-enabled state when the reset signal Reset_n is in an enabled state.

[0133] It should be noted that, taking the repair control circuit 22 including four control sub-circuits as an example, as shown in Figure 4, the first sub-circuit (PPR Info 0) is a shared circuit, and the corresponding repair resource is PPR0. The first first control signal and the first second control signal it receives are both ground signals GND, the first status indication signal received is recorded as PPR_unused0, and the first status indication signal output is recorded as PPR_ok0. The second sub-circuit (PPR Info 1), the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3) are non-shared circuits, and the corresponding repair resources are PPR1, PPR2 and PPR3 respectively; the second first control signal received by the second sub-circuit (PPR Info 1) is the start signal mppr_on, the second second control signal received is PPR_pre_ok1 (i.e., PPR_ok0), the second status indication signal received is recorded as PPR_unused1, and the second status indication signal output is recorded as PPR_ok1. The same applies to the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3), and no further details are given.

[0134] In this embodiment, four repair resources may be allocated to each half Bank in the memory, but other allocation methods may also be used, which are not specifically limited here.

[0135] As shown in FIG4 , the second sub-circuit (PPR Info 1), the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3) all receive the start signal mppr_on and are controlled thereby to determine whether to perform a repair operation according to the start signal mppr_on.

[0136] The mode selection circuit 21 may be implemented by a latch LAT, wherein the latch LAT includes a first input terminal, a second input terminal, a reset terminal, and an output terminal. The reset signal Reset_n is used to reset the start signal mppr_on output by the latch LAT. For example, the reset signal Reset_n can be a low-level (logic 0) valid signal. In this way, when the level state of Reset_n is logic 0, regardless of the state of the enable signal mppr_n and the preset clock signal LatClk, the start signal mppr_on will be reset to a non-enabled state (logic 0); when the level state of the reset signal Reset_n is logic 1 (high level), when the clock edge of the preset clock signal LatClk arrives, the latch LAT can sample and latch the enable signal mppr_n according to the preset clock signal LatClk to obtain the start signal mppr_on. Here, the enable signal mppr_n can be a low-level valid signal, that is, when the enable signal mppr_n is logic 0, it indicates that it is in the enabled state. After sampling and latching by the latch LAT, a high-level start signal mppr_on is obtained, indicating that the start signal mppr_on is in the enabled state.

[0137] The preset clock signal LatClk may be generated based on the repair command signal and the initial clock signal. The initial clock signal may be a system clock or other signal. The preset clock signal LatClk may be generated based on a logical AND operation performed on the repair command signal and the initial clock signal. When the repair command signal PPR_cmd is enabled, the preset clock signal LatClk generates a short pulse, which serves as a sampling clock for the latch LAT and the control sub-circuit 23.

[0138] Furthermore, the latch LAT can be a latch composed of NAND gates. As shown in FIG4 , the latch LAT includes a first NAND gate NA1 and a second NAND gate NA2 , wherein:

[0139] The first input terminal of the first NAND gate NA1 serves as the first input terminal of the latch LAT, and is used to receive the enable signal mppr_n;

[0140] The second input terminal of the first NAND gate NA1 is connected to the output terminal of the second NAND gate NA2;

[0141] The output end of the first NAND gate NA1 serves as the output end of the latch LAT, and is used to output the start signal mppr_on. The output end of the first NAND gate NA1 is connected to the first input end of the second NAND gate NA2.

[0142] The second input terminal of the second NAND gate NA2 serves as the second input terminal of the latch LAT, for receiving the preset clock signal LatClk;

[0143] The third input terminal of the second NAND gate NA2 serves as a reset terminal of the latch LAT, and is used to receive a reset signal Reset_n.

[0144] It should be noted that, taking the first repair operation as MPPR and the second repair operation as HPPR as an example, the enable signal mppr_n is in the enabled state to indicate starting the MPPR, and the enable signal mppr_n is sampled and latched to obtain the start signal mppr_on to control the non-shared circuit to be turned off.

[0145] For each control subcircuit 23, see FIG5 , which shows a detailed structural diagram of a control subcircuit provided by an embodiment of the present disclosure. As shown in FIG5 , the i-th control subcircuit 23 includes a sampling circuit 231, a first logic subcircuit 2321, a second logic subcircuit 2322, and a third logic subcircuit 2323, wherein:

[0146] The sampling circuit 231 is configured to receive the i-th state indication signal PPR_unused i-1 and a preset clock signal LatClk, sample the i-th state indication signal PPR_unused i-1 according to the preset clock signal LatClk, and generate an i-th sampling indication signal PPR_cur_ok_n i-1; the state of the i-th sampling indication signal PPR_cur_ok_n i-1 is opposite to the state of the i-th state indication signal PPR_unused i-1;

[0147] The first logic sub-circuit 2321 is configured to receive the i-th sampling indication signal PPR_cur_ok_n i-1 and the i-th first control signal (mppr_on or GND); perform logic processing on the i-th sampling indication signal PPR_cur_ok_n i-1 and the i-th first control signal (mppr_on or GND) to generate an i-th first intermediate signal; when the i-th first control signal (mppr_on) is in an enabled state, the i-th first intermediate signal is in an enabled state; and when the i-th first control signal (mppr_on or GND) is in a disabled state, the state of the i-th first intermediate signal is the same as the state of the i-th sampling indication signal PPR_cur_ok_n i-1;

[0148] The second logic sub-circuit 2322 is configured to receive the i-th first intermediate signal and the i-th second control signal (PPR_pre_ok i-1 or GND); perform logic processing on the i-th first intermediate signal and the i-th second control signal (PPR_pre_ok i-1 or GND) to generate an i-th second intermediate signal; when the i-th first intermediate signal is in an enabled state, the i-th second intermediate signal is in a disabled state; and when the i-th first intermediate signal is in a disabled state, the state of the i-th second intermediate signal is opposite to the state of the i-th second control signal (PPR_pre_ok i-1 or GND);

[0149] The third logic sub-circuit 2323 is used to receive the i-th second intermediate signal and the repair command signal PPR_cmd; perform logic processing based on the i-th second intermediate signal and the repair command signal PPR_cmd to generate the i-th repair indication signal PPR_ok i-1; wherein, when the i-th second intermediate signal and the repair command signal PPR_cmd are both in the enabled state, the i-th repair indication signal PPR_ok i-1 is in the enabled state; otherwise, the i-th repair indication signal PPR_ok i-1 is in the disabled state.

[0150] It should be noted that FIG5 uses a control sub-circuit 23 that is not the first and belongs to the non-shared circuit 25 as an example. If it is a control sub-circuit 23 in the shared circuit 24, the first logic sub-circuit 2321 does not receive the start signal mppr_on, but instead receives the preset signal GND. If it is the first control sub-circuit 23, the second logic sub-circuit 2322 does not receive the previous status indication signal (i.e., PPR_pre_ok i-1), but instead receives the preset signal GND.

[0151] As shown in FIG5 , in the i-th control sub-circuit, the sampling circuit 231 includes a flip-flop DFF, wherein:

[0152] The input terminal D of the flip-flop DFF is used to receive the i-th state indication signal PPR_unused i-1;

[0153] The clock terminal CK of the flip-flop DFF is used to receive a preset clock signal LatClk;

[0154] The output terminal Qn of the flip-flop DFF is used to output the i-th sampling indication signal PPR_cur_ok_n i-1.

[0155] It should be noted that, as shown in FIG5 , the sampling circuit 231 can be specifically implemented by a flip-flop (e.g., a D flip-flop DFF). Here, the sampling circuit 231 further includes a clock terminal CK, and the inverting output terminal Qn of the DFF outputs the i-th sampling indication signal PPR_cur_ok_n i-1. Therefore, the state of the i-th sampling indication signal PPR_cur_ok_n i-1 is opposite to the state indication signal PPR_unused i-1.

[0156] As shown in FIG5 , in the i-th control sub-circuit 23 , the first logic sub-circuit 2321 includes an OR gate OR, the second logic sub-circuit 2322 includes a NOR gate NOR, and the third logic sub-circuit 2323 includes an AND gate AND, wherein:

[0157] A first input terminal of the OR gate OR is used to receive the i-th sampling indication signal PPR_cur_ok_n i-1; a second input terminal of the OR gate OR is used to receive the i-th first control signal (mppr_on / GND); an output terminal of the OR gate OR is connected to the second input terminal of the NOR gate NOR, and is used to output the i-th first intermediate signal;

[0158] A first input terminal of the NOR gate NOR is used to receive the i-th second control signal (PPR_pre_ok i-1 or GND); a second input terminal of the NOR gate NOR is used to receive the i-th first intermediate signal; an output terminal of the NOR gate NOR is connected to the second input terminal of the AND gate AND, and is used to output the i-th second intermediate signal;

[0159] A first input terminal of the AND gate AND is used to receive the repair command signal PPR_cmd; a second input terminal of the AND gate AND is used to receive the i-th second intermediate signal; and an output terminal of the AND gate AND is used to output the i-th repair indication signal PPR_ok i-1.

[0160] In combination with the aforementioned FIG. 4 and FIG. 5 , on this basis, refer to FIG. 6 , which shows a signal timing diagram provided by an embodiment of the present disclosure. As shown in FIG6 , it is a signal timing corresponding to a control subcircuit 23 in the non-shared circuit 25. At time T1, the clock signal LatClk becomes high, the enable signal mppr_n is low (enabled state), and the reset signal Rsset_n is high. Thus, the latch LAT performs a latching process according to the enable signal mppr_n, and obtains the start signal mppr_on (high level) in the enabled state. At this time, for the OR gate OR, since the start signal mppr_on of one of the input signals is high, the first intermediate signal outputted by the OR gate is high regardless of the state of the other input signal. Furthermore, for the NOR gate NOR, since the first intermediate signal of one of its input signals is high, the second intermediate signal outputted by the NOR gate is always low regardless of the state of the other input signal. Furthermore, for the AND gate AND, since the second intermediate signal of one of its input signals is low, the repair indication signal PPR_ok outputted by the AND gate is always low regardless of the state of the other input signal. That is, for the control subcircuit 23 in the non-shared circuit 25, as long as the enable signal mppr_n is at a low level (enabled state), the status indication signal output by the control subcircuit 23 is in a disabled state, thereby ensuring that in the first repair mode, the non-shared circuit 25 is turned off and no repair operation is performed.

[0161] At time T2 , the reset signal Reset_n resets the start signal mppr_on to a low level (disabled state).

[0162] At time T3, the clock signal LatClk becomes high, the enable signal mppr_n is at a high level (disabled state), and the reset signal Reset_n is high, so that the latch LAT performs a latching process according to the enable signal mppr_n, and obtains the start signal mppr_on (low level) in the disabled state; at the same time, the trigger DFF samples and latches the state indication signal PPR_unused at a high level (enabled state) according to the clock signal LatClk, and outputs a sampling indication signal PPR_cur_ok_n at a low level at its inverting output terminal. At this time, for the OR gate OR, since the start signal mppr_on of one of the input signals is low, its output signal is the same as The level state of the other input signal is the same. In Figure 6, the sampling indication signal PPR_cur_ok_n is at a low level, then the first intermediate signal is at a low level (if the sampling indication signal PPR_cur_ok_n is at a high level, then the first intermediate signal is at a high level); further, for the NOR gate, since the first intermediate signal of one of its input signals is at a low level, its output signal is opposite to the level state of the other input signal. In Figure 6, since the second control signal PPR_pre_ok is at a low level, the second intermediate signal is at a high level; and further, for the AND gate AND, the second intermediate signal is at a high level, and the repair command signal is also at a high level (enabled state), so that the output indication signal PPR_ok is at a high level.

[0163] Since the first control signal received by each control sub-circuit 23 in the shared circuit 24 is logic 0, its timing is consistent with the timing of the control sub-circuit 23 in the non-shared circuit 25 when the enable signal mppr_n is 1 (the start signal mppr_on is 0), which will not be described in detail here. That is, when the first control signal (the start signal mppr_on or the preset signal GND) is at a low level (disabled state), for each control sub-circuit 23 in the repair control circuit 22, if the following conditions are met: the repair indication signal PPR_unused is in an enabled state (indicating that the repair resource corresponding to the control sub-circuit 23 is available), the second control signal PPR_pre_ok is in a disabled state (indicating that the repair resource corresponding to the previous control sub-circuit 23 is not performing a repair operation), and the repair command signal PPR_cmd is in an enabled state (indicating that the repair shared circuit 20 is in a repair working state), the control sub-circuit 23 will output an enabled repair indication signal. Otherwise, if any of these conditions are not met, the repair sub-circuit 23 will output a disabled repair indication signal.

[0164] Simulations have shown that the repair sharing circuit 20 can enable HPPR and MPPR to share repair resources.

[0165] In short, the embodiments of the present disclosure provide a circuit for realizing MPPR and HPPR resource sharing, and a simple implementation method is introduced to reduce chip size consumption. That is: MPPR and HPPR share some redundant resources and HPPR exclusively uses some resources. In the example of Figure 4, 4 hPPR resources are allocated to each half Bank. (The priority is: PPR0>PPR 1>PPR 2>PPR 3), where PPR0 is a shared resource that not only executes HPPR but also MPPR, while PPR1 / 2 / 3 is only used for HPPR. This solution introduces a simple but efficient design to realize the sharing of PPR resources between MPPR and HPPR of DDR5, which can achieve SPEC requirements under the limited circuit implementation based on the current HPPR design, thereby reducing design time and size cost.

[0166] In another embodiment of the present disclosure, see FIG7 , which shows a flowchart of a repair and undo method provided by an embodiment of the present disclosure. As shown in FIG7 , the method may include:

[0167] S701: receiving a preset clock signal and an enable signal through a mode selection circuit, performing latch processing according to the preset clock signal and the enable signal, and generating a start signal.

[0168] S702: Receive a start signal and N status indication signals through the repair control circuit, perform logical processing based on the start signal and the N status indication signals, and output N repair indication signals through the N control sub-circuits respectively. Each status indication signal is used to indicate whether the repair resource corresponding to its corresponding control sub-circuit is available.

[0169] Among them, when the start signal is in the enabled state and the repair indication signal output by the first control subcircuit in the shared circuit is in the enabled state, the first repair operation is performed according to the repair resource corresponding to the first control subcircuit, and the first control subcircuit is any one of the M control subcircuits

[0170] It should be noted that the repair sharing method provided in the embodiment of the present disclosure is applied to the repair sharing circuit 20 in the aforementioned embodiment. For details not disclosed in this embodiment, please refer to the description of the aforementioned embodiment for understanding, and no further details will be given here.

[0171] In another embodiment of the present disclosure, referring to Figure 8 , a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure is shown. As shown in Figure 8 , the memory 80 at least includes the repair sharing circuit 20 in the aforementioned embodiment.

[0172] It should be noted that the memory 80 can be a semiconductor memory such as DRAM. For DRAM, it can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., without any limitation here.

[0173] Since the memory 80 includes the repair sharing circuit 20 , the repair sharing function can be realized, and the chip area can be saved, which is beneficial to the integration of the memory and reduces the cost.

[0174] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0175] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0176] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0177] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0178] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0179] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0180] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. Industrial Applicability

[0181] In an embodiment of the present disclosure, the mode selection circuit latches the enable signal using a preset clock signal, obtains a start signal and sends it to the repair control circuit. If the start signal is in an enabled state, it indicates that it is necessary to control the execution of the first repair operation, thereby combining the status indication signal, and the first control sub-circuit in the shared circuit will output a repair indication signal in an enabled state to use the corresponding repair resources to perform the first repair operation; if the start signal is in a non-enabled state, it indicates that it is necessary to control the execution of the second repair operation, thereby combining the status indication signal, and the second control sub-circuit in the repair control circuit will output a repair indication signal in an enabled state to use the corresponding repair resources to perform the second repair operation; thereby, when resources are limited, the control of the enable signal allows the first repair operation and the second repair operation to share the repair resources, which is beneficial to the integration of the memory and saves costs.

Claims

1. A repair sharing circuit (20), comprising a mode selection circuit (21) and a repair control circuit (22), wherein the repair control circuit (22) comprises N control subcircuits (23), wherein M control subcircuits (23) of the N control subcircuits (23) serve as a shared circuit (24), and each of the control subcircuits (23) corresponds to a repair resource, wherein N and M are both integers greater than 0, and M is less than N, wherein: The mode selection circuit (21) is used to receive a preset clock signal (LatClk) and an enable signal (mppr_n), perform latch processing according to the preset clock signal (LatClk) and the enable signal (mppr_n), and generate a start signal (mppr_on); The repair control circuit (22) is used to receive the start signal (mppr_on) and N status indication signals, perform logic processing according to the start signal (mppr_on) and the N status indication signals, and output N repair indication signals respectively through the N control subcircuits (23), each of the status indication signals being used to indicate whether the repair resource corresponding to the corresponding control subcircuit (23) is available; When the start signal (mppr_on) is in an enabled state and the repair indication signal output by the first control subcircuit in the shared circuit (24) is in an enabled state, a first repair operation is performed according to the repair resources corresponding to the first control subcircuit, and the first control subcircuit is any one of the M control subcircuits (23).

2. The repair sharing circuit (20) according to claim 1, wherein: When the start signal (mppr_on) is in a non-enabled state and the repair indication signal output by the second control subcircuit in the repair control circuit (22) is in an enabled state, a second repair operation is performed according to the repair resources corresponding to the second control subcircuit, and the second control subcircuit is any one of the N control subcircuits (23).

3. The repair sharing circuit (20) according to claim 2, wherein: The remaining (NM) control subcircuits (23) of the N control subcircuits (23) serve as non-shared circuits (25), and the mode selection circuit (21) comprises a latch (LAT), wherein: The first input end of the latch (LAT) is used to receive the enable signal (mppr_n), the second input end of the latch (LAT) is used to receive the preset clock signal (LatClk), the output end of the latch (LAT) is used to output the start signal (mppr_on), and the output end of the latch (LAT) is respectively connected to each of the control sub-circuits (23) in the non-shared circuit (25).

4. The repair sharing circuit (20) according to claim 3, wherein: The latch (LAT) further comprises a reset terminal, and the reset terminal is used to receive a reset signal (Rsset_n), wherein: The latch (LAT) is used to control the start signal (mppr_on) to be reset to a non-enabled state when the reset signal (Rsset_n) is in an enabled state.

5. The repair sharing circuit (20) according to claim 4, wherein: The latch (LAT) comprises a first NAND gate (NA1) and a second NAND gate (NA2), wherein: The first input terminal of the first NAND gate (NA1) serves as the first input terminal of the latch (LAT) for receiving the enable signal (mppr_n); The second input terminal of the first NAND gate (NA1) is connected to the output terminal of the second NAND gate (NA2); The output end of the first NAND gate (NA1) serves as the output end of the latch (LAT) for outputting the start signal (mppr_on), and the output end of the first NAND gate (NA1) is connected to the first input end of the second NAND gate (NA2); The second input terminal of the second NAND gate (NA2) serves as the second input terminal of the latch (LAT) for receiving the preset clock signal (LatClk); The third input terminal of the second NAND gate (NA2) serves as a reset terminal of the latch (LAT) and is used to receive the reset signal (Rsset_n).

6. The repair sharing circuit (20) according to any one of claims 3 to 5, wherein: The i-th control subcircuit (23) is used to receive the i-th first control signal, the i-th second control signal, the i-th state indication signal and the repair command signal; The i-th repair indication signal is generated by performing logical processing according to the i-th first control signal, the i-th second control signal, the i-th state indication signal and the repair command signal; wherein i is an integer greater than 0 and less than or equal to N, and when i is greater than 0 and less than N, the output end of the i-th control subcircuit (23) is connected to the i+1-th control subcircuit (23); if the i-th control subcircuit (23) belongs to the shared circuit (24), the i-th first control signal is a preset signal; if the i-th control subcircuit (23) belongs to the non-shared circuit (25), the i-th first control signal is the start signal (mppr_on); when i is equal to 1, the first second control signal is a preset signal; when i is greater than 1 and less than or equal to N, the i-th second control signal is the i-1-th repair indication signal; Wherein, when the i-th first control signal is in an enabled state and the i-th control subcircuit (23) belongs to the non-shared circuit (25), the i-th repair indication signal is in a disabled state; when the i-th first control signal is in an enabled state and the i-th control subcircuit (23) belongs to the shared circuit (24), or when the i-th first control signal is in a disabled state, if the i-th state indication signal is in an enabled state, the i-th second control signal is in a disabled state, and the repair command signal is in an enabled state, the i-th repair indication signal is in an enabled state.

7. The repair sharing circuit (20) according to claim 6, wherein: The i-th control subcircuit (23) comprises a sampling circuit (231), a first logic subcircuit (2321), a second logic subcircuit (2322) and a third logic subcircuit (2323), wherein: The sampling circuit (231) is used for receiving the i-th state indication signal and the preset clock signal (LatClk), sampling the i-th state indication signal according to the preset clock signal (LatClk), and generating an i-th sampling indication signal; the state of the i-th sampling indication signal is opposite to the state of the i-th state indication signal; The first logic subcircuit (2321) is used for receiving the i-th sampling indication signal and the i-th first control signal; performing logic processing according to the i-th sampling indication signal and the i-th first control signal to generate an i-th first intermediate signal; when the i-th first control signal is in an enabled state, the i-th first intermediate signal is in an enabled state, and when the i-th first control signal is in a disabled state, the state of the i-th first intermediate signal is the same as the state of the i-th sampling indication signal; The second logic subcircuit (2322) is used for receiving the i-th first intermediate signal and the i-th second control signal; performing logic processing according to the i-th first intermediate signal and the i-th second control signal to generate the i-th second intermediate signal; when the i-th first intermediate signal is in an enabled state, the i-th second intermediate signal is in a disabled state, and when the i-th first intermediate signal is in a disabled state, the state of the i-th second intermediate signal is opposite to the state of the i-th second control signal; The third logic subcircuit (2323) is used to receive the i-th second intermediate signal and the repair command signal; perform logic processing according to the i-th second intermediate signal and the repair command signal to generate the i-th repair indication signal; wherein, when the i-th second intermediate signal and the repair command signal are both in an enabled state, the i-th repair indication signal is in an enabled state, otherwise, the i-th repair indication signal is in a disabled state.

8. The repair sharing circuit (20) according to claim 7, wherein: In the i-th control subcircuit (23), the sampling circuit (231) comprises a trigger (DFF), wherein: The input end of the trigger (DFF) is used to receive the i-th state indication signal; The clock terminal of the flip-flop (DFF) is used to receive the preset clock signal (LatClk); The output end of the trigger (DFF) is used to output the i-th sampling indication signal.

9. The repair sharing circuit (20) according to claim 7 or 8, wherein: In the i-th control subcircuit (23), the first logic subcircuit (2321) includes an OR gate (OR), the second logic subcircuit (2322) includes a NOR gate (NOR), and the third logic subcircuit (2323) includes an AND gate (AND), wherein: The first input end of the OR gate (OR) is connected to the output end of the sampling circuit (231) for receiving the i-th sampling indication signal; the second input end of the OR gate (OR) is used to receive the i-th first control signal; the output end of the OR gate (OR) is connected to the second input end of the NOR gate (NOR) for outputting the i-th first intermediate signal; The first input end of the NOR gate (NOR) is used to receive the i-th second control signal; the second input end of the NOR gate (NOR) is used to receive the i-th first intermediate signal; the output end of the NOR gate (NOR) is connected to the second input end of the AND gate (AND) to output the i-th second intermediate signal; The first input end of the AND gate (AND) is used to receive the repair command signal; the second input end of the AND gate (AND) is used to receive the i-th second intermediate signal; and the output end of the AND gate (AND) is used to output the i-th repair indication signal.

10. The repair sharing circuit (20) according to any one of claims 6 to 9, wherein: N=4, M=1, the N control subcircuits (23) include a first subcircuit (PPR Info 0), a second subcircuit (PPR Info 1), a third subcircuit (PPR Info 2) and a fourth subcircuit (PPR Info 3), and the first subcircuit (PPR Info 0) serves as the shared circuit (24), and the second subcircuit (PPR Info 1), the third subcircuit (PPR Info 2) and the fourth subcircuit (PPR Info 3) serve as the non-shared circuit (25); wherein: The output end of the mode selection circuit (21) is respectively connected to the second sub-circuit (PPR Info 1), the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3), and is used to send the start signal (mppr_on) to the second sub-circuit (PPR Info 1), the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3).

11. The repair sharing circuit (20) according to any one of claims 1 to 10, wherein: The repair sharing circuit (20) further comprises: A register circuit (26), used for setting N state indication signals and sending the N state indication signals to the N control sub-circuits (23) respectively; Wherein, when the i-th state indication signal is in an enabled state, it indicates that the repair resource corresponding to the i-th control subcircuit (23) is available, where i is an integer greater than 0 and less than or equal to N.

12. The repair sharing circuit (20) according to any one of claims 2 to 10, wherein: The first repair operation includes a test post-packaging repair (MPPR), and the second repair operation includes a hard post-packaging repair (HPPR).

13. The repair sharing circuit (20) according to any one of claims 1 to 12, wherein: The preset clock signal (LatClk) is generated according to the repair command signal and the initial clock signal.

14. A repair sharing method, applied to the repair sharing circuit (20) according to any one of claims 1 to 13, the method comprising: Receiving a preset clock signal (LatClk) and an enable signal (mppr_n) through the mode selection circuit (21), performing latch processing according to the preset clock signal (LatClk) and the enable signal (mppr_n), and generating a start signal (mppr_on); The repair control circuit (22) receives the start signal (mppr_on) and N status indication signals, performs logic processing according to the start signal (mppr_on) and the N status indication signals, and outputs N repair indication signals respectively through the N control subcircuits (23), each of the status indication signals being used to indicate whether the repair resource corresponding to the corresponding control subcircuit (23) is available; When the start signal (mppr_on) is in an enabled state and the repair indication signal output by the first control subcircuit in the shared circuit (24) is in an enabled state, a first repair operation is performed according to the repair resources corresponding to the first control subcircuit, and the first control subcircuit is any one of the M control subcircuits (23).

15. A memory (80) comprising the repair sharing circuit (20) according to any one of claims 1 to 13.

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