Preparation method for semiconductor structure and semiconductor structure

Abstract

Provided are a preparation method for a semiconductor structure and a semiconductor structure. The preparation method for a semiconductor structure comprises: providing a substrate; forming a plurality of landing pad structures arranged at intervals on an array region of the substrate, and forming a first conductive layer on a peripheral region of the substrate, wherein a sacrificial spacer layer is formed on at least one side of each of the landing pad structures, and a gap exists between every two adjacent landing pad structures; forming a dielectric layer on the landing pad structures and the first conductive layer, wherein the dielectric layer covers openings of the gaps; removing the dielectric layer on the array region to expose the gaps; and removing the sacrificial spacer layers to form air gaps.

Description

Semiconductor structure preparation method and semiconductor structure

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on Chinese patent application number 202310870269.4, application date July 14, 2023, and invention name “Method for preparing semiconductor structure and semiconductor structure”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0004] Reducing parasitic bitline capacitance (CBL) in advanced dynamic random access memory (DRAM) processes has always been a challenge and key focus in technology development. Air gaps have significantly improved the parasitic capacitance between the bitline (BL) and the storage node (NC).

[0005] However, in the related process, the process cost of forming the air gap is high, and the effect of the formed air gap is poor.

[0006] Summary of the Invention

[0007] In view of this, embodiments of the present disclosure provide a method for preparing a semiconductor structure and a semiconductor structure.

[0008] According to a first aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising:

[0009] Providing a substrate, the substrate comprising an array region and a peripheral region;

[0010] forming a plurality of landing pad structures arranged at intervals on the array region, and forming a first conductive layer on the peripheral region, wherein a sacrificial spacer layer is formed on at least one side of the landing pad structures; wherein a gap exists between two adjacent landing pad structures;

[0011] forming a dielectric layer on the landing pad structure and the first conductive layer, wherein the dielectric layer covers the opening of the gap;

[0012] forming a second conductive layer on the dielectric layer in the peripheral region;

[0013] removing the dielectric layer in the array area to expose the gap;

[0014] The sacrificial spacer layer is removed to form an air gap.

[0015] In some embodiments, the material of the dielectric layer includes at least one of the following: undoped silica glass, phosphorus-doped silica glass, boron-phosphorus-doped silica glass, undoped spin-coated glass, boron-doped spin-coated glass, phosphorus-doped spin-coated glass, undoped tetraethoxysilane, phosphorus-doped tetraethoxysilane, or boron-doped tetraethoxysilane.

[0016] In some embodiments, the method further comprises:

[0017] Before forming the dielectric layer, forming a first insulating layer covering the surface of the landing pad structure, the top surface of the sacrificial spacer layer, and the first conductive layer; the thickness of the first insulating layer is less than half of the minimum inner diameter of the gap;

[0018] forming the dielectric layer on the first insulating layer, wherein the bottom surface of the dielectric layer is flush with or higher than the top surface of the landing pad structure;

[0019] Before removing the sacrificial spacer layer, at least a portion of the first insulating layer is removed to expose a top surface of the sacrificial spacer layer.

[0020] In some embodiments, removing at least a portion of the first insulating layer to expose a top surface of the sacrificial spacer layer includes:

[0021] A dry etching process is used to remove the first insulating layer covering the top surface of the sacrificial spacer layer and the top surface of the landing pad structure to expose the top surface of the sacrificial spacer layer; alternatively, a wet etching process is used to remove the entire first insulating layer located in the array area to expose the top surface of the sacrificial spacer layer.

[0022] In some embodiments, removing the sacrificial spacer layer to form an air gap comprises:

[0023] The sacrificial spacer layer is removed by a wet etching process to form an air gap.

[0024] In some embodiments, the method further comprises:

[0025] After the air gap is formed, a second insulating layer is formed in the gap between two adjacent landing pad structures, where the second insulating layer covers the opening of the air gap.

[0026] In some embodiments, before forming a plurality of landing pad structures spaced apart on the array area, the method further comprises:

[0027] forming a plurality of bit line structures on the array region, wherein the bit line structures extend along a first direction and a sacrificial spacer is formed on the sidewalls of the bit line structures;

[0028] Contact holes and isolation structures are formed between the bit line structures and are alternately arranged along a first direction, wherein the contact holes expose the substrate; the first direction is parallel to the surface of the substrate;

[0029] A storage node contact plug is formed in the contact hole; and the landing pad structure is located on the storage node contact plug.

[0030] In some embodiments, forming a plurality of landing pad structures spaced apart on the array area includes:

[0031] forming a landing pad material layer on the storage node contact plug, wherein a top surface of the landing pad material layer is higher than a top surface of the bit line structure;

[0032] A portion of the landing pad material layer and a portion of the bit line structure are etched back to form the landing pad structure and the gap located on one side of the landing pad structure, wherein a projection of the landing pad structure on the substrate partially overlaps with a projection of the bit line structure on the substrate.

[0033] In some embodiments, the method further comprises:

[0034] Before forming the second conductive layer, forming a trench penetrating the dielectric layer in the peripheral region, wherein the trench exposes a surface of the first conductive layer;

[0035] A conductive layer contact plug is formed in the trench; the first conductive layer and the second conductive layer are electrically connected through the conductive layer contact plug.

[0036] According to a second aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, including:

[0037] a substrate comprising an array region and a peripheral region;

[0038] a bit line structure located on the array region, the bit line structure extending along a first direction;

[0039] Landing pad structures are located between the bit line structures and are spaced apart along a first direction; the first direction is parallel to the surface of the substrate;

[0040] an air gap located between the landing pad structure and the bit line structure;

[0041] a first conductive layer located on the peripheral region;

[0042] a first insulating layer conformally covering the first conductive layer;

[0043] a dielectric layer, located on the first insulating layer;

[0044] The second conductive layer is located on the dielectric layer.

[0045] In some embodiments, the material of the dielectric layer includes at least one of the following:

[0046] Undoped silica glass, phosphorus-doped silica glass, boron-phosphorus-doped silica glass, undoped spin-on glass, boron-doped spin-on glass, phosphorus-doped spin-on glass, undoped tetraethoxysilane, phosphorus-doped tetraethoxysilane, or boron-doped tetraethoxysilane.

[0047] In some embodiments, a dimension of the first insulating layer along a direction parallel to the thickness of the substrate is smaller than a dimension of the dielectric layer along a direction parallel to the thickness of the substrate.

[0048] In some embodiments, the air gap is located on both sides of the bit line structure, and an extension direction of the air gap is the same as an extension direction of the bit line structure.

[0049] In some embodiments, the semiconductor structure further comprises:

[0050] a storage node contact plug, the landing pad structure being located on the storage node contact plug;

[0051] A bit line contact plug, wherein the bit line structure is located on the bit line contact plug;

[0052] The air gap is at least partially located between the storage node contact plug and the bit line structure.

[0053] In some embodiments, an isolation trench is formed in the dielectric layer, a bottom surface of the isolation trench is lower than a bottom surface of the second conductive layer, and a projection of the isolation trench on the substrate is located between projections of the second conductive layer on the substrate.

[0054] In the disclosed embodiment, a dielectric layer is formed on the landing pad structure and the first conductive layer, so that the dielectric layer covers the opening of the gap but does not fill the gap. Thus, after the second conductive layer is formed in the peripheral region, when the dielectric layer in the array region is removed, no residue from the removed dielectric layer will appear in the gap, because the dielectric layer does not fill the gap. Furthermore, in the disclosed embodiment, after removing the dielectric layer, the sacrificial spacer layer can be easily and conveniently exposed, and then the sacrificial spacer layer can be removed to form the air gap. Therefore, the solution provided by the disclosed embodiment is simple in process, low in cost, and has a good air gap effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0056] FIG1 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0057] FIG2a is a first structural diagram of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0058] FIG2 b is a second structural schematic diagram of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0059] FIG2c is a third structural schematic diagram of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0060] FIG2 d is a fourth structural schematic diagram of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0061] FIG2e is a fifth structural diagram of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0062] FIG2f is a sixth structural diagram of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0063] FIG2g is a seventh structural diagram of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0064] FIG2h is a structural schematic diagram eight of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0065] FIG2i is a ninth structural diagram of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0066] FIG3 a is a first structural diagram of another semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0067] FIG3 b is a second structural schematic diagram of another semiconductor structure during the preparation process provided by an embodiment of the present disclosure;

[0068] FIG4 is a schematic structural diagram of a semiconductor structure provided by a semiconductor embodiment.

[0069] DESCRIPTION OF NUMERALS AND SIGNS: Substrate 10; Array region 11; Peripheral region 12; Gate structure 13; Gate insulating layer 131; First gate conductive layer 132; Second gate conductive layer 133; Third gate conductive layer 134; Capping layer 135; Gate spacer 14; Isolation sidewall 101; Isolation structure 15; Landing pad structure 20; Landing pad material layer 200; Capacitor structure 21; First conductive layer 31; First conductive layer material layer 310; Second conductive layer 32; Conductive layer contact plug 33; Trench T; Sacrificial spacer 41; Air gap 42; Gap 50; Dielectric layer 60; Isolation trench 601; First insulating layer 71; Second insulating layer 72; Bit line structure 80; First bit line conductive layer 81; Second bit line conductive layer 82; Bit line capping layer 83; Contact hole 901; storage node contact plug 91; bit line contact plug 92. DETAILED DESCRIPTION

[0070] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0071] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0072] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0073] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0074] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0075] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0076] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0077] Related art methods for forming air gaps include adding an additional process to form air gaps on the sidewalls of the bit lines in the array region, after forming the peripheral metal layer and before forming the capacitor structure. However, this approach requires multiple film deposition and etching steps. Furthermore, this approach carries the risk of residual photoresist (PR) between the landing pads, which can affect air gap formation and even cause air gap formation failure.

[0078] The present disclosure provides a method for preparing a semiconductor structure. For details, please refer to FIG1 . As shown in FIG1 , the method includes the following steps:

[0079] Step 101: providing a substrate, the substrate including an array region and a peripheral region;

[0080] Step 102: forming a plurality of spaced-apart landing pad structures on the array region, and forming a first conductive layer on the peripheral region, wherein a sacrificial spacer layer is formed on at least one side of the landing pad structures; wherein a gap exists between two adjacent landing pad structures;

[0081] Step 103: forming a dielectric layer on the landing pad structure and the first conductive layer, wherein the dielectric layer covers the opening of the gap;

[0082] Step 104: forming a second conductive layer on the dielectric layer in the peripheral region;

[0083] Step 105: removing the dielectric layer in the array area to expose the gaps;

[0084] Step 106: Remove the sacrificial spacer layer to form an air gap.

[0085] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to specific embodiments.

[0086] Figures 2a to 3b are structural schematic diagrams of the semiconductor structure provided by an embodiment of the present disclosure during the preparation process; among them, Figure 2b is a top view schematic diagram of the array area in Figure 2a, and the structural schematic diagram of the array area in Figure 2a is a cross-sectional structural schematic diagram taken along line AA′ in Figure 2b.

[0087] First, referring to FIG. 2 a , step 101 is performed to provide a substrate 10 , wherein the substrate 10 includes an array region 11 and a peripheral region 12 .

[0088] In one embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. It may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), it may also be a stacked structure, such as Si / SiGe, etc., it may also be other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.

[0089] The substrate 10 includes an active region and an isolation region (not shown in FIG. 2 a ). The isolation region defines the substrate 10 into a plurality of discrete active regions.

[0090] A gate structure 13 is formed on the substrate 10 in the peripheral region 12. The gate structure 13 includes a gate insulating layer 131, a first gate conductive layer 132, a second gate conductive layer 133, a third gate conductive layer 134, and a capping layer 135, which are stacked sequentially from bottom to top. The gate insulating layer 131 may be made of, but not limited to, oxide; the first gate conductive layer 132 may be made of, but not limited to, polysilicon; the second gate conductive layer 133 may be made of, but not limited to, titanium nitride; the third gate conductive layer 134 may be made of, but not limited to, metal tungsten; and the capping layer 135 may be made of, but not limited to, oxide, nitride, metal oxide, and oxynitride.

[0091] In one embodiment, the semiconductor structure further includes a gate spacer layer 14 , and the gate spacer layer 14 covers the sidewalls of the gate structure 13 .

[0092] The active region of the substrate 10 in the peripheral region 12 includes a first source / drain region and a second source / drain region (not labeled in FIG. 2 a ) located on opposite sides of the gate structure 13 .

[0093] The semiconductor structure further includes a connecting pillar (not marked in FIG. 2 a ), which electrically connects the first conductive layer with the first source and drain region and the second source and drain region.

[0094] Next, referring to Figures 2a to 2c, step 102 is performed to form a plurality of landing pad structures 20 arranged at intervals on the array area 11, and a first conductive layer 31 is formed on the peripheral area 12. A sacrificial spacer layer 41 is formed on at least one side of the landing pad structure 20; wherein, a gap 50 exists between two adjacent landing pad structures 20.

[0095] Specifically, before forming a plurality of landing pad structures 20 arranged at intervals on the array area 11, the method further includes:

[0096] A plurality of bit line structures 80 are formed on the array region 11 . The bit line structures 80 extend along a first direction. Sacrificial spacers 41 and isolation spacers 101 are formed on sidewalls of the bit line structures 80 .

[0097] Between the bit line structures 80, contact holes 901 and isolation structures 15 are formed alternately arranged along a first direction (see FIG. 2 b ), and the contact holes 901 expose the substrate 10. The first direction intersects with the second direction and is parallel to the surface of the substrate 10.

[0098] A storage node contact plug 91 is formed in the contact hole 901 ; the landing pad structure 20 is located on the storage node contact plug 91 .

[0099] The first direction is an extending direction of the bit line structure 80 , and the second direction is an arrangement direction of the bit line structure 80 .

[0100] In some embodiments, the first direction is perpendicular to the second direction.

[0101] In other embodiments, the angle between the first direction and the second direction is less than 90°.

[0102] In actual operation, the bit line structure 80 and the storage node contact plug 91 can be formed by any one of the following processes, or a combination thereof: physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). The physical vapor deposition process is a technique that uses physical methods under vacuum conditions to vaporize a material source and a solid or liquid surface into gaseous atoms, molecules, or partially ionize them into ions, and then deposits a thin film with certain special functions on the substrate surface through a low-pressure gas (or plasma) process. The chemical vapor deposition process mainly utilizes one or more gaseous compounds or single substances containing thin film elements to chemically react on the surface of the substrate 10 to form a thin film. The atomic layer deposition process is a method that can deposit a material on the substrate surface layer by layer in the form of a single atomic film.

[0103] In some embodiments, after forming the bit line structure 80, an isolation structure 15 extending along the second direction may be formed first. The bit line structure 80 and the isolation structure 15 enclose an initial contact hole. Using the bit line structure 80 and the isolation structure 15 as a mask, etching is performed along the initial contact hole to remove a portion of the substrate 10, forming a contact hole 901. The contact hole 901 is then filled with a storage node contact plug 91. In other embodiments, after forming the bit line structure 80, an initial storage node contact material is filled between the bit line structures 80. The initial storage node contact material is etched to form a plurality of storage node contact plugs 91 arranged in an array along the first direction and the second direction, and spacing spaces between the plurality of storage node contact plugs 91. The isolation structure 15 is formed within the spacing spaces.

[0104] It should be noted that in order to more clearly show the positional relationship between the bit line structure 80, the contact hole 901 and the isolation structure 15, structures such as the storage node contact plug 91, the landing pad material layer 200, the sacrificial spacer layer 41, and the isolation sidewall 101 in Figure 2a are omitted in Figure 2b.

[0105] The bitline structure 80 includes a first bitline conductive layer 81, a second bitline conductive layer 82, and a bitline capping layer 83 stacked in sequence. The material of the first bitline conductive layer 81 includes, but is not limited to, titanium nitride, tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof; the material of the second bitline conductive layer 82 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta); and the material of the bitline capping layer 83 includes, but is not limited to, silicon nitride. In one embodiment, the first bitline conductive layer 81 is a titanium nitride layer, and the second bitline conductive layer 82 is a tungsten metal layer.

[0106] In one embodiment, the method further includes: before forming the bit line structure 80 , forming a bit line contact plug 92 , wherein the bit line structure 80 is located on the bit line contact plug 92 .

[0107] The bit line structure 80 is electrically connected to the active region through a bit line contact plug 92. The material of the bit line contact plug 92 includes, but is not limited to, polysilicon.

[0108] In actual operation, the bit line contact plug 92 may be formed by any one of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process, or a combination thereof.

[0109] In one embodiment, forming a plurality of landing pad structures 20 spaced apart on the array area 11 includes:

[0110] 2a, a landing pad material layer 200 is formed on the storage node contact plug 91, and the top surface of the landing pad material layer 200 is higher than the top surface of the bit line structure 80;

[0111] Referring to FIG. 2c , a portion of the landing pad material layer 200 and a portion of the bitline structure 80 are etched back to form the landing pad structure 20 and a gap 50 located on one side of the landing pad structure 20. The projection of the landing pad structure 20 on the substrate 10 partially overlaps with the projection of the bitline structure 80 on the substrate 10. The projection of the storage node contact plugs 91 on the substrate 10 can be arranged in a square pattern, while the projection of the top surface of the landing pad structure 20 on the substrate 10 can be arranged in a hexagonal pattern. The formation of the gap 50 changes the layout of the landing pad structure 20, thereby improving the integration density of the capacitor structure 21 (see FIG. 4 ) subsequently formed on the landing pad structure 20.

[0112] 2 c , a portion of the landing pad structure 20 covers the surface of the bit line structure 80 , so that the projections of the landing pad structure 20 and the bit line structure 80 on the substrate 10 partially overlap.

[0113] 2 a , while the landing pad material layer 200 is being formed, a first conductive layer material layer 310 is formed on the substrate 10 in the peripheral region 12 .

[0114] In actual operation, the landing pad material layer 200 and the first conductive layer material layer 310 may be formed by any one of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process, or a combination thereof.

[0115] 2 c , while a portion of the landing pad material layer 200 is etched back to form the landing pad structure 20 , a portion of the first conductive layer material layer 310 is etched away to form the first conductive layer 31 .

[0116] The material of the first conductive layer 31 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0117] 2 d , the method further includes forming a first insulating layer 71 covering the surface of the landing pad structure 20 , the top surface of the sacrificial spacer layer 41 , and the first conductive layer 31 before forming the dielectric layer 60 ; the thickness of the first insulating layer 71 is less than half of the minimum inner diameter of the gap 50 .

[0118] Before forming dielectric layer 60, a first insulating layer 71 is formed to protect landing pad structure 20 from damage during subsequent processing. The thickness of first insulating layer 71 is less than half the minimum inner diameter of void 50, indicating that first insulating layer 71 does not completely fill void 50. However, it also reduces the opening of void 50, preventing dielectric layer 60 in array region 11 from entering void 50. Furthermore, the small width of first insulating layer 71 makes subsequent removal easier, simplifying the process.

[0119] In actual operation, the first insulating layer 71 may be formed by any one of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process, or a combination thereof.

[0120] The material of the first insulating layer 71 includes, but is not limited to, silicon nitride, hydrocarbons or polymers that can be thermally decomposed.

[0121] Next, referring to FIG. 2 e , step 103 is performed to form a dielectric layer 60 on the landing pad structure 20 and the first conductive layer 31 , wherein the dielectric layer 60 covers the opening of the gap 50 .

[0122] In one embodiment, a dimension of the first insulating layer 71 along a direction parallel to the thickness of the substrate 10 is smaller than a dimension of the dielectric layer 60 along the direction parallel to the thickness of the substrate 10 .

[0123] In actual operation, the dielectric layer 60 can be formed by a non-conformal deposition method, such as using any one of a physical vapor deposition process and a chemical vapor deposition process or a combination thereof. The dielectric layer 60 is formed at a deposition rate of .

[0124] Specifically, a dielectric layer 60 is formed on the first insulating layer 71 , and a bottom surface of the dielectric layer 60 is flush with or higher than a top surface of the landing pad structure 20 .

[0125] It should be noted that the first insulating layer 71 may only cover the sidewalls of the landing pad structure 20, in which case the bottom surface of the dielectric layer 60 is flush with the top surface of the landing pad structure 20. Alternatively, the first insulating layer 71 may only cover the sidewalls and top surface of the landing pad structure 20, in which case the bottom surface of the dielectric layer 60 is higher than the top surface of the landing pad structure 20. The fact that the bottom surface of the dielectric layer 60 is flush with or higher than the top surface of the landing pad structure 20 indicates that the dielectric layer 60 does not fill or does not completely fill the gap 50, but only covers the opening of the gap 50. This allows for quick and convenient subsequent removal of the dielectric layer 60, exposing the sacrificial spacer layer 41, which can then be removed to form the air gap 42. This solution simplifies the process, reduces costs, and improves compatibility.

[0126] In one embodiment, the dielectric layer 60 is made of a plurality of materials that can be deposited to form a rapid shape without filling the gaps 50 between the landing pad structures 20 .

[0127] In some specific embodiments, a doped or undoped silicon oxide material layer formed by a thermal chemical vapor deposition (Thermal CVD) process or a high-density plasma (HDP) process, such as undoped silica glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG); boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped tetraethoxysilane (BTEOS), silicon oxide formed using tetraethyl orthosilicate (TEOS), silicon oxide formed using a high aspect ratio process (HARP), or other suitable materials can be used as the material of the dielectric layer 60.

[0128] Next, referring to FIG. 2 f , step 104 is performed to form a second conductive layer 32 on the dielectric layer 60 in the peripheral region 12 .

[0129] The material of the second conductive layer 32 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0130] The above method further includes: before forming the second conductive layer 32 , forming a trench T penetrating the dielectric layer 60 in the peripheral region 12 , wherein the trench T exposes the surface of the first conductive layer 31 ;

[0131] A conductive layer contact plug 33 is formed in the trench T; the first conductive layer 31 and the second conductive layer 32 are electrically connected via the conductive layer contact plug 33. The conductive layer contact plug 33 can be formed in the same deposition step as the landing pad material layer 200 and the first conductive layer material layer 310.

[0132] Continuing with FIG. 2 f , step 105 is performed to remove the dielectric layer 60 in the array region 11 to expose the gap 50 .

[0133] Next, step 106 is performed to remove the sacrificial spacer layer 41 to form an air gap 42 .

[0134] In one embodiment, before removing the sacrificial spacer layer 41 , at least a portion of the first insulating layer 71 is removed to expose the top surface of the sacrificial spacer layer 41 .

[0135] Specifically, Figures 2g and 2h are schematic diagrams of the process of removing the first insulating layer 71 according to one embodiment of the present disclosure, and Figures 3a and 3b are schematic diagrams of the process of removing the first insulating layer 71 according to another embodiment of the present disclosure. The embodiments shown in Figures 2g and 2h are described in detail below.

[0136] 2g, at least a portion of the first insulating layer 71 is removed to expose the top surface of the sacrificial spacer layer 41, including:

[0137] The first insulating layer 71 covering the top surface of the sacrificial spacer layer 41 and the top surface of the landing pad structure 20 is removed by a dry etching process to expose the top surface of the sacrificial spacer layer 41 .

[0138] In this embodiment, the first insulating layer 71 covering the top surface of the sacrificial spacer layer 41 is removed to expose the top surface of the sacrificial spacer layer 41, so that the sacrificial spacer layer 41 can be subsequently removed to form an air gap 42; and the first insulating layer 71 covering the top surface of the landing pad structure 20 is removed to expose the landing pad structure 20, so that the capacitor structure 21 can be subsequently formed on the landing pad structure 20 (see Figure 4).

[0139] Next, referring to FIG. 2 h , the sacrificial spacer layer 41 is removed to form an air gap 42 .

[0140] Removing the sacrificial spacer layer 41 to form the air gap 42 includes: removing the sacrificial spacer layer 41 by a wet etching process to form the air gap 42 .

[0141] In other embodiments, a dry etching process may be used to remove the sacrificial spacer layer 41. Specifically, an etching gas including gaseous hydrogen fluoride may be used to perform the etching process on the sacrificial spacer layer 41. Gaseous hydrogen fluoride has good diffusion properties, which facilitates the full removal of the sacrificial spacer layer 41, thereby obtaining a larger air gap 42 and improving the effect of reducing parasitic capacitance between the bit line structures 80 and between the bit line structure 80 and the storage node contact plug 91.

[0142] Continuing with FIG2h , while removing the sacrificial spacer layer 41 and forming the air gap 42 , an isolation trench 601 is formed in the dielectric layer 60 of the peripheral region 12 using the second conductive layer 32 as a mask. The bottom surface of the isolation trench 601 is lower than the bottom surface of the second conductive layer 32 , and the projection of the isolation trench 601 on the substrate 10 is located between the projections of the second conductive layer 32 on the substrate 10 .

[0143] Subsequently, a low dielectric constant material may be formed in the isolation trench 601 to reduce the parasitic capacitance between the second conductive layers 32 .

[0144] The embodiments shown in FIG. 3 a and FIG. 3 b are described in detail below.

[0145] Referring first to FIG. 3 a , a wet etching process is used to remove the entire first insulating layer 71 located in the array region 11 to expose the top surface of the sacrificial spacer layer 41 .

[0146] Specifically, phosphoric acid (H 3 PO 4 ) solution may be used as an etching solution to remove the first insulating layer 71 .

[0147] Next, referring to FIG. 3 b , the sacrificial spacer layer 41 is removed to form an air gap 42 .

[0148] In this embodiment, the process of removing the sacrificial spacer layer 41 is the same as the process in the embodiment shown in FIG. 2 h , and will not be described again here.

[0149] Next, referring to FIG. 2i , the method further includes forming a second insulating layer 72 within the gap 50 between two adjacent landing pad structures 20 after forming the air gap 42. The second insulating layer 72 covers the opening of the air gap 42, the surface of the landing pad structure 20, fills the gap 50, and covers the surface of the second conductive layer 32. The second insulating layer 72 may also fill the isolation trench 601. Furthermore, by removing the second insulating layer 72 covering the top surface of the landing pad structure 20, the landing pad structure 20 can be exposed, facilitating the subsequent formation of the capacitor structure 21 on the landing pad structure 20 (see FIG. 4 ).

[0150] After the air gap 42 is formed, a second insulating layer 72 is deposited to cover the air gap 42 to ensure that the air gap 42 is in a vacuum state, thereby improving the effect of the air gap 42 in reducing parasitic capacitance.

[0151] It is understandable that, in the embodiments shown in FIG. 3 a and FIG. 3 b , after the air gap 42 is formed, a second insulating layer 72 may also be formed at the opening of the air gap 42 .

[0152] In the disclosed embodiment, a dielectric layer 60 is formed on the landing pad structure 20 and the first conductive layer 31. The dielectric layer 60 covers the opening of the void 50 but does not fill the void 50. Thus, after the second conductive layer 32 is formed in the peripheral region 12, when the dielectric layer 60 in the array region 11 is removed, no residue of the removed dielectric layer 60 will appear in the void 50, because the dielectric layer 60 does not fill the void 50. Consequently, the formation of the air gap 42 will not be affected by the residue. Furthermore, in the disclosed embodiment, after removing the dielectric layer 60, the sacrificial spacer layer 41 can be easily and conveniently exposed, and then the sacrificial spacer layer 41 can be removed to form the air gap 42. Therefore, the solution provided by the disclosed embodiment has a simple process, low cost, and effectively forms the air gap 42.

[0153] An embodiment of the present disclosure further provides a semiconductor structure, and FIG4 is a schematic structural diagram of the semiconductor structure provided by the semiconductor embodiment.

[0154] As shown in Figure 4, the semiconductor structure includes: a substrate 10, including an array region 11 and a peripheral region 12; a bit line structure 80 located on the array region 11, and the bit line structure 80 extends along a first direction; landing pad structures 20 located between the bit line structures 80 and arranged in the first direction; the first direction intersects with the second direction and is parallel to the surface of the substrate 10; an air gap 42 located between the landing pad structure 20 and the bit line structure 80; a first conductive layer 31 located on the peripheral region 12; a first insulating layer 71 conformally covering the first conductive layer 31; a dielectric layer 60 located on the first insulating layer 71; and a second conductive layer 32 located on the dielectric layer 60.

[0155] In one embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc. It may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), it may also be a stacked structure, such as Si / SiGe, etc., or it may be other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.

[0156] The substrate 10 includes an active region and an isolation region (not shown in FIG. 4 ). The isolation region defines the substrate 10 into a plurality of discrete active regions.

[0157] A gate structure 13 is formed on the substrate 10 in the peripheral region 12. The gate structure 13 includes a gate insulating layer 131, a first gate conductive layer 132, a second gate conductive layer 133, a third gate conductive layer 134, and a capping layer 135, which are stacked sequentially from bottom to top. The gate insulating layer 131 may be made of, but not limited to, oxide; the first gate conductive layer 132 may be made of, but not limited to, polysilicon; the second gate conductive layer 133 may be made of, but not limited to, titanium nitride; the third gate conductive layer 134 may be made of, but not limited to, metal tungsten; and the capping layer 135 may be made of, but not limited to, oxide, nitride, metal oxide, and oxynitride.

[0158] In one embodiment, the semiconductor structure further includes a gate spacer layer 14 , and the gate spacer layer 14 covers the sidewalls of the gate structure 13 .

[0159] The active region of the substrate 10 in the peripheral region 12 includes a first source / drain region and a second source / drain region (not labeled in FIG. 4 ) located on opposite sides of the gate structure 13 .

[0160] The semiconductor structure further includes a connecting pillar (not marked in FIG. 4 ), which electrically connects the first conductive layer 31 with the first source and drain regions and the second source and drain regions.

[0161] The first conductive layer 31 is located on the peripheral region 12. The material of the first conductive layer 31 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0162] The first insulating layer 71 conformally covers the first conductive layer 31. The material of the first insulating layer 71 includes but is not limited to silicon nitride.

[0163] In some embodiments, as shown in FIG. 4 , the first insulating layer 71 covers not only a portion of the first conductive layer 31 , but also sidewalls of the landing pad structure 20 in the array region 11 .

[0164] In some other embodiments, the first insulating layer 71 only includes a portion covering the first conductive layer 31 .

[0165] The dielectric layer 60 is located on the first insulating layer 71. In one embodiment, the material of the dielectric layer 60 includes at least one of the following: undoped silica glass, phosphorus-doped silica glass, boron-phosphorus-doped silica glass, undoped spin-on glass, boron-doped spin-on glass, or phosphorus-doped spin-on glass. The dielectric layer 60 can be formed by depositing undoped tetraethoxysilane, phosphorus-doped tetraethoxysilane, or boron-doped tetraethoxysilane as a deposition source.

[0166] In one embodiment, a dimension of the first insulating layer 71 along a direction parallel to the thickness of the substrate 10 is smaller than a dimension of the dielectric layer 60 along the direction parallel to the thickness of the substrate 10 .

[0167] The second conductive layer 32 is located on the dielectric layer 60. The material of the second conductive layer 32 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0168] In one embodiment, the semiconductor structure further includes a conductive layer contact plug 33 penetrating the dielectric layer 60 , and the first conductive layer 31 and the second conductive layer 32 are electrically connected via the conductive layer contact plug 33 .

[0169] In one embodiment, an isolation trench 601 is formed in the dielectric layer 60 . The bottom surface of the isolation trench 601 is lower than the bottom surface of the second conductive layer 32 . The projection of the isolation trench 601 on the substrate 10 is located between the projections of the second conductive layer 32 on the substrate 10 .

[0170] In one embodiment, the isolation trench 601 is filled with a material having a low dielectric constant, which can reduce the parasitic capacitance between the second conductive layers 32 .

[0171] In one embodiment, as shown in FIG. 4 , the semiconductor structure includes: bit line structures 80 located on the array region 11 , the bit line structures 80 extending along a first direction, and landing pad structures 20 spaced apart along the first direction between the bit line structures 80 .

[0172] The bitline structure 80 includes a first bitline conductive layer 81, a second bitline conductive layer 82, and a bitline capping layer 83 stacked in sequence. The material of the first bitline conductive layer 81 includes, but is not limited to, titanium nitride, tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof; the material of the second bitline conductive layer 82 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta); and the material of the bitline capping layer 83 includes, but is not limited to, silicon nitride. In one embodiment, the first bitline conductive layer 81 is a titanium nitride layer, and the second bitline conductive layer 82 is a tungsten metal layer.

[0173] An air gap 42 is located between the landing pad structure 20 and the bit line structure 80 .

[0174] In one embodiment, the semiconductor structure further includes: a storage node contact plug 91, a landing pad structure 20 located on the storage node contact plug 91; a capacitor structure 21 located on the landing pad structure 20; a bit line contact plug 92, a bit line structure 80 located on the bit line contact plug 92; and an air gap 42 at least partially located between the storage node contact plug 91 and the bit line structure 80.

[0175] The bit line structure 80 is electrically connected to the active region through a bit line contact plug 92. The material of the bit line contact plug 92 includes, but is not limited to, polysilicon.

[0176] The air gap 42 may also be located between the bit line structure 80 and the storage node contact plug 91 , so that the air gap 42 can better reduce the parasitic capacitance between the bit line structure 80 and the storage node contact plug 91 .

[0177] The semiconductor structure further includes isolation structures 15 (see FIG. 2 b ) positioned between the bitline structures 80 and arranged alternately with the storage node contact plugs 91 along a first direction. Isolation spacers 101 are also formed on the sidewalls of the bitline structures 80 along a second direction. The isolation structures 15 can separate the storage node contact plugs 91 arranged along the first direction, and the isolation spacers 101 can insulate the bitline structures 80 from the landing pad structures 20.

[0178] In one embodiment, the air gap 42 is located on both sides of the bit line structure 80 , and the extending direction of the air gap 42 is the same as the extending direction of the bit line structure 80 .

[0179] The semiconductor structure further includes a second insulating layer 72, which covers the opening of the air gap 42, fills the void 50, and is located between the second conductive layers 32. The second insulating layer 72 may be made of a low dielectric constant material to reduce parasitic capacitance between the landing pad structures 20 and between the second conductive layers 32.

[0180] After the air gap 42 is formed, a second insulating layer 72 is deposited to cover the air gap 42 to ensure that the air gap 42 is in a vacuum state, thereby improving the effect of the air gap 42 in reducing parasitic capacitance.

[0181] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure. Industrial Applicability

[0182] In the disclosed embodiment, a dielectric layer is formed on the landing pad structure and the first conductive layer, so that the dielectric layer covers the opening of the gap but does not fill the gap. Thus, after the second conductive layer is formed in the peripheral region, when the dielectric layer in the array region is removed, no residue from the removed dielectric layer will appear in the gap, because the dielectric layer does not fill the gap. Furthermore, in the disclosed embodiment, after removing the dielectric layer, the sacrificial spacer layer can be easily and conveniently exposed, and then the sacrificial spacer layer can be removed to form the air gap. Therefore, the solution provided by the disclosed embodiment is simple in process, low in cost, and has a good air gap effect.

Claims

1. A method for preparing a semiconductor structure, comprising: Providing a substrate (10), wherein the substrate (10) comprises an array region (11) and a peripheral region (12); A plurality of landing pad structures (20) arranged at intervals are formed on the array area (11), and a first conductive layer (31) is formed on the peripheral area (12), wherein a sacrificial spacing layer (41) is formed on at least one side of the landing pad structure (20); wherein a gap (50) exists between two adjacent landing pad structures (20); forming a dielectric layer (60) on the landing pad structure (20) and the first conductive layer (31), wherein the dielectric layer (60) covers the opening of the gap (50); forming a second conductive layer (32) on the dielectric layer (60) in the peripheral region (12); removing the dielectric layer (60) in the array region (11) to expose the gap (50); The sacrificial spacer layer (41) is removed to form an air gap (42).

2. The method according to claim 1, wherein: The material of the dielectric layer (60) includes at least one of the following: undoped silicon glass, phosphorus-doped silicon glass, boron-phosphorus-doped silicon glass, undoped spin-coated glass, boron-doped spin-coated glass, and phosphorus-doped spin-coated glass.

3. The method according to claim 1 or 2, wherein: The method further comprises: Before forming the dielectric layer (60), a first insulating layer (71) is formed to cover the surface of the landing pad structure (20), the top surface of the sacrificial spacer layer (41) and the first conductive layer (31); the thickness of the first insulating layer (71) is less than half of the minimum inner diameter of the gap (50); forming the dielectric layer (60) on the first insulating layer (71), wherein the bottom surface of the dielectric layer (60) is flush with or higher than the top surface of the landing pad structure (20); Before removing the sacrificial spacer layer (41), at least a portion of the first insulating layer (71) is removed to expose the top surface of the sacrificial spacer layer (41).

4. The method according to claim 3, wherein: The step of removing at least a portion of the first insulating layer (71) to expose the top surface of the sacrificial spacer layer (41) comprises: Using a dry etching process to remove the first insulating layer (71) covering the top surface of the sacrificial spacer layer (41) and the top surface of the landing pad structure (20), so as to expose the top surface of the sacrificial spacer layer (41); or, The entire first insulating layer (71) located in the array area (11) is removed by a wet etching process to expose the top surface of the sacrificial spacer layer (41).

5. The method according to any one of claims 1 to 4, wherein: The step of removing the sacrificial spacer layer (41) to form the air gap (42) comprises: removing the sacrificial spacer layer (41) by a wet etching process to form the air gap (42).

6. The method according to any one of claims 1 to 5, wherein: The method further comprises: After the air gap (42) is formed, a second insulating layer (72) is formed in the gap (50) between two adjacent landing pad structures (20), wherein the second insulating layer (72) covers the opening of the air gap (42).

7. The method according to any one of claims 1 to 6, wherein: Before forming a plurality of landing pad structures (20) arranged at intervals on the array area (11), the method further comprises: A plurality of bit line structures (80) are formed on the array region (11), wherein the bit line structures (80) extend along a first direction, and a sacrificial spacer layer (41) is formed on the sidewalls of the bit line structures (80); Contact holes (901) and isolation structures (15) are formed between the bit line structures (80) and are arranged alternately along a first direction, wherein the contact holes (901) expose the substrate (10); the first direction is parallel to the surface of the substrate (10); A storage node contact plug (91) is formed in the contact hole (901); and the landing pad structure (20) is located on the storage node contact plug (91).

8. The method according to claim 7, wherein: A plurality of landing pad structures (20) arranged at intervals are formed on the array area (11), comprising: A landing pad material layer (200) is formed on the storage node contact plug (91), wherein the landing pad material layer (200) The top surface of the bit line structure (80) is higher than the top surface of the bit line structure (80); A portion of the landing pad material layer (200) and a portion of the bit line structure (80) are etched back to form the landing pad structure (20) and the gap (50) located on one side of the landing pad structure (20), wherein a projection of the landing pad structure (20) on the substrate (10) partially overlaps with a projection of the bit line structure (80) on the substrate (10).

9. The method according to any one of claims 1 to 8, wherein: The method further comprises: Before forming the second conductive layer (32), forming a trench (T) penetrating the dielectric layer (60) of the peripheral region (12), wherein the trench (T) exposes the surface of the first conductive layer (31); A conductive layer contact plug (33) is formed in the trench (T); the first conductive layer (31) and the second conductive layer (32) are electrically connected via the conductive layer contact plug (33).

10. A semiconductor structure comprising: A substrate (10) comprising an array region (11) and a peripheral region (12); A bit line structure (80) located on the array region (11), the bit line structure (80) extending along a first direction; Landing pad structures (20) are arranged between the bit line structures (80) and are spaced apart along a first direction; the first direction is parallel to the surface of the substrate (10); an air gap (42) located between the landing pad structure (20) and the bit line structure (80); A first conductive layer (31) located on the peripheral region (12); A first insulating layer (71) conformally covers the first conductive layer (31); A dielectric layer (60) located on the first insulating layer (71); The second conductive layer (32) is located on the dielectric layer (60).

11. The semiconductor structure according to claim 10, wherein: The material of the dielectric layer (60) includes at least one of the following: Undoped silica glass, phosphorus-doped silica glass, boron-phosphorus-doped silica glass, undoped spin-coated glass, boron-doped spin-coated glass, phosphorus-doped spin-coated glass, undoped tetraethoxysilane, phosphorus-doped tetraethoxysilane, or boron-doped tetraethoxysilane.

12. The semiconductor structure according to claim 10 or 11, wherein: The dimension of the first insulating layer (71) along a direction parallel to the thickness of the substrate (10) is smaller than the dimension of the dielectric layer (60) along a direction parallel to the thickness of the substrate (10).

13. The semiconductor structure according to any one of claims 10 to 12, wherein: The air gap (42) is located on both sides of the bit line structure (80), and the extension direction of the air gap (42) is the same as the extension direction of the bit line structure (80).

14. The semiconductor structure according to any one of claims 10 to 13, wherein: The semiconductor structure further comprises: A storage node contact plug (91), the landing pad structure (20) being located on the storage node contact plug (91); A bit line contact plug (92), the bit line structure (80) being located on the bit line contact plug (92); The air gap (42) is at least partially located between the storage node contact plug (91) and the bit line structure (80).

15. The semiconductor structure according to any one of claims 10 to 14, wherein: An isolation groove (601) is formed in the dielectric layer (60), the bottom surface of the isolation groove (601) is lower than the bottom surface of the second conductive layer (32), and the projection of the isolation groove (601) on the substrate (10) is located between the projections of the second conductive layer (32) on the substrate (10).

16. The semiconductor structure according to claim 14, wherein: The semiconductor structure further comprises: a capacitor structure (21), wherein the capacitor structure (21) is located on the landing pad structure (20).

17. The semiconductor structure according to any one of claims 10 to 14, wherein: The semiconductor structure further comprises: a second insulating layer (72), wherein the second insulating layer (72) covers the opening of the air gap (42) and is located between the second conductive layers (32).

18. The semiconductor structure according to claim 17, wherein: The second insulating layer (72) includes a low dielectric constant material.

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