Circuit board and display device including the same

Abstract

In an organic EL display device (1), a laminate (36p) covering a first gate electrode (24) of a first TFT (50A) is formed by laminating two types of inorganic insulating films. A second TFT (50B) is configured inside the laminate. A first contact hole (Ha) penetrating the conductor region (22b) of the first semiconductor layer and a second contact hole (Hb) penetrating the first gate electrode are formed in a laminated insulating film (36) comprising the laminate and a first gate insulating film (23) covering a first semiconductor layer (22) of the first TFT. The laminated structure of the laminate lacks a second gate insulation film (32) and is mutually identical in the locations where the first and second contact holes are formed.

Description

Circuit board and display device including same

[0001] The present disclosure relates to a circuit board and a display device including the same.

[0002] Various display devices, such as liquid crystal display devices and organic electroluminescence (EL) display devices, include a circuit board called a backplane. A known circuit board has a hybrid structure that combines polysilicon thin film transistors (TFTs) having a semiconductor layer made of polysilicon with oxide semiconductor TFTs having a semiconductor layer made of oxide semiconductor.

[0003] In a circuit board having a hybrid structure, polysilicon TFTs and oxide semiconductor TFTs are formed in separate layers on the same substrate. Generally, due to process temperature conditions, polysilicon TFTs are formed first, and oxide semiconductor TFTs are formed later. Many contact holes are formed in the circuit board for wiring to both TFTs. An example of such a circuit board is disclosed in Patent Document 1.

[0004] International Publication No. 2020 / 184533

[0005] The circuit board described above has a laminated structure in which a plurality of inorganic insulating films are stacked to insulate conductive parts such as wiring, electrodes, and semiconductor layers. This laminated structure includes two or more types of inorganic insulating films made of different inorganic insulating materials. One of the inorganic insulating films includes a gate insulating film that constitutes an oxide semiconductor TFT. This gate insulating film may be used in a process for partially converting the semiconductor layer of the oxide semiconductor TFT into a conductor.

[0006] In this case, the gate insulating film is patterned to remove unnecessary portions. The gate insulating film may be patterned so that it covers the contact hole formation portion located near the oxide semiconductor TFT, but does not cover the contact hole formation portion relatively far from the oxide semiconductor TFT. In this case, the laminated structure of the inorganic insulating film differs between the contact hole formation portion and the other contact hole formation portion.

[0007] When a contact hole formed in a region of an oxide semiconductor TFT that does not include a gate insulating film penetrates to a layer below a contact hole formed in a region that includes the gate insulating film, and both contact holes are formed simultaneously by dry etching, etching conditions are determined to match the former contact hole. However, because the gate insulating film of the oxide semiconductor TFT is included in the formation location of the latter contact hole, there is a risk that a film residue of the inorganic insulating film will be formed at the bottom of the contact hole. If a film residue is formed at the bottom of the contact hole, a connection failure will occur in the wiring through the contact hole.

[0008] An object of the present disclosure is to prevent connection defects from occurring in wiring through contact holes in a circuit board on which a gate insulating film of an oxide semiconductor TFT is patterned.

[0009] The disclosed technology is directed to a circuit board. The circuit board according to the disclosed technology includes a substrate, a first conductive portion provided on the substrate, a first insulating film provided to cover the first conductive portion, a second conductive portion provided on the first insulating film, and a second insulating film provided to cover the second conductive portion. The second insulating film is formed by stacking at least two types of inorganic insulating films made of different inorganic insulating materials. A first thin film transistor is formed within the second insulating film, the first semiconductor layer being made of an oxide semiconductor, and a first gate insulating film provided to partially cover the first semiconductor layer and constituting one inorganic insulating film layer in the second insulating film. A first contact hole penetrating the first conductive portion and a second contact hole penetrating the second conductive portion are formed in the stacked insulating film made of the first insulating film and the second contact hole. The stacked structure of the inorganic insulating films constituting the second insulating film is identical at the penetrating portion of the first contact hole and the penetrating portion of the second contact hole, excluding the first gate insulating film.

[0010] According to the technique of the present disclosure, in a circuit substrate on which the first gate insulating film constituting the first TFT is patterned, it is possible to prevent connection failures from occurring in the wiring through the second contact hole.

[0011] FIG. 1 is a plan view illustrating a schematic configuration of an organic EL display device according to an embodiment. FIG. 2 is a cross-sectional view of the organic EL display device taken along line II-II in FIG. 1. FIG. 3 is a plan view illustrating pixels and various wirings constituting a display region of the organic EL display device according to an embodiment. FIG. 4 is a cross-sectional view of the organic EL display device taken along line IV-IV in FIG. 3. FIG. 5 is a plan view illustrating a schematic configuration of a layer below a conductive layer forming a source line and a power line in a portion of a circuit board according to an embodiment corresponding to one subpixel. FIG. 6 is a plan view illustrating a schematic configuration (excluding the second gate insulating film) including a conductive layer forming a source line and a power line in a portion of a circuit board according to an embodiment corresponding to one subpixel. FIG. 7 is an equivalent circuit diagram illustrating a pixel circuit according to an embodiment. FIG. 8 is a cross-sectional view illustrating a schematic configuration of a first TFT. FIG. 9 is a cross-sectional view illustrating a schematic configuration of a second TFT. FIG. 10A is a cross-sectional view of a first contact hole and its surroundings taken along line A-A in FIG. 5. FIG. 10B is a cross-sectional view of the second contact hole and its periphery taken along line B-B in FIG. 5. FIG. 10C is a cross-sectional view of the third contact hole and its periphery taken along line C-C in FIG. 5. FIG. 10D is a cross-sectional view of the fourth contact hole and its periphery taken along line D-D in FIG. 5. FIG. 10E is a cross-sectional view of the fifth contact hole and its periphery taken along line E-E in FIG. 5. FIG. 11A is a cross-sectional view showing a laminated structure of an inorganic insulating film including a laminated body and a laminated insulating film in a region where a first contact hole is to be formed taken along line A-A in FIG. 5. FIG. 11B is a cross-sectional view showing a laminated structure of an inorganic insulating film including a laminated body and a laminated insulating film in a region where a second contact hole is to be formed taken along line B-B in FIG. 5. FIG. 11C is a cross-sectional view showing a laminated structure of an inorganic insulating film including a laminated body and a laminated insulating film in a region where a third contact hole is to be formed taken along line C-C in FIG. 5. FIG. 11D is a cross-sectional view showing a laminated structure of an inorganic insulating film including a laminated body and a laminated insulating film in a region where a fourth contact hole is to be formed taken along line D-D in FIG. 5. Fig. 11E is a cross-sectional view showing a laminate structure of an inorganic insulating film including a laminate and a laminated insulating film in a region where a fifth contact hole is to be formed, taken along line E-E in Fig. 5. Fig. 12A is a cross-sectional view when a resist pattern for forming a first contact hole is formed on the laminate structure of Fig. 11A.12B is a cross-sectional view of a state where a resist pattern for forming a second contact hole is formed on the stacked structure of FIG. 11B . FIG. 12C is a cross-sectional view of a state where a resist pattern for forming a third contact hole is formed on the stacked structure of FIG. 11C . FIG. 12D is a cross-sectional view of a state where a resist pattern for forming a fourth contact hole is formed on the stacked structure of FIG. 11D . FIG. 12E is a cross-sectional view of a state where a resist pattern for forming a fifth contact hole is formed on the stacked structure of FIG. 11E . FIG. 13A is a cross-sectional view showing a state where a first contact hole has been formed halfway through the first step. FIG. 13B is a cross-sectional view showing a state where a second contact hole has been formed to a predetermined through-position through the first step. FIG. 13C is a cross-sectional view showing a state where a third contact hole has been formed to a predetermined through-position through the first step. FIG. 13D is a cross-sectional view showing a state where a fourth contact hole has been formed to a predetermined through-position through the first step. FIG. 13E is a cross-sectional view showing a state where a fifth contact hole has been formed to a predetermined through-position through the first step. FIG. 14A is a cross-sectional view showing the state in which the first gate insulating film remaining at the bottom of the first contact hole has been removed by performing the second step. FIG. 14B is a cross-sectional view showing the state of the second contact hole after performing the second step. FIG. 14C is a cross-sectional view showing the state of the third contact hole after performing the second step. FIG. 14D is a cross-sectional view showing the state of the fourth contact hole after performing the second step. FIG. 14E is a cross-sectional view showing the state of the fifth contact hole after performing the second step. FIG. 15 is a plan view corresponding to FIG. 5 of an organic EL display device of a comparative example. FIG. 16A is a cross-sectional view showing the state in which the first contact hole has been formed by performing the first step in the manufacture of an organic EL display device of a comparative example. FIG. 16B is a cross-sectional view showing the state in which the second contact hole has been formed by performing the first step in the manufacture of an organic EL display device of a comparative example. FIG. 16C is a cross-sectional view showing the state in which the third contact hole has been formed by performing the first step in the manufacture of an organic EL display device of a comparative example.Fig. 16D is a cross-sectional view showing a state in which a fourth contact hole is formed by performing the first step in the manufacture of an organic EL display device of the comparative example. Fig. 16E is a cross-sectional view showing a state in which a fifth contact hole is formed by performing the first step in the manufacture of an organic EL display device of the comparative example. Fig. 17A is a cross-sectional view showing a state in which a first contact hole is formed by performing the second step in the manufacture of an organic EL display device of the comparative example. Fig. 17B is a cross-sectional view showing a state in which a second contact hole is formed by performing the second step in the manufacture of an organic EL display device of the comparative example. Fig. 17C is a cross-sectional view showing a state in which a third contact hole is formed by performing the second step in the manufacture of an organic EL display device of the comparative example. Fig. 17D is a cross-sectional view showing a state in which a fourth contact hole is formed by performing the second step in the manufacture of an organic EL display device of the comparative example. Fig. 17E is a cross-sectional view showing a state in which a fifth contact hole is formed by performing the second step in the manufacture of an organic EL display device of the comparative example.

[0012] Exemplary embodiments will be described in detail below with reference to the drawings. In the following embodiments, an organic EL display device will be described as an example of a display device according to the present disclosure. Note that the drawings are intended to conceptually explain the technology of the present disclosure. Therefore, in the drawings, dimensions, ratios, or numbers may be exaggerated or simplified to facilitate understanding of the technology of the present disclosure.

[0013] In the following embodiments, the term "first direction" refers to the horizontal direction of the screen when the display device is oriented in a predetermined state of use. The term "second direction" refers to the direction perpendicular to the first direction and to the vertical direction of the screen when the display device is oriented in a predetermined state of use. A row of components such as subpixels refers to a horizontal arrangement of multiple components in a row in the first direction. A column of components such as subpixels refers to a vertical arrangement of multiple components in a row in the second direction.

[0014] In the following embodiments, when a component such as a film, layer, or element is provided or formed on another component such as another film, layer, or element, it does not only mean that the other component exists directly on top of the other component, but also includes cases where another component such as a film, layer, or element is interposed between the two components.

[0015] In the following embodiments, unless otherwise specified, a description that a certain component is connected to another component means that the components are electrically connected. This description not only means a direct connection, but also an indirect connection via other components, within the scope of the gist of the technology of the present disclosure. This description also includes a case where another component is integrated with a certain component, that is, a part of a certain component constitutes the other component.

[0016] In the following embodiments, a description that a certain component is in the same layer as another component means that the certain component is formed in the same process as the other component. A description that a certain component is a lower layer than the other component means that the certain component is deposited in an earlier process than the other component or is formed from a film deposited in an earlier process. A description that a certain component is an upper layer than the other component means that the certain component is deposited in a later process than the other component or is formed from a film deposited in a later process.

[0017] In the following embodiments, a description that a certain component is identical to or equivalent to another component does not mean only a state in which the certain component and the other component are completely identical or completely equivalent, but also a state in which the certain component and the other component are substantially identical or substantially equivalent, such as fluctuating within the range of manufacturing variations or tolerances.

[0018] In the following embodiments, the terms first, second, third, etc. are used to distinguish between terms to which these terms are attached, and do not limit the number of terms or even their order.

[0019] The organic EL display device 1 of this embodiment is used as a display for a mobile device such as a multi-function phone called a smartphone or a tablet terminal. The organic EL display device 1 may also be used as a display for various other devices such as a personal computer (PC) or a television set.

[0020] --Configuration of Organic EL Display Device-- The organic EL display device 1 is a display device that uses organic EL elements, also known as OLEDs (Organic Light Emitting Diodes). The organic EL display device 1 employs an active matrix drive system and is configured to provide full-color display. As shown in Figures 1 and 2, the organic EL display device 1 has a display area DA and a frame area FA.

[0021] The display area DA is an area for displaying an image and constitutes a screen. The display area DA is provided, for example, in a rectangular shape. The display area DA may be a substantially rectangular shape, such as a shape with at least one arc-shaped side, a shape with at least one arc-shaped corner, or a shape with a notch on at least one side, or may be any other shape.

[0022] As shown in Fig. 3, the display area DA is composed of a plurality of pixels PX. The plurality of pixels PX are arranged in a matrix. Each pixel PX is composed of three sub-pixels SP. The three sub-pixels SP are a sub-pixel SPr that emits red light, a sub-pixel SPg that emits green light, and a sub-pixel SPb that emits blue light. These three sub-pixels SPr, SPg, and SPb are arranged, for example, in a striped pattern.

[0023] The display area DA is provided with a plurality of organic EL elements 65 and a plurality of pixel circuits PC. The plurality of organic EL elements 65 are provided corresponding to a plurality of sub-pixels SP. Each sub-pixel SP is formed by an organic EL element 65. The pixel circuit PC is a circuit for each sub-pixel, and controls the light emission of the organic EL element 65 that constitutes the corresponding sub-pixel SP.

[0024] 1 and 2 , the frame area FA is an area that constitutes a non-display portion outside the screen. The frame area FA is provided around the display area DA, for example, in the shape of a rectangular frame. The frame area FA may have a frame shape other than a rectangle. The frame area FA includes a terminal portion TP and a bent portion BP.

[0025] The terminal portion TP is a portion for connecting to an external circuit such as a display control circuit (source driver). The terminal portion TP is provided near the outer edge of a portion constituting one side of the frame area FA extending in the first direction Dx, and extends along that side. Although not shown, the terminal portion TP has multiple terminals. A wiring board CB such as an FPC (Flexible Printed Circuit) is connected to the terminal portion TP.

[0026] The bent portion BP is provided between the terminal portion TP and the display area DA and extends horizontally across the entire frame area FA in the first direction. The frame area FA is bent at the bent portion BP to form a U-shape, for example, by about 180° (shown by the two-dot chain line in FIG. 2 ). This positions the terminal portion TP on the rear side of the organic EL display device 1.

[0027] A driving circuit DC is provided in the frame area FA. The driving circuit DC is arranged in a portion of the frame area FA that forms a side (each of the left and right sides in FIG. 1 ) adjacent to the side on which the terminal portion TP is provided. The driving circuit DC is monolithically formed as part of the TFT layer 20, which will be described later. The driving circuit DC includes a gate driver and an emission driver.

[0028] In addition, a first frame line 40a and a second frame line 40b are provided in the frame area FA. The first frame line 40a and the second frame line 40b are both power supply trunk lines that are formed to surround the display area DA and extend to the terminal portion TP. A high-level power supply voltage (ELVDD) is supplied to the first frame line 40a via the wiring board CB. A low-level power supply voltage (ELVSS) is supplied to the second frame line 40b via the wiring board CB.

[0029] 2 , the organic EL display device 1 includes a circuit board 5, a light-emitting element layer 60, and a sealing film 80. The circuit board 5 includes a substrate layer 10 and a TFT layer (thin film transistor) 20.

[0030] <Substrate Layer> The substrate layer 10 is an example of a substrate that forms the base of the organic EL display device 1. The substrate layer 10 in this example is a substrate made of a flexible resin. The substrate layer 10 is formed of an organic resin material such as polyimide resin, polyamide resin, or epoxy resin. The substrate layer 10 is made of an organic insulating layer made of the organic resin material described above, and a silicon oxide (SiO ２ A protective film 11 is attached to the back surface of the substrate layer 10.

[0031] <TFT Layer> The TFT layer 20 is provided on the substrate layer 10. In addition to the drive circuit DC described above, the TFT layer 20 includes a base coat film 21, various wirings 40, and a plurality of pixel circuits PC shown in Figures 3 and 4. The drive circuit DC, the various wirings 40, and the pixel circuits PC are provided on the base coat film 21. The base coat film 21 is provided on the substrate layer 10 and extends over substantially the entire surface of the substrate layer 10.

[0032] The various wirings 40 include the first frame line 40a and the second frame line 40b described above. In addition, the various wirings 40 include a plurality of gate lines 40g, a plurality of light-emitting control lines 40e, a plurality of initialization lines 40i, a plurality of power supply lines 40p, and a plurality of source lines 40s. Each of the gate lines 40g, the light-emitting control lines 40e, the initialization lines 40i, the power supply lines 40p, and the source lines 40s is provided in the display area DA.

[0033] The gate lines 40g are wirings that transmit gate signals to the pixel circuits PC. The gate lines 40g are arranged at intervals in the second direction Dy and extend parallel to each other in the first direction Dx. The gate lines 40g include first gate lines 40ga and second gate lines 40gb.

[0034] The first gate line 40ga is a gate line 40g used to control the P-channel TFT 50. The second gate line 40gb is a gate line 40g used to control the N-channel TFT 50. The first gate line 40ga and the second gate line 40gb are provided for each row of sub-pixels SP. Each first gate line 40ga and each second gate line 40gb is drawn out to the frame area FA and connected to a gate driver of the drive circuit DC.

[0035] Each of the plurality of light-emitting control lines 40e is a wiring that transmits an emission signal to the pixel circuit PC. The plurality of light-emitting control lines 40e are arranged at intervals in the second direction Dy and extend parallel to each other in the first direction Dx. The light-emitting control lines 40e include a first light-emitting control line 40ea and a second light-emitting control line 40eb.

[0036] The first light-emitting control line 40ea is a light-emitting control line 40e used to control the P-channel TFT 50. The second light-emitting control line 40eb is a light-emitting control line 40e used to control the N-channel TFT 50. The first light-emitting control line 40ea and the second light-emitting control line 40eb are provided for each row of sub-pixels SP. Each second light-emitting control line 40eb is connected to a corresponding first light-emitting control line 40ea. Each first light-emitting control line 40ea is drawn out to the frame area FA and connected to an emission driver of the drive circuit DC.

[0037] The multiple initialization lines 40i are wirings that apply an initialization voltage to the pixel circuits PC. The multiple initialization lines 40i are arranged at intervals from one another in the second direction Dy and extend parallel to one another in the first direction Dx. An initialization line 40i is provided for each row of subpixels SP. Each initialization line 40i is drawn out to the frame area FA and connected to the drive circuit DC or the second frame line 40b.

[0038] Each of the multiple power supply lines 40p is a wiring that applies a predetermined high-level power supply voltage (ELVDD) to the pixel circuits PC. The multiple power supply lines 40p are arranged at intervals from one another in the first direction Dx and extend parallel to one another in the second direction Dy. One power supply line 40p is provided for each column of sub-pixels SP. Each power supply line 40p is drawn out into the frame area FA and connected to the first frame line 40a.

[0039] Each of the multiple source lines 40s is a wiring that transmits a source signal to the pixel circuit PC. The multiple source lines 40s are arranged at intervals from one another in the first direction Dx and extend parallel to one another in the second direction Dy. One source line 40s is provided for each column of subpixels SP. Each source line 40s is drawn to a terminal portion TP and connected to a display control circuit (source driver) via a wiring substrate CB.

[0040] The first gate line 40ga, the first light-emitting control line 40ea, and the initialization line 40i are formed of the same material in the same layer as a first gate electrode 24 (described later). The second gate line 40gb and the second light-emitting control line 40eb are formed of the same material in the same layer as a second gate electrode 33 (described later) and a second capacitor electrode 30. The power supply line 40p and the source line 40s are formed of the same material in the same layer as a first terminal electrode 37, a second terminal electrode 38, and a relay line 40r (described later).

[0041] Each pixel circuit PC is connected to a first gate line 40ga, a second gate line 40gb, a first light-emitting control line 40ea, a second light-emitting control line 40eb, an initialization line 40i, a power supply line 40p, and a source line 40s. Each pixel circuit PC operates based on signals and voltages supplied by these various wirings 40, and in each frame, resets the charge accumulated in the pixel electrode 61 and then supplies a drive current corresponding to the source signal to the organic EL element 65.

[0042] 4 to 7, the pixel circuit PC includes a plurality of TFTs 50 and a capacitor 55. The plurality of TFTs 50 constituting the pixel circuit PC include a first TFT 50A and a second TFT 50B. The first TFT 50A, the second TFT 50B, and the capacitor 55 are provided corresponding to a plurality of sub-pixels SP, and a pixel circuit PC is constituted for each sub-pixel SP.

[0043] As shown in Fig. 8, the first TFT 50A is configured as a top-gate type with a top-contact structure. The configuration of the first TFT 50A shown in Fig. 8 is applied to the writing TFT 50c and the power supply TFT 50e of this example (see Fig. 5). The first TFT 50A has a first semiconductor layer 22, a first gate insulating film 23, a first gate electrode 24, an interlayer insulating film 35, a first terminal electrode 37, and a second terminal electrode 38.

[0044] The first semiconductor layer 22 is provided in an island shape on the base coat film 21, and is provided continuously for the multiple first TFTs 50A. The first semiconductor layer 22 may be separated into individual first TFTs 50A. The first semiconductor layer 22 includes a channel region 22a and a pair of conductor regions 22b. The channel region 22a is provided between the pair of conductor regions 22b. The pair of conductor regions 22b are provided spaced apart from each other with the channel region 22a sandwiched between them. The conductor regions 22b, which are part of the first semiconductor layer 22, are an example of a first conductive portion.

[0045] The first gate insulating film 23 is provided continuously over the multiple first TFTs 50A so as to cover the multiple first semiconductor layers 22. The first gate insulating film 23 may be provided in an island shape on each first semiconductor layer 22 and separated individually for each first TFT 50A. The first gate electrode 24 is provided on the first gate insulating film 23. The first gate electrode 24 overlaps with the channel region 22a of the first semiconductor layer 22 via the first gate insulating film 23. The first gate electrode 24 of a predetermined TFT 50 (drive TFT 50d) is an example of a second conductive portion.

[0046] The interlayer insulating film 35 is provided to cover the plurality of first gate electrodes 24. The interlayer insulating film 35 is configured by laminating a first interlayer insulating film 26 and a second interlayer insulating film 34 in this order on the first gate insulating film 23. The first interlayer insulating film 26 in this example has a two-layer structure and is configured by laminating a lower first interlayer insulating film 26a and an upper first interlayer insulating film 26b in this order. The second interlayer insulating film 34 in this example has a two-layer structure and is configured by laminating a lower second interlayer insulating film 34a and an upper second interlayer insulating film 34b in this order.

[0047] The first terminal electrode 37 and the second terminal electrode 38 are provided at positions spaced apart from each other. The first terminal electrode 37 and the second terminal electrode 38 are connected to different conductor regions 22b of the first semiconductor layer 22. One of the first terminal electrode 37 and the second terminal electrode 38 (the first terminal electrode 37 in the example shown in FIG. 8 ) is provided on the interlayer insulating film 35 and is connected to the conductor region 22b of the first semiconductor layer 22 via a first contact hole Ha formed in the first gate insulating film 23 and the interlayer insulating film 35.

[0048] The other of the first terminal electrode 37 and the second terminal electrode 38 (the second terminal electrode 38 in the example shown in FIG. 8 ) is formed integrally with the conductor region 22b. That is, in the first TFT 50A having adjacent channel regions 22a with a common conductor region 22b interposed therebetween, one terminal electrode is the conductor region 22b. Both the first terminal electrode 37 and the second terminal electrode 38 may be the conductor region 22b of the first semiconductor layer 22. This configuration is applied to the drive TFT 50d of this example (see FIG. 5 ).

[0049] Furthermore, the first terminal electrode 37 and the second terminal electrode 38 may each be provided on the first interlayer insulating film 26 and connected to the conductor region 22b of the first semiconductor layer 22 via a sixth contact hole Hf formed in the first interlayer insulating film 26. This configuration is applied to the light-emission control TFT 50f of this example (see FIG. 5). Alternatively, the first terminal electrode 37 and the second terminal electrode 38 may both be provided on the interlayer insulating film 35 and connected to the conductor region 22b of the first semiconductor layer 22 via a first contact hole Ha formed in the interlayer insulating film 35.

[0050] As shown in FIG. 9, the second TFT 50B is configured as a top-gate type with a bottom-contact structure. The configuration of the second TFT 50B shown in FIG. 9 is applied to the initialization TFT 50a, compensation TFT 50b, and anode discharge TFT 50g of this example (see FIG. 5). The second TFT 50B is provided inside a stack 36p, which will be described later. The second TFT 50B has a third terminal electrode 28, a fourth terminal electrode 29, a second semiconductor layer 31, a second gate insulating film 32, and a second gate electrode 33. The second semiconductor layer 31 is an example of a semiconductor layer. The second gate insulating film is an example of a gate insulating film.

[0051] The second semiconductor layer 31 is provided in an island shape on the first interlayer insulating film 26, and is provided continuously for the plurality of second TFTs 50B. The second semiconductor layer 31 may be separated for each second TFT 50B. The second semiconductor layer 31 includes a channel region 31a and a pair of conductor regions 31b. The channel region 31a is provided between the pair of conductor regions 31b. The pair of conductor regions 31b are provided spaced apart from each other with the channel region 31a sandwiched therebetween.

[0052] One conductor region 31b in the second semiconductor layer 31 partially overlaps the third terminal electrode 28, and the other conductor region 31b partially overlaps each of the fourth terminal electrodes 29. In this manner, the third terminal electrode 28 and the fourth terminal electrode 29 each overlap and are connected to a portion of the second semiconductor layer 31. The second gate insulating film 32 is formed in an island shape on the first interlayer insulating film 26, and is provided continuously for the plurality of second TFTs 50B. The second gate insulating film 32 may be separated individually for each second TFT 50B.

[0053] The second gate insulating film 32 is provided so as to partially cover the multiple second semiconductor layers 31 and overlaps with the channel region 31a of each second semiconductor layer 31. The second gate insulating film 32 forms one inorganic insulating layer in a stack 36p described below. The second gate electrode 33 is provided on the second gate insulating film 32 and overlaps with the channel region 31a of the second semiconductor layer 31 via the second gate insulating film 32. The second gate electrode 33 is formed integrally with the second gate line 40gb.

[0054] The capacitor 55 includes a first capacitance electrode 25, a second capacitance electrode 30, and a second gate insulating film 32. The first capacitance electrode 25 is an example of a third conductive portion (conductive layer). The first capacitance electrode 25 is provided on an upper first interlayer insulating film 26b. The first capacitance electrode 25 is formed in the same layer and from the same material as the third terminal electrode 28 and the fourth terminal electrode 29. The upper first interlayer insulating film 26b is located below the second gate insulating film 32. The second capacitance electrode 30 is provided on the second gate insulating film 32. The first capacitance electrode 25 and the second capacitance electrode 30 overlap each other with the second gate insulating film 32 interposed therebetween.

[0055] 10 , the first interlayer insulating film 26 (lower first interlayer insulating film 26 a, upper first interlayer insulating film 26 b), the second gate insulating film 32, and the second interlayer insulating film 34 (lower second interlayer insulating film 34 a, upper second interlayer insulating film 34 b) form a stacked body 36 p provided to cover the multiple first gate electrodes 24. The stacked body 36 p is an example of a second insulating film.

[0056] The first gate insulating film 23, the first interlayer insulating film 26, the second gate insulating film 32, and the second interlayer insulating film 34 constitute a stacked insulating film 36. First to seventh contact holes Ha, Hb, Hc, Hd, He, Hf, and Hg, which will be described in detail later, are formed in the stacked insulating film 36. In addition, a relay line 40r shown in FIG. 6 is provided on the stacked insulating film 36. The relay line 40r is a wiring that relays the connection between the pixel circuit PC and the organic EL element 65.

[0057] The first gate insulating film 23, the lower first interlayer insulating film 26a, the upper first interlayer insulating film 26b, the second gate insulating film 32, the lower second interlayer insulating film 34a, and the upper second interlayer insulating film 34b are made of, for example, silicon oxide (SiO ２ The insulating film may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxynitride, etc. These various inorganic insulating films may be made of a single layer film or a multilayer film.

[0058] Specifically, the first gate insulating film 23, the upper first interlayer insulating film 26b, the second gate insulating film 32, and the lower second interlayer insulating film 34a are each made of silicon oxide (SiO ２ The lower first interlayer insulating film 26a and the upper second interlayer insulating film 34b are each made of silicon nitride (SiNx). The stacked body 36p is configured by stacking two types of inorganic insulating films made of different inorganic insulating materials.

[0059] The laminated body 36p in this example is configured by laminating two types of inorganic insulating films in multiple layers. The multiple inorganic insulating films that make up the laminated body 36p include silicon oxide (SiO ２ The upper first interlayer insulating film 26b, the second gate insulating film 32, and the lower second interlayer insulating film 34a are examples of the first inorganic insulating film. The lower second interlayer insulating film 34a and the upper second interlayer insulating film 34b are examples of the second inorganic insulating film.

[0060] The various wirings and electrodes described above are made of metal materials such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), etc. These various wirings and electrodes may be made of a single layer film or a multilayer film.

[0061] The first semiconductor layer 22 is made of polysilicon. The polysilicon that constitutes the first semiconductor layer 22 is, for example, low temperature polycrystalline silicon (LTPS). The second semiconductor layer 31 is made of an oxide semiconductor. The oxide semiconductor that constitutes the second semiconductor layer 31 is, for example, an In—Ga—Zn—O-based semiconductor.

[0062] The In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not limited. The In—Ga—Zn—O-based semiconductor may be amorphous or crystalline. Furthermore, the second semiconductor layer may include another oxide semiconductor in addition to or instead of the In—Ga—Zn—O-based semiconductor.

[0063] Other oxide semiconductors include, for example, In—Sn—Zn—O-based semiconductors (e.g., In ２ O ３ -SnO ２ In—Sn—Zn—O based semiconductors may include In—Sn—Zn—O based semiconductors, which are ternary oxides of In (indium), Sn (tin) and Zn (zinc).

[0064] Other oxide semiconductors may include In—Al—Zn—O based semiconductors, In—Al—Sn—O based semiconductors, Zn—O based semiconductors, In—Zn—O based semiconductors, Zn—Ti—O based semiconductors, Cd—Ge—O based semiconductors, Cd—Pb—O based semiconductors, CdO (cadmium oxide), Mg—Zn—O based semiconductors, and In—Ga—Sn—O based semiconductors.

[0065] Other oxide semiconductors include In—Ga—O-based semiconductors, Zr—In—Zn—O-based semiconductors, Hf—In—Zn—O-based semiconductors, Al—Ga—Zn—O-based semiconductors, and InGaO ３ (ZnO) ５ , magnesium zinc oxide (Mg ｘ Zn １－ｘ O), cadmium zinc oxide (Cd ｘ Zn １－ｘ O) may also be included.

[0066] 4, 8, and 9, the planarization film 58 is provided on the second interlayer insulating film 34 so as to cover the various wirings 40, the plurality of TFTs 50, and the plurality of capacitors 55 in the display area DA. The planarization film 58 extends over the entire display area DA. The surface of the TFT layer 20 is planarized by the planarization film 58.

[0067] An eighth contact hole Hh is formed for each sub-pixel SP in the planarization film 58. As shown in Fig. 6, the eighth contact hole Hh penetrates to the relay line 40r. The planarization film 58 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (Spin On Glass) material.

[0068] <Light Emitting Element Layer> As also shown in Figure 4, the light emitting element layer 60 is provided on the circuit board 5 (TFT layer 20). The light emitting element layer 60 includes a plurality of organic EL elements (organic electroluminescence elements) 65 and an edge cover 66. The organic EL elements 65 are an example of a light emitting element. The organic EL elements 65 are configured as a top emission type. Light emitted by the organic EL elements 65 is extracted to the sealing film 80 side.

[0069] A plurality of organic EL elements 65 are provided corresponding to a plurality of sub-pixels SP. Each organic EL element 65 constitutes a sub-pixel SP. The light emission of each organic EL element 65 is controlled by the operation of the corresponding pixel circuit PC. Each organic EL element 65 has a pixel electrode 61, an organic EL layer 62, and a common electrode 63.

[0070] The pixel electrodes 61 are provided on the planarization film 58. The pixel electrodes 61 are arranged in a matrix corresponding to each of the plurality of sub-pixels SP. Each pixel electrode 61 is connected to the pixel circuit PC (relay line 40r) via an eighth contact hole Hh. The pixel electrode 61 functions as an anode and injects holes into the organic EL layer 62. It is preferable to use a conductive material with a large work function for the pixel electrodes 61.

[0071] Examples of materials for the pixel electrodes 61 include metals such as silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), indium (In), and tin (Sn). The material for the pixel electrodes 61 may be a metal compound or an alloy. The material for the pixel electrodes 61 may be a conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrodes 61 may be formed of a single layer film or a laminated film.

[0072] The edge cover 66 is provided on the planarization film 58. The edge cover 66 is located above the pixel electrodes 61. The edge cover 66 is formed in a lattice shape so as to separate the multiple pixel electrodes 61. Specifically, the edge cover 66 extends between adjacent pixel electrodes 61 and around the periphery of the display area DA, and covers the outer edge (peripheral end portion) of each pixel electrode 61.

[0073] The edge cover 66 has a plurality of openings 67 corresponding to the sub-pixels SP. Each opening 67 partially exposes the pixel electrode 61 from the edge cover 66. The edge cover 66 is made of the same material as the planarizing film 58, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.

[0074] The organic EL layer 62 is provided on each pixel electrode 61 within the opening 67 of the edge cover 66. The organic EL layer 62 has a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer are stacked in this order on the pixel electrode 61 and are made of known compounds suitable for their respective functions. The organic EL layer 62 emits light when a current is applied between the pixel electrode 61 and the common electrode 63.

[0075] The common electrode 63 is provided as a continuous common film spanning multiple subpixels SP, extending across the entire display area DA. The common electrode 63 covers the edge cover 66 and each organic EL layer 62, and overlaps each pixel electrode 61 via the organic EL layer 62. The common electrode 63 also extends into the frame area FA and is connected to the second frame line 40b. The common electrode 63 functions as a cathode and injects electrons into the organic EL layer 62. It is preferable that the common electrode 63 be made of a conductive material with a small work function.

[0076] Examples of materials for the common electrode 63 include conductive oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). The material for the common electrode 63 may be a metal such as silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), calcium (Ca), or ytterbium (Yb). The material for the common electrode 63 may be a metal compound or an alloy. The common electrode 63 may be formed of a single layer film or a laminated film.

[0077] 4 , the sealing film 80 is provided on the light-emitting element layer 60. The sealing film 80 covers and seals the plurality of organic EL elements 65, protecting each organic EL element 65 (particularly the organic EL layer 62) from moisture, oxygen, and the like. The sealing film 80 is provided over the entire display area DA and extends into the frame area FA. The sealing film 80 has a first inorganic sealing layer 81, an organic sealing layer 82, and a second inorganic sealing layer 83.

[0078] The first inorganic sealing layer 81, the organic sealing layer 82, and the second inorganic sealing layer 83 are provided in this order on the light-emitting element layer 60. The first inorganic sealing layer 81 and the second inorganic sealing layer 83 extend further toward the outer periphery of the frame area FA than the organic sealing layer 82 and overlap each other in the outer portion of the frame area FA. The organic sealing layer 82 is enclosed by the first inorganic sealing layer 81 and the second inorganic sealing layer 83.

[0079] The first inorganic sealing layer 81 and the second inorganic sealing layer 83 are each made of an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The organic sealing layer 82 is made of an organic resin material such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, polyamide resin, etc. The organic sealing layer 82 is formed by applying a liquid material.

[0080] 7 is a pixel circuit PC corresponding to the sub-pixel SP in the mth row and nth column (m and n are positive integers). In the equivalent circuit diagram of Fig. 7, the first terminal electrode 37 of the first TFT 50A is indicated by "T1", and the second terminal electrode 38 is indicated by "T2". The third terminal electrode 28 of the second TFT 50B is indicated by "T3", and the fourth terminal electrode 29 is indicated by "T4".

[0081] 7, a source line 40s with (m) added to its reference symbol is the m-th source line 40s corresponding to the m-th row subpixel SP. A first gate line 40ga, a second gate line 40gb, an emission control line 40e, and an initialization line 40i with (n) added to its reference symbol are the m-th first gate line 40ga, the second gate line 40gb, the emission control line 40e, and the initialization line 40i corresponding to the n-th column subpixel SP, respectively. Furthermore, a second gate line 40gb with (n-2) added to its reference symbol is the n-2-th second gate line 40gb that is scanned two lines before the n-th second gate line 40gb.

[0082] The pixel circuit PC includes a plurality of TFTs 50, each of which is an initialization TFT 50a, a compensation TFT 50b, a writing TFT 50c, a driving TFT 50d, a power supply TFT 50e, a light emission control TFT 50f, and an anode discharge TFT 50g. The writing TFT 50c, the driving TFT 50d, the power supply TFT 50e, and the light emission control TFT 50f are P-channel TFTs 50, and are formed by a first TFT 50A. The initialization TFT 50a, the compensation TFT 50b, and the anode discharge TFT 50g are N-channel TFTs 50, and are formed by a second TFT 50B.

[0083] The initialization TFT 50a is provided between the second gate line 40gb(n-2) of the second previous stage (n-2 stages), the initialization line 40i(n) of the current stage, and the capacitor 55. The second gate electrode 33 of the initialization TFT 50a is connected to the second gate line 40gb(n-2). The third terminal electrode 28 of the initialization TFT 50a is connected to the initialization line 40i(n). The fourth terminal electrode 29 of the initialization TFT 50a is connected to the second capacitance electrode 30 of the capacitor 55.

[0084] The compensation TFT 50b is provided between the second gate line 40gb(n) of the current row (nth row) and the driving TFT 50d. The second gate electrode 33 of the compensation TFT 50b is connected to the second gate line 40gb(n). The third terminal electrode 28 of the compensation TFT 50b is connected to the second terminal electrode 38 of the driving TFT 50d. The fourth terminal electrode 29 of the compensation TFT 50b is connected to the first gate electrode 24 of the driving TFT 50d.

[0085] The writing TFT 50c is provided between the first gate line 40ga(n) of its own row (nth row), the source line 40s(m) of its own row (mth row), and the driving TFT 50d. The first gate electrode 24 of the writing TFT 50c is connected to the first gate line 40ga(n). The first terminal electrode 37 of the writing TFT 50c is connected to the source line 40s(m). The second terminal electrode 38 of the writing TFT 50c is connected to the first terminal electrode 37 of the driving TFT 50d.

[0086] The driver TFT 50d is provided between the initialization TFT 50a, the compensation TFT 50b, the capacitor 55, the writing TFT 50c, the power supply TFT 50e, and the emission control TFT 50f. The first gate electrode 24 of the driver TFT 50d is connected to the fourth terminal electrode 29 of the compensation TFT 50b and the fourth terminal electrode 29 of the initialization TFT 50a. The first terminal electrode 37 of the driver TFT 50d is connected to the second terminal electrode 38 of the writing TFT 50c and the second terminal electrode 38 of the power supply TFT 50e. The second terminal electrode 38 of the driver TFT 50d is connected to the third terminal electrode 28 of the compensation TFT 50b and the first terminal electrode 37 of the emission control TFT 50f.

[0087] The power supply TFT 50e is provided between the light-emitting control line 40e(n) of the current stage (nth stage), the power supply line 40p, and the driving TFT 50d. The first gate electrode 24 of the power supply TFT 50e is connected to the light-emitting control line 40e(n). The first terminal electrode 37 of the power supply TFT 50e is connected to the power supply line 40p. The second terminal electrode 38 of the power supply TFT 50e is connected to the first terminal electrode 37 of the driving TFT 50d.

[0088] The light-emission control TFT 50f is provided between the light-emission control line 40e(n) of the current row (nth row), the driving TFT 50d, and the organic EL element 65. The first gate electrode 24 of the light-emission control TFT 50f is connected to the light-emission control line 40e(n). The first terminal electrode 37 of the light-emission control TFT 50f is connected to the second terminal electrode 38 of the driving TFT 50d. The second terminal electrode 38 of the light-emission control TFT 50f is connected to the pixel electrode 61 of the organic EL element 65.

[0089] The anode discharge TFT 50g is provided between the light-emitting control line 40e(n) of its own row (nth row), the initialization line 40i(n) of its own row (nth row), and the organic EL element 65. The second gate electrode 33 of the anode discharge TFT 50g is connected to the light-emitting control line 40e(n). The third terminal electrode 28 of the anode discharge TFT 50g is connected to the pixel electrode 61 of the organic EL element 65. The fourth terminal electrode 29 of the anode discharge TFT 50g is connected to the initialization line 40i(n).

[0090] The capacitor 55 is provided between the power supply line 40p, the initialization TFT 50a, and the driving TFT 50d. The first capacitance electrode 25 of the capacitor 55 is connected to the first gate electrode 24 of the driving TFT 50d, the fourth terminal electrode 29 of the initialization TFT 50a, and the fourth terminal electrode 29 of the compensation TFT 50b. The second capacitance electrode 30 of the capacitor 55 is connected to the power supply line 40p.

[0091] 5, the second gate insulating film 32 included in the stacked insulating film 36 is provided so as to correspond to the second gate line 40gb integral with the second gate electrode 33 of the initialization TFT 50a in plan view. The second gate insulating film 32 is also provided so as to extend between the second gate line 40gb integral with the second gate electrode 33 of the compensation TFT 50b and the second gate line 40gb integral with the second gate electrode 33 of the anode discharge TFT 50g.

[0092] An opening 32a is formed in the second gate insulating film 32 so as to include within it a portion corresponding to the second contact hole Hb in plan view and its periphery. The opening 32a in this example is also formed so as to correspond to the conductor region 31b of the second semiconductor layer 31 of the compensation TFT 50b in plan view. The opening 32a may be formed separately in the portion of the second gate insulating film 32 corresponding to the second contact hole Hb and in the portion corresponding to the conductor region 31b of the second semiconductor layer 31 of the compensation TFT 50b.

[0093] A plurality of first contact holes Ha, a plurality of second contact holes Hb, a plurality of third contact holes Hc, a plurality of fourth contact holes Hd, and a plurality of fifth contact holes He are formed in the stacked insulating film 36. Each of the first contact holes Ha, each of the second contact holes Hb, each of the third contact holes Hc, each of the fourth contact holes Hd, and each of the fifth contact holes He is formed collectively in the stacked insulating film 36 and opens in the surface of the upper second interlayer insulating film 34b.

[0094] Two first contact holes Ha are provided for each pixel circuit PC (see FIGS. 5 and 6 ). One of the first contact holes Ha is a contact hole for connecting the first terminal electrode 37 of the writing TFT 50 c to the conductor region 22 b of the first semiconductor layer 22, and penetrates into the conductor region 22 b. The other first contact hole Ha is a contact hole for connecting the second terminal electrode 38 of the power supply TFT 50 e to the conductor region 22 b of the first semiconductor layer 22, and penetrates into the conductor region 22 b. As shown in FIG. 10A , the laminated structure of the inorganic insulating film at the penetration portion of the first contact hole Ha includes the first gate insulating film 23, the lower first interlayer insulating film 26 a, the upper first interlayer insulating film 26 b, the lower second interlayer insulating film 34 a, and the upper second interlayer insulating film 34 b.

[0095] One second contact hole Hb is provided for each pixel circuit PC (see FIGS. 5 and 6). The second contact hole Hb is a contact hole for connecting the power supply line 40p to the first gate electrode 24 of the drive TFT 50d, and penetrates the first gate electrode 24. As shown in FIG. 10B, the laminated structure of the inorganic insulating film at the penetration portion of the second contact hole Hb is made up of a lower first interlayer insulating film 26a, an upper first interlayer insulating film 26b, a lower second interlayer insulating film 34a, and an upper second interlayer insulating film 34b.

[0096] One third contact hole Hc is provided for each pixel circuit PC (see FIGS. 5 and 6). The third contact hole Hc is a contact hole for connecting the power supply line 40p to the first capacitance electrode 25 of the capacitor 55, and penetrates the first capacitance electrode 25. As shown in FIG. 10C, the stacked structure of inorganic insulating films at the penetration portion of the third contact hole Hc is made up of the second gate insulating film 32, the lower second interlayer insulating film 34a, and the upper second interlayer insulating film 34b. In this way, the stacked structure of inorganic insulating films forming the stack 36p includes the second gate insulating film 32 at the penetration portion of the third contact hole Hc.

[0097] One fourth contact hole Hd is provided for each pixel circuit PC (see FIGS. 5 and 6 ). A first common terminal electrode 39a, which forms the second terminal electrode 38 of the emission control TFT 50f and the first terminal electrode 37 of the anode discharge TFT 50g, is provided on the first interlayer insulating film 26. One of the fourth contact holes Hd is a contact hole for connecting the relay line 40r to the first common terminal electrode 39a and penetrates the first common terminal electrode 39a. The other fourth contact hole Hd is a contact hole for connecting the power supply line 40p to the fourth terminal electrode 29 of the initialization TFT 50a and penetrates the fourth terminal electrode 29. As shown in FIG. 10D , the laminated structure of the inorganic insulating film at the penetration point of the fourth contact hole Hd consists of a lower second interlayer insulating film 34a and an upper second interlayer insulating film 34b.

[0098] One fifth contact hole He is provided for each pixel circuit PC (see FIGS. 5 and 6). The fifth contact hole He is a contact hole for connection to the second capacitance electrode 30 of the capacitor 55, and penetrates to the second capacitance electrode 30. As shown in FIG. 10E, the laminated structure of the inorganic insulating film at the penetration point of the fifth contact hole He is made up of a lower second interlayer insulating film 34a and an upper second interlayer insulating film 34b.

[0099] Thus, of the first to fifth contact holes Ha, Hb, Hc, Hd, and He, the first contact hole Ha penetrates all the way to the lowest layer. The second gate insulating film 32 is provided in the stacked insulating film 36 at the penetration location of the third contact hole Hc, but is not provided at the penetration locations of the first contact hole Ha, the second contact hole Hb, the fourth contact hole Hd, and the fifth contact hole He. The stacked structure of the inorganic insulating films constituting the stack 36p above the first semiconductor layer 22 in the stacked insulating film 36 is the same at the penetration location of the first contact hole Ha and the penetration location of the second contact hole Hb, and does not include the second gate insulating film 32.

[0100] 5 and 6, a plurality of sixth contact holes Hf and a plurality of seventh contact holes Hg are further formed in the stacked insulating film 36. Each of the sixth contact holes Hf and each of the seventh contact holes Hg opens in the surface of the upper first interlayer insulating film 26b.

[0101] Two sixth contact holes Hf are provided for each pixel circuit PC. One sixth contact hole Hf is a contact hole for connecting the third terminal electrode 28 of the compensation TFT 50 b to the first terminal electrode 37 of the emission control TFT 50 f, and penetrates the first terminal electrode 37. The other sixth contact hole Hf is a contact hole for connecting the second terminal electrode 38 of the emission control TFT 50 f to the conductor region 22 b of the first semiconductor layer 22, and penetrates the conductor region 22 b.

[0102] One seventh contact hole Hg is provided for each pixel circuit PC. A second common terminal electrode 39b is provided, which serves as the third terminal electrode 28 of the initialization TFT 50a and the fourth terminal electrode 29 of the anode discharge TFT 50g. The seventh contact hole Hg is a contact hole for connecting the second common terminal electrode 39b to the initialization line 40i, and penetrates the initialization line 40i.

[0103] —Operation of Organic EL Display Device— In the organic EL display device 1, the corresponding light-emission control line 40e is first selected and set to an active state (high level) in each sub-pixel SP. When the light-emission control line 40e is set to an active state, the power supply TFT 50e and the light-emission control TFT 50f are set to an off state, and the organic EL element 65 is set to a non-light-emitting state.

[0104] Furthermore, when the light emission control line 40e is activated, the anode discharge TFT 50g is turned on. When the anode discharge TFT 50g is turned on, the voltage of the initialization line 40i is applied to the pixel electrode 61 of the organic EL element 65. This resets the charge accumulated in the pixel electrode 61.

[0105] Next, the second gate line 40gb, which is scanned two lines before the second gate line 40gb corresponding to the non-light-emitting organic EL element 65, is selected and set to an active state (High level). When the second gate line 40gb in the second line before the previous one is set to an active state, a gate signal is input to the initialization TFT 50a via that second gate line 40gb.

[0106] When a gate signal is input to the initialization TFT 50a, the initialization TFT 50a is turned on. When the initialization TFT 50a is turned on, the voltage (initialization voltage) of the initialization line 40i is applied to the capacitor 55. This causes the charge in the capacitor 55 to be discharged, and the voltage applied to the first gate electrode 24 of the driving TFT 50d is initialized.

[0107] Next, the first gate line 40ga corresponding to the non-emitting organic EL element 65 is selected and set to an active state (high level). When the first gate line 40ga is set to an active state, the compensation TFT 50b is set to an on state. Then, when the second gate line 40gb corresponding to the non-emitting organic EL element 65 is selected and set to an inactive state (low level), the writing TFT 50c is set to an on state.

[0108] When the compensation TFT 50b and the writing TFT 50c are turned on, the driving TFT 50d is turned into a diode-connected state, and a predetermined voltage corresponding to the source signal transmitted via the source line 40s is written into the capacitor 55 via the driving TFT 50d. Subsequently, the light-emitting control line 40e corresponding to the non-light-emitting organic EL element 65 is turned into an inactive state (low level).

[0109] When the light-emission control line 40e is inactivated, the power supply TFT 50e and the light-emission control TFT 50f are turned on, and a drive current corresponding to the voltage applied to the first gate electrode 24 of the drive TFT 50d is supplied from the power supply line 40p to the organic EL element 65. In this way, each organic EL element 65 emits light at a brightness corresponding to the drive current. As a result, an image is displayed in the display area DA of the organic EL display device 1.

[0110] -Method of Manufacturing Organic EL Display Device- To manufacture the organic EL display device 1, first, an organic resin material is applied to the surface of a glass substrate and baked, thereby forming a substrate layer 10 on the glass substrate.

[0111] Next, the TFT layer 20, the light-emitting element layer 60, and the sealing film 80 are formed in this order on the substrate layer 10 using a known film formation method such as plasma CVD (Chemical Vapor Deposition), sputtering, or vacuum deposition, a known coating method such as spin coating or slit coating, or a known patterning technique such as photolithography.

[0112] Thereafter, the glass substrate is peeled off from the substrate layer 10 by, for example, irradiating the rear surface of the substrate layer 10 with laser light from the glass substrate side. Next, a protective film 11 is attached to the rear surface of the substrate layer 10. A polarizing plate and a cover panel are attached to the surface of the sealing film 80. Furthermore, a wiring substrate CB is connected to the terminal portion TP. As a result, a display control circuit (source driver) is mounted on the panel that constitutes the organic EL display device 1.

[0113] In this manner, the organic EL display device 1 can be manufactured.

[0114] <Contact Hole Forming Process> In the process of forming the TFT layer 20, a hole forming process is performed after the upper second interlayer insulating film 34b is formed to form the stacked insulating film 36. The first to fifth contact holes Ha, Hb, He, Hd, and He are formed collectively by photolithography in the locations where the first to fifth contact holes Ha, Hb, He, Hd, and He are to be formed in the stacked insulating film 36 shown in FIGS. 11A to 11E (regions indicated by two-dot chain lines; the same applies to FIGS. 12A to 12E ).

[0115] In the hole formation process, first, a photosensitive resin is applied to a substrate on which a stacked insulating film 36 has been formed by a known application method such as spin coating or slit coating to form a photosensitive resin coating film. The photosensitive resin coating film is then pre-baked, exposed to light, developed, and post-baked. This forms a resist 100 having openings 101 at the locations where the first to fifth contact holes Ha, Hb, Hc, Hd, and He will be formed, as shown in FIGS. 12A to 12E .

[0116] Then, the laminated insulating film 36 is dry-etched using the resist 100 as a mask. In the hole formation process of this example, two-stage dry etching is performed, in which the laminated insulating film 36 is etched at a relatively high etching rate and then at a relatively low etching rate. Specifically, the hole formation process includes a first step and a second step.

[0117] In the first step, the stacked insulating film 36 is dry-etched to a depth equal to or greater than a predetermined depth common to the first to fifth contact holes Ha, Hb, Hc, Hd, and He, but shallower than the depth of the first contact hole Ha. In this example, the stacked insulating film 36 is dry-etched to the penetration position of the second contact hole Hb (the position of the first gate electrode). At this time, in the locations where the second to fifth contact holes Hb, Hc, Hd, and He are formed, the metal layers (the first gate electrode 24, the first capacitor electrode 25, the common terminal electrode 39, and the second capacitor electrode 30) exposed at the bottom function as an etching stopper.

[0118] 13A to 13E, the first step forms second to fifth contact holes Hb, Hc, Hd, and He, penetrating to their respective predetermined penetration positions. At this time, the first contact hole Ha is formed only to the same position as the second contact hole Hb, i.e., to a midpoint position. The first gate insulating film 23 remains at the bottom of the first contact hole Ha.

[0119] In the first step of dry etching, a first etching gas is used. The first etching gas is, for example, sulfur hexafluoride (SF ６ The first etching gas is a mixture of silicon dioxide (SiO ２ The first etching gas exhibits a relatively high etching rate for silicon oxide (SiO ２ ) is lower than the etching rate for silicon nitride (SiNx).

[0120] In the second step, the stacked insulating film 36 is dry-etched to a depth where the first contact hole Ha penetrates. At this time, the metal layers (the first gate electrode 24, the first capacitor electrode 25, the common terminal electrode 39, and the second capacitor electrode 30) function as etching stoppers where the second to fifth contact holes Hb, Hc, Hd, and He are formed. As shown in FIGS. 14A to 14E , by performing the second step, the first gate insulating film 23 remaining at the bottom of the first contact hole Ha is removed, and the first contact hole Ha is formed to penetrate to a predetermined penetration position (a position where the conductor region 22b of the first semiconductor layer 22 is exposed at the bottom).

[0121] In the second step of dry etching, a second etching gas is used. The second etching gas is tetracarbon octafluoride (C ４ F ８ ), argon (Ar), and hydrogen (H ２ The second etching gas is a mixture of silicon dioxide (SiO ２ ) and silicon nitride (SiNx).２ ) is higher than the etching rate for silicon nitride (SiNx).

[0122] In this manner, the first to fifth contact holes Ha, Hb, Hc, Hd, and He are formed in the laminated insulating film 36.

[0123] 15 , the second gate insulating film 32 is also provided at the penetration portion of the second contact hole Hb. In this case, the stacked structure of the stacked insulating film 36 at the penetration portion of the second contact hole Hb is made up of the lower first interlayer insulating film 26 a, the upper first interlayer insulating film 26 b, the second gate insulating film 32, the lower second interlayer insulating film 34 a, and the upper second interlayer insulating film 34 b, and is different from the stacked structure of the stacked insulating film 36 at the penetration portion of the first contact hole Ha.

[0124] In the manufacture of an organic EL display device 1 including this comparative example circuit board 5, as shown in FIGS. 16A-16E and 17A-17E, when the first through fifth contact holes Ha, Hb, Hec, Hd, and He are simultaneously formed in the stacked insulating film 36, the depths of the holes formed by the first dry etching step differ between the locations of the first contact hole Ha and the second contact hole Hb in the stacked insulating film 36, resulting in a step depending on the presence or absence of the second gate insulating film 32 (see FIGS. 16A and 16B). As a result, even if the deepest first contact hole Ha penetrates to a predetermined position during the second dry etching step, the second contact hole Hb may not penetrate to the predetermined position, resulting in a film residue Rf of the lower first interlayer insulating film 26a at the bottom of the second contact hole Hb (see FIGS. 17A and 17B). This can result in poor connection to the wiring through the second contact hole Hb.

[0125] In contrast, in the circuit board 5 of this embodiment, the laminate structure of the inorganic insulating films forming the laminate 36p is identical between the penetration portion of the first contact hole Ha and the penetration portion of the second contact hole Hb, without including the second gate insulating film 32. As a result, when the first through fifth contact holes Ha, Hb, Hec, Hd, and He are simultaneously formed in the laminated insulating film 36 during the manufacturing of the organic EL display device 1, the depths of the holes formed by the first dry etching step are the same at the formation portions of the first contact hole Ha and the second contact hole Hb in the laminated insulating film 36 (see FIGS. 13A and 13B). This allows the second contact hole Hb to penetrate to a predetermined penetration position, and after the second step is performed, no film residue Rf is present at the bottom of the second contact hole Hb (see FIG. 14B). As a result, poor connection to the wiring through the second contact hole Hb can be prevented.

[0126] Furthermore, in the circuit board 5 of this embodiment, the laminated structure of inorganic insulating films forming the laminate 36p includes the second gate insulating film 32 at the portion through which the third contact hole Hc penetrates. To avoid including the second gate insulating film 32 at the portion through which the third contact hole Hc penetrates the laminate 36p, it is possible to form an opening in the second gate insulating film 32 so as to include the portion corresponding to the third contact hole Hc and its periphery in a planar view. However, forming such an opening requires an extra margin between the third contact hole Hc and its neighboring components to stabilize the relationship between the opening and its surrounding components (e.g., whether or not it overlaps in a planar view), which is disadvantageous in achieving high resolution in the organic EL display device 1. In contrast, the configuration of this embodiment does not require an opening to be formed in the portion of the second gate insulating film 32 corresponding to the third contact hole Hc and its periphery. This eliminates the aforementioned constraints on the position of the third contact hole Hc, which is advantageous in achieving high resolution in the organic EL display device 1.

[0127] Other Embodiments In the above embodiment, the first contact hole Ha is a contact hole that penetrates into the conductor region 22b of the first semiconductor layer 22, and the second contact hole Hb is a contact hole that penetrates into the first gate electrode 24, but this is not limiting. For example, the first contact hole Ha may be a contact hole that penetrates into a conductive layer, such as a wiring or an electrode, that is provided on the base coat film 21, separate from the first semiconductor layer 22. In this case, the conductive layer exposed at the bottom of the first contact hole Ha corresponds to the first conductive portion.

[0128] Furthermore, the second contact hole Hb may be a contact hole that penetrates a conductive layer, such as a wiring or electrode, provided on the first gate insulating film 23, separate from the first gate electrode 24. In this case, the conductive layer exposed at the bottom of the second contact hole Hb corresponds to the second conductive portion. For example, the conductive layer may be formed in the same layer and from the same material as the first gate electrode 24. In short, it is sufficient that the first contact hole Ha penetrates to a layer lower than the second contact hole Hb, and the second contact hole Hb penetrates to a layer lower than the second gate insulating film 32.

[0129] In the above embodiment, the circuit board 5 according to the technology of the present disclosure has been described as having a hybrid structure that combines the first TFT 50A (polysilicon TFT) having the first semiconductor layer 22 made of polysilicon and the second TFT 50B (oxide semiconductor TFT) having the second semiconductor layer 31 made of an oxide semiconductor, but is not limited to this. The circuit board 5 according to the technology of the present disclosure may not include the first TFT 50A.

[0130] In the above embodiment, the first interlayer insulating film 26 and the second interlayer insulating film 34 each have a two-layer structure, but this is not limiting. Each of the first interlayer insulating film 26 and the second interlayer insulating film 34 may have a single-layer structure, or may be configured by stacking three or more layers of inorganic insulating films.

[0131] In the above embodiment, the stacked structure of inorganic insulating films forming the stack 36p includes the second gate insulating film 32 at the portion where the third contact hole Hc passes through, but this is not limited to this. For example, an opening may be formed in the second gate insulating film 32 so as to include within the portion corresponding to the third contact hole Hc and its periphery in plan view. As a result, the second gate insulating film 32 may not be included at the portion where the third contact hole Hc passes through the stack 36p.

[0132] In the above embodiment, two-stage dry etching is performed in the hole formation process, but this is not limited to this. The dry etching performed in the hole formation process may be performed only once using a single etching gas. Furthermore, if the laminated insulating film 36 has a large number of inorganic insulating film layers, dry etching in the hole formation process may be performed three or more times. In this case, three or more types of etching gases may be used as needed.

[0133] In the above embodiment, the organic EL layer 62 is provided individually for each subpixel SP, but this is not limited to this. The organic EL layer 62 may be provided as a continuous layer common to multiple subpixels SP. In this case, the organic EL display device 1 may be provided with a color filter or the like to express color tones in each subpixel SP.

[0134] In the above embodiment, each pixel PX is configured with sub-pixels SP of three colors, but this is not limited to this. The sub-pixels SP that configure each pixel PX may be of four or more colors. Furthermore, the three sub-pixels SP that configure each pixel PX are arranged in a stripe pattern, but this is not limited to this. The arrangement of the multiple sub-pixels SP may be another arrangement, such as a pentile arrangement.

[0135] In the above embodiment, the pixel electrode 61 functions as an anode and the common electrode 63 functions as a cathode, but this is not limiting. The organic EL display device 1 may be configured so that the pixel electrode 61 functions as a cathode and the common electrode 63 functions as an anode. In this case, the organic EL layer 62 has an inverted stacked structure.

[0136] In the above embodiment, the organic EL layer 62 has a five-layer structure including a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, but is not limited to this. The organic EL layer 62 may have a three-layer structure including a hole injection / transport layer, a light-emitting layer, and an electron injection / transport layer, or any other laminated structure may be adopted.

[0137] In the above embodiment, the substrate of the organic EL display device 1 is the substrate layer 10, but this is not limiting. The substrate may be made of any material, such as a plastic substrate made of polyethylene terephthalate (PET) or a glass substrate.

[0138] In the above embodiment, an organic EL display device 1 is exemplified as a display device according to the present disclosure, but the present disclosure is not limited thereto. The technology of the present disclosure can be applied to a display device including a plurality of light-emitting elements. An example of such a display device is a quantum dot display device including QLEDs (Quantum-dot Light Emitting Diodes), which are light-emitting elements using a quantum dot-containing layer. The technology of the present disclosure can also be applied to liquid crystal display devices and plasma display devices.

[0139] As described above, preferred embodiments have been described as examples of the technology of the present disclosure. However, the technology of the present disclosure is not limited to these, and can be applied to embodiments in which appropriate modifications, substitutions, additions, omissions, etc. are made. It will be understood by those skilled in the art that various modifications are possible to the above-described embodiments without departing from the spirit of the technology of the present disclosure, and that such modifications also fall within the scope of the technology of the present disclosure.

[0140] As described above, the technology of the present disclosure is useful for a circuit board and a display device including the same.

[0141] DA Display area Ha First contact hole Hb Second contact hole Hc Third contact hole SP Sub-pixel 1 Organic EL display device (display device) 5 Circuit board 10 Substrate layer (substrate) 22 First semiconductor layer 22b Conductor region of first semiconductor layer (first conductive portion) 23 First gate insulating film (first insulating film) 24 First gate electrode (second conductive portion) 25 First capacitor electrode (third conductive portion, conductive layer) 26a Lower first interlayer insulating film (inorganic insulating film, second inorganic insulating film) 26b Upper first interlayer insulating film (inorganic insulating film, first inorganic insulating film) 31 Second semiconductor layer (semiconductor layer) 32 Second gate insulating film (gate insulating film, first inorganic insulating film) 34a Lower second interlayer insulating film (inorganic insulating film, first inorganic insulating film) 34b Upper second interlayer insulating film (inorganic insulating film, second inorganic insulating film) 36 Stacked insulating film 36p Laminate (second insulating film) 50A First TFT (first thin film transistor) 50B Second TFT (thin film transistor, second thin film transistor) 60 Light-emitting element layer 65 Organic EL element (light-emitting element)

Claims

1. A circuit board comprising: a substrate; a first conductive portion provided on the substrate; a first insulating film provided so as to cover the first conductive portion; a second conductive portion provided on the first insulating film; and a second insulating film provided so as to cover the second conductive portion, the second insulating film being configured by laminating at least two types of inorganic insulating films made of mutually different inorganic insulating materials; a thin film transistor is provided inside the second insulating film, the thin film transistor having a semiconductor layer made of an oxide semiconductor and a gate insulating film provided so as to partially cover the semiconductor layer and forming one inorganic insulating film in the second insulating film; a first contact hole penetrating the first conductive portion and a second contact hole penetrating the second conductive portion are formed in the laminated insulating film made of the first insulating film and the second insulating film; and a laminated structure of the inorganic insulating film forming the second insulating film is identical to each other at a penetration portion of the first contact hole and a penetration portion of the second contact hole, without including the gate insulating film.

2. A circuit board according to claim 1, comprising a first thin film transistor having a first semiconductor layer made of polysilicon, the thin film transistor being a second thin film transistor having a second semiconductor layer as the semiconductor layer and a second gate insulating film as the gate insulating film, and the first conductive portion being a part of the first semiconductor layer.

3. A circuit board as described in claim 2, wherein the first thin film transistor has a first gate insulating film provided so as to cover the first semiconductor layer, and a first gate electrode provided on the first gate insulating film, and the second conductive portion is a conductive layer formed of the same material as the first gate electrode or in the same layer as the first gate electrode.

4. A circuit board according to any one of claims 1 to 3, wherein a third conductive portion is provided on an inorganic insulating film located below the gate insulating film among the plurality of inorganic insulating films constituting the second insulating film, a third contact hole is formed in the second insulating film, penetrating to the third conductive portion, and the laminated structure of the inorganic insulating films constituting the second insulating film includes the gate insulating film at the penetration point of the third contact hole.

5. A circuit board as claimed in claim 4, wherein the thin film transistor has a terminal electrode overlapping and connected to a portion of the semiconductor layer, and the third conductive portion is the terminal electrode or a conductive layer formed in the same layer as the terminal electrode and made of the same material.

6. A circuit board according to any one of claims 1 to 5, wherein the second insulating film is formed by laminating at least two types of inorganic insulating films in multiple layers.

7. A circuit board according to any one of claims 1 to 6, wherein the plurality of inorganic insulating films constituting the second insulating film include a first inorganic insulating film made of silicon oxide and a second inorganic insulating film made of silicon nitride.

8. A display device comprising the circuit board according to any one of claims 1 to 7.

9. A display device according to claim 8, comprising a light emitting element layer provided on the circuit board, the light emitting element layer having a plurality of light emitting elements provided corresponding to a plurality of sub-pixels forming a display area, and the first contact hole and the second contact hole being formed for each of the sub-pixels.

10. The display device according to claim 9, wherein the light-emitting element is an organic electroluminescence element.

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