Light detection device, imaging device, and method for manufacturing light detection device

Abstract

The present invention suppresses an increase in dark current caused by a defect at an interface of an element isolation layer embedded in a semiconductor layer on which light is incident.　This light detection device comprises: a first conductivity-type impurity diffusion layer provided at a light incident position; a second conductivity-type impurity diffusion layer bonded to the first conductivity-type impurity diffusion layer; an element isolation layer embedded in the first conductivity-type impurity diffusion layer so as to isolate the second conductivity-type impurity diffusion layer; and a pinning layer spaced apart from the second conductivity-type impurity diffusion layer and provided at an interface between the first conductivity-type impurity diffusion layer and the element isolation layer. The element isolation layer may be continuously provided so as to surround the periphery of the second conductivity-type impurity diffusion layer.

Description

Photodetection device, imaging device, and method for manufacturing a photodetection device

[0001] The present technology relates to a photodetector, an imaging device, and a method for manufacturing the photodetector. More specifically, the present technology relates to a photodetector, an imaging device, and a method for manufacturing the photodetector, in which an element isolation layer is embedded in a semiconductor layer into which light is incident.

[0002] In order to isolate the photoelectric conversion unit, STI (Shallow Trench Isolation) is sometimes used. ＋ A CMOS image sensor has been proposed in which a p-type silicon substrate disposed on a substrate has an STI region etched from its surface and filled with silicon dioxide (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2008-160132

[0004] However, in the above-mentioned conventional technology, if the region of the depletion layer in contact with the STI increases, there is a risk that dark current will increase due to defects at the interface of the STI.

[0005] This technology was developed in light of these circumstances, and aims to suppress an increase in dark current caused by defects at the interface of an isolation layer buried in a semiconductor layer where light is incident.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a photodetector including: a first conductivity type impurity diffusion layer provided at a position where light is incident; a second conductivity type impurity diffusion layer joined to the first conductivity type impurity diffusion layer; an element isolation layer embedded in the first conductivity type impurity diffusion layer so as to isolate the second conductivity type impurity diffusion layer; and a pinning layer spaced from the second conductivity type impurity diffusion layer and provided at an interface between the first conductivity type impurity diffusion layer and the element isolation layer, thereby achieving the effect of pinning the interface between the first conductivity type impurity diffusion layer and the element isolation layer while reducing the capacitance of the second conductivity type impurity diffusion layer.

[0007] In the first aspect, the element isolation layer may be provided continuously so as to surround the periphery of the second conductivity type impurity diffusion layer, thereby reducing the capacitance of the entire periphery of the second conductivity type impurity diffusion layer.

[0008] In the first aspect, the pinning layer may be provided continuously so as to surround the outer periphery of the element isolation layer, thereby providing the effect of pinning the interface of the entire outer periphery of the element isolation layer.

[0009] In the first aspect, the pinning layer may be provided on the bottom surface of the element isolation layer, thereby providing the effect of pinning the bottom surface of the element isolation layer.

[0010] In the first aspect, the inner circumferential surface of the element isolation layer may have a step provided at a position deeper than the depth of the second conductivity type impurity diffusion layer, thereby preventing a pinning layer from being formed at a position shallower than the step on the inner circumferential surface side of the element isolation layer.

[0011] In the first aspect, the first conductivity type impurity diffusion layer may be used as a collector of a bipolar phototransistor, the second conductivity type impurity diffusion layer may be used as a base of the bipolar phototransistor, and the emitter of the bipolar phototransistor may be joined to the base, thereby reducing the base capacitance of the bipolar phototransistor and pinning the interface between the collector and the element isolation layer.

[0012] In the first aspect, the emitter of the bipolar phototransistor may be provided at a position where it is in contact with the element isolation layer, thereby reducing the junction area between the emitter and base of the bipolar phototransistor and reducing the base capacitance.

[0013] In the first aspect, the second conductivity type impurity diffusion layer may be used in a second conductivity type well in which a channel is formed in a MOSFET phototransistor, and a first conductivity type source layer and a first conductivity type drain layer may be provided in the second conductivity type well, spaced apart via the channel. This reduces the capacitance of the well in which the channel of the MOSFET phototransistor is formed, and pins the interface between the substrate in which the well is formed and the element isolation layer.

[0014] According to a second aspect, there is provided an imaging device including a pixel array unit in which pixels are arranged in a matrix in a row direction and a column direction, each pixel including a photoelectric conversion unit that converts light into an electric signal, the photoelectric conversion unit including a first conductivity type impurity diffusion layer provided at a position where the light is incident, a second conductivity type impurity diffusion layer joined to the first conductivity type impurity diffusion layer, an element isolation layer embedded in the first conductivity type impurity diffusion layer so as to isolate the second conductivity type impurity diffusion layer, and a pinning layer spaced from the second conductivity type impurity diffusion layer and provided at an interface between the first conductivity type impurity diffusion layer and the element isolation layer, thereby achieving an effect of pinning the interface between the first conductivity type impurity diffusion layer and the element isolation layer while reducing the capacitance of the second conductivity type impurity diffusion layer provided in the pixel.

[0015] In the second aspect, the element isolation layer may be provided continuously so as to surround the periphery of the second conductivity type impurity diffusion layer, thereby reducing the capacitance of the entire periphery of the second conductivity type impurity diffusion layer provided in the pixel.

[0016] In the second aspect, the pinning layer may be provided continuously so as to surround the outer periphery of the element isolation layer, thereby providing the effect of pinning the interface of the entire outer periphery of the element isolation layer provided in the pixel.

[0017] In the second aspect, the pinning layer may be provided on the bottom surface of the element isolation layer, thereby providing the effect of pinning the bottom surface of the element isolation layer provided in the pixel.

[0018] In the second aspect, the inner circumferential surface of the element isolation layer may be located at a position deeper than the depth of the second conductivity type impurity diffusion layer, thereby preventing a pinning layer from being formed at a position shallower than the step on the inner circumferential surface side of the element isolation layer provided in the pixel.

[0019] In a second aspect, the pinning layer may be continuously provided from the outer peripheral surface of the isolation layer through the bottom of the isolation layer to a position in the depth direction of the step on the inner peripheral surface of the isolation layer, thereby providing an effect of pinning the interface between the first conductivity type impurity diffusion layer and the isolation layer while providing a gap separating the second conductivity type impurity diffusion layer and the pinning layer.

[0020] In a second aspect, the first conductivity type impurity diffusion layer may be used as a collector of a bipolar phototransistor, the second conductivity type impurity diffusion layer may be used as a base of the bipolar phototransistor, and the emitter of the bipolar phototransistor may be joined to the base, thereby reducing the base capacitance of the bipolar phototransistor provided in the pixel and pinning the interface between the collector and the element isolation layer.

[0021] In the second aspect, the emitter of the bipolar phototransistor may be provided at a position in contact with the element isolation layer, thereby reducing the junction area between the emitter and base of the bipolar phototransistor provided in the pixel, thereby reducing the base capacitance.

[0022] In a second aspect, the second conductivity type impurity diffusion layer may be used for a second conductivity type well in which a channel is formed in a MOSFET phototransistor, and a first conductivity type source layer and a first conductivity type drain layer spaced apart via the channel are provided in the second conductivity type well, thereby reducing the capacitance of the well in which the channel of the MOSFET phototransistor provided in the pixel is formed and pinning the interface between the substrate in which the well is formed and the element isolation layer.

[0023] A third aspect of the present invention is a method for manufacturing a photodetector, comprising the steps of: forming a trench in a first-conductivity-type impurity diffusion region, the trench having a high-concentration first-conductivity-type impurity diffusion layer formed on a part of a sidewall thereof; forming an isolation layer embedded in the trench; and forming a second-conductivity-type impurity diffusion layer separated by the isolation layer and joined to the first-conductivity-type impurity diffusion region at a position spaced apart from the high-concentration first-conductivity-type impurity diffusion layer, thereby providing an effect that a pinning layer provided at an interface between the first-conductivity-type impurity diffusion layer and the isolation layer is formed spaced apart from the second-conductivity-type impurity diffusion layer.

[0024] In a third aspect, the step of forming the trench in the first-conductivity-type impurity diffusion region, the high-concentration first-conductivity-type impurity diffusion layer being provided on a portion of the sidewall, may include the steps of: forming the high-concentration first-conductivity-type impurity diffusion layer in the first-conductivity-type impurity diffusion region spaced apart from a surface of the first-conductivity-type impurity diffusion region by ion implantation; and forming the trench in the first-conductivity-type impurity diffusion region so that the high-concentration first-conductivity-type impurity diffusion layer remains on a portion of the sidewall. This provides the effect of preventing an increase in the number of steps and forming the pinning layer provided at the interface between the first-conductivity-type impurity diffusion layer and the element isolation layer so as to be spaced apart from the second-conductivity-type impurity diffusion layer.

[0025] In a third aspect, the step of forming the trench in the first-conductivity-type impurity diffusion region, the high-concentration first-conductivity-type impurity diffusion layer being provided on a part of the sidewall, may include the steps of forming a trench in the first-conductivity-type impurity diffusion region, forming a mask on the sidewall of the trench, etching the bottom of the trench whose sidewall is covered with the mask to form a step in the trench located at a position in a depth direction of the mask, and introducing first-conductivity-type impurities into the sidewall of the trench exposed from the mask, thereby providing an effect that a pinning layer provided at the interface between the first-conductivity-type impurity diffusion layer and the element isolation layer is located at a position separated from the second-conductivity-type impurity diffusion layer in a self-aligned manner.

[0026] 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment. 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment. 3 is a block diagram showing a circuit configuration example of a pixel provided in the solid-state imaging device according to the first embodiment. 4 is a cross-sectional view showing a configuration example of a photodetector applied to a pixel according to the first embodiment. 5 is a diagram showing a configuration example of a photodetector according to the first embodiment. 6 is a cross-sectional view showing a manufacturing method of a photodetector according to the first embodiment. 7 is a cross-sectional view showing a manufacturing method of a photodetector according to the first embodiment. 8 is a cross-sectional view showing a manufacturing method of a photodetector according to the first embodiment. 9 is a cross-sectional view showing a manufacturing method of a photodetector according to the first embodiment. 10 is a cross-sectional view showing a configuration example of a photodetector according to the second embodiment. 11 is a cross-sectional view showing a configuration example of a photodetector according to the third embodiment. 12 is a cross-sectional view showing a configuration example of a photodetector according to the fourth embodiment. 13 is a diagram showing a configuration example of a photodetector according to the fifth embodiment. 14 is a plan view showing a configuration example of a photodetector according to the sixth embodiment. 15 is a plan view showing a configuration example of a photodetector according to the seventh embodiment. 16 is a cross-sectional view showing a configuration example of a photodetector according to the eighth embodiment. 17 is a cross-sectional view showing a configuration example of a photodetector according to the ninth embodiment. 18 is a cross-sectional view showing a configuration example of a photodetector according to the tenth embodiment. 16A and 16B are cross-sectional views showing a manufacturing method of a photodetector according to a tenth embodiment. FIG. 16A are cross-sectional views showing a manufacturing method of a photodetector according to a tenth embodiment. FIG. 16B are cross-sectional views showing a manufacturing method of a photodetector according to a tenth embodiment. FIG. 16C are cross-sectional views showing a manufacturing method of a photodetector according to a tenth embodiment. FIG. 16D are cross-sectional views showing a manufacturing method of a photodetector according to a tenth embodiment. FIG. 16E are cross-sectional views showing a manufacturing method of a photodetector according to a tenth embodiment. FIG. 16F are cross-sectional views showing a configuration example of a photodetector according to an eleventh embodiment. FIG. 16F are a diagram showing a configuration example of a photodetector according to a twelfth embodiment. FIG. 16G are a perspective view showing an example of a stack of a solid-state imaging device according to a thirteenth embodiment. FIG. 16H are a block diagram showing a schematic configuration example of a vehicle control system. FIG. 16I are explanatory views showing an example of an installation position of an imaging unit.

[0027] Modes for carrying out the present technology (hereinafter referred to as embodiments) will be described below. The descriptions will be made in the following order: 1. First embodiment (an example in which a pinning layer spaced apart from the base is provided at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor) 2. Second embodiment (an example in which a pinning layer is provided from the outer peripheral surface to the bottom surface of an element isolation layer at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor) 3. Third embodiment (an example in which a pinning layer is provided at the bottom surface of an element isolation layer at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor) 4. Fourth embodiment (an example in which a pinning layer spaced apart from the base is provided at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor, and an emitter is provided on a part of the base) 5. 5. Fifth embodiment (an example in which a pinning layer spaced apart from the base is provided at the interface between the collector and an isolation layer that isolates the base of a bipolar phototransistor, and an isolation layer that isolates the emitter) 6. Sixth embodiment (an example in which a pinning layer spaced apart from the base is provided at the interface between the collector and an isolation layer that isolates the base of a bipolar phototransistor, and an edge of the outer peripheral surface of the isolation layer has a finite curvature) 7. Seventh embodiment (an example in which a pinning layer spaced apart from the base is provided at the interface between the collector and an isolation layer that isolates the base of a bipolar phototransistor, and the planar shapes of the base and emitter are rectangular) 8. Eighth embodiment (an example in which a pinning layer spaced apart from the base is provided at the interface between the collector and an isolation layer that isolates the base of a bipolar phototransistor, and an undoped layer is provided between the base and the collector) 9. 9. Ninth embodiment (an example in which a pinning layer spaced apart from the base is provided at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor, and the bipolar phototransistor is configured with an NPN junction) 10. Tenth embodiment (an example in which a pinning layer spaced apart from the base is provided at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor, and a step is provided in the depth direction of the element isolation layer)11. Eleventh embodiment (an example in which a pinning layer spaced apart from a well is provided at the interface between an isolation layer that isolates a well in which a channel of a MOSFET phototransistor is formed and a substrate) 12. Twelfth embodiment (an example in which a pinning layer spaced apart from a cathode is provided at the interface between an isolation layer that isolates a cathode of a photodiode and an anode) 13. Thirteenth embodiment (an example in which semiconductor chips in which a solid-state imaging device is formed are stacked) 14. Application to a moving body

[0028] 1 is a diagram showing an example of the configuration of an imaging device according to a first embodiment. Note that the drawings used in the following description may differ in scale and shape from the actual structure in order to make each component easier to understand.

[0029] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.

[0030] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an image of the subject on the light receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, an aperture, etc. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0031] The solid-state imaging device 102 converts light from a subject into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 102 may be, for example, a complementary metal oxide semiconductor (CMOS) image sensor, a charge coupled device (CCD), or an event-based vision sensor.

[0032] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0033] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0034] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0035] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0036] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0037] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0038] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0039] The pixel array unit 111 includes a plurality of pixels PIX. The pixels PIX are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel PIX generates a pixel signal based on photoelectric conversion. The photoelectric conversion element may be a photodiode, a bipolar phototransistor, or a MOSFET phototransistor. Each pixel PIX can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel PIX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PIX row by row when reading out a signal from each pixel PIX. The vertical signal line VSL transmits the signal read out from the pixel PIX to the column signal processing unit 114 for each column. The pixels PIX may be arranged in a Bayer array or a quad-Bayer array.

[0040] The pixel array unit 111 may include a vertical signal line VSL for each column. Here, the vertical signal line VSL can transmit signals read out from the pixels PIX in the column direction.

[0041] The vertical scanning circuit 112 scans the pixels PIX to be read in the column direction. The vertical scanning circuit 112 may be configured to include a vertical register. Here, when reading out a signal from each pixel PIX, the vertical scanning circuit 112 can drive each pixel PIX row by row via a horizontal drive line HSL.

[0042] The column readout circuit 113 can form a source follower with each pixel PIX when reading out a signal from the pixel PIX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL based on the charge held in the pixel PIX. The column readout circuit 113 may support either constant current readout or capacitive load readout.

[0043] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PIX. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PIX. The column signal processing unit 114 can also perform analog-to-digital (AD) conversion processing based on the signals transmitted in the column direction from each pixel PIX, and output an image pickup signal Gout.

[0044] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the result of comparing the pixel signal read from the pixel PIX with a reference signal.

[0045] The horizontal scanning circuit 115 scans the pixels PIX to be read in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0046] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.

[0047] 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. Note that in this figure, an example is shown in which the photoelectric conversion element provided in each pixel PIX is a bipolar phototransistor.

[0048] 1, a pixel PIX includes a phototransistor 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 can be MOS (Metal Oxide Semiconductor) transistors.

[0049] The amplification transistor 124 and the selection transistor 125 are connected in series. The collector of the phototransistor 121 is connected to the floating diffusion FD via the transfer transistor 122. The emitter of the phototransistor 121 is connected to the power supply potential VSS. The power supply potential VSS can be lower than the power supply potential VDD. The power supply potential VSS may be the ground potential. The floating diffusion FD is connected to the power supply potential VDD via the reset transistor 123. The power supply potential VDD is connected to the vertical signal line VSL via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0050] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, reset signal RST, and selection signal SEL can be transmitted to each pixel PIX via the horizontal drive line HSL in FIG.

[0051] When the transfer transistor 122 is turned on, the charge amplified by the phototransistor 121 is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes depending on the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is applied to the vertical signal line VSL via the selection transistor 125 and transmitted via the vertical signal line VSL. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0052] 4 is a cross-sectional view showing an example of the configuration of a photodetector applied to a pixel according to the first embodiment. The figure shows an example of the configuration of a photodetector 130 for one pixel of a back-illuminated image sensor. The figure also shows a bipolar phototransistor as an example of the photodetector 130.

[0053] In the figure, the photodetector 130 includes a P-type semiconductor substrate 131. A light receiving surface MA is provided on the back side of the P-type semiconductor substrate 131. A pixel isolation layer 132 is provided on the P-type semiconductor substrate 131 to separate the photodetector 130 into pixels PIX. The pixel isolation layer 132 can be disposed at the boundary between the pixels PIX. The P-type semiconductor substrate 131 separated by the pixel isolation layer 132 can be disposed at the position where incident light is incident. An STI buried in the P-type semiconductor substrate 131 can be used as the pixel isolation layer 132. The P-type semiconductor substrate 131 can be used as the collector of a bipolar phototransistor.

[0054] An N-type impurity diffusion layer 134 is provided in the P-type semiconductor substrate 131 and is joined to the P-type semiconductor substrate 131. The N-type impurity diffusion layer 134 can be provided on the surface side of the P-type semiconductor substrate 131. In this case, the P-type semiconductor substrate 131 and the N-type impurity diffusion layer 134 form a PN junction, and a depletion layer can be formed at the junction surface between the P-type semiconductor substrate 131 and the N-type impurity diffusion layer 134. The N-type impurity diffusion layer 134 can be used as the base of a bipolar phototransistor. The P-type semiconductor substrate 131 is an example of a first conductivity type impurity diffusion layer as defined in the claims. The N-type impurity diffusion layer 134 is an example of a second conductivity type impurity diffusion layer as defined in the claims.

[0055] The P-type semiconductor substrate 131 also includes a P-type impurity diffusion layer 134 ＋ A P type impurity diffusion layer 135 is provided. ＋ The P-type impurity diffusion layer 135 can be stacked on the N-type impurity diffusion layer 134. ＋ The P-type impurity diffusion layer 135 can be used as the emitter of a bipolar phototransistor. ＋ The impurity diffusion layer 135 can be in ohmic contact with the emitter electrode of the bipolar phototransistor.

[0056] The P-type semiconductor substrate 131 has a side surface of the N-type impurity diffusion layer 134 and a P ＋ An element isolation layer 133 is provided to isolate the side surface of the N-type impurity diffusion layer 135 from the P-type semiconductor substrate 131. The element isolation layer 133 can be formed from the surface of the P-type semiconductor substrate 131 to a position deeper than the depth of the N-type impurity diffusion layer 134. An STI buried in the P-type semiconductor substrate 131 can be used as the element isolation layer 133. By providing the element isolation layer 133 on the side surface of the N-type impurity diffusion layer 134, the base capacitance of the bipolar phototransistor can be reduced and the response speed of the bipolar phototransistor can be improved.

[0057] Furthermore, a pinning layer 137 is provided in the P-type semiconductor substrate 131. The pinning layer 137 can be provided at the interface between the P-type semiconductor substrate 131 and the element isolation layer 133, spaced apart from the N-type impurity diffusion layer 134. For example, the pinning layer 137 may be provided continuously from the outer circumferential surface of the element isolation layer 133, through the bottom surface of the element isolation layer 133, to the lower end of the inner circumferential surface of the element isolation layer 133. ＋ An N-type impurity diffusion layer can be used. In this case, the pinning layer 137 can pin holes at the interface between the P-type semiconductor substrate 131 and the element isolation layer 133. Therefore, the pinning layer 137 can reduce dark current caused by defects at the interface between the P-type semiconductor substrate 131 and the element isolation layer 133, thereby improving the image quality of the imaging device. Here, by separating the pinning layer 137 from the N-type impurity diffusion layer 134, an increase in the base capacitance of the bipolar phototransistor can be suppressed, and a decrease in the response speed of the bipolar phototransistor can be suppressed.

[0058] The P-type semiconductor substrate 131 is ＋ A P type impurity diffusion layer 136 is provided. ＋ The impurity diffusion layer 136 can be disposed between the pixel isolation layer 132 and the element isolation layer 133. ＋ The impurity diffusion layer 136 can be in ohmic contact with the collector electrode of the bipolar phototransistor.

[0059] The photodetector 130 may be sensitive to visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like. The material of the P-type semiconductor substrate 131 can be selected from semiconductors such as Si, GaAs, InGaAs, and InGaAsP. The material of the pixel isolation layer 132 and the element isolation layer 133 can be selected from SiO ２ , SiN, Al ２ O ３ The insulating material can be selected from the following:

[0060] A light-shielding layer 141 is formed on the back surface side of the P-type semiconductor substrate 131. The light-shielding layer 141 can be provided with an opening that allows light to enter the P-type semiconductor substrate 131 through the light-receiving surface MA. In this case, the light-shielding layer 141 can be disposed on the boundary between pixels PIX to suppress crosstalk of light entering each pixel PIX. The light-shielding layer 141 can be made of a metal such as Al, Cu, or Cr.

[0061] Furthermore, a color filter 142 is formed on the back surface of the P-type semiconductor substrate 131 so as to cover the light-shielding layer 141. An on-chip lens 143 is formed on the color filter 142. The material of the color filter 142 and the on-chip lens 143 is, for example, SiO ２ The color filter 142 may be an insulating film made of silicon nitride, silicon nitride, silicon carbide, silicon nitride, or the like, or may be a transparent resin such as acrylic or polycarbonate. The color filter 142 may contain a pigment. The color filter 142 may be arranged in a Bayer array or a quad-Bayer array, for example. The color filter 142 may include an RGB filter, a complementary color filter, or a white filter.

[0062] 5 is a diagram showing a configuration example of a photodetector according to the first embodiment, where "a" in the figure is a cross-sectional view showing the configuration example of the photodetector according to the first embodiment, and "b" in the figure is a plan view showing the configuration example of the photodetector according to the first embodiment.

[0063] In the figure, the pixel isolation layer 132 is provided continuously so as to surround the periphery of the pixel PIX. The element isolation layer 133 is formed by an N-type impurity diffusion layer 134 and a P ＋The pinning layer 137 is provided continuously so as to surround the periphery of the N-type impurity diffusion layer 135. The pinning layer 137 is provided continuously so as to surround the periphery of the element isolation layer 133. In this case, the pinning layer 137 may cover the entire periphery and the entire bottom surface of the element isolation layer 133. The pinning layer 137 may also cover the lower end of the inner periphery of the pixel isolation layer 132. This makes it possible to increase the pinning area of ​​the interface between the P-type semiconductor substrate 131 and the element isolation layer 133 while separating the pinning layer 137 from the N-type impurity diffusion layer 134, thereby increasing the effect of reducing dark current caused by defects at that interface. P ＋ The impurity diffusion layer 136 is provided continuously between the pixel isolation layer 132 and the element isolation layer 133 and spaced apart from the pinning layer 137 .

[0064] 6 to 9 are cross-sectional views showing a method for manufacturing the photodetector according to the first embodiment.

[0065] 6A, a resist pattern RE1 having an opening KA1 is formed on a P-type semiconductor substrate 131 using lithography. The position of the opening KA1 can be set to correspond to the planar position of the bottom surface of the element isolation layer 133. Then, using the resist pattern RE1 as a mask, P-type impurities are ion-implanted into the P-type semiconductor substrate 131 to form an ion-implanted layer 137A in the P-type semiconductor substrate 131. By adjusting the ion-implantation energy, the ion-implanted layer 137A can be formed at a position deeper than the position of the N-type impurity diffusion layer 134. The dose of the P-type impurity in the ion-implanted layer 137A can be adjusted to correspond to the impurity concentration of the pinning layer 137. The P-type semiconductor substrate 131 is an example of a first-conductivity-type impurity diffusion region as defined in the claims. The ion-implanted layer 137A is an example of a high-concentration first-conductivity-type impurity diffusion layer as defined in the claims.

[0066] Next, as shown in FIG. 6B, the resist pattern RE1 is removed by ashing or other methods. Then, a resist pattern RE2 having an opening KA2 is formed on the P-type semiconductor substrate 131 using lithography. The position of the opening KA2 can be set so as to include the planar position of the outer peripheral surface of the element isolation layer 133. Then, using the resist pattern RE2 as a mask, P-type impurities are ion-implanted into the P-type semiconductor substrate 131, thereby forming an ion-implanted layer 137B in the P-type semiconductor substrate 131. At this time, by adjusting the ion-implantation energy, the ion-implanted layer 137B can be formed continuously from the position of the ion-implanted layer 137A to the surface of the P-type semiconductor substrate 131. The dose of the P-type impurity in the ion-implanted layer 137B can be made to correspond to the impurity concentration of the pinning layer 137.

[0067] 7a, the resist pattern RE2 is removed by ashing or other methods. After forming a hard mask material, a hard mask pattern RE3 having an opening KA3 is formed on the P-type semiconductor substrate 131 using lithography. The position of the opening KA3 can correspond to the planar position of the element isolation layer 133. The material of the hard mask material can be a material with a lower etching rate than the P-type semiconductor substrate 131. For example, the material of the hard mask material can be SiO ２ , SiN, Al ２ O ３ The hard mask pattern RE3 can be selected from among insulators such as those mentioned above. The P-type semiconductor substrate 131 is then etched using the hard mask pattern RE3 as a mask, thereby forming a trench 138 in the P-type semiconductor substrate 131. The depth of the trench 138 can correspond to the embedding depth of the element isolation layer 133. At this time, the ion implantation layers 137A, 137B are selectively etched so that the ion implantation layers 137A, 137B remain from the outer peripheral surface of the trench 138, through the bottom surface, to the lower end of the inner peripheral surface, thereby forming the pinning layer 137. Note that anisotropic etching such as RIE (Reactive Ion Etching) can be used to etch the P-type semiconductor substrate 131.

[0068] 7B, an element isolation layer 133 is formed on the P-type semiconductor substrate 131 by chemical vapor deposition (CVD) so as to be embedded in the trench 138. At this time, the pinning layer 137 is disposed so as to extend from the outer peripheral surface of the element isolation layer 133, through the bottom surface of the element isolation layer 133, and to the lower end of the inner peripheral surface of the element isolation layer 133.

[0069] Next, as shown in FIG. 8A, the element isolation layer 133 is thinned by CMP (Chemical Mechanical Polishing) or etch-back, thereby exposing the surface of the P-type semiconductor substrate 131.

[0070] 8B, a resist pattern RE4 having an opening KA4 is formed on the P-type semiconductor substrate 131 using lithography. The position of the opening KA4 can be set so that the edge of the opening KA4 is located on the element isolation layer 133. Then, using the resist pattern RE4 as a mask, N-type impurities are ion-implanted into the P-type semiconductor substrate 131, thereby forming an N-type impurity diffusion layer 134 in the P-type semiconductor substrate 131. At this time, by adjusting the energy of the ion implantation, the N-type impurity diffusion layer 134 can be formed at a position shallower than the position of the pinning layer 137 on the inner circumferential surface side of the element isolation layer 133.

[0071] 9, the resist pattern RE4 is removed by ashing or the like. Then, a resist pattern RE5 having openings KA5 and KA6 is formed on the P-type semiconductor substrate 131 using lithography. The position of the opening KA5 can be set so that the edge of the opening KA5 is located on the element isolation layer 133. The position of the opening KA6 can be set so that the edge of the opening KA5 is located on the P-type semiconductor substrate 131. ＋ The resist pattern RE5 can be made to correspond to the position in the plane direction of the P-type impurity diffusion layer 136. Then, by ion-implanting P-type impurities into the P-type semiconductor substrate 131 using the resist pattern RE5 as a mask, the P ＋ A P-type impurity diffusion layer 135 is formed on the N-type impurity diffusion layer 134. ＋ A P-type impurity diffusion layer 136 is formed in a P-type semiconductor substrate 131 .

[0072] As described above, in the first embodiment, the pinning layer 137, spaced apart from the base, is provided at the interface between the collector and the element isolation layer 133 that isolates the base of the bipolar phototransistor. This reduces the base capacitance of the bipolar phototransistor while pinning the interface between the collector of the bipolar phototransistor and the element isolation layer 133. This makes it possible to improve the response speed of the bipolar phototransistor while reducing the dark current of the bipolar phototransistor.

[0073] 2. Second Embodiment In the first embodiment described above, pinning layer 137 spaced apart from the base is provided at the interface between element isolation layer 133, which isolates the base of a bipolar phototransistor, and the collector. In this second embodiment, a pinning layer is provided from the outer peripheral surface to the bottom surface of element isolation layer 133 at the interface between element isolation layer 133, which isolates the base of a bipolar phototransistor, and the collector.

[0074] FIG. 10 is a cross-sectional view showing an example of the configuration of a photodetector according to the second embodiment.

[0075] In the figure, the photodetector 200 includes a pinning layer 237 instead of the pinning layer 137 of the first embodiment described above. Other configurations of the photodetector 200 of the second embodiment are similar to the configurations of the photodetector 130 of the first embodiment described above.

[0076] The pinning layer 237 can be provided continuously from the outer peripheral surface of the element isolation layer 133 to the bottom surface of the element isolation layer 133. In this case, the pinning layer 237 can be prevented from being formed on the inner peripheral surface of the element isolation layer 133.

[0077] As described above, in the second embodiment, the pinning layer 237 is provided at the interface between the collector and the element isolation layer 133, which isolates the base of the bipolar phototransistor, from the outer circumferential surface to the bottom surface of the element isolation layer 133. This makes it possible to improve the response speed of the bipolar phototransistor while reducing the dark current of the bipolar phototransistor. In this case, it is no longer necessary to form the pinning layer 237 on part of the inner circumferential surface of the element isolation layer 133, and the manufacturing process can be simplified.

[0078] 3. Third Embodiment In the first embodiment described above, pinning layer 137 spaced apart from the base is provided at the interface between the collector and element isolation layer 133 that isolates the base of the bipolar phototransistor. In this third embodiment, a pinning layer is provided on the bottom surface of element isolation layer 133, which is part of the interface between the collector and element isolation layer 133 that isolates the base of the bipolar phototransistor.

[0079] FIG. 11 is a cross-sectional view showing an example of the configuration of a photodetector according to the third embodiment.

[0080] In the figure, the photodetector 300 includes a pinning layer 337 instead of the pinning layer 137 of the first embodiment described above. Other configurations of the photodetector 300 of the third embodiment are similar to the configurations of the photodetector 130 of the first embodiment described above.

[0081] The pinning layer 337 can be provided continuously on the bottom surface of the element isolation layer 133. In this case, the pinning layer 237 can be formed so as not to be formed on the outer peripheral surface and inner peripheral surface of the element isolation layer 133.

[0082] As described above, in the third embodiment, the pinning layer 337 is provided at the interface between the collector and the bottom surface of the element isolation layer 133 that isolates the base of the bipolar phototransistor. This makes it possible to reduce the dark current of the bipolar phototransistor while improving the response speed of the bipolar phototransistor. In this case, it is no longer necessary to form the pinning layer 337 on parts of the outer and inner surfaces of the element isolation layer 133, which simplifies the manufacturing process.

[0083] 4. Fourth Embodiment In the first embodiment described above, the emitter is laminated on the base of the bipolar phototransistor. In this fourth embodiment, the emitter is laminated on a part of the surface of the base of the bipolar phototransistor.

[0084] 12 is a diagram showing a configuration example of a photodetector according to a fourth embodiment, where "a" in the figure is a cross-sectional view showing the configuration example of the photodetector according to the fourth embodiment, and "b" in the figure is a plan view showing the configuration example of the photodetector according to the fourth embodiment.

[0085] In the figure, the photodetector 400 has the same structure as the N-type impurity diffusion layer 134 and the P-type impurity diffusion layer 135 of the first embodiment. ＋ Instead of the N-type impurity diffusion layer 135, an N-type impurity diffusion layer 434 and a P-type impurity diffusion layer ＋ The photodetector 400 of the fourth embodiment is otherwise similar in configuration to the photodetector 130 of the first embodiment.

[0086] The N-type impurity diffusion layer 434 is joined to the P-type semiconductor substrate 131. In this case, the N-type impurity diffusion layer 434 can be disposed at a position where its periphery is surrounded by the element isolation layer 133. The N-type impurity diffusion layer 434 is spaced apart from the pinning layer 137. The N-type impurity diffusion layer 434 can be used as the base of a bipolar phototransistor.

[0087] P ＋ The N-type impurity diffusion layer 435 is laminated on a part of the surface of the N-type impurity diffusion layer 434. The part of the surface of the N-type impurity diffusion layer 434 is P ＋ The P-type impurity diffusion layer 435 can be exposed. ＋ The P-type impurity diffusion layer 435 can be in ohmic contact with the emitter electrode of the bipolar phototransistor. ＋ The impurity diffusion layer 435 can be used as the emitter of a bipolar phototransistor.

[0088] As described above, in the fourth embodiment, the pinning layer 137 is provided at the interface between the collector and the element isolation layer 133 that isolates the base of the bipolar phototransistor, and the emitter is laminated on part of the surface of the base of the bipolar phototransistor. This makes it possible to reduce the junction area between the base and emitter as well as the junction area between the base and collector of the bipolar phototransistor, and also pins the interface between the collector of the bipolar phototransistor and the element isolation layer 133. This makes it possible to improve the response speed of the bipolar phototransistor and reduce the dark current of the bipolar phototransistor.

[0089] The emitter of the bipolar phototransistor is preferably disposed in a position where the side surface of the emitter contacts the element isolation layer 133. For example, the emitter of the bipolar phototransistor is preferably disposed in one of the four corners of the base of the bipolar phototransistor. In this case, two of the four side surfaces of the emitter of the bipolar phototransistor can be brought into contact with the element isolation layer 133 while suppressing the complexity of the manufacturing process. This makes it possible to reduce the contact area between the side surface of the emitter and the base of the bipolar phototransistor, and to reduce the base capacitance of the bipolar phototransistor.

[0090] 5. Fifth Embodiment In the first embodiment described above, the emitter is laminated on the base of the bipolar phototransistor. In this fifth embodiment, a pinning layer 137 spaced apart from the base is provided at the interface between the collector and an isolation layer 133 that isolates the base of the bipolar phototransistor, and an isolation layer that isolates the emitter is provided at the base.

[0091] 13 is a diagram showing a configuration example of a photodetector according to a fifth embodiment, where "a" in the figure is a cross-sectional view showing the configuration example of the photodetector according to the fifth embodiment, and "b" in the figure is a plan view showing the configuration example of the photodetector according to the fifth embodiment.

[0092] In the figure, the photodetector 500 has the same structure as the N-type impurity diffusion layer 134 and the P-type impurity diffusion layer 135 of the first embodiment. ＋ Instead of the N-type impurity diffusion layer 135, an N-type impurity diffusion layer 534 and a P-type impurity diffusion layer ＋ The photodetector 500 includes a doped impurity diffusion layer 535. The photodetector 500 further includes an element isolation layer 533 in addition to the components of the photodetector 130 of the first embodiment. The remaining configuration of the photodetector 500 of the fifth embodiment is similar to the configuration of the photodetector 130 of the first embodiment.

[0093] The N-type impurity diffusion layer 534 is joined to the P-type semiconductor substrate 131. In this case, the N-type impurity diffusion layer 534 can be disposed at a position where its periphery is surrounded by the element isolation layer 133. The N-type impurity diffusion layer 534 is spaced apart from the pinning layer 137. The N-type impurity diffusion layer 534 can be used as the base of a bipolar phototransistor.

[0094] P ＋ The P-type impurity diffusion layer 535 is laminated on a part of the surface of the N-type impurity diffusion layer 534. ＋ The P-type impurity diffusion layer 535 can be used as the emitter of a bipolar phototransistor. ＋ The impurity diffusion layer 535 can be in ohmic contact with the emitter electrode of the bipolar phototransistor.

[0095] The element isolation layer 533 is P ＋ The element isolation layer 533 separates the side surface of the P-type impurity diffusion layer 535 from the N-type impurity diffusion layer 534. ＋ The element isolation layer 533 can be formed to a position deeper than the depth of the P-type impurity diffusion layer 535. ＋ The P-type impurity diffusion layer 535 is continuously formed so as to surround the P-type impurity diffusion layer 535. ＋ This can reduce the capacitance of the entire outer peripheral surface of the N-type impurity diffusion layer 535. The element isolation layer 533 can be formed by an STI buried in the N-type impurity diffusion layer 534. Note that part of the element isolation layer 533 may be in contact with the element isolation layer 133.

[0096] As described above, in the fifth embodiment, pinning layer 137 is provided at the interface between the collector and element isolation layer 133 that isolates the base of the bipolar phototransistor, while element isolation layer 533 that isolates the emitter is provided at the base. This makes it possible to reduce the junction area between the base and emitter as well as the junction area between the base and collector of the bipolar phototransistor, and also makes it possible to pin the interface between the collector of the bipolar phototransistor and element isolation layer 133. This makes it possible to improve the response speed of the bipolar phototransistor and reduce the dark current of the bipolar phototransistor.

[0097] 6. Sixth Embodiment In the first embodiment described above, the planar shape of the outer peripheral surface of the element isolation layer 133 is square. In this sixth embodiment, a pinning layer spaced apart from the base is provided at the interface between the collector and the element isolation layer that isolates the base of a bipolar phototransistor, and the corners of the outer peripheral surface of the element isolation layer are given a finite curvature.

[0098] FIG. 14 is a plan view showing an example of the configuration of a photodetector according to the sixth embodiment.

[0099] In the figure, the photodetector 600 has the same structure as the element isolation layer 133, the N-type impurity diffusion layer 134, and the P-type impurity diffusion layer 135 of the first embodiment. ＋ Instead of the N-type impurity diffusion layer 135 and the pinning layer 137, an element isolation layer 633, an N-type impurity diffusion layer 634, and a P-type impurity diffusion layer 635 are provided. ＋ The photodetector 600 of the sixth embodiment includes a dopant diffusion layer 635 and a pinning layer 637. Other configurations of the photodetector 600 of the sixth embodiment are similar to those of the photodetector 130 of the first embodiment described above.

[0100] The corners of the side surfaces of the N-type impurity diffusion layer 634 and the P ＋ The corners of the side surfaces of the N-type impurity diffusion layer 635 are similar to the corners of the side surfaces of the N-type impurity diffusion layer 134 of the first embodiment and the P-type impurity diffusion layer 635 of the first embodiment. ＋ A finite curvature is given to the corner of the side surface of the N-type impurity diffusion layer 135. At this time, the corner of the side surface of the N-type impurity diffusion layer 634 and the corner of the P-type impurity diffusion layer 635 are ＋The corners of the side surfaces of the N-type impurity diffusion layer 635 may be configured to include a part of a cylindrical surface. The N-type impurity diffusion layer 634 can be used as the base of a bipolar phototransistor. ＋ The impurity diffusion layer 635 can be used as the emitter of a bipolar phototransistor.

[0101] The corners of the side surfaces of the element isolation layer 633 are given a finite curvature like the corners of the side surfaces of the element isolation layer 133 of the first embodiment. In this case, the corners of the side surfaces of the element isolation layer 633 may be configured to include a part of a cylindrical surface. The element isolation layer 633 is formed around the periphery of the N-type impurity diffusion layer 634 and the P-type impurity diffusion layer 635. ＋ The insulating layer 634 is provided along the periphery of the impurity diffusion layer 635 .

[0102] The corners of the side surfaces of the pinning layer 637 are given a finite curvature similar to the corners of the side surfaces of the pinning layer 137 of the first embodiment described above. In this case, the corners of the side surfaces of the pinning layer 637 may be configured to include part of a cylindrical surface. The pinning layer 637 is provided along the periphery of the element isolation layer 633.

[0103] As described above, in the sixth embodiment, the pinning layer 637, which is spaced apart from the base, is provided at the interface between the collector and the element isolation layer 633 that isolates the base of the bipolar phototransistor, and a finite curvature is imparted to the corners of the outer periphery of the element isolation layer 633. This allows the outer periphery of the element isolation layer 633 to be configured with a curved surface, making it possible to suppress electric field concentration.

[0104] 7. Seventh Embodiment In the first embodiment described above, the planar shapes of the base and emitter of the bipolar phototransistor are square, element isolation layer 133 is provided around them, and pinning layer 137, spaced apart from the base, is provided at the interface between element isolation layer 133 and the collector. In this seventh embodiment, the planar shapes of the base and emitter of the bipolar phototransistor are rectangular, element isolation layer is provided around them, and pinning layer 137, spaced apart from the base, is provided at the interface between the element isolation layer and the collector.

[0105] FIG. 15 is a plan view showing an example of the configuration of a photodetector according to the seventh embodiment.

[0106] In the figure, the photodetector 700 has the same structure as the first embodiment, including the element isolation layer 133, the N-type impurity diffusion layer 134, and the P ＋ Instead of the N-type impurity diffusion layer 135 and the pinning layer 137, an element isolation layer 733, an N-type impurity diffusion layer 734, and a P-type impurity diffusion layer 735 are provided. ＋ The photodetector 700 of the seventh embodiment includes a dopant diffusion layer 735 and a pinning layer 737. Other configurations of the photodetector 700 of the seventh embodiment are similar to those of the photodetector 130 of the first embodiment described above.

[0107] The planar shape of the N-type impurity diffusion layer 734 and the P ＋ The N-type impurity diffusion layer 735 has a rectangular planar shape. The N-type impurity diffusion layer 734 can be used as the base of a bipolar phototransistor. ＋ The impurity diffusion layer 735 can be used as the emitter of a bipolar phototransistor.

[0108] The plane shape of the side surface of the element isolation layer 733 is rectangular. The element isolation layer 733 is formed around the N-type impurity diffusion layer 734 and the P-type impurity diffusion layer 735. ＋ The insulating layer 734 is provided along the periphery of the impurity diffusion layer 735 .

[0109] The pinning layer 737 has a rectangular planar shape on the side surface thereof. The pinning layer 737 is provided along the periphery of the element isolation layer 733.

[0110] As described above, in the seventh embodiment, the planar shapes of the base and emitter of the bipolar phototransistor are rectangular, the element isolation layer 733 is provided around them, and the pinning layer 737, spaced apart from the base, is provided at the interface between the element isolation layer 733 and the collector. This improves the degree of freedom in the layout of the base and emitter of the bipolar phototransistor, and also improves the flexibility in the arrangement of pixel transistors and the like.

[0111] 8. Eighth Embodiment In the first embodiment described above, a pinning layer spaced apart from the base is provided at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor, and the base and collector are joined together. In this eighth embodiment, a pinning layer spaced apart from the base is provided at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor, and a non-doped layer is provided between the base and collector.

[0112] FIG. 16 is a cross-sectional view showing an example of the configuration of a photodetector according to the eighth embodiment.

[0113] In the figure, a photodetector 800 is obtained by adding a non-doped layer 801 to the photodetector 130 of the first embodiment described above. The other configurations of the photodetector 800 of the eighth embodiment are similar to the configurations of the photodetector 130 of the first embodiment described above.

[0114] The non-doped layer 801 can be provided between the P-type semiconductor substrate 131 and the N-type impurity diffusion layer 134. In this case, the non-doped layer 801 may be in contact with the element isolation layer 133 and the pinning layer 137. The planar size of the non-doped layer 801 may be larger than the planar size of the N-type impurity diffusion layer 134. An intrinsic semiconductor may be used for the non-doped layer 801. The non-doped layer 801 may be formed by implanting N-type impurities so as to cancel the P-type impurities in the P-type semiconductor substrate 131.

[0115] As described above, in the eighth embodiment, the pinning layer 137 spaced apart from the base is provided at the interface between the collector and the element isolation layer 133 that isolates the base of the bipolar phototransistor, and the non-doped layer 801 is provided between the base and the collector. This makes it possible to reduce not only the capacitance on the side surface of the base of the bipolar phototransistor but also the capacitance on the bottom surface of the base, and also pins the interface between the collector of the bipolar phototransistor and the element isolation layer 133. This makes it possible to improve the response speed of the bipolar phototransistor and reduce the dark current of the bipolar phototransistor.

[0116] 9. Ninth Embodiment In the first embodiment described above, a pinning layer spaced apart from the base is provided at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor, and the bipolar phototransistor is configured with a PNP junction. In this ninth embodiment, a pinning layer spaced apart from the base is provided at the interface between the collector and an element isolation layer that isolates the base of a bipolar phototransistor, and the bipolar phototransistor is configured with an NPN junction.

[0117] FIG. 17 is a cross-sectional view showing an example of the configuration of a photodetector according to the ninth embodiment.

[0118] In the figure, the photodetector 900 has a P-type semiconductor substrate 131, an N-type impurity diffusion layer 134, and a P ＋ Instead of the N-type impurity diffusion layers 135 and 136 and the pinning layer 137, an N-type semiconductor substrate 931, a P-type impurity diffusion layer 934 ... ＋ The photodetector 900 of the ninth embodiment includes type impurity diffusion layers 935 and 936 and a pinning layer 937. Other configurations of the photodetector 900 of the ninth embodiment are similar to those of the photodetector 130 of the first embodiment described above.

[0119] The photodetector 900 includes an N-type semiconductor substrate 931, a P-type impurity diffusion layer 934, and an N ＋ The conductivity types of the N-type impurity diffusion layers 935 and 936 and the pinning layer 937 are set to be opposite to the respective conductivity types of the photodetector 130. ＋ The other configurations of the type impurity diffusion layers 935 and 936 and the pinning layer 937 are similar to those of the photodetector 130 .

[0120] As described above, in the ninth embodiment, the pinning layer 937 spaced apart from the base is provided at the interface between the collector and the element isolation layer 133 that isolates the base of the bipolar phototransistor, and the bipolar phototransistor is configured as an NPN junction, thereby improving the response speed of the bipolar phototransistor and reducing the dark current of the bipolar phototransistor.

[0121] 10. Tenth Embodiment In the first embodiment described above, pinning layer 137 spaced apart from the base is provided at the interface between the collector and element isolation layer 133 that isolates the base of the bipolar phototransistor. In this tenth embodiment, a pinning layer spaced apart from the base is provided at the interface between the collector and element isolation layer that isolates the base of the bipolar phototransistor, and a step is provided in the depth direction of the element isolation layer.

[0122] FIG. 18 is a cross-sectional view showing an example of the configuration of a photodetector according to the tenth embodiment.

[0123] In the figure, the photodetector 1000 includes an element isolation layer 1033 instead of the element isolation layer 133 and pinning layer 137 of the first embodiment described above. The other configurations of the photodetector 1000 of the tenth embodiment are similar to the configurations of the photodetector 130 of the first embodiment described above.

[0124] The element isolation layer 1033 is formed on the side surface of the N-type impurity diffusion layer 134 and the P ＋ The element isolation layer 1033 isolates the side surface of the N-type impurity diffusion layer 135 from the P-type semiconductor substrate 131. The element isolation layer 1033 can be formed from the surface of the P-type semiconductor substrate 131 to a position deeper than the depth of the N-type impurity diffusion layer 134. As the element isolation layer 1033, an STI buried in the P-type semiconductor substrate 131 can be used.

[0125] At this time, steps DA1 and DA2 are provided in the element isolation layer 1033 in the depth direction. The step DA1 can be formed at the same depth position along the outer circumferential surface of the element isolation layer 1033. The step DA2 can be formed at the same depth position along the inner circumferential surface of the element isolation layer 1033. The depth positions of the steps DA1 and DA2 can be set to be equal to each other. The depth positions of the steps DA1 and DA2 can be set to be deeper than the depth position of the N-type impurity diffusion layer 134.

[0126] The pinning layer 1037 can be provided at the interface between the P-type semiconductor substrate 131 and the element isolation layer 1033, spaced apart from the N-type impurity diffusion layer 134. For example, the pinning layer 1037 may be provided continuously from the outer circumferential surface of the element isolation layer 1033 through the bottom surface of the element isolation layer 1033 to the position of the step DA2 on the inner circumferential surface of the element isolation layer 1033. The thickness of the pinning layer 1037 may be thinner than the depth of each of the steps DA1 and DA2. ＋ A type impurity diffusion layer can be used.

[0127] 19 to 24 are cross-sectional views showing a method for manufacturing a photodetector according to the tenth embodiment.

[0128] 19A, after a hard mask material is deposited, a hard mask pattern RE11 having an opening KA11 is formed on the P-type semiconductor substrate 131 using lithography. The position of the opening KA11 can correspond to the embedding position of the element isolation layer 1033. Then, the P-type semiconductor substrate 131 is etched using the hard mask pattern RE11 as a mask, thereby forming a trench TRH in the P-type semiconductor substrate 131. The depth of the trench TRH can correspond to the positions of the steps DA1 and DA2 of the element isolation layer 1033. Note that anisotropic etching such as RIE can be used to etch the P-type semiconductor substrate 131.

[0129] 19B, a protective film 1001 is formed on the P-type semiconductor substrate 131 by CVD so as to cover the side surfaces of the trenches TRH. The thickness of the protective film 1001 can correspond to the depths of the steps DA1 and DA2 of the element isolation layer 1033. The protective film 1001 can be made of, for example, SiN.

[0130] 20 a, the protective film 1001 on the bottom surface of the trench TRH is removed using the hard mask pattern RE11 and the protective film 1001 on the side surface of the trench TRH as a mask. Furthermore, the P-type semiconductor substrate 131 is etched using the hard mask pattern RE11 and the protective film 1001 on the side surface of the trench TRH as a mask, thereby increasing the depth of the trench TRH. The increase in the depth of the trench TRH can be made to correspond to the length of the pinning layer 1037 on the inner periphery side of the element isolation layer 1033 in the depth direction. At this time, steps DA1' and DA2' corresponding to the steps DA1 and DA2 of the element isolation layer 1033 are formed on the side surface of the trench TRH.

[0131] 20B, a buried layer 1002 is formed on the hard mask pattern RE11 by CVD so as to be embedded in the trench TRH. The buried layer 1002 may be made of a material having a lower etching rate than the protective film 1001. For example, the buried layer 1002 may be made of polycrystalline silicon.

[0132] Next, as shown in FIG. 21a, the buried layer 1002 is thinned by CMP or etch-back to expose the surface of the hard mask pattern RE11.

[0133] 21b, a resist pattern RE12 having an opening KA12 is formed on the hard mask pattern RE11 using lithography. The position of the opening KA12 can be set at a position where the end of the protective film 1001 on the outer periphery of the trench TRH is exposed. At this time, the end of the resist pattern RE12 may be located on the buried layer 1002. Then, the protective film 1001 on the outer periphery of the trench TRH is selectively etched using the resist pattern RE12 as a mask, thereby removing the protective film 1001 on the outer periphery of the trench TRH.

[0134] 22A, the buried layer 1002 buried in the trench TRH is removed. The buried layer 1002 can be removed by isotropic etching such as wet etching.

[0135] 22b, a P-type impurity is introduced into the P-type semiconductor substrate 131 using the hard mask pattern RE11 and the protective film 1001 as a mask, thereby forming a pinning layer 1037 in the trench TRH. At this time, the pinning layer 1037 can be formed from the outer peripheral surface of the trench TRH, through the bottom surface, to the position of the step DA2' on the inner peripheral surface. The thickness of the pinning layer 1037 may be thinner than the depth of each of the steps DA1 and DA2, or may be equal to the depth of each of the steps DA1 and DA2. The introduction of the P-type impurity into the P-type semiconductor substrate 131 may be performed by plasma doping or solid-phase diffusion.

[0136] 23A, the hard mask pattern RE11 and the protective film 1001 are removed from the P-type semiconductor substrate 131. The hard mask pattern RE11 and the protective film 1001 may be removed by isotropic etching such as wet etching.

[0137] 23 b, an element isolation layer 1033 is formed on the P-type semiconductor substrate 131 by CVD so as to be embedded in the trench TRH. Here, steps DA1 and DA2 corresponding to the steps DA1′ and DA2′ of the trench TRH are formed on the side surfaces of the element isolation layer 1033. At this time, the pinning layer 1037 is disposed from the outer peripheral surface of the element isolation layer 1033 to the position of the step DA2 on the inner peripheral surface of the element isolation layer 1033, via the bottom surface of the element isolation layer 1033.

[0138] Next, as shown in FIG. 24a, the element isolation layer 1033 is thinned by CMP or etch-back to expose the surface of the P-type semiconductor substrate 131.

[0139] 24b, a resist pattern RE13 having an opening KA13 is formed on the P-type semiconductor substrate 131 based on lithography. The position of the opening KA13 can be set so that the edge of the opening KA13 is located on the element isolation layer 1033. Then, by ion-implanting N-type impurities into the P-type semiconductor substrate 131 using the resist pattern RE13 as a mask, an N-type impurity diffusion layer 134 is formed in the P-type semiconductor substrate 131. Furthermore, by ion-implanting P-type impurities into the P-type semiconductor substrate 131 using the resist pattern RE13 as a mask, a P-type impurity diffusion layer 134 is formed in the P-type semiconductor substrate 131. ＋ An N-type impurity diffusion layer 135 is formed on the N-type impurity diffusion layer 134 .

[0140] As described above, in the tenth embodiment, pinning layer 1037 spaced apart from the base is provided at the interface between the collector and element isolation layer 1033, which isolates the base of the bipolar phototransistor, and steps DA1 and DA2 are provided in the depth direction of element isolation layer 1033. This allows the position of pinning layer 1037 to be defined at the position of step DA2 on the inner circumferential surface side of element isolation layer 1033, and pinning layer 1037 to be spaced apart from the base of the bipolar phototransistor in a self-aligned manner. Therefore, it is possible to reduce the base capacitance of the bipolar phototransistor while suppressing variations in the base capacitance of the bipolar phototransistor, and to improve the response speed of the bipolar phototransistor.

[0141] 11. Eleventh Embodiment In the first embodiment described above, pinning layer 137 spaced apart from the base is provided at the interface between the collector and element isolation layer 133 that isolates the base of a bipolar phototransistor. In this eleventh embodiment, a pinning layer spaced apart from the well is provided at the interface between the substrate and an element isolation layer that isolates a well in which a channel of a MOSFET phototransistor is formed.

[0142] 25 is a cross-sectional view showing an example of the configuration of a photodetector according to the eleventh embodiment, in which a CMD (Charge Modulation Device) type phototransistor is shown as an example of a MOSFET type phototransistor.

[0143] In the figure, the photodetector 1100 includes a P-type semiconductor substrate 131. A light receiving surface MA is provided on the back side of the P-type semiconductor substrate 131. A pixel isolation layer 132 that separates the photodetector 1100 into pixels PIX is provided on the P-type semiconductor substrate 131. The P-type semiconductor substrate 131 separated by the pixel isolation layer 132 can be provided at an incident position of incident light.

[0144] An N-type impurity diffusion layer 1101 joined to the P-type semiconductor substrate 131 is provided in the P-type semiconductor substrate 131. The N-type impurity diffusion layer 1101 can be provided on the surface side of the P-type semiconductor substrate 131. In this case, the P-type semiconductor substrate 131 and the N-type impurity diffusion layer 1101 form a PN junction, and a depletion layer can be formed at the junction surface between the P-type semiconductor substrate 131 and the N-type impurity diffusion layer 1101. The N-type impurity diffusion layer 1101 can be used as an N-well in which a channel of a CMD-type phototransistor is formed.

[0145] The N-type impurity diffusion layer 1101 has P ＋ P type impurity diffusion layers 1102 and 1103 are provided. ＋ The impurity diffusion layers 1102 and 1103 can be arranged to sandwich the channel of the CMD phototransistor. ＋ The impurity diffusion layer 1102 can be used as the source of a CMD-type phototransistor. ＋ The impurity diffusion layer 1103 can be used as the drain of a CMD type phototransistor.

[0146] A gate electrode 1105 is formed on the N-type impurity diffusion layer 1101 via a gate insulating film 1104. The gate electrode 1105 can be disposed on a channel formed in the CMD type phototransistor. Sidewalls 1106 are formed on the side walls of the gate electrode 1105. The gate insulating film 1104 is made of, for example, SiO２ The sidewalls 1106 may be made of, for example, SiN, and the gate electrode 1105 may be made of, for example, polycrystalline silicon.

[0147] An element isolation layer 133 is provided on the P-type semiconductor substrate 131. The element isolation layer 133 is formed between the side surface of the N-type impurity diffusion layer 1101 and the P ＋ The element isolation layer 133 isolates the side surfaces of the N-type impurity diffusion layers 1102 and 1103 from the P-type semiconductor substrate 131. The element isolation layer 133 is continuously provided so as to surround the periphery of the N-type impurity diffusion layer 1101. The element isolation layer 133 can be formed from the surface of the P-type semiconductor substrate 131 to a position deeper than the depth of the N-type impurity diffusion layer 1101. By providing the element isolation layer 133 on the side surface of the N-type impurity diffusion layer 1101, the well capacitance of the CMD phototransistor can be reduced and the response speed of the CMD phototransistor can be improved.

[0148] Furthermore, a pinning layer 137 is provided in the P-type semiconductor substrate 131. The pinning layer 137 can be provided at the interface between the P-type semiconductor substrate 131 and the element isolation layer 133, spaced apart from the N-type impurity diffusion layer 1101. The pinning layer 137 pins holes at the interface between the P-type semiconductor substrate 131 and the element isolation layer 133, and can reduce dark current caused by defects at the interface between the P-type semiconductor substrate 131 and the element isolation layer 133. Here, by spaced apart the pinning layer 137 from the N-type impurity diffusion layer 1101, an increase in the well capacitance of the CMD phototransistor can be suppressed, and a decrease in the response speed of the CMD phototransistor can be suppressed.

[0149] The P-type semiconductor substrate 131 is ＋ A P type impurity diffusion layer 1107 is provided. ＋ The impurity diffusion layer 1107 can be disposed between the pixel isolation layer 132 and the element isolation layer 133. ＋ The impurity diffusion layer 1107 can be in ohmic contact with the well electrode of the CMD type phototransistor.

[0150] In a CMD type phototransistor, by controlling the gate potential, it is possible to switch between resetting the pixel, reading out a signal, and accumulating charges.

[0151] In this way, in the eleventh embodiment, a pinning layer spaced apart from the well is provided at the interface between the substrate and an isolation layer that isolates the well in which the channel of the MOSFET phototransistor is formed, thereby improving the response speed of the bipolar phototransistor and reducing the dark current of the bipolar phototransistor.

[0152] 12. Twelfth Embodiment In the first embodiment described above, pinning layer 137 spaced apart from the base is provided at the interface between the collector and element isolation layer 133 that isolates the base of a bipolar phototransistor. In this twelfth embodiment, pinning layer 137 spaced apart from the cathode is provided at the interface between the anode and element isolation layer 133 that isolates the cathode of a photodiode.

[0153] 26 is a diagram showing a configuration example of a photodetector according to a twelfth embodiment, in which "a" in the figure is a cross-sectional view showing the configuration example of the photodetector according to the twelfth embodiment, and "b" in the figure is a plan view showing the configuration example of the photodetector according to the twelfth embodiment.

[0154] In the figure, the photodetector 1200 includes an N-type impurity diffusion layer 1234 instead of the N-type impurity diffusion layer 134 of the first embodiment. ＋ The dopant diffusion layers 135 and 136 are removed. At this time, the photodetector 1200 can be configured as a photodiode. The other configurations of the photodetector 1200 of the twelfth embodiment are the same as those of the photodetector 130 of the first embodiment described above.

[0155] The N-type impurity diffusion layer 1234 is bonded to the P-type semiconductor substrate 131. At this time, the P-type semiconductor substrate 131 and the N-type impurity diffusion layer 1234 form a PN junction, and a depletion layer can be formed at the junction surface between the P-type semiconductor substrate 131 and the N-type impurity diffusion layer 1234. The N-type impurity diffusion layer 1234 can be disposed at a position surrounded by the element isolation layer 133. The N-type impurity diffusion layer 1234 is separated from the pinning layer 137. Here, the P-type semiconductor substrate 131 can be used as the anode of a photodiode. The N-type impurity diffusion layer 1234 can be used as the cathode of the photodiode.

[0156] As described above, in the twelfth embodiment, the pinning layer 137, which is spaced apart from the cathode, is provided at the interface between the anode and the element isolation layer 133 that isolates the cathode of the photodiode. This makes it possible to pin the interface between the anode of the photodiode and the element isolation layer 133 while reducing the cathode capacitance of the photodiode. This makes it possible to improve the response speed of the photodiode while reducing the dark current of the photodiode.

[0157] 13. Thirteenth Embodiment In the first embodiment described above, pinning layer 137 spaced apart from the base is provided at the interface between the collector and element isolation layer 133 that isolates the base of the bipolar phototransistor. In this thirteenth embodiment, semiconductor chips are stacked to form a solid-state imaging device having a pixel array portion in which pixels are arranged in a matrix.

[0158] FIG. 27 is a perspective view showing an example of a stack of layers in a solid-state imaging device according to the thirteenth embodiment.

[0159] In the figure, the solid-state imaging device includes semiconductor chips 1321 and 1322. The semiconductor chip 1322 is stacked on the semiconductor chip 1321.

[0160] A pixel array section 1323 is formed in the semiconductor chip 1322. In the pixel array section 1323, pixels 1331 are arranged in a matrix in the row and column directions. Each pixel 1331 can be provided with a photodetector according to any one of the first to twelfth embodiments described above. Pad electrodes 1332 and via electrodes 1333 are formed around the pixel array section 1323. The via electrodes 1333 penetrate the semiconductor chip 1322 and can electrically connect the semiconductor chips 1321 and 1322 to each other.

[0161] A peripheral circuit 1324 is formed on the semiconductor chip 1321. A column readout circuit 1325, a column ADC 1326, a communication interface 1327, and an oscillation circuit 1328 are formed in the peripheral circuit 1324. The column readout circuit 1325 and the column ADC 1326 may be formed so as to correspond to positions on both sides of the pixel array unit 1323 in the column direction.

[0162] As described above, in the thirteenth embodiment, the semiconductor chip 1322 on which the pixel array section 1323 is formed is stacked on the semiconductor chip 1321 on which the peripheral circuit 1324 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0163] 14. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0164] FIG. 28 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0165] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 28, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0166] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0167] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0168] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0169] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0170] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0171] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0172] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0173] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0174] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 28, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0175] FIG. 29 is a diagram showing an example of the installation position of the imaging unit 12031.

[0176] In FIG. 29, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0177] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0178] 29 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0179] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0180] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0181] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0182] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0183] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and other components of the above-described configuration. Specifically, for example, the photodetection devices according to the first to twelfth embodiments described above can be applied to the imaging unit 12031 and other components. By applying the technology according to the present disclosure to the vehicle control system 12000, the response speed of the imaging unit 12031 can be improved while the image quality of the imaging unit 12031 can be improved.

[0184] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0185] The present technology may also be configured as follows: (1) A photodetector comprising: a first conductivity type impurity diffusion layer provided at a position where light is incident; a second conductivity type impurity diffusion layer joined to the first conductivity type impurity diffusion layer; an element isolation layer embedded in the first conductivity type impurity diffusion layer so as to isolate the second conductivity type impurity diffusion layer; and a pinning layer spaced from the second conductivity type impurity diffusion layer and provided at an interface between the first conductivity type impurity diffusion layer and the element isolation layer. (2) The photodetector according to (1), in which the element isolation layer is continuously provided so as to surround the periphery of the second conductivity type impurity diffusion layer. (3) The photodetector according to (1) or (2), in which the pinning layer is continuously provided so as to surround the outer periphery of the element isolation layer. (4) The photodetector according to any of (1) to (3), in which the pinning layer is provided on a bottom surface of the element isolation layer. (5) The photodetector according to any one of (1) to (4), wherein an inner peripheral surface of the element isolation layer has a step provided at a position deeper in the depth direction than a position of the second conductivity type impurity diffusion layer. (6) The photodetector according to any one of (1) to (6), wherein the first conductivity type impurity diffusion layer is used as a collector of a bipolar phototransistor, and the second conductivity type impurity diffusion layer is used as a base of the bipolar phototransistor, and an emitter of the bipolar phototransistor is joined to the base. (7) The photodetector according to (6), wherein the emitter of the bipolar phototransistor is provided at a position in contact with the element isolation layer. (8) The photodetector according to any one of (1) to (6), wherein the second conductivity type impurity diffusion layer is used as a second conductivity type well in which a channel is formed in a MOSFET phototransistor, and a first conductivity type source layer and a first conductivity type drain layer are provided in the second conductivity type well, separated by the channel.(9) An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in the row and column directions, the pixels comprising a photoelectric conversion section that converts light into an electric signal, the photoelectric conversion section comprising: a first conductivity type impurity diffusion layer provided at a position where the light is incident; a second conductivity type impurity diffusion layer joined to the first conductivity type impurity diffusion layer; an element isolation layer embedded in the first conductivity type impurity diffusion layer so as to isolate the second conductivity type impurity diffusion layer; and a pinning layer spaced from the second conductivity type impurity diffusion layer and provided at an interface between the first conductivity type impurity diffusion layer and the element isolation layer. (10) The imaging device according to (9), wherein the element isolation layer is provided continuously so as to surround the periphery of the second conductivity type impurity diffusion layer. (11) The imaging device according to (9) or (10), wherein the pinning layer is provided continuously so as to surround the outer periphery of the element isolation layer. (12) The imaging device according to any of (9) to (11), wherein the pinning layer is provided on a bottom surface of the element isolation layer. (13) The imaging device according to any one of (9) to (12), wherein the inner peripheral surface of the element isolation layer includes a step provided at a position deeper in the depth direction than the position of the second conductivity type impurity diffusion layer. (14) The imaging device according to any one of (9) to (13), wherein the pinning layer is provided continuously from the outer peripheral surface of the element isolation layer, through the bottom of the element isolation layer, to the depth direction position of the step of the inner peripheral surface of the element isolation layer. (15) The imaging device according to any one of (9) to (14), wherein the first conductivity type impurity diffusion layer is used as a collector of a bipolar phototransistor, and the second conductivity type impurity diffusion layer is used as a base of the bipolar phototransistor, and an emitter of the bipolar phototransistor is joined to the base. (16) The photodetector according to (15), wherein the emitter of the bipolar phototransistor is provided at a position in contact with the element isolation layer. (17) The imaging device described in any one of (9) to (15), wherein the second conductivity type impurity diffusion layer is used for a second conductivity type well in which a channel is formed in a MOSFET type phototransistor, and a first conductivity type source layer and a first conductivity type drain layer are provided in the second conductivity type well and spaced apart via the channel.(18) A method for manufacturing a photodetector, comprising the steps of: forming a trench in a first-conductivity-type impurity diffusion region, the trench having a high-concentration first-conductivity-type impurity diffusion layer provided on a portion of a sidewall thereof; forming an element isolation layer embedded in the trench; and forming a second-conductivity-type impurity diffusion layer isolated by the element isolation layer and joined to the first-conductivity-type impurity diffusion region at a position spaced apart from the high-concentration first-conductivity-type impurity diffusion layer. (19) A method for manufacturing a photodetector, according to claim 18, wherein the step of forming the trench in the first-conductivity-type impurity diffusion region, the high-concentration first-conductivity-type impurity diffusion layer provided on a portion of the sidewall thereof, comprises the steps of: forming the high-concentration first-conductivity-type impurity diffusion layer in the first-conductivity-type impurity diffusion region by ion implantation, the high-concentration first-conductivity-type impurity diffusion layer being spaced apart from a surface of the first-conductivity-type impurity diffusion region; and forming the trench in the first-conductivity-type impurity diffusion region so that the high-concentration first-conductivity-type impurity diffusion layer remains on a portion of the sidewall thereof. (20) The method for manufacturing a photodetector according to claim 18, wherein the step of forming the trench in the first conductivity type impurity diffusion region, the trench having the high concentration first conductivity type impurity diffusion layer on a part of the sidewall, comprises the steps of: forming a trench in the first conductivity type impurity diffusion region; forming a mask on the sidewall of the trench; etching the bottom of the trench whose sidewall is covered with the mask to form a step in the trench located at a position in the depth direction of the mask; and introducing first conductivity type impurities into the sidewall of the trench exposed from the mask.

[0186] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit 121 Photodiode 122 Transfer transistor 123 Reset transistor 124 Amplification transistor 125 Selection transistor PIX Pixel HSL Horizontal drive line VSL Vertical signal line 131 P-type semiconductor substrate 132 Pixel isolation layer 133 Element isolation layer 134 N-type impurity diffusion layer 135, 136 P ＋ Type impurity diffusion layer 137 Pinning layer 141 Light-shielding layer 142 Color filter 143 On-chip lens

Claims

1. A photodetector comprising: a first conductive type impurity diffusion layer provided at a position where light is incident; a second conductive type impurity diffusion layer joined to said first conductive type impurity diffusion layer; an element isolation layer embedded in said first conductive type impurity diffusion layer so as to isolate said second conductive type impurity diffusion layer; and a pinning layer spaced apart from said second conductive type impurity diffusion layer and provided at an interface between said first conductive type impurity diffusion layer and said element isolation layer.

2. The photodetector according to claim 1, wherein the element isolation layer is provided continuously so as to surround the periphery of the second conductivity type impurity diffusion layer.

3. The photodetector according to claim 1, wherein the pinning layer is provided continuously so as to surround the outer periphery of the element isolation layer.

4. The photodetector according to claim 1, wherein the pinning layer is provided on the bottom surface of the element isolation layer.

5. The photodetector according to claim 1, wherein the inner peripheral surface of the element isolation layer is provided with a step provided at a position deeper in the depth direction than the position of the second conductive type impurity diffusion layer.

6. The photodetector according to claim 1, wherein the first conductive type impurity diffusion layer is used as a collector of a bipolar phototransistor, the second conductive type impurity diffusion layer is used as a base of the bipolar phototransistor, and the emitter of the bipolar phototransistor is joined to the base.

7. The photodetector according to claim 6, wherein the emitter of the bipolar phototransistor is provided at a position in contact with the element isolation layer.

8. The photodetector according to claim 1, wherein the second conductivity type impurity diffusion layer is used in a second conductivity type well in which a channel is formed in a MOSFET phototransistor, and a first conductivity type source layer and a first conductivity type drain layer are provided in the second conductivity type well and spaced apart via the channel.

9. An imaging device comprising a pixel array section in which pixels are arranged in a matrix in row and column directions, each pixel comprising a photoelectric conversion section for converting light into an electrical signal, the photoelectric conversion section comprising: a first conductive type impurity diffusion layer provided at a position where the light is incident; a second conductive type impurity diffusion layer joined to the first conductive type impurity diffusion layer; an element isolation layer embedded in the first conductive type impurity diffusion layer so as to isolate the second conductive type impurity diffusion layer; and a pinning layer spaced from the second conductive type impurity diffusion layer and provided at an interface between the first conductive type impurity diffusion layer and the element isolation layer.

10. The imaging device according to claim 9, wherein the element isolation layer is provided continuously so as to surround the periphery of the second conductivity type impurity diffusion layer.

11. The imaging device according to claim 9, wherein the pinning layer is provided continuously so as to surround the outer periphery of the element isolation layer.

12. The imaging device according to claim 9, wherein the pinning layer is provided on a bottom surface of the element isolation layer.

13. The imaging device according to claim 9, wherein the inner peripheral surface of the element isolation layer is provided with a step provided at a position deeper in the depth direction than the position of the second conductivity type impurity diffusion layer.

14. The imaging device according to claim 9, wherein the pinning layer is provided continuously from the outer peripheral surface of the element isolation layer through the bottom of the element isolation layer to a depth position of the step on the inner peripheral surface of the element isolation layer.

15. The imaging device according to claim 9, wherein the first conductive type impurity diffusion layer is used as a collector of a bipolar phototransistor, the second conductive type impurity diffusion layer is used as a base of the bipolar phototransistor, and the emitter of the bipolar phototransistor is joined to the base.

16. The photodetector according to claim 15, wherein the emitter of the bipolar phototransistor is provided at a position in contact with the element isolation layer.

17. The imaging device according to claim 9, wherein the second conductivity type impurity diffusion layer is used in a second conductivity type well in which a channel is formed in a MOSFET phototransistor, and a first conductivity type source layer and a first conductivity type drain layer are provided in the second conductivity type well and spaced apart via the channel.

18. A method for manufacturing a photodetector comprising the steps of: forming a trench in a first conductivity type impurity diffusion region, the trench having a high concentration first conductivity type impurity diffusion layer provided on part of a sidewall; forming an element isolation layer embedded in the trench; and forming a second conductivity type impurity diffusion layer separated from the high concentration first conductivity type impurity diffusion layer and joined to the first conductivity type impurity diffusion region by the element isolation layer.

19. A method for manufacturing a photodetector as described in claim 18, wherein the step of forming the trench in the first conductivity type impurity diffusion region, having the high concentration first conductivity type impurity diffusion layer provided on a portion of the sidewall, comprises the steps of: forming the high concentration first conductivity type impurity diffusion layer in the first conductivity type impurity diffusion region spaced from a surface of the first conductivity type impurity diffusion region based on ion implantation; and forming the trench in the first conductivity type impurity diffusion region such that the high concentration first conductivity type impurity diffusion layer remains on a portion of the sidewall.

20. A method for manufacturing a photodetector as described in claim 18, wherein the step of forming the trench in the first conductivity type impurity diffusion region, the trench having the high concentration first conductivity type impurity diffusion layer provided on a portion of the sidewall, comprises the steps of: forming a trench in the first conductivity type impurity diffusion region; forming a mask on the sidewall of the trench; etching the bottom of the trench whose sidewall is covered with the mask to form a step in the trench at a position in the depth direction of the mask; and introducing a first conductivity type impurity into the sidewall of the trench exposed from the mask.

Images