Selector-integrated phase change memory element and operation method thereof

Abstract

The present invention relates to a selector-integrated phase change memory element and an operation method thereof. A selector-integrated phase change memory element according to one embodiment of the present invention comprises: bit lines that extend in a first direction; word lines that extend in a second direction perpendicular to the first direction; and phase change layers that are interposed at each of the intersections between the bit lines and the word lines, are used as data storage due to the crystal state being changed by voltage pulses applied through the bit lines and the word lines, and are used as a selector to selectively receive the voltage pulses.

Description

Selector-integrated phase-change memory device and its operating method

[0001] The present invention relates to a phase change memory device integrated with a selection element and an operating method thereof.

[0002] Rapid advancements in information technology (IT) are driving the demand for next-generation memory devices featuring ultra-high speed, high capacity, and high density, making them ideal for the development of portable information and communication systems and devices capable of wirelessly processing large amounts of data. While 3D V-NAND memory currently offers the highest density, its ability to achieve ultra-high density is expected to be limited due to increasing string heights and the process challenges of forming layers exceeding 100.

[0003] To replace this, next-generation memory devices such as STT-MRAM, FeRAM, ReRAM, and PCRAM, which have superior power, data retention, and write / read characteristics compared to conventional memory devices, are being studied.

[0004] Among these, PCRAM (hereinafter, phase change memory) changes the crystal state of the phase change layer between crystalline and amorphous as heat generated by a voltage pulse applied between the upper electrode and the lower electrode is supplied to the phase change layer, so that it has low resistance when in the crystalline state and high resistance when in the amorphous state, thereby being able to display a binary value corresponding to each resistance state (for example, when the crystal state of the phase change layer is in the crystalline state and has low resistance, it displays a set state of binary value [0], and when the crystal state of the phase change layer is in the amorphous state and has high resistance, it displays a reset state of binary value [1]).

[0005] These phase-change memories are being actively studied as next-generation semiconductor memory devices because they can be manufactured at low cost and operate at high speeds, and structures implemented with various three-dimensional architectures are being proposed to improve the two-dimensional scaling limitations.

[0006] However, existing phase-change memories have the disadvantage of being difficult to implement high integration because they require a selection element that selectively supplies or blocks voltage pulses to the phase-change layer.

[0007] Moreover, existing phase change memories have the problem of reduced integration because they additionally require an intermediate electrode placed between the phase change layer and the selection element in addition to the selection element.

[0008] Accordingly, there is a need to propose a phase-change memory device that solves the shortcomings and problems of existing phase-change memories.

[0009] The background technology described above is technology that the inventor possessed or acquired in the process of deriving the disclosure of the present invention, and cannot necessarily be said to be publicly known technology disclosed to the general public prior to the present application.

[0010] The present invention is intended to solve the above-described problem, and the purpose of the present invention is to provide a phase change memory device with a structure that includes a phase change layer used as a selection element to selectively receive voltage pulses while being used as a data storage by changing a crystal state by voltage pulses applied through bit lines and word lines, and an operating method thereof, in order to improve the integration level through a structure that does not include a selection element.

[0011] At this time, the embodiments provide a phase change memory device with an integrated selection element based on a phase change layer formed of a single element material including a group 16 element so that the crystal state is changed between a low resistance state and a high resistance state within a crystalline state by a voltage pulse, and an operating method thereof, in order to solve the problem that a material deterioration phenomenon such as a phase separation phenomenon occurs in an external environment of unstable temperature and humidity in an amorphous state and the disadvantage that power consumption is high for recording in a high resistance state in an amorphous state and reading in a high resistance state.

[0012] In addition, the embodiments provide a phase-change memory device integrated with a selection element that controls the threshold voltage values ​​of each of a set operation and a reset operation, and an operating method thereof, in order to implement a memory operation based on a phase-change layer formed of a single element material.

[0013] However, the problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0014] A phase change memory device integrated with a selection element according to one embodiment of the present invention includes bit lines extending in a first direction; word lines extending in a second direction orthogonal to the first direction; and a phase change layer interposed at each of intersections between the bit lines and the word lines, the phase change layer being used as a data storage device by changing a crystal state by a voltage pulse applied through the bit lines and the word lines, and being used as a selection element to selectively receive the voltage pulse.

[0015] In one embodiment, the phase change layer may be formed of a material whose crystal state changes between a low resistance state and a high resistance state within a crystalline state by the voltage pulse.

[0016] In one embodiment, the phase change layer may be formed of a single element material including a Group 16 element such that the crystal state changes between the low resistance state and the high resistance state within the crystalline state.

[0017] In one embodiment, the phase-change memory device integrated with the selection element can control the rise time, the hold time, and the fall time of the voltage pulse differently from each other in a set operation that changes the crystal state of the phase-change layer to the low resistance state and in a reset operation that changes the crystal state of the phase-change layer to the high resistance state.

[0018] In one embodiment, the phase-change memory device integrated with the selection element can adjust the rise time, hold time, and fall time of the voltage pulse during the set operation to be shorter than the reset operation.

[0019] In one embodiment, the phase-change memory device integrated with the selection element can control the grain size or interface characteristics of the phase-change layer by controlling the rise time, hold time, and fall time of the voltage pulse differently in the set state and the reset state, thereby controlling the threshold voltage values ​​of each of the set operation and the reset operation.

[0020] In one embodiment, the selective element-integrated phase-change memory device may have a structure in which the word lines arranged along the first direction are connected to each of the bit lines.

[0021] In one embodiment, the phase-change memory device integrated with the selection element may have a structure in which the word lines are connected to each of the bit lines along the first direction and along a third direction orthogonal to the first direction and the second direction.

[0022] According to another embodiment of the present invention, a method for operating a phase-change memory device with an integrated selection element includes: bit lines extending in a first direction; word lines extending in a second direction orthogonal to the first direction; and a phase-change layer interposed at each of intersections between the bit lines and the word lines, the method comprising: applying a voltage pulse through the bit lines and the word lines; selectively receiving the voltage pulse when the phase-change layer is used as a selection element; and performing a memory operation for recording or deleting data by changing a crystal state by the voltage pulse when the phase-change layer is used as a data storage.

[0023] In one embodiment, the performing step may include one of: performing a set operation for recording the data by changing the crystal state of the phase change layer to a low resistance state within the crystalline state; or performing a reset operation for deleting the data by changing the crystal state of the phase change layer to a high resistance state within the crystalline state.

[0024] In one embodiment, the phase change layer may be formed of a single element material including a Group 16 element such that the crystal state changes between the low resistance state and the high resistance state within the crystalline state.

[0025] In one embodiment, the applying step may include a step of adjusting the rising time, holding time, and falling time of the voltage pulse differently from each other in the set operation and the reset operation.

[0026] In one embodiment, the adjusting step may include one of: adjusting the rising time, holding time, and falling time of the voltage pulse during the set operation to be shorter than the reset operation; or adjusting the rising time, holding time, and falling time of the voltage pulse during the reset operation to be longer than the set operation.

[0027] In one embodiment, the applying step may include a step of controlling the grain size or interface characteristics of the phase change layer by differently adjusting the rise time, hold time, and fall time of the voltage pulse in the set state and the reset state, thereby controlling the threshold voltage values ​​of each of the set operation and the reset operation.

[0028] In one embodiment, the operating method of the phase-change memory device with integrated selection element may further include a step of performing a read operation for reading the crystal state of the phase-change layer by applying a voltage pulse having a value between the value of the voltage pulse during the set operation and the value of the voltage pulse during the reset operation.

[0029] The embodiments propose a phase change memory device integrated with a selection element having a structure including a phase change layer used as a selection element to selectively supply voltage pulses while being used as a data storage by changing a crystal state by voltage pulses applied through bit lines and word lines, and an operating method thereof, thereby achieving a technical effect of improving integration through a structure that does not include a selection element.

[0030] At this time, the embodiments propose a phase-change memory device with a selector-integrated phase-change layer formed of a single element material including a group 16 element so that the crystal state is changed between a low-resistance state and a high-resistance state within a crystalline state by a voltage pulse, and an operating method thereof, thereby achieving a technical effect that solves the problem of a material deterioration phenomenon such as a phase separation phenomenon occurring in an external environment of unstable temperature and humidity in a phase-change layer having an amorphous state and the disadvantage of high power consumption for recording in a high-resistance state in an amorphous state and reading out a high-resistance state.

[0031] In addition, the embodiments can propose a phase-change memory device and an operating method thereof that integrate a selection element to control the threshold voltage values ​​of each of a set operation and a reset operation in order to implement a memory operation based on a phase-change layer formed of a single element material.

[0032] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0033] FIGS. 1A and 1B are simplified circuit diagrams illustrating a phase change memory device integrated with a selection element according to one embodiment of the present invention.

[0034] FIGS. 2A to 2C are drawings illustrating a phase change memory device integrated with a selection element according to one embodiment of the present invention.

[0035] FIGS. 3A to 3C are drawings illustrating a phase change memory device integrated with a selection element according to another embodiment of the present invention.

[0036] FIGS. 4A to 4C are drawings illustrating a phase change memory device integrated with a selection element according to another embodiment of the present invention.

[0037] FIG. 5 is a diagram illustrating a voltage pulse applied between a bit line and a word line to explain the memory operation of a phase-change memory device integrated with a selection element according to embodiments of the present invention.

[0038] FIG. 6 is a flowchart illustrating an operating method of a phase-change memory device integrated with a selection element according to one embodiment of the present invention.

[0039] FIG. 7 is a perspective view schematically illustrating an electronic system including a phase-change memory device integrated with a selection element according to one embodiment of the present invention.

[0040] Hereinafter, embodiments are described in detail with reference to the attached drawings. However, the embodiments may be modified in various ways, and the scope of the patent application is not limited or restricted by these embodiments. It should be understood that all modifications, equivalents, or alternatives to the embodiments are included within the scope of the patent application.

[0041] The terms used in the examples are for illustrative purposes only and should not be construed as limiting. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "have" are intended to indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood to not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0042] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the embodiments pertain. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0043]

[0044] In addition, when describing with reference to the attached drawings, identical components will be assigned the same reference numerals regardless of the drawing numbers, and redundant descriptions thereof will be omitted. When describing embodiments, if a detailed description of a related known technology is judged to unnecessarily obscure the gist of the embodiment, the detailed description will be omitted.

[0045] Additionally, in describing components of an embodiment, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0046] Components included in one embodiment and components with common functions will be described using the same names in other embodiments. Unless otherwise stated, the descriptions given in one embodiment may also apply to other embodiments, and detailed descriptions will be omitted to the extent of overlap.

[0047]

[0048] Hereinafter, a phase change memory device integrated with a selection element, which is used as a data storage device by changing the crystal state by voltage pulses applied through bit lines and word lines of the present invention, and which includes a phase change layer used as a selection element to selectively receive voltage pulses, and an operating method thereof, will be described in detail with reference to embodiments and drawings. However, the present invention is not limited to these embodiments and drawings.

[0049]

[0050] A phase change memory device integrated with a selection element according to one embodiment of the present invention includes bit lines extending in a first direction; word lines extending in a second direction orthogonal to the first direction; and a phase change layer interposed at each of intersections between the bit lines and the word lines, the phase change layer being used as a data storage device by changing a crystal state by a voltage pulse applied through the bit lines and the word lines, and being used as a selection element to selectively receive the voltage pulse.

[0051] FIGS. 1A and 1B are simplified circuit diagrams illustrating a phase change memory device integrated with a selection element according to one embodiment of the present invention.

[0052] Referring to FIGS. 1A and 1B, a selector-integrated phase change memory device according to one embodiment may include bit lines (BLs), word lines (WLs), and a phase change layer (SIP; Selector-Integrated Phase layer).

[0053] Bit lines (BLs) can be arranged two-dimensionally while extending in a first direction (D1) and being spaced apart from each other along a second direction (a direction orthogonal to the first direction; D2).

[0054] Hereinafter, the first direction (D1), the second direction (D2), and the third direction (the direction orthogonal to the first and second directions; D3) are orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0055] Word lines (WLs) can be arranged two-dimensionally, spaced apart from each other along the first direction (D1), and extending in the second direction (D2).

[0056] Each of the bit lines (BLs) and the word lines (WLs) may include at least one selected from a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), gold (Au), etc.), a doped semiconductor (e.g., doped silicon), or a conductive metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) to which a voltage pulse can be applied.

[0057] At this time, each of the bit lines (BLs) and the word lines (WLs) may be formed to be optimized for the phase change layer (SIP) in order to control the current flow of the phase change layer (SIP), taking into account the characteristics of the phase change layer (SIP) described below (the phase change layer (SIP) is formed of a single element material including a group 16 element so that the crystal state thereof is changed between a low resistance state and a high resistance state within a crystalline state by a voltage pulse). For example, each of the bit lines (BLs) and the word lines (WLs) may be formed by depositing a metal nitride or metal material such as TiN, TaN or W based on DC sputtering or DC reactive sputtering.

[0058] A phase-change layer (SIP) is interposed at each intersection between bit lines (BLs) and word lines (WLs), and its crystal state changes due to heat generated by a voltage pulse applied between the bit lines (BLs) and word lines (WLs), so that it can be used as data storage, and at the same time, it can be used as a selection element (Ovonic threshold switch; OTS) to selectively receive the voltage pulse. For this purpose, the phase-change layer (SIP) can be formed of a chalcogenide material including a group 16 element.

[0059] Hereinafter, applying a voltage pulse between bit lines (BLs) and word lines (WLs) means applying a voltage pulse through the bit lines (BLs) and word lines (WLs) so that a voltage difference is generated in the phase change layer (SIP).

[0060] In this way, since the phase-change layer (SIP) is used as a data storage device as well as a selection device, the selection device-integrated phase-change memory device can be implemented with a structure that does not include a selection device, thereby improving integration.

[0061] A thin film formed from a single element material based on Group 16 elements has a relatively low crystallization temperature and melting point, unlike a thin film formed from a multi-element material based on Group 16 elements, and thus has the characteristic of always maintaining a crystalline state.

[0062] Based on these characteristics, the phase change layer (SIP) can be formed of a single element material containing a group 16 element so that the crystal state changes between a low-resistance state and a high-resistance state within the crystalline state by a voltage pulse, unlike a conventional phase change layer in which the crystal state changes between an amorphous state and a crystalline state by a voltage pulse.

[0063] For example, a phase change layer (SIP) can be formed of a single element material including a Group 16 chalcogenide element, such as selenium (Se) or tellurium (Te), such that the crystal state changes between a low-resistance state and a high-resistance state within the crystalline state.

[0064] Here, the change of the phase change layer (SIP) between a low resistance state and a high resistance state within the crystalline state means that the phase change layer (SIP) changes to a crystalline state that is a low resistance state (set state) within the crystalline state through a set operation, or changes to a crystalline state that is a high resistance state (reset state) within the crystalline state through a reset operation.

[0065] That is, the phase change layer (SIP) can have a low resistance state or a high resistance state depending on the voltage pulse while always maintaining a crystalline state.

[0066] Hereinafter, a low resistance state means a state having a relatively low resistance compared to a high resistance state, or a resistance state that is below a preset threshold resistance value. Similarly, a high resistance state means a state having a relatively high resistance compared to a low resistance state, or a resistance state that is above a preset threshold resistance value.

[0067] In this way, since the phase change layer (SIP) is formed of a single element material based on a Group 16 chalcogenide element, the set state and reset state are implemented within the crystalline state, and the amorphous state is excluded from the set state or reset state, thereby preventing material deterioration phenomena such as phase separation due to an external environment of unstable temperature and humidity, and achieving a technical effect of reducing power consumption for recording and reading.

[0068] The phase change layer (SIP) can be formed using physical vapor deposition (sputtering, molecular beam, epitaxy, thermal evaporator, pulsed laser deposition, etc.) or chemical vapor deposition (chemical vapor deposition, atomic layer deposition, etc.).

[0069] The phase change memory device with integrated selection element implements a memory operation based on a phase change layer (SIP) formed of a single element material as described above, and has threshold voltage values ​​(V) for each of the set operation and reset operation. th, set , V th, reset ) can be adjusted to suit the phase change layer (SIP) formed from a single element material.

[0070] More specifically, the phase-change memory device with an integrated selector can control the grain size or interface characteristics of the phase-change layer (SIP) by adjusting the rise time, hold time, and fall time of the voltage pulse differently in the set operation and the reset operation, thereby controlling the threshold voltage values ​​of the set operation and the reset operation, respectively. A detailed description thereof will be described with reference to Fig. 5.

[0071] The above-described selective element-integrated phase-change memory device may have a two-dimensional structure in which word lines (WLs) arranged along a first direction (D1) are connected to each of bit lines (BLs), as illustrated in FIG. 1a, depending on an implementation example, or may have a three-dimensional structure in which word lines (WLs) arranged along a first direction (D1) and simultaneously arranged along a third direction (D3) are connected to each of bit lines (BLs), as illustrated in FIG. 1b. A detailed description thereof will be described with reference to FIGS. 2a to 2c, 3a to 3c, or 4a to 4c.

[0072]

[0073] FIGS. 2A to 2C are diagrams illustrating a phase change memory device with an integrated selection element according to an embodiment of the present invention. More specifically, FIG. 2A is a perspective view illustrating a phase change memory device with an integrated selection element according to an embodiment, FIG. 2B is a cross-sectional view illustrating a phase change memory device with an integrated selection element according to an embodiment, which corresponds to a cross-section taken along line A-A' of FIG. 2A, and FIG. 2C is a cross-sectional view illustrating a phase change memory device with an integrated selection element according to an embodiment, which corresponds to a cross-section taken along line B-B' of FIG.

[0074] Referring to FIGS. 2A to 2C, a phase-change memory device integrated with a selection element according to one embodiment includes a substrate (SUB), an insulating layer (ILD) formed on a horizontal plane formed by a first direction (D1) and a second direction (D2) on the substrate (SUB), word lines (WLs) extending in the second direction (D2) on the insulating layer (ILD) and arranged along the first direction (D1), bit lines (BLs) extending in the first direction (D1) and arranged along the second direction (D2), and phase-change layers (SIP) interposed between the word lines (WLs) and the bit lines (BLs), wherein the word lines (WLs) are implemented in a two-dimensional mushroom structure having a shape in which they each protrude toward the phase-change layers (SIP), and thus can be expressed as an equivalent simplified circuit diagram illustrated in FIG. 1A.

[0075] The substrate (SUB) may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystalline silicon substrate, or a single crystalline epitaxial layer grown on the substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P type impurity).

[0076] The insulating layer (ILD) may be formed of a dielectric material such as silicon oxide that has insulating properties to insulate the word lines (WLs) and bit lines (BLs) from each other so that the word lines (WLs) and bit lines (BLs) are electrically connected only through the phase change layers (SIP).

[0077] Each of the bit lines (BLs) and word lines (WLs) can be formed of a conductive material as described above through FIGS. 1A and 1B so that a voltage pulse can be applied to change the crystal state of each of the phase change layers (SIPs).

[0078] Each of the phase change layers (SIPs) can be formed of a single element material comprising a Group 16 element such that the crystal state is changed between a low resistance state and a high resistance state within the crystalline state by a voltage pulse, as described above with reference to FIGS. 1A and 1B.

[0079] According to one embodiment, the phase-change memory device integrated with a selection element is not limited to or restricted to the two-dimensional mushroom structure illustrated in the drawings, and may be implemented in various structures, assuming that it includes word lines (WLs) and bit lines (BLs) to which voltage pulses for memory operation are applied, and phase-change layers (SIPs) interposed between the word lines (WLs) and bit lines (BLs), according to an implementation example.

[0080]

[0081] FIGS. 3A to 3C are diagrams illustrating a phase change memory device with an integrated selection element according to another embodiment of the present invention. More specifically, FIG. 3A is a perspective view illustrating a phase change memory device with an integrated selection element according to another embodiment, FIG. 3B is a cross-sectional view illustrating a phase change memory device with an integrated selection element according to another embodiment, which corresponds to a cross-section taken along line A-A' of FIG. 3A, and FIG. 3C is a cross-sectional view illustrating a phase change memory device with an integrated selection element according to another embodiment, which corresponds to a cross-section taken along line B-B' of FIG.

[0082] Referring to FIGS. 3a to 3c, a phase-change memory device integrated with a selection element according to another embodiment of the present invention includes a substrate (SUB), an insulating layer (ILD) formed on a horizontal plane formed by a first direction (D1) and a second direction (D2) on the substrate (SUB), word lines (WLs) extending in the second direction (D2) on the insulating layer (ILD) and arranged along the first direction (D1), bit lines (BLs) extending in the first direction (D1) and arranged along the second direction (D2), and phase-change layers (SIP) interposed between the word lines (WLs) and the bit lines (BLs), wherein the phase-change layers (SIP) have a recessed shape protruding toward the word lines (WLs), and the bit lines (BLs) have a shape protruding toward the phase-change layers (SIP), and a two-dimensional semi-confined mushroom structure. By being implemented, it can be expressed as an equivalent simplified circuit diagram as shown in Fig. 1a.

[0083] The substrate (SUB) may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystalline silicon substrate, or a single crystalline epitaxial layer grown on the substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P type impurity).

[0084] The insulating layer (ILD) may be formed of a dielectric material such as silicon oxide that has insulating properties to insulate the word lines (WLs) and bit lines (BLs) from each other so that the word lines (WLs) and bit lines (BLs) are electrically connected only through the phase change layers (SIP).

[0085] Each of the bit lines (BLs) and word lines (WLs) can be formed of a conductive material as described above through FIGS. 1A and 1B so that a voltage pulse can be applied to change the crystal state of each of the phase change layers (SIPs).

[0086] Each of the phase change layers (SIPs) can be formed of a single element material comprising a Group 16 element such that the crystal state is changed between a low resistance state and a high resistance state within the crystalline state by a voltage pulse, as described above with reference to FIGS. 1A and 1B.

[0087] According to another embodiment, the phase-change memory device integrated with a selection element is not limited to or restricted to the two-dimensional quasi-bound mushroom structure illustrated in the drawings, and may be implemented in various structures, assuming that it includes word lines (WLs) and bit lines (BLs) to which voltage pulses for memory operation are applied, and phase-change layers (SIP) interposed between the word lines (WLs) and bit lines (BLs), according to an implementation example.

[0088]

[0089] FIGS. 4A to 4C are diagrams illustrating a phase change memory device with an integrated selection element according to another embodiment of the present invention. More specifically, FIG. 4A is a perspective view illustrating a phase change memory device with an integrated selection element according to another embodiment of the present invention, FIG. 4B is a cross-sectional view illustrating a phase change memory device with an integrated selection element according to another embodiment of the present invention, which corresponds to a cross-section taken along line A-A' of FIG. 4A, and FIG. 4C is a cross-sectional view illustrating a phase change memory device with an integrated selection element according to another embodiment of the present invention, which corresponds to a cross-section taken along line B-B' of FIG.

[0090] Referring to FIGS. 4a to 4c, a phase-change memory device integrated with a selection element according to another embodiment is implemented with a three-dimensional heater-all around structure including a substrate (SUB), insulating layers (ILD) and word lines (WLs) alternately stacked along a third direction (D3) on a horizontal plane formed by a first direction (D1) and a second direction (D2) on the substrate (SUB), bit lines (BLs) extending in the first direction (D1) and arranged along the second direction (D2), and phase-change layers (SIP) formed to penetrate the insulating layers (ILD) and word lines (WLs) alternately stacked and come into contact with the word lines (WLs) and bit lines (BLs), thereby being expressed as an equivalent simplified circuit diagram as shown in FIG. 1b.

[0091] The substrate (SUB) may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystalline silicon substrate, or a single crystalline epitaxial layer grown on the substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P type impurity).

[0092] The insulating layer (ILD) may be formed of a dielectric material such as silicon oxide that has insulating properties to insulate the word lines (WLs) and bit lines (BLs) from each other so that the word lines (WLs) and bit lines (BLs) are electrically connected only through the phase change layers (SIP).

[0093] Each of the bit lines (BLs) and word lines (WLs) can be formed of a conductive material as described above through FIGS. 1A and 1B so that a voltage pulse can be applied to change the crystal state of each of the phase change layers (SIPs).

[0094] Each of the phase change layers (SIPs) can be formed of a single element material comprising a Group 16 element such that the crystal state is changed between a low resistance state and a high resistance state within the crystalline state by a voltage pulse, as described above with reference to FIGS. 1A and 1B.

[0095] According to another embodiment, the phase-change memory device integrated with a selection element is not limited to or restricted to the three-dimensional heater all-around structure illustrated in the drawings, and may be implemented in various structures, assuming that it includes word lines (WLs) and bit lines (BLs) to which voltage pulses for memory operation are applied, and phase-change layers (SIPs) interposed between the word lines (WLs) and bit lines (BLs), according to an implementation example.

[0096]

[0097] FIG. 5 is a diagram illustrating a voltage pulse applied between a bit line and a word line to explain the memory operation of a phase-change memory device integrated with a selection element according to embodiments of the present invention.

[0098] Referring to FIG. 5, the phase change memory device with integrated selection element according to the embodiments considers that the phase change layer (SIP) is formed of a single element material including a group 16 element so that the crystal state is changed between a low resistance state and a high resistance state within a crystalline state by a voltage pulse as described above through FIGS. 1A and 1B, and by controlling the grain size or interface characteristics of the phase change layer (SIP) by adjusting the rise time, hold time, and fall time of the voltage pulse differently in the set operation and the reset operation, the threshold voltage values ​​of each of the set operation and the reset operation can be adjusted to suit the phase change layer (SIP).

[0099] Specifically, the phase-change memory device with integrated selection element can adjust the rise time, hold time, and fall time of the voltage pulse during the set operation to be shorter than the reset operation, as shown in the drawing, and can adjust the rise time, hold time, and fall time of the voltage pulse during the reset operation to be longer than the set operation.

[0100] The set operation performed in this manner may be a write operation that records data in the phase change layer (SIP), and the reset operation may be a delete operation that deletes data recorded in the phase change layer (SIP).

[0101] Although the drawing shows that the voltage pulse applied during the set operation is a positive value and the voltage pulse applied during the reset operation is a negative value, the present invention is not limited or restricted thereto.

[0102] For the read operation, the phase change memory device with integrated selector is set to a value (V) when the voltage pulse is operated as shown in the drawing. th, set ) and value (V) during reset operation th, reset ) between values ​​(V th, set <V read < V th, reset ) with a voltage pulse (V read) can be applied between bit lines (BLs) and word lines (WLs) to read the crystal state of the phase change layer (SIP).

[0103] The detailed steps in which the above-described write operation (set operation), delete operation (reset operation), and read operation are performed are described with reference to FIG. 6.

[0104]

[0105] According to another embodiment of the present invention, a method for operating a phase-change memory device with an integrated selection element includes: bit lines extending in a first direction; word lines extending in a second direction orthogonal to the first direction; and a phase-change layer interposed at each of intersections between the bit lines and the word lines, the method comprising: applying a voltage pulse through the bit lines and the word lines; selectively receiving the voltage pulse when the phase-change layer is used as a selection element; and performing a memory operation for recording or deleting data by changing a crystal state by the voltage pulse when the phase-change layer is used as a data storage.

[0106] FIG. 6 is a flowchart illustrating an operating method of a phase-change memory device with an integrated selection element according to one embodiment of the present invention. The operating method described below is based on the assumption that the memory operation is performed by the phase-change memory device with an integrated selection element having the structure described above with reference to FIGS. 1A to 4C, and may utilize the voltage pulse illustrated in FIG. 5.

[0107] Referring to FIG. 6, in step (610), the selection element-integrated memory element can apply voltage pulses through bit lines (BLs) and word lines (WLs).

[0108] At this time, in step (610), the memory element integrated with the selection element can adjust the value of the voltage pulse differently depending on whether to perform a set operation for recording data or a reset operation for deleting data.

[0109] In particular, in step (610), the memory element integrated with the selection element can adjust the rise time, hold time, and fall time of the voltage pulse differently in the set operation and the reset operation.

[0110] For example, a memory device with an integrated selector element can adjust the rise time, hold time, and fall time of a voltage pulse during a set operation to be shorter than during a reset operation.

[0111] As another example, a memory device with an integrated selector element can adjust the rise time, hold time, and fall time of a voltage pulse during a reset operation to be longer than during a set operation.

[0112] In this way, the memory device with an integrated selection element can control the grain size or interface characteristics of the phase change layer by adjusting the rise time, hold time, and fall time of the voltage pulse differently in the set operation and reset operation, thereby controlling the threshold voltage value of each of the set operation and reset operation.

[0113] In step (620), the selective element integrated memory element can selectively supply a voltage pulse to the phase change layer (SIP) as the phase change layer (SIP) is used as the selective element.

[0114] In step (630), the selective element-integrated memory element can perform a memory operation of recording or deleting data by changing the crystal state of the phase change layer (SIP) by a voltage pulse as the phase change layer (SIP) is used as a data storage.

[0115] More specifically, in step (630), the selective element-integrated memory element can perform a set operation to record data by changing the crystal state of the phase change layer (SIP) to a low resistance state within the crystalline state, or a reset operation to delete data by changing the crystal state of the phase change layer (SIP) to a high resistance state within the crystalline state.

[0116] To this end, the phase change layer (SIP) can be formed of a single element material containing a group 16 element such that the crystal state changes between a low-resistance state and a high-resistance state within the crystalline state.

[0117] Although not depicted as a separate step in the drawing, separately from the described write operation or erase operation, the memory device integrated with the selection element can perform a read operation to read the crystal state of the phase change layer (SIP) by applying a voltage pulse having a value between the value during the set operation and the value during the reset operation through the bit lines (BLs) and word lines (WLs).

[0118] The driving of the phase change memory device integrated with a selection element according to one embodiment of the present invention is, for example, by applying voltage to a phase change layer (SIP) through a word line (WL1, WL2, etc.) and a bit line (BL1, BL2, etc.), and the device operation can be driven and a current can be received as an output value accordingly. The phase change layer (SIP) may be composed of a single-element chalcogenide thin film.

[0119] According to one embodiment of the present invention, the driving of a phase-change memory device integrated with a selection element can store digital information of '0' or '1' by controlling the degree of Joule-heating generation according to an applied electrical pulse. More specifically, it is an operation method that changes the magnitude of the threshold voltage through changes in the grain size, defect level, and interface state with the lower electrode by controlling the properties of a single-element chalcogenide thin film by controlling the shape of the electrical pulse, particularly the fall time.

[0120] The 'erasure' process is as follows. The magnitude (voltage) of the electrical pulse is set to be higher than the melting point of the single-element chalcogenide thin film. In addition, the falling speed of the electrical pulse is set very fast. At this time, a falling time of 20 ns can be adopted. After this 'erasure' process, the SOM device has a high threshold voltage (V th , maintains the characteristics of reset.

[0121] The "recording" process is as follows. The magnitude (voltage) of the electrical pulse is set to be higher than the melting point of the single-element chalcogenide thin film. Furthermore, the falling speed of the electrical pulse is set very slowly. A falling time of 1 microsecond can be adopted. After this "recording" process, the SOM device maintains its low threshold voltage (Vth, set) characteristics.

[0122] During the 'delete' and 'write' processes, the voltage can adopt both positive and negative directions. For example, the 'delete' process can adopt a negative voltage, and the 'write' process can adopt a positive voltage.

[0123] The voltage during the 'delete' process and the 'write' process usually adopts a voltage greater than the high threshold voltage and the low threshold voltage.

[0124] The 'read' process is as follows. The magnitude (voltage) of the electrical pulse during the 'read' process is set as follows: Vth, set < Vread < Vth, reset.

[0125] When the selector-integrated phase-change memory device is in the 'erase' state, the read voltage is less than the threshold voltage (Vth, reset) of the device, so only a low current flows through the device, indicating a high-resistance state.

[0126] When a phase-change memory device with an integrated selector is in a 'write' state, the read voltage is greater than the threshold voltage (Vth, set) of the device, causing a higher current to flow through the device, indicating a low-resistance state.

[0127] Any SOM element can be addressed by selecting a word line (WL1, WL2, etc.) and a bit line (BL1, BL2, etc.), and the memory operation can be programmed by applying an electrical pulse between the word line and the bit line. In addition, the programmed information can be read by measuring the current value through the bit line at this time.

[0128]

[0129] FIG. 7 is a perspective view schematically illustrating an electronic system including a phase-change memory device integrated with a selection element according to one embodiment of the present invention.

[0130] Referring to FIG. 7, an electronic system (700) including a three-dimensional flash memory according to embodiments may include a main substrate (701), a controller (702) mounted on the main substrate (701), one or more semiconductor packages (703), and a DRAM (704).

[0131] The semiconductor package (703) and DRAM (704) can be connected to the controller (702) by wiring patterns (705) provided on the main substrate (701).

[0132] The main board (701) may include a connector (706) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (706) may vary depending on the communication interface between the electronic system (700) and the external host.

[0133] The electronic system (700) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (700) may operate by power supplied from an external host, for example, through a connector (706). The electronic system (700) may further include a PMIC (Power Management Integrated Circuit) that distributes power supplied from the external host to a controller (702) and a semiconductor package (703).

[0134] The controller (702) can write data to the semiconductor package (703) or read data from the semiconductor package (703), and can improve the operating speed of the electronic system (700).

[0135] The DRAM (704) may be a buffer memory to mitigate the speed difference between the semiconductor package (703), which is a data storage space, and an external host. The DRAM (704) included in the electronic system (700) may also function as a type of cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package (703). When the electronic system (700) includes the DRAM (704), the controller (702) may further include a DRAM controller for controlling the DRAM (704) in addition to the NAND controller for controlling the semiconductor package (703).

[0136] The semiconductor package (703) may include first and second semiconductor packages (703a, 1303b) that are spaced apart from each other. The first and second semiconductor packages (703a, 1303b) may each be a semiconductor package including a plurality of semiconductor chips (720). Each of the first and second semiconductor packages (703a, 1303b) may include a package substrate (710), semiconductor chips (720) on the package substrate (710), adhesive layers (730) disposed on a lower surface of each of the semiconductor chips (720), connection structures (740) that electrically connect the semiconductor chips (720) and the package substrate (710), and a molding layer (750) that covers the semiconductor chips (720) and the connection structures (740) on the package substrate (710).

[0137] The package substrate (710) may be a printed circuit board including package upper pads (711). Each of the semiconductor chips (720) may include input / output pads (721). Each of the semiconductor chips (720) may include a selective element-integrated phase-change memory device described above with reference to FIGS. 1A to 6.

[0138] The connection structures (740) may be, for example, bonding wires that electrically connect the input / output pads (721) and the package upper pads (711). Accordingly, in each of the first and second semiconductor packages (703a, 1303b), the semiconductor chips (720) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (711) of the package substrate (710). According to embodiments, in each of the first and second semiconductor packages (703a, 1303b), the semiconductor chips (720) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (740).

[0139] Unlike the illustration, the controller (702) and the semiconductor chips (720) may be included in a single package. The controller (702) and the semiconductor chips (720) may be mounted on a separate interposer substrate different from the main substrate (701), and the controller (702) and the semiconductor chips (720) may be connected to each other by wiring provided on the interposer substrate.

[0140]

[0141] Although the embodiments described above have been described with limited drawings, those skilled in the art will appreciate that various technical modifications and variations can be applied based on the above. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0142] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Bit lines formed extending in the first direction; Word lines formed extending in a second direction orthogonal to the first direction; and A phase change layer interposed at each of the intersection points between the bit lines and the word lines, and used as a data storage device by changing the crystal state by a voltage pulse applied through the bit lines and the word lines, and used as a selection element to selectively receive the voltage pulse; including, Selector-integrated phase-change memory device.

2. In paragraph 1, The above phase change layer is, A material formed by the voltage pulse changing between a low resistance state and a high resistance state within a crystalline state, Selector-integrated phase-change memory device.

3. In paragraph 2, The above phase change layer is, The above crystal state is formed of a single element material containing a group 16 element so that the crystal state changes between the low resistance state and the high resistance state within the crystalline state, Selector-integrated phase-change memory device.

4. In paragraph 2, The above-mentioned selector-integrated phase-change memory device is, The rise time, hold time and fall time of the voltage pulse are controlled differently from each other in the set operation that changes the crystal state of the phase change layer to the low resistance state and the reset operation that changes the crystal state of the phase change layer to the high resistance state. Selector-integrated phase-change memory device.

5. In paragraph 4, The above-mentioned selector-integrated phase-change memory device is, In the above set operation, the rise time, hold time and fall time of the voltage pulse are adjusted to be shorter than the reset operation. Selector-integrated phase-change memory device.

6. In paragraph 4, The above-mentioned selector-integrated phase-change memory device is, By controlling the grain size or interface characteristics of the phase change layer by adjusting the rise time, hold time and fall time of the voltage pulse differently in the set state and the reset state, the threshold voltage value of each of the set operation and the reset operation is controlled. Selector-integrated phase-change memory device.

7. In paragraph 1, The above-mentioned selector-integrated phase-change memory device is, A structure in which the word lines listed along the first direction are connected to each of the bit lines, Selector-integrated phase-change memory device.

8. In paragraph 1, The above-mentioned selector-integrated phase-change memory device is, A structure in which the word lines are connected to each of the bit lines along the first direction and along a third direction orthogonal to the first direction and the second direction, Selector-integrated phase-change memory device.

9. A method for operating a phase-change memory device with an integrated selection element, comprising: bit lines extending in a first direction; word lines extending in a second direction orthogonal to the first direction; and a phase-change layer interposed at each of the intersections between the bit lines and the word lines. A step of applying a voltage pulse through the bit lines and the word lines; A step of selectively supplying the voltage pulse to the phase change layer as the phase change layer is used as a selection element; and A step of performing a memory operation of recording or deleting data by changing the crystal state of the phase change layer by the voltage pulse as the phase change layer is used as a data storage; including, Method of operating a phase change memory device with an integrated selection element.

10. In paragraph 9, The steps performed above are: A step of performing a set operation for recording the data by changing the crystal state of the phase change layer to a low resistance state within a crystalline state; or A step of performing a reset operation to delete the data by changing the crystal state of the phase change layer to a high resistance state within the crystal state; comprising any one of the steps, An operating method of a phase-change memory device integrated with a selection element.

11. In paragraph 10, The above phase change layer is, wherein the crystal state is formed of a single element material containing a group 16 element such that the crystal state changes between the low resistance state and the high resistance state within the crystalline state; An operating method of a phase-change memory device integrated with a selection element.

12. In paragraph 10, The above authorization step is, A step of adjusting the rise time, hold time and fall time of the voltage pulse differently from each other in the set operation and the reset operation; including, An operating method of a phase-change memory device integrated with a selection element.

13. In paragraph 12, The above adjusting steps are: A step of adjusting the rise time, hold time and fall time of the voltage pulse during the above set operation to be shorter than the reset operation; or A step of adjusting the rise time, hold time and fall time of the voltage pulse during the reset operation to be longer than the set operation; comprising any one of the steps, An operating method of a phase-change memory device integrated with a selection element.

14. In paragraph 10, The above authorization step is, A step of controlling the grain size or interface characteristics of the phase change layer by differently adjusting the rise time, hold time and fall time of the voltage pulse in the set state and the reset state, thereby controlling the threshold voltage value of each of the set operation and the reset operation; including, An operating method of a phase-change memory device integrated with a selection element.

15. In paragraph 10, The operating method of the above-mentioned selective element-integrated phase change memory device is as follows: A step of performing a read operation for reading the crystal state of the phase change layer by applying a voltage pulse having a value between the set operation value of the voltage pulse and the reset operation value; including more, An operating method of a phase-change memory device integrated with a selection element.

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