Interrupt handling method, apparatus and device

Abstract

The present application relates to the technical field of computers. Provided are an interrupt handling method, an apparatus and a device, which are used for solving the problem of system hang or firmware hang caused when a non-fatal error triggers a large amount of interrupts. The method comprises: firmware receives a plurality of interrupts within a first duration, the plurality of interrupts being triggered when a non-fatal error occurs in a hardware layer; on the basis of interrupt information and layered shielding information of the plurality of interrupts, the firmware shields interrupts, after the first duration, of a target shielding object corresponding to the plurality of interrupts, the layered shielding information being used for indicating a plurality of shielding objects, the plurality of shielding objects being obtained by layering interrupt transmission, and the plurality of shielding objects comprising the target shielding object; and the firmware sends to a kernel driver the interrupt information of the plurality of interrupts.

Description

Interrupt processing method, device and equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on July 27, 2023, with application number 202310942590.9 and application name “A method, device and apparatus for handling interruptions”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to an interrupt processing method, apparatus, and device. Background Art

[0003] In a system on a chip (SoC), a large number of non-fatal errors (NFEs) may occur suddenly. These non-fatal errors can include correctable errors (CE) and non-fatal uncorrectable errors. For example, when the memory in the SoC has a large number of faulty areas (for example, multiple pages are abnormal at the same time) and / or the faulty areas are frequently accessed, the memory will experience a large number of non-fatal errors. These non-fatal errors can trigger a large number of interrupts, affecting normal business access and even causing system or firmware hangs.

[0004] Summary of the Invention

[0005] The present application provides an interrupt processing method, apparatus, and device for solving the problem of system or firmware hang caused by non-fatal errors triggering a large number of interrupts.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, an interrupt processing method is provided, which is applied to firmware, the firmware being used to run on a hardware layer, the hardware layer being able to include hardware modules such as processors, accelerators, memories, I / O units, sensors, and buses, the method comprising: the firmware receiving multiple interrupts in a first duration, the multiple interrupts being triggered when non-fatal errors occur in the hardware layer, the non-fatal errors being able to include correctable errors and non-fatal uncorrectable errors; the firmware shielding the interrupts of target shielding objects corresponding to the multiple interrupts after the first duration based on the interrupt information and hierarchical shielding information of the multiple interrupts, the hierarchical shielding information being used to indicate multiple shielding objects, the multiple shielding objects being obtained by hierarchically performing transmission of interrupts, the multiple shielding objects including the target shielding object; the firmware sending the interrupt information of the multiple interrupts to a kernel driver.

[0008] In the above technical solution, when the firmware receives multiple interrupts triggered by non-fatal errors in the first time period, it can send the interrupt information of the multiple interrupts to the kernel driver. At the same time, the firmware can also shield the interrupts of the target shielding objects corresponding to the multiple interrupts after the first time period based on the interrupt information of the multiple interrupts and the hierarchical shielding information. The hierarchical shielding information is used to indicate multiple shielding objects, and the multiple shielding objects are obtained by layering the transmission of interrupts. The hierarchical shielding strategy avoids the situation where a large number of non-fatal errors trigger a large number of interrupts, thereby solving the problem of system hang or firmware hang.

[0009] In a possible implementation of the first aspect, the multiple shielding objects include at least one of the following: a hardware module in the hardware layer, an interrupt line for transmitting interrupts, and an interrupt bit in a status register for storing interrupts. In a possible example, the multiple layers obtained by layering may include a hardware module layer, an interrupt line layer, and an interrupt bit layer. The shielding objects in the hardware module layer may include multiple different hardware modules, for example, the shielding objects in the hardware module layer include a CPU, an accelerator, and a memory. The shielding objects in the interrupt line layer may include multiple different interrupt lines, for example, the shielding objects in the interrupt line layer include multiple interrupt lines identified by different interrupt numbers. The shielding objects in the interrupt bit layer may include different interrupt bit layers, for example, the shielding objects in the interrupt bit layer include different interrupt bits.

[0010] In a possible implementation of the first aspect, the firmware masks the interruptions of the target masking objects corresponding to the multiple interruptions after a first duration based on the interruption information and hierarchical masking information of the multiple interruptions, including: the interruption information of each interruption is used to indicate the masking object corresponding to the interruption; when the multiple interruptions belong to the target masking object and the number of the multiple interruptions reaches a preset threshold corresponding to the target masking object, the firmware masks the interruptions of the target masking object after the first duration. Exemplarily, when the firmware receives an interrupt, the firmware can determine the hardware module, interrupt line and interrupt bit corresponding to the interrupt based on the hardware module identifier, interrupt number and error type in the interrupt information of the interrupt; then, the firmware can obtain different layers according to the layering, and count the number of interrupts corresponding to each hardware module that triggers the interrupt, the number of interrupts corresponding to each interrupt line, and the number of interrupts corresponding to each interrupt bit; when the number of interrupts corresponding to a certain hardware module reaches a preset threshold, the hardware module becomes the target shielding object, and the firmware shields the interrupts of the hardware module after a first time length; when the number of interrupts corresponding to a certain interrupt line reaches a preset threshold, the interrupt line becomes the target shielding object, and the firmware shields the interrupts of the interrupt line after the first time length; when the number of interrupts corresponding to a certain interrupt bit layer reaches a preset threshold, the interrupt bit layer becomes the target shielding object, and the firmware shields the interrupts of the interrupt bit layer after the first time length.

[0011] In a possible implementation of the first aspect, the interrupt information of each interrupt includes at least one of the following: a hardware module identifier, an interrupt line identifier, and an error type of a non-fatal error corresponding to the interrupt bit. The hardware module identifier is used to indicate the hardware module in which the non-fatal error corresponding to the interrupt occurs; the interrupt line identifier is used to indicate the interrupt line that transmits the interrupt, for example, the interrupt line identifier can be an interrupt number. The error type of the non-fatal error corresponding to the interrupt bit can also be referred to as the error type corresponding to the interrupt or the fault type corresponding to the interrupt, which can be used to determine the interrupt bit of the status register storing the interrupt. Exemplarily, the error type can include a single-bit error and a multi-bit error.

[0012] In a possible implementation of the first aspect, the method further includes: when the interrupt information includes the hardware module identifier, the firmware determines the hardware module to which each interrupt belongs based on the hardware module identifier in the interrupt information of each interrupt; and / or, when the interrupt information includes the interrupt line identifier, the firmware determines the interrupt line to which each interrupt belongs based on the interrupt line identifier in the interrupt information of each interrupt; and / or, when the interrupt information includes the error type of the non-fatal error corresponding to the interrupt bit, the firmware determines the interrupt bit to which each interrupt belongs based on the error type in the interrupt information of each interrupt.

[0013] In one possible implementation of the first aspect, the hardware layer includes a first hardware system, the firmware includes first firmware running on the first hardware system, the non-fatal error includes an RSA specification error and / or a security error, and the first firmware is configured to mask shielding objects corresponding to the RSA specification error and / or security error. In this possible implementation, by masking interrupts triggered by RSA specification errors and / or security errors, the first firmware can avoid system or firmware hangs caused by triggering a large number of interrupts.

[0014] In one possible implementation of the first aspect, the hardware layer further includes a second hardware system, the firmware further includes second firmware running on the second hardware system, the non-fatal error includes a non-RSA specification error, and the second firmware is configured to mask a mask object corresponding to the non-RSA specification error. In this possible implementation, by masking interrupts triggered by non-RSA specification errors, the second firmware can avoid system or firmware hangs caused by triggering a large number of interrupts.

[0015] In a possible implementation of the first aspect, for non-RSA specification errors, the method further includes: the second firmware unmasking a masked object from the multiple masked objects after a second delay. In this possible implementation, the second firmware unmasks the masked object from the multiple masked objects after a second delay, thereby avoiding system or firmware hangs caused by interrupts triggered by a large number of non-RSA specification errors while not affecting the subsequent processing of interrupts triggered by non-fatal errors, thereby ensuring user experience.

[0016] In a possible implementation of the first aspect, the unmasking is performed after the last interrupt among the multiple interrupts is processed; or, the unmasking is performed in a polling manner. In the above possible implementation, when the impact of the interrupt after the first duration is large, by performing the unmasking after the last interrupt among the multiple interrupts is processed, the unmasking can be performed as early as possible, thereby reducing the impact of the masked interrupt; when the impact of the interrupt after the first duration is small, performing the unmasking in a polling manner can avoid the interrupt of a masked object after the first duration being blocked for a long time, thereby ensuring the performance of different masked objects.

[0017] In a possible implementation manner of the first aspect, the first firmware communicates with the kernel driver through an Advanced Platform Error Interface (APEI), and the second firmware communicates with the kernel driver through an Inter-Core Error Message (IPEM) interface.

[0018] In a second aspect, an interrupt processing method is provided, which is applied to a kernel driver, wherein the kernel driver is used to run on a hardware layer, and the hardware layer may include hardware modules such as processors, accelerators, memories, I / O units, sensors and buses. The method includes: the kernel driver receives interrupt information of multiple interrupts sent by firmware, the multiple interrupts are received by the firmware in a first time period, and the multiple interrupts are triggered when non-fatal errors occur in the hardware layer; the kernel driver processes the multiple interrupts according to the interrupt information of the multiple interrupts; wherein the target shielding objects corresponding to the multiple interrupts are shielded by the firmware after the first time period, and the firmware is shielded according to the interrupt information of the multiple interrupts and the hierarchical shielding information, the multiple shielding objects are obtained by hierarchically transmitting the interrupts, and the multiple shielding objects include the target shielding object.

[0019] In the above technical solution, when the firmware receives multiple interrupts triggered by non-fatal errors in the first time period, it can send interrupt information of the multiple interrupts to the kernel driver so that the kernel driver can process the multiple interrupts. At the same time, the firmware can also mask the interrupts of the target masking objects corresponding to the multiple interrupts after the first time period based on the interrupt information and hierarchical masking information of the multiple interrupts. The hierarchical masking information is used to indicate multiple masking objects, and the multiple masking objects are obtained by layering the transmission of interrupts. The hierarchical masking strategy avoids the situation where a large number of non-fatal errors trigger a large number of interrupts, thereby solving the problem of system hang or firmware hang.

[0020] In a possible implementation of the second aspect, the multiple shielding objects include at least one of the following: a hardware module in the hardware layer, an interrupt line for transmitting interrupts, and an interrupt bit in a status register for storing interrupts. In a possible example, the multiple layers obtained by layering may include a hardware module layer, an interrupt line layer, and an interrupt bit layer. The shielding objects in the hardware module layer may include multiple different hardware modules, for example, the shielding objects in the hardware module layer include a CPU, an accelerator, and a memory. The shielding objects in the interrupt line layer may include multiple different interrupt lines, for example, the shielding objects in the interrupt line layer include multiple interrupt lines identified by different interrupt numbers.

[0021] In a possible implementation of the second aspect, the interrupt information includes at least one of the following: a hardware module identifier, an interrupt line identifier, and an error type of the non-fatal error corresponding to the interrupt bit. The hardware module identifier is used to indicate the hardware module in which the non-fatal error corresponding to the interrupt occurs; the interrupt line identifier is used to indicate the interrupt line that transmits the interrupt, for example, the interrupt line identifier can be an interrupt number. The error type of the non-fatal error corresponding to the interrupt bit can also be referred to as the error type corresponding to the interrupt or the fault type corresponding to the interrupt, which can be used to determine the interrupt bit of the status register storing the interrupt. Exemplarily, the error type can include a single-bit error and a multi-bit error.

[0022] In a possible implementation of the second aspect, the non-fatal error includes an RSA specification error and / or a security error, and the method further includes: the kernel driver unmasking the masked shielded objects among the multiple masked objects after a second delay. In the above possible implementation, the kernel driver unmasks the masked shielded objects among the multiple masked objects after a second delay, thereby avoiding system or firmware hangs caused by interrupts triggered by a large number of RSA specification errors and / or security errors while not affecting the subsequent processing of interrupts triggered by non-fatal errors, thereby ensuring user experience.

[0023] In a possible implementation of the second aspect, the unmasking is performed after the last interrupt among the multiple interrupts is processed; or, the unmasking is performed in a polling manner. In the above possible implementation, when the impact of the interrupt after the first duration is large, by performing the unmasking after the last interrupt among the multiple interrupts is processed, the unmasking can be performed as early as possible, thereby reducing the impact of the masked interrupt; when the impact of the interrupt after the first duration is small, performing the unmasking in a polling manner can avoid the interrupt of a certain masked object after the first duration being blocked for a long time, thereby ensuring the performance of different masked objects.

[0024] In a possible implementation of the second aspect, the non-fatal error also includes a non-RSA specification error, the firmware includes a first firmware and a second firmware, the first firmware is used to mask interrupts triggered by RSA specification errors and / or security errors, the second firmware is used to mask and unmask interrupts triggered by non-RSA specification errors, the first firmware communicates with the kernel driver through the Advanced Platform Fault Interface APEI, and the second firmware communicates with the kernel driver through the inter-core error message IPEM interface.

[0025] According to a third aspect, an interrupt processing device is provided, which is applied to firmware, and the firmware is used to run on the hardware layer. The device includes: a receiving unit, which is used to receive multiple interrupts in a first time period, and the multiple interrupts are triggered when a non-fatal error occurs in the hardware layer; a processing unit, which is used to mask the interrupts of the target masking objects corresponding to the multiple interrupts after the first time period according to the interrupt information and hierarchical masking information of the multiple interrupts, and the hierarchical masking information is used to indicate multiple masking objects, and the multiple masking objects are obtained by hierarchically transmitting the interrupts, and the multiple masking objects include the target masking object; a sending unit, which is used to send the interrupt information of the multiple interrupts to the kernel driver.

[0026] In a possible implementation manner of the third aspect, the multiple shielding objects include at least one of the following: a hardware module in the hardware layer, an interrupt line for transmitting an interrupt, and an interrupt bit of a status register for storing an interrupt.

[0027] In a possible implementation of the third aspect, the processing unit is also used to: the interruption information of each interruption is used to indicate the shielding object corresponding to the interruption; when the multiple interruptions belong to the target shielding object and the number of the multiple interruptions reaches a preset threshold corresponding to the target shielding object, the interruption of the target shielding object after the first time length is shielded.

[0028] In a possible implementation manner of the third aspect, the interrupt information includes at least one of the following: a hardware module identifier, an interrupt line identifier, and an error type of the non-fatal error corresponding to the interrupt bit.

[0029] In a possible implementation of the third aspect, the processing unit is further used to: when the interrupt information includes the hardware module identifier, determine the hardware module to which each interrupt belongs based on the hardware module identifier in the interrupt information of each interrupt; and / or, when the interrupt information includes the interrupt line identifier, determine the interrupt line to which each interrupt belongs based on the interrupt line identifier in the interrupt information of each interrupt; and / or, when the interrupt information includes the error type of the non-fatal error corresponding to the interrupt bit, determine the interrupt bit to which each interrupt belongs based on the error type in the interrupt information of each interrupt.

[0030] In a possible implementation of the third aspect, the hardware layer includes a first hardware system, the firmware includes a first firmware running on the first hardware system, the non-fatal error includes an RSA specification error and / or a security error, and the first firmware is used to shield a shielding object corresponding to the RSA specification error and / or security error.

[0031] In a possible implementation of the third aspect, the hardware layer also includes a second hardware system, the firmware also includes a second firmware running on the second hardware system, the non-fatal error includes a non-RSA specification error, and the second firmware is used to shield the shielding object corresponding to the non-RSA specification error.

[0032] In a possible implementation manner of the third aspect, for the non-RSA specification error, the processing unit is further configured to: unmask a masked object among the multiple masked objects after a delay of a second time period.

[0033] In a possible implementation of the third aspect, the unmasking is performed after the last interrupt among the multiple interrupts is processed; or, the unmasking is performed in a polling manner.

[0034] In a fourth aspect, an interrupt processing device is provided, which is applied to a kernel driver, which is used to run on a hardware layer. The device includes: a receiving unit, which is used to receive interrupt information of multiple interrupts sent by firmware, and the multiple interrupts are received by the firmware in a first time period, and the multiple interrupts are triggered when non-fatal errors occur in the hardware layer; a processing unit, which is used to process the multiple interrupts according to the interrupt information of the multiple interrupts; wherein the interrupts of the target shielding objects corresponding to the multiple interrupts after the first time period are shielded by the firmware, and the firmware is shielded according to the interrupt information of the multiple interrupts and the hierarchical shielding information. The multiple shielding objects are obtained by layering the transmission of interrupts, and the multiple shielding objects include the target shielding object.

[0035] In a possible implementation manner of the fourth aspect, the multiple shielding objects include at least one of the following: a hardware module in the hardware layer, an interrupt line for transmitting interrupts, and an interrupt bit of a status register for storing interrupts.

[0036] In a possible implementation manner of the fourth aspect, the interrupt information includes at least one of the following: a hardware module identifier, an interrupt line identifier, and an error type of the non-fatal error corresponding to the interrupt bit.

[0037] In a possible implementation manner of the fourth aspect, the non-fatal error includes an RSA specification error and / or a security error, and the processing unit is further configured to: unmask a masked object among the multiple masked objects after a delay of a second time period.

[0038] In a possible implementation of the fourth aspect, the unmasking is performed after the last interrupt among the multiple interrupts is processed; or, the unmasking is performed in a polling manner.

[0039] In a possible implementation of the fourth aspect, the non-fatal error also includes a non-RSA specification error, the firmware includes a first firmware and a second firmware, the first firmware is used to mask interrupts triggered by RSA specification errors and / or security errors, the second firmware is used to mask and unmask interrupts triggered by non-RSA specification errors, the first firmware communicates with the kernel driver through the Advanced Platform Fault Interface APEI, and the second firmware communicates with the kernel driver through the inter-core error message IPEM interface.

[0040] Another aspect of the present application provides an interrupt processing device, which includes a processor and a memory, wherein the memory stores instructions, and the processor executes the instructions in the memory to enable the device to execute the interrupt processing method provided by the first aspect or any possible implementation of the first aspect, the second aspect or any possible implementation of the second aspect.

[0041] Another aspect of the present application provides an interrupt handling device, which includes a hardware layer, and firmware and a kernel driver running on the hardware layer, the firmware including the interrupt handling device provided by the third aspect or any possible implementation of the third aspect, and the kernel driver including the interrupt handling device provided by the fourth aspect or any possible implementation of the fourth aspect.

[0042] In another aspect of the present application, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed by a device, the device executes the interrupt handling method provided by the first aspect or any possible implementation of the first aspect.

[0043] In another aspect of the present application, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed by a device, the device executes the interrupt handling method provided by the second aspect or any possible implementation of the second aspect.

[0044] In another aspect of the present application, a computer program product is provided, which includes: a computer program (also referred to as code, or instructions), which, when executed, enables a computer to execute an interrupt handling method as provided in the first aspect or any possible implementation of the first aspect.

[0045] In another aspect of the present application, a computer program product is provided, which includes: a computer program (also referred to as code, or instructions), which, when executed, enables a computer to execute the interrupt handling method provided in the second aspect or any possible implementation of the second aspect.

[0046] It can be understood that the beneficial effects that can be achieved by any of the interrupt processing devices, interrupt processing equipment, computer-readable storage media and computer program products provided above can correspond to the beneficial effects of the interrupt processing method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic diagram of the structure of the hardware layer of an electronic device provided in an embodiment of the present application;

[0048] FIG2 is a schematic diagram of the structure of a software layer of an electronic device provided in an embodiment of the present application;

[0049] FIG3 is a flow chart of an interrupt handling method provided in an embodiment of the present application;

[0050] FIG4 is a flow chart of another interrupt handling method provided in an embodiment of the present application;

[0051] FIG5 is a schematic diagram of an interrupt processing provided by an embodiment of the present application;

[0052] FIG6 is a schematic diagram of another interrupt processing provided by an embodiment of the present application;

[0053] FIG7 is a schematic structural diagram of an interrupt processing device provided in an embodiment of the present application;

[0054] FIG8 is a schematic structural diagram of another interrupt processing device provided in an embodiment of the present application;

[0055] FIG9 is a schematic structural diagram of an interrupt processing device provided in an embodiment of the present application;

[0056] FIG10 is a schematic diagram of the structure of another interrupt processing device provided in an embodiment of the present application;

[0057] FIG11 is a schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use this description and technology and do not limit the scope of this application.

[0059] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0060] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0061] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or multiple.

[0062] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered a broadly defined electronic communication connection.

[0063] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0064] The technical solution of the present application can be applied to various electronic devices, and can also be applied to chips of electronic devices, for example, the chip can be a system on chip (SoC). The electronic devices may include, but are not limited to: mobile phones, tablet computers, laptop computers, wearable devices, computers, ultra-mobile personal computers (UMPCs), netbooks, camcorders, cameras, in-vehicle devices (e.g., cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), virtual reality (VR) devices, or augmented reality (AR) devices.

[0065] Figure 1 is a schematic diagram of the hardware layer structure of an electronic device provided in an embodiment of the present application. The electronic device may include a memory 101, a processor 102, an input / output (I / O) unit 103, and a bus 104. The memory 101, processor 102, and I / O unit 103 are interconnected via the bus 104.

[0066] The memory 101 can be used to store data, software programs, and modules, and mainly includes a program storage area and a data storage area. The program storage area can store an operating system and applications required for at least one function, such as a sound playback function, an image playback function, etc. The data storage area can store data created based on the use of the electronic device, such as audio data, image data, a phone book, etc. In some feasible embodiments, the memory 101 can include one memory or multiple memories, which can include but are not limited to: random access memory (RAM), double data rate synchronous dynamic random access memory (DDR SRAM) (DDR for short), high bandwidth memory (HBM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc. In addition, the memory may also include: a floppy disk, a hard disk such as a built-in hard disk and a mobile hard disk, a magnetic disk, an optical disk, a magneto-optical disk such as a compact disc read-only memory (CD_ROM), a digital video disc read-only memory (DVD_ROM), or any other form of storage medium known in the technical field.

[0067] The processor 102 is used to control and manage the actions of the electronic device, such as by running or executing software programs and / or modules stored in the memory 101, and calling data stored in the memory 101, to perform various functions of the electronic device and process data, thereby controlling the electronic device as a whole. Optionally, the processor 102 may include one or more processing units, which may include a central processing unit (CPU), an application processor, a general-purpose processor, and an accelerator. The accelerator may include but is not limited to: a digital signal processor (DSP), a network processor (NPU), a graphics processing unit (GPU), an image signal processor (ISP), a matrix calculation unit, a video decoder (VDEC), a video encoder (VENC), a microcontroller or a microprocessor, etc. Furthermore, the processor 102 may also include other hardware circuits or accelerators, such as application-specific integrated circuits, field-programmable gate arrays or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Optionally, the processor 102 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc.

[0068] The I / O unit 103 can be used to implement the input and output functions of the electronic device. In some feasible embodiments, the I / O unit 103 may include an input unit and an output unit. The input unit can be used to receive input digital or character information and generate key signal input related to user settings and function control of the electronic device. Exemplarily, the input unit may include a touch screen and other input devices. The touch screen can collect user touch operations on or near it (such as operations performed by the user using a finger, stylus, or any other suitable object or accessory on or near the touch screen) and drive corresponding connected devices according to a pre-set program. Optionally, other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control buttons, power on / off buttons, etc.), a trackball, a mouse, a joystick, etc. The display unit can be used to display information input by the user or information provided to the user, as well as various menus of the electronic device. In one example, the display unit may include a display screen, which can be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc. Furthermore, the touch screen may cover the display screen. When the touch screen detects a touch operation on or near the touch screen, it transmits the information to the processor 102 to determine the type of touch event. The processor then provides a corresponding visual output on the display screen based on the type of touch event. Although the touch screen and the display screen are used as two independent components to implement the input and output functions of the electronic device above, in some embodiments, the touch screen and the display screen can be integrated to implement the input and output functions of the electronic device.

[0069] The bus 104 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc.

[0070] Furthermore, the electronic device may also include a power supply (eg, a battery) for supplying power to various components. The power supply may be logically connected to the processor 102 via a power management system, thereby managing charging, discharging, and power consumption through the power management system.

[0071] Although not shown, the electronic device may further include a radio frequency (RF) circuit, a sensor component, an audio circuit, a wireless fidelity (WiFi) module, and a Bluetooth module, etc., which are not described in detail in the embodiments of the present application. It will be understood by those skilled in the art that the electronic device structure shown in FIG1 does not constitute a limitation on the electronic device, and may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0072] In one possible embodiment, the hardware layer of the electronic device may include a first hardware system and a second hardware system. The first hardware system may be referred to as a general-purpose hardware system, and the second hardware system may be referred to as a small-core hardware system or a dedicated hardware system. For example, the first hardware system may include one or more processors (e.g., CPUs), accelerators, memory, I / O interfaces, and buses; the second hardware system may include one or more small cores and buses.

[0073] The first hardware system can be used to implement hardware and software integrity design, fault detection, fault logging, and hardware error correction and suppression capabilities. The second hardware system can include an independent power supply and clock domain design, an independent bus design, sensor IP, and dual fault reporting capabilities. Compared to the first hardware system, the second hardware system can provide more secure and reliable fault detection, logging, error correction, and error detection capabilities.

[0074] Figure 2 is a structural diagram of the software layer of an electronic device provided in an embodiment of the present application. The software layer runs on the hardware layer of the electronic device. The software layer may include an EL3 layer and an EL1 layer. The EL3 layer may also be called a firmware layer.

[0075] The EL3 layer may include one or more firmwares. In a possible embodiment, taking the example of an electronic device having a hardware layer including a first hardware system and a second hardware system, the EL3 layer may include a first firmware running on the first hardware system and a second firmware running on the second hardware system, and the first firmware may be a trusted firmware (TF). In a possible example, the first firmware and the EL1 layer may communicate through an advanced platform error interface (APEI), and the second firmware and the EL1 layer may communicate through an inter-processor error message (IPEM) interface.

[0076] The EL1 layer may include one or more of a kernel driver, an operating system (OS), a management framework, operators, and applications. In one possible example, the EL1 layer may include a virtualization / OS framework, a device management framework, and a unified abnormal event reporting channel. It may also include operators or applications related to functions such as node isolation, fault repair / function degradation / plane switching / backup, autonomous driving system intrusion detection, single-machine early warning, and maintenance testing.

[0077] In an embodiment of the present application, the hardware layer can be used to be responsible for fault detection, error correction and suppression, the EL3 layer can be used to provide a unified interrupt fault reporting interface, and is responsible for the interrupt counting and masking functions of the fault, and the EL1 layer can be used to be responsible for aggregating the interrupts reported by EL3 to the fault management framework, and at the same time perform different unmasking operations according to the unmasking strategy.

[0078] It can be understood that the above Figure 2 only takes the example of the hardware layer including the first hardware system and the second hardware system to illustrate the structure of the software layer of the electronic device, and does not constitute a limitation to the embodiments of the present application. The software layer can also include more or fewer software structures than shown in the figure, or combine certain software structures, or arrange different software structures.

[0079] During use, electronic devices often experience a large number of sudden non-fatal errors (NFEs). These non-fatal errors can include correctable errors (CEs) and non-fatal, uncorrectable errors. These non-fatal errors are typically generated by hardware modules within the electronic device or chip, such as a CPU, memory, accelerator, or other components. Exemplarily, the memory can be memory, such as double data rate synchronous dynamic random access memory (DDR SRAM) (DDR) or high bandwidth memory (HBM). Taking memory as an example, the causes of a large number of sudden non-fatal errors are generally twofold: a large fault area (e.g., multiple memory pages experiencing simultaneous faults) and a high access frequency to the fault area. This is primarily determined by the device's business scenario and the memory fault detection (e.g., scrub) cycle. These non-fatal errors can trigger a large number of interrupts, impacting normal business access and even causing system or firmware freezes.

[0080] In the related art, a strategy for implementing statistics and threshold control of correctable errors on hardware modules is provided. Specifically, for the CPU, the correctable errors occurring on all industrial input / output (IIO) submodules and ultra path interconnect (UPI) links are counted. When the counted number reaches the threshold, the corresponding event is triggered. For the IIO submodules, the report can be made according to the system management interrupt (SMI), and for the UPI link, the report can be made according to the correctable system management interrupt (CSMI). For the memory, the correctable error statistics are made according to each bank in the memory, and the interrupt report is triggered by the funnel algorithm. The specific report can be SMI, non-maskable interrupt (NMI) or ERROR_N[0]. The above report is limited to platform use and is not visible to the operating system (OS) and virtual machine monitor (VMM).

[0081] This method achieves error statistics and threshold control through technical hardening, but it lacks flexibility. Furthermore, due to cost considerations, this method is typically only applied to key hardware modules, such as the CPU and memory, rather than hardening error counting and threshold control for all hardware modules. Consequently, this method is ineffective.

[0082] Based on this, an embodiment of the present application provides an interrupt processing method, which can be used to, when a non-fatal error triggers multiple interrupts in a first time period, according to the interrupt information and hierarchical shielding information of the multiple interrupts, shield the interrupts of the target shielding objects corresponding to the multiple interrupts after the first time period, the hierarchical shielding information is used to indicate multiple shielding objects, the hierarchical shielding information is used to indicate multiple shielding objects, the multiple shielding objects are obtained in layers, and the multiple shielding objects include the target shielding object, thereby avoiding the situation where a large number of non-fatal errors trigger a large number of interrupts, that is, suppressing the generation of interrupt storms, and then solving the problem of system hang or firmware hang, while improving the flexibility of interrupt shielding.

[0083] In an embodiment of the present application, an interrupt may refer to a signal used to suspend the execution of the current program by the processor and switch to processing the program corresponding to the new situation. The interrupt may usually be triggered when a hardware module of the device fails or an error occurs, and the hardware module that triggers the interrupt may also be called an interrupt source. An interrupt line may refer to a channel for transmitting an interrupt triggered by an interrupt source to an interrupt controller. Usually, one interrupt source may correspond to multiple interrupt lines. An interrupt bit may also be an interrupt status flag, which is used to indicate the error type corresponding to the error that triggered the interrupt. Usually, one interrupt line may correspond to multiple interrupt bits.

[0084] FIG3 is a schematic diagram of the structure of an interrupt handling method provided in an embodiment of the present application. The method may include the following steps. The method may be applied to an interrupt handling device, wherein the interrupt handling device includes a hardware layer, and firmware and a kernel driver running on the hardware layer. For example, the interrupt handling device may be the electronic device provided above.

[0085] S301: The firmware receives a plurality of interrupts in a first duration, where the plurality of interrupts are triggered when a non-fatal error occurs at the hardware layer.

[0086] The hardware layer includes multiple hardware modules, such as processors, accelerators, memories, I / O units, sensors, and buses. For example, the processors may include central processing units (CPUs), application processors (APPs), and general-purpose processors (GPRSs). The accelerators may include digital signal processors (DSPs), network processors (NPUs), graphics processing units (GPUs), image signal processors (ISPs), matrix computing units (MCUs), video decoders (VDECs), and video encoders (VENCs). The memories may include memory, such as DDR or HBM.

[0087] In addition, the non-fatal error may include a correctable error (CE) error and a non-fatal uncorrectable error. The non-fatal error is divided according to the reliability, availability and serviceability (RSA) specification, and may include an RSA specification error and a non-RSA specification error. The non-fatal error may also include errors divided according to other protocol specifications, such as, the non-fatal error may also include a safety error.

[0088] In a possible embodiment, when multiple non-fatal errors occur in the hardware module in the hardware layer, each of the multiple non-fatal errors will trigger an interrupt, so that the multiple non-fatal errors can trigger multiple interrupts, so that the firmware can receive the multiple interrupts. Among them, the multiple non-fatal errors can be non-fatal errors that occur in the hardware module in the hardware layer within a first time length, and each non-fatal error triggers an interrupt, so that the firmware can receive multiple interrupts within the first time length. The above-mentioned first time length can be pre-set, for example, the first time length can be 5 seconds, 10 seconds or 20 seconds, etc. The embodiment of the present application does not limit the specific value of the first time length.

[0089] S302: The firmware masks the interrupts of the target shielding objects corresponding to the multiple interrupts after the first duration based on the interrupt information and hierarchical shielding information of the multiple interrupts, wherein the hierarchical shielding information is used to indicate multiple shielding objects, which are obtained by hierarchical transmission of the interrupts, and the multiple shielding objects include the target shielding object.

[0090] The interruption information of the multiple interruptions may include the interruption information of each interruption in the multiple interruptions. The interruption information of the multiple interruptions may be obtained by the firmware based on the multiple interruptions. For example, the firmware may parse each received interruption to obtain the corresponding interruption information, or the firmware may obtain the interruption information of each interruption through querying. This embodiment of the present application does not impose specific restrictions on this.

[0091] Optionally, the interrupt information of each interrupt may include at least one of the following: a hardware module identifier, an interrupt line identifier, and an error type of the non-fatal error corresponding to the interrupt. The hardware module identifier is used to indicate the hardware module in which the non-fatal error corresponding to the interrupt occurs; the interrupt line identifier is used to indicate the interrupt line that transmits the interrupt, for example, the interrupt line identifier may be an interrupt number. The error type of the non-fatal error corresponding to the interrupt may also be referred to as the error type corresponding to the interrupt or the fault type corresponding to the interrupt, and may be used to indicate the interrupt bit of the status register storing the interrupt. Exemplarily, the error type may include a single-bit error and a multi-bit error.

[0092] In addition, the multiple layers obtained by the stratification may include one or more of a hardware module layer, an interrupt line layer, and an interrupt bit layer. The multiple shielding objects may include one or more shielding objects in each layer. In a possible example, the multiple layers may include a hardware module layer, an interrupt line layer, and an interrupt bit layer. The shielding objects in the hardware module layer may include multiple different hardware modules, for example, the shielding objects in the hardware module layer include a CPU, an accelerator, and a memory. The shielding objects in the interrupt line layer may include multiple different interrupt lines, for example, the shielding objects in the interrupt line layer include multiple interrupt lines identified by different interrupt numbers. The shielding objects in the interrupt bit layer may include different interrupt bit layers, for example, the shielding objects in the interrupt bit layer include interrupt bits corresponding to different error types.

[0093] In a possible embodiment, the interruption information of each interruption can be used to indicate the shielding object corresponding to the interruption in multiple layers. The firmware shields the interruption of the target shielding object corresponding to the multiple interruptions after the first time length based on the interruption information and layered shielding information of the multiple interruptions. It can include: when the multiple interruptions belong to the target shielding object among the multiple shielding objects, and the number of the multiple interruptions reaches a preset threshold corresponding to the target shielding object, the firmware shields the interruption of the target shielding object after the first time length.

[0094] Exemplarily, when the firmware receives an interrupt, the firmware can determine the hardware module, interrupt line and interrupt bit corresponding to the interrupt based on the hardware module identifier, interrupt number and error type in the interrupt information of the interrupt; then, the firmware can count the number of interrupts corresponding to each hardware module that triggers the interrupt, the number of interrupts corresponding to each interrupt line, and the number of interrupts corresponding to each interrupt bit according to different layers; when the number of interrupts corresponding to a certain hardware module reaches a preset threshold, the hardware module becomes the target shielding object, and the firmware shields the interrupts of the hardware module after the first time length; when the number of interrupts corresponding to a certain interrupt line reaches the preset threshold, the interrupt line becomes the target shielding object, and the firmware shields the interrupts of the interrupt line after the first time length; when the number of interrupts corresponding to a certain interrupt bit reaches the preset threshold, the interrupt bit becomes the target shielding object, and the firmware shields the interrupts of the interrupt bit after the first time length.

[0095] It can be understood that the preset thresholds corresponding to the shielding objects in the multiple layers may be the same or different, and the preset thresholds corresponding to different shielding objects in the same layer may also be the same or different. The specific settings can be made by technical personnel in this field according to actual needs, and the embodiments of the present application do not impose specific restrictions on this.

[0096] S303: The firmware sends the interrupt information of the multiple interrupts to the kernel driver. S303 and S302 may be performed in any order, and FIG3 is taken as an example in which S303 is performed after S302.

[0097] Optionally, the firmware may also send other information about each of the multiple interrupts to the kernel driver. For example, the other information may include the interrupt address and interrupt priority, etc., which is not specifically limited in the embodiments of the present application. The interrupt information and other information of each interrupt may be sent together (i.e., sent once) or separately (i.e., sent multiple times).

[0098] In one possible embodiment, when the firmware receives each of the multiple interrupts, the firmware may also send interrupt information about the interrupt to the kernel driver while counting and masking interrupts as described in S302 above. Optionally, an operating system (OS) may also run on the hardware layer of the interrupt handling device. The firmware may send the interrupt information about the interrupt to the OS, which in turn sends the interrupt information about the interrupt to the kernel driver.

[0099] S304: The kernel driver receives the interrupt information of the multiple interrupts and processes the multiple interrupts.

[0100] In a possible embodiment, for each of the multiple interrupts, when the kernel driver receives the interrupt information of the interrupt sent by the firmware, the kernel driver can process the interrupt according to the interrupt information, and process the next interrupt after the processing is completed, until the multiple interrupts are processed.

[0101] In an embodiment of the present application, when the firmware receives multiple interrupts triggered by non-fatal errors in the first time period, it can send corresponding interrupt information to the kernel driver so that the kernel driver can process the multiple interrupts. At the same time, the firmware can also mask the interrupts of the target masking objects corresponding to the multiple interrupts after the first time period based on the interrupt information and hierarchical masking information of the multiple interrupts. The hierarchical masking information is used to indicate multiple masking objects, and the multiple masking objects are obtained by layering the transmission of interrupts. The multiple masking objects include the target masking object, so that the hierarchical masking strategy avoids the situation where a large number of non-fatal errors trigger a large number of interrupts, thereby solving the problem of system hang or firmware hang, and improving the flexibility of interrupt masking.

[0102] Furthermore, the hardware layer of the interrupt processing device includes a first hardware system, the firmware includes a first firmware running on the first hardware system, the non-fatal error includes an RSA specification error and / or a security error, and the first firmware can be used to shield the shielding object corresponding to the RSA specification error and / or security error. That is, the first firmware can receive multiple interrupts triggered by RSA specification errors and / or security errors, and shield the interrupts of the target shielding objects corresponding to the multiple interrupts based on the interrupt information and layered shielding information of the multiple interrupts. Optionally, the first firmware communicates with the kernel driver through the Advanced Platform Error Interface APEI, so that the first firmware can send interrupt information to the kernel driver through the APEI, and the kernel driver handles the interrupt corresponding to the RSA specification error and / or security error.

[0103] In another possible embodiment, the hardware layer of the interrupt processing device also includes a second hardware system, the firmware also includes a second firmware running on the second hardware system, the non-fatal error includes a non-RSA specification error, and the second firmware is used to shield the shielding object corresponding to the non-RSA specification error. That is, the second firmware can receive multiple interrupts triggered by non-RSA specification errors, and shield the interrupts of the target shielding objects corresponding to the multiple interrupts based on the interrupt information and hierarchical shielding information of the multiple interrupts. Optionally, the second firmware communicates with the kernel driver through the inter-core error message IPEM interface, so that the second firmware can send interrupt information to the kernel driver through the IPEM interface, and the kernel driver handles the interrupt corresponding to the non-RSA specification error.

[0104] Furthermore, as shown in FIG4 , after S304 , the method further includes: S305 a and S305 b .

[0105] S305a: For an RSA specification error, the kernel driver unmasks the masked objects among the multiple masked objects after a second delay. That is, for an interrupt triggered by an RSA specification error, the first firmware masks the multiple masked objects, and the kernel driver unmasks the multiple masked objects.

[0106] Optionally, for a security error, the kernel driver may also unmask a masked object among the multiple masked objects after delaying for a second period of time.

[0107] S305b: For non-RSA standard errors, the second firmware unmasks the masked objects among the multiple masked objects after a second delay. That is, for interrupts triggered by non-RSA standard errors, the second firmware masks and unmasks the multiple masked objects.

[0108] The second duration can be pre-set, for example, the second duration can be 5 minutes, 8 minutes or 10 minutes, etc. The embodiment of the present application does not limit the specific value of the second duration. In addition, the second durations of the delay of shielded objects in different layers during unshielding can be the same or different, and the second durations of the delay of different shielded objects in the same layer can also be the same or different. For example, the second duration of the delay corresponding to the hardware module can be 8 minutes, and the second duration of the delay corresponding to the interrupt line can be 5 minutes; or, the second duration of the delay corresponding to the CPU in the hardware module can be 5 minutes, and the second duration of the delay corresponding to the memory can be 8 minutes.

[0109] In one possible embodiment, when the kernel driver unmasks a masked object, it may delay for a second time period after the last interrupt among multiple interrupts is processed, and then unmask the masked object. For example, when a CPU in a hardware module experiences multiple non-fatal errors within a first time period and triggers multiple interrupts, and the firmware masks the interrupts of the CPU after the first time period, the kernel driver may delay for a second time period after processing the last interrupt among the multiple interrupts triggered by the CPU, and then unmask the CPU.

[0110] In another possible embodiment, when the kernel driver unmasks the masked shielded object, the kernel driver can unmask the masked shielded object in a polling manner. Exemplarily, the firmware sequentially masks the CPU interrupt, the memory interrupt, and the I / O unit interrupt in the hardware module. The kernel driver can unmask the shielded object in the following polling manner, specifically including: unmasking the CPU after the CPU interrupt has been masked for a second time period, unmasking the memory after the memory interrupt has been masked for a second time period, and unmasking the I / O unit after the I / O unit interrupt has been masked for a second time period.

[0111] Optionally, when a masked object among the masked objects in the different layers will cause the interrupt processing device to be unavailable after unmasking, or the interrupt processing device needs to be reset when unmasking, the kernel driver may not unmask the masked object. When a masked object among the masked objects in the different layers will not affect the use of the interrupt processing device after unmasking, or the interrupt processing device does not need to be reset, the kernel driver may unmask the masked object according to the relevant description of unmasking above.

[0112] In an embodiment of the present application, the kernel driver unmasks the masked objects among the multiple masked objects after the second time period, thereby avoiding system or firmware hangs caused by a large number of non-fatal error-triggered interrupts while not affecting the kernel driver's processing of interrupts triggered by later non-fatal errors, thereby ensuring user experience. In addition, in the above possible implementation methods, when the impact of the interrupt after the first time period is large, by performing unmasking after the last interrupt among the multiple interrupts is completed, the masking can be performed as early as possible, thereby reducing the impact of the masked interrupt; when the impact of the interrupt after the first time period is small, performing unmasking in a polling manner can avoid the interrupt of a certain masked object after the first time period from being blocked for a long time, thereby ensuring the performance of different masked objects.

[0113] For ease of understanding, the solutions provided in the embodiments of the present application are illustrated below from different levels and perspectives using Figures 5 and 6.

[0114] In a possible embodiment, as shown in FIG5 , the interrupt processing device includes an EL1 layer and an EL3 layer, the EL1 layer includes an operating system OS and a kernel driver, and the EL3 layer includes a first firmware and a second firmware. For an RSA specification error, the method may include: when an RSA specification error occurs in the hardware layer and triggers an interrupt, the first firmware receives the interrupt triggered by the RSA specification error, and masks the masked objects in different layers according to the hierarchical masking strategy described in S302 above, the hierarchical masking may include masking according to hardware modules, interrupt lines, and interrupt bits; the first firmware sends interrupt information corresponding to the interrupt to the kernel driver through the operating system OS, the kernel driver processes the interrupt and unmasks it according to the unmasking strategy, the unmasking strategy may include unmasking after a certain period of time after the last interrupt is processed, or unmasking in a polling manner. For non-RSA specification errors, the method may include: when a non-RSA specification error occurs in the hardware layer and triggers an interrupt, the second firmware receives the interrupt triggered by the non-RSA specification error, and masks the masked objects in different layers according to the hierarchical masking strategy described in S302 above, and the hierarchical masking may include masking according to hardware modules, interrupt lines and interrupt bits; the second firmware unmasks according to the unmasking strategy, and the unmasking strategy may include unmasking after a certain period of time after the last interrupt processing is completed, or unmasking in a polling manner.

[0115] In another possible embodiment, as shown in Figure 6, the interrupt handling device includes a hardware layer, as well as small core firmware, trusted firmware TF, operating system OS, and kernel drivers running on the hardware layer. The trusted firmware TF includes a monitor and RAS firmware. The kernel driver includes a device management module and various management drivers. The device management module includes a fault distribution driver. Optionally, the interrupt handling device may also include a user-mode driver, which includes a device management interface library.

[0116] For an RSA specification error, the method may include: S1. an RSA specification error source at the hardware layer triggers a serial peripheral interface (SPI) interrupt; S2. when a monitor in the trusted firmware receives the SPI interrupt, submitting a RAS record read to the RAS firmware, so that after the RSA specification error source writes the RAS record, the RAS firmware can read the RAS record, i.e., count the number of RAS specification errors (or triggered interrupts); S3. the RAS firmware generates an APEI table entry (i.e., interrupt information sent via the APEI), where APEI table entry × N represents the generated APEI table entry; S4. a software interrupt notifies the operating system (OS); S5. the operating system (OS) reads the APEI table entry; S6. the operating system (OS) notifies the device management module of the fault (i.e., the RAS specification error); and S7. a fault distribution driver in the device management module distributes the fault to various management drivers, so that the various management drivers perform RAS error processing. The above-mentioned trusted firmware serves as interrupt suppression point 1 and can shield shielded objects in different layers according to the layered shielding strategy; various management drivers serve as interrupt suppression point 2 and can unshield shielded objects in different layers according to the unshielding strategy.

[0117] For non-RSA standard errors, the small core firmware can receive the interrupt triggered by the non-RSA standard error and mask the masked objects in different layers according to the layered masking strategy described in S302 above, and can also unmask them according to the unmasking strategy. For the interrupt that has been received, the small core firmware can also send interrupt information to various management drivers to enable them to handle the interrupt for non-RSA errors. The above-mentioned small core firmware acts as interrupt suppression point 3 and can mask the masked objects in different layers according to the layered masking strategy, and unmask the masked objects in different layers according to the unmasking strategy.

[0118] The RSA standard error source in FIG5 and FIG6 above represents the hardware module where the RSA standard error occurs, and the non-RSA standard error source represents the hardware module where the non-RSA standard error occurs.

[0119] In an embodiment of the present application, when the firmware receives multiple interrupts triggered by non-fatal errors in the first time period, it can send corresponding interrupt information to the kernel driver so that the kernel driver can process the multiple interrupts. At the same time, the firmware can also shield the interrupts of the target shielding objects corresponding to the multiple interrupts after the first time period based on the interrupt information and hierarchical shielding information of the multiple interrupts. The hierarchical shielding information is used to indicate multiple shielding objects, and the multiple shielding objects are obtained in layers, thereby avoiding the situation where a large number of non-fatal errors trigger a large number of interrupts through the hierarchical shielding strategy, thereby solving the problem of system or firmware hanging. In addition, after a certain period of time, the kernel driver can unshield the shielded shielding objects in the shielding objects in the different layers, thereby avoiding the system or firmware hanging due to the interrupts triggered by a large number of non-fatal errors while not affecting the kernel driver's processing of the interrupts triggered by the later non-fatal errors, thereby ensuring the user experience.

[0120] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the interaction between the firmware and the kernel driver. It can be understood that, in order to realize the above functions, the interrupt processing device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0121] The embodiment of the present application can divide the functional modules of the interrupt processing device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above functional modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The following is an example of dividing each functional module according to the corresponding function:

[0122] FIG7 is a schematic diagram of the structure of an interrupt processing device provided in an embodiment of the present application. The interrupt processing device can be applied to firmware, which is configured to run on a hardware layer. The device includes a receiving unit 401, a processing unit 402, and a sending unit 403. The receiving unit 401 is configured to execute S301 in the above-mentioned method embodiment for supporting the device; the processing unit 402 is configured to execute S302 and S305b in the above-mentioned method embodiment for supporting the device, and / or other technical processes described herein; and the sending unit 403 is configured to execute S303 in the above-mentioned method embodiment for supporting the device.

[0123] It can be understood that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and the embodiment of the present application will not be repeated here.

[0124] FIG8 is a schematic diagram of the structure of another interrupt processing device provided in an embodiment of the present application. The interrupt processing device can be applied to a kernel driver that is configured to run at a hardware layer. The device includes a receiving unit 501 and a processing unit 502. The receiving unit 501 is configured to execute S304 of the aforementioned method embodiment supporting the device, and / or other technical processes described herein; the processing unit 502 is configured to execute S305a of the aforementioned method embodiment supporting the device.

[0125] It can be understood that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and the embodiment of the present application will not be repeated here.

[0126] Figure 9 is a schematic diagram of the structure of an interrupt handling device provided in an embodiment of the present application. The interrupt handling device includes a hardware layer, as well as firmware and a kernel driver running on the hardware layer. The hardware layer may include, but is not limited to, memory, a processor, an I / O unit, and a bus. In the interrupt handling device, the firmware can be used to execute the firmware steps of the above method embodiment, and the kernel driver can be used to execute the kernel driver steps of the above method embodiment.

[0127] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0128] In another embodiment of the present application, as shown in FIG10 , an interrupt handling device is further provided. The interrupt handling device includes a processor and a memory, wherein the memory stores instructions, and the processor executes the instructions in the memory to cause the interrupt handling device to execute any of the interrupt handling methods provided above. Optionally, the interrupt handling device may further include an I / O unit and a bus, wherein the processor, the memory, and the I / O unit are coupled via the bus.

[0129] The processor may be a central processing unit, a general-purpose processor, a baseband processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It may implement or execute the various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of this application. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc.

[0130] In another embodiment of the present application, as shown in FIG11 , a chip is further provided, which includes a processor and an interface circuit, wherein the interface circuit is used to support the processor in communicating, so that when the processor runs instructions in the memory, the chip executes the interrupt handling method provided above.

[0131] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another device, or ignoring or not implementing certain features.

[0132] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0133] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0134] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. The readable storage medium may include: a USB flash drive, a mobile hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk, etc., which can store program code. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0135] In another embodiment of the present application, a computer-readable storage medium is also provided, which stores instructions. When a device (which can be a single-chip microcomputer, chip or electronic device, etc.) or a processor executes the steps of the firmware in the above method embodiment.

[0136] In another embodiment of the present application, a computer-readable storage medium is also provided, which stores instructions. When a device (which can be a single-chip microcomputer, chip or electronic device, etc.) or a processor executes the kernel driving steps in the above method embodiment.

[0137] In another embodiment of the present application, a computer program product is provided. The computer program product includes computer-executable instructions. When at least one processor of a device executes the instructions, the device performs the steps of the firmware in the above method embodiment.

[0138] In another embodiment of the present application, a computer program product is provided. The computer program product includes computer-executable instructions. When at least one processor of a device executes the instructions, the device performs the kernel-driven steps in the above method embodiment.

[0139] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An interrupt processing method, characterized in that: Applied in firmware, the firmware is used to run on a hardware layer, the method includes: The firmware receives a plurality of interrupts in a first duration, wherein the plurality of interrupts are triggered when a non-fatal error occurs in the hardware layer; The firmware masks interruptions of target masking objects corresponding to the multiple interruptions after the first duration according to the interruption information and hierarchical masking information of the multiple interruptions, wherein the hierarchical masking information is used to indicate multiple masking objects, the multiple masking objects are obtained by hierarchically performing transmission of interruptions, and the multiple masking objects include the target masking object; The firmware sends interrupt information of the multiple interrupts to a kernel driver.

2. The method according to claim 1, characterized in that The plurality of shielding objects include at least one of the following: a hardware module in the hardware layer, an interrupt line for transmitting an interrupt, and an interrupt bit of a status register for storing an interrupt.

3. The method according to claim 1 or 2, characterized in that: The firmware masks interrupts of target masking objects corresponding to the multiple interrupts after the first duration according to the interrupt information and hierarchical masking information of the multiple interrupts, including: The interrupt information of each interrupt is used to indicate the shielding object corresponding to the interrupt. When the multiple interrupts belong to the target shielding object and the number of the multiple interrupts reaches a preset threshold corresponding to the target shielding object, the firmware shields the interrupt of the target shielding object after the first time length.

4. The method according to claim 3, characterized in that The interrupt information includes at least one of the following: a hardware module identifier, an interrupt line identifier, and an error type of the non-fatal error corresponding to an interrupt bit.

5. The method according to claim 4, characterized in that The method further comprises: When the interrupt information includes the hardware module identifier, the firmware determines the hardware module to which each interrupt belongs according to the hardware module identifier in the interrupt information of each interrupt; and / or, When the interrupt information includes the interrupt line identifier, the firmware determines the interrupt line to which each interrupt belongs according to the interrupt line identifier in the interrupt information of each interrupt; and / or, When the interrupt information includes the error type of the non-fatal error corresponding to the interrupt bit, the firmware determines the interrupt bit to which each interrupt belongs according to the error type in the interrupt information of each interrupt.

6. The method according to any one of claims 1 to 5, characterized in that: The hardware layer includes a first hardware system, the firmware includes a first firmware running on the first hardware system, the non-fatal errors include RSA specification errors and / or security errors, and the first firmware is used to shield shielding objects corresponding to the RSA specification errors and / or security errors.

7. The method according to any one of claims 1 to 6, characterized in that: The hardware layer also includes a second hardware system, the firmware also includes a second firmware running on the second hardware system, the non-fatal error includes a non-RSA standard error, and the second firmware is used to shield a shielding object corresponding to the non-RSA standard error.

8. The method according to claim 7, characterized in that For the non-RSA specification error, the method further includes: The second firmware unshields the shielded shielded objects among the plurality of shielded objects after delaying for a second time period.

9. The method according to claim 8, characterized in that The unmasking is performed after the last interrupt processing of the multiple interrupts is completed; or, the unmasking is performed in a polling manner.

10. An interrupt processing method, characterized in that: Applied in a kernel driver, the kernel driver is used to run on a hardware layer, and the method includes: The kernel driver receives interrupt information of multiple interrupts sent by the firmware, the multiple interrupts are received by the firmware in a first time period, and the multiple interrupts are triggered when a non-fatal error occurs in the hardware layer; The kernel driver processes the multiple interrupts according to the interrupt information of the multiple interrupts; Among them, the target shielding objects corresponding to the multiple interrupts are shielded by the firmware after the first time length, and the firmware is shielded according to the interrupt information and hierarchical shielding information of the multiple interrupts. The multiple shielding objects are obtained by layering the transmission of interrupts, and the multiple shielding objects include the target shielding object.

11. The method according to claim 10, characterized in that The plurality of shielding objects include at least one of the following: a hardware module in the hardware layer, an interrupt line for transmitting an interrupt, and an interrupt bit of a status register for storing an interrupt.

12. The method according to claim 10 or 11, characterized in that: The interrupt information includes at least one of the following: a hardware module identifier, an interrupt line identifier, and an error type of the non-fatal error corresponding to an interrupt bit.

13. The method according to any one of claims 10 to 12, characterized in that: The non-fatal error includes an RSA specification error and / or a security error, and the method further includes: The kernel driver unmasks the masked masked objects among the multiple masked objects after delaying for a second time period.

14. The method according to claim 13, characterized in that The unmasking is performed after the last interrupt processing of the multiple interrupts is completed; or, the unmasking is performed in a polling manner.

15. An interrupt processing device, characterized in that: Applied in firmware, the firmware is used to run on a hardware layer, and the device includes: A receiving unit, configured to receive a plurality of interrupts in a first duration, wherein the plurality of interrupts are triggered when a non-fatal error occurs in the hardware layer; a processing unit, configured to shield the interruption of the target shielding objects corresponding to the multiple interruptions after the first duration according to the interruption information and hierarchical shielding information of the multiple interruptions, wherein the hierarchical shielding information is used to indicate multiple shielding objects, the multiple shielding objects are obtained by hierarchically performing transmission of the interruption, and the multiple shielding objects include the target shielding object; The sending unit is used to send the interrupt information of the multiple interrupts to the kernel driver.

16. The device according to claim 15, characterized in that The plurality of shielding objects include at least one of the following: a hardware module in the hardware layer, an interrupt line for transmitting an interrupt, and an interrupt bit of a status register for storing an interrupt.

17. The device according to claim 15 or 16, characterized in that The processing unit is also used for: The interruption information of each interruption is used to indicate the shielding object corresponding to the interruption. When the multiple interruptions belong to the target shielding object and the number of the multiple interruptions reaches the preset threshold corresponding to the target shielding object, the interruption of the target shielding object after the first duration is shielded.

18. The device according to claim 17, characterized in that The interrupt information includes at least one of the following: a hardware module identifier, an interrupt line identifier, and an error type of the non-fatal error corresponding to an interrupt bit.

19. The device according to claim 18, characterized in that The processing unit is also used for: When the interrupt information includes the hardware module identifier, determining the hardware module to which each interrupt belongs according to the hardware module identifier in the interrupt information of each interrupt; and / or, When the interruption information includes the interruption line identifier, determining the interruption line to which each interruption belongs according to the interruption line identifier in the interruption information of each interruption; and / or, When the interrupt information includes the error type of the non-fatal error corresponding to the interrupt bit, the interrupt bit to which each interrupt belongs is determined according to the error type in the interrupt information of each interrupt.

20. The device according to any one of claims 15 to 19, characterized in that The hardware layer includes a first hardware system, the firmware includes a first firmware running on the first hardware system, the non-fatal errors include RSA specification errors and / or security errors, and the first firmware is used to shield shielding objects corresponding to the RSA specification errors and / or security errors.

21. The device according to any one of claims 15 to 20, characterized in that The hardware layer also includes a second hardware system, the firmware also includes a second firmware running on the second hardware system, the non-fatal error includes a non-RSA standard error, and the second firmware is used to shield a shielding object corresponding to the non-RSA standard error.

22. The device according to claim 21, characterized in that For the non-RSA specification error, the processing unit is further configured to: After a delay of a second time period, the masked masked objects among the plurality of masked objects are unmasked.

23. The device according to claim 22, characterized in that The unmasking is performed after the last interrupt processing of the multiple interrupts is completed; or, the unmasking is performed in a polling manner.

24. An interrupt processing device, characterized in that: Applied to a kernel driver, the kernel driver is used to run on a hardware layer, and the device includes: A receiving unit, configured to receive interrupt information of a plurality of interrupts sent by the firmware, wherein the plurality of interrupts are received by the firmware in a first time period, and the plurality of interrupts are triggered when a non-fatal error occurs in the hardware layer; a processing unit, configured to process the plurality of interruptions according to the interruption information of the plurality of interruptions; Among them, the target shielding objects corresponding to the multiple interrupts are shielded by the firmware after the first time length, and the firmware is shielded according to the interrupt information and hierarchical shielding information of the multiple interrupts. The multiple shielding objects are obtained by layering the transmission of interrupts, and the multiple shielding objects include the target shielding object.

25. The device according to claim 24, characterized in that The plurality of shielding objects include at least one of the following: a hardware module in the hardware layer, an interrupt line for transmitting an interrupt, and an interrupt bit of a status register for storing an interrupt.

26. The device according to claim 24 or 25, characterized in that The interrupt information includes at least one of the following: a hardware module identifier, an interrupt line identifier, and an error type of the non-fatal error corresponding to an interrupt bit.

27. The device according to any one of claims 24 to 26, characterized in that The non-fatal error includes an RSA specification error and / or a security error, and the processing unit is further configured to: After a delay of a second time period, the masked masked objects among the plurality of masked objects are unmasked.

28. The device according to claim 27, characterized in that The unmasking is performed after the last interrupt processing of the multiple interrupts is completed; or, the unmasking is performed in a polling manner.

29. An interrupt processing device, characterized in that: The interrupt processing device includes a hardware layer, and firmware and a kernel driver running on the hardware layer, the firmware includes the interrupt processing device as described in any one of claims 15-23, and the kernel driver includes the interrupt processing device as described in any one of claims 24-28.

30. An interrupt processing device, characterized in that: The interrupt processing device comprises a processor and a memory, wherein instructions are stored in the memory, and the processor runs the instructions in the memory so that the device executes the interrupt processing method according to any one of claims 1 to 14.

31. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed by a device, the device executes the interrupt processing method according to any one of claims 1 to 14.

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