Power amplifier, control method, radio frequency processing system, and signal transmitting device

Abstract

This embodiment provides a power amplifier, a control method, a radio frequency processing system, and a signal transmitting device, applied to the technical field of wireless communications. The power amplifier comprises a gate bias circuit, a drain bias circuit, and a power transistor. The gate bias circuit comprises a first power supply interface and a second power supply interface. There is a voltage difference between a first voltage signal received at the input end of the first power supply interface and a second voltage signal received at the input end of the second power supply interface. The gate of the power transistor is used for receiving a radio frequency signal; a plurality of signal slice identifiers are carried on the radio frequency signal. When a first signal slice identifier carries valid data, the gate of the power transistor is coupled with the output end of the first power supply interface. When the first signal slice carries no valid data or when no radio frequency signal is received, the gate of the power transistor is coupled with the output end of the second power supply interface. According to this embodiment, a gate bias voltage signal is adjusted on the basis of the data volume, thereby greatly reducing power consumption of the power amplifier.

Description

Power amplifier, control method, radio frequency processing system and signal transmitting device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on July 24, 2023, with application number 202310921145.4 and application name “Power Amplifier, Control Method, Radio Frequency Processing System and Signal Transmitter”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of wireless communication technology, and in particular to a power amplifier, a control method, a radio frequency processing system, and a signal transmitting device. Background Art

[0003] The power amplifier includes a gate bias circuit, a drain bias circuit, and at least one power transistor. The gate bias circuit is coupled to the gate of the power transistor to output a gate bias voltage signal. The drain bias circuit is coupled to the drain of the power transistor to output a drain DC signal (e.g., a drain bias voltage signal or a drain bias current signal). The gate bias voltage signal and the drain DC signal control the biasing of the at least one power transistor in an amplifying state. When the power transistor is operating in the amplifying state, the gate of the power transistor receives a first RF signal. The first RF signal carries multiple signal slice symbols. In this case, the gate bias voltage signal controls the conduction of the channel between the source and drain of the power transistor to change the signal power of a second RF signal output through the drain of the power transistor, so that the second RF signal exhibits a gain amplification factor relationship with the first RF signal. In other words, the first RF signal is power amplified to obtain the second RF signal. In actual operation, the amount of data carried by the signal slice symbol varies depending on factors such as the number of users, service interaction type, and network protocol used. Different data amounts result in different signal powers in the first RF signal. Based on the design principles of power amplifiers in practical applications, the signal power of most first RF signals needs to be within the low- to medium-power range of the power amplifier. However, in this low- to medium-power range, the conversion efficiency (i.e., the efficiency of the power amplifier) ​​of the power supplied to the power amplifier (i.e., the power supplied to the drain DC signal) is very low, resulting in significant power waste. Power amplifier power consumption is the largest source of power consumption in wireless communications.

[0004] To reduce the power consumption of the power amplifier, one improvement involves providing a voltage follower circuit within the power amplifier. This circuit adjusts the magnitude of the drain DC signal output by the drain bias circuit based on changes in the output power of the second RF signal. This improves the conversion efficiency of the drain DC signal while still meeting normal power amplification requirements, thereby reducing the power consumption of the power amplifier. However, this approach suffers from high control latency and slow response speed, resulting in limited reductions in power consumption.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a power amplifier, a control method, a radio frequency processing system, and a signal transmitting device, which significantly reduce the power consumption of the power amplifier.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a power amplifier is provided, comprising a gate bias circuit, a drain bias circuit, and at least one power transistor. The drain bias circuit is coupled to the drain of the at least one power transistor. The gate bias circuit comprises a first power supply interface and a second power supply interface. A first voltage signal received at the input end of the first power supply interface and a second voltage signal received at the input end of the second power supply interface have a certain voltage difference. The gate of the at least one power transistor is used to receive a radio frequency signal; the radio frequency signal carries multiple signal slice symbols. When the first signal slice symbol carries valid data, the gate of the at least one power transistor is coupled to the output end of the first power supply interface. When the first signal slice symbol does not carry valid data, or when no radio frequency signal is received, the gate of the at least one power transistor is coupled to the output end of the second power supply interface.

[0009] In an embodiment of the present application, a drain bias circuit outputs a drain DC signal (e.g., a drain bias voltage signal or a drain bias current signal) to the drain of a power transistor. A gate bias circuit outputs a gate bias voltage signal to the gate of the power transistor. The gate bias voltage signal and the drain DC signal control the power transistor to be in an amplification state. When the power transistor is in the amplification state, the gate of the power transistor receives an RF signal, and based on the drain DC signal at the drain of the power transistor, an RF signal can be output from the drain. The RF signal output by the drain and the RF signal received by the gate exhibit a gain amplification relationship, i.e., power amplification. Regardless of whether the power transistor receives an RF signal, a drain DC signal always exists at the drain of the power transistor. The drain DC signal is considered the power supplied to the power transistor. The ratio between the power of the RF signal output from the drain of the power transistor and the supplied power can be considered the efficiency of the power transistor. The higher the efficiency of the power transistor, the higher the utilization rate of the supplied power of the power amplifier. The lower the efficiency of the power transistor, the greater the wasted power consumption of the power amplifier. When the gate of the power transistor does not output an RF signal, or the first signal slice symbol corresponding to the received RF signal does not carry valid data, the power amplifier is in an idle state. In this idle state, the power transistor's efficiency is extremely low, resulting in significant wasted power consumption. A first voltage signal and a second voltage signal are set with a certain voltage difference. When the first voltage signal serves as the gate bias voltage signal, the channel width between the drain and source of the power transistor is set to a first width. When the second voltage signal serves as the gate bias voltage signal, the channel width between the drain and source of the power transistor is set to a second width. The first width is greater than the second width. The larger the channel width of the power transistor, the greater the voltage or current on the drain. In practical applications, when the first signal slice symbol does not carry valid data or when no RF signal is received, the power amplifier is in an idle state. In this case, the voltage or current on the drain of the power transistor can be reduced based on the second voltage signal, thereby reducing drain power consumption. When the first signal slice symbol carries valid data, the voltage or current on the drain of the power transistor can be adjusted based on the first voltage signal to meet normal power amplification requirements of the power amplifier. Through the above operations, the power consumption waste in the idle state can be greatly reduced.

[0010] In one possible implementation, the gate bias circuit further includes a voltage adjustment circuit. The voltage adjustment circuit is configured to adjust the magnitude of the first voltage signal to a first voltage value when the first signal slice symbol carries valid data. The first voltage value corresponds to the data volume range in which the valid data carried by the first signal slice symbol falls. In this embodiment of the present application, when the first signal slice symbol corresponding to the RF signal received by the power transistor carries valid data, it indicates that the power amplifier is operating in a data load state. However, in actual applications, the data volume of each signal slice symbol varies due to factors such as the number of users, service volume, and network protocol. The smaller the data volume of the signal slice symbol, the lower the power of the corresponding RF signal. To avoid significant drain power consumption during power amplification of RF signals with small data volumes, multiple data volume ranges can be divided according to the data volume, and corresponding voltage values ​​can be set for each data volume range. Different voltage values ​​result in different channel conduction widths for the power transistor. With different channel conduction widths, normal power amplification of RF signals of corresponding power is achieved while minimizing drain power consumption. In actual work, the first voltage signal can be adjusted to a first voltage value corresponding to the data volume interval based on the voltage adjustment circuit according to the data volume interval in which the valid data carried by the first signal slice symbol on the received RF signal is located, and the first voltage signal with the first voltage value is output to the gate of the power tube as the gate bias voltage signal.

[0011] In one possible embodiment, the voltage adjustment circuit is a voltage divider circuit. The voltage divider circuit includes multiple voltage divider output terminals. The multiple voltage divider output terminals correspond one-to-one to multiple data volume intervals. Wherein: when the first signal slice symbol carries valid data and the data volume of the valid data is in the first data volume interval, the input terminal of the voltage divider circuit is coupled to the output terminal of the first power supply interface, and the gate of at least one power tube is connected to the first voltage divider output terminal. The first voltage divider output terminal is the voltage divider output terminal corresponding to the first data volume interval. In an embodiment of the present application, the first voltage signal can be divided by the voltage divider circuit to obtain first voltage signals of various voltage values ​​corresponding to different data volume intervals. And the first voltage signals of corresponding voltage values ​​are output respectively through multiple voltage divider output terminals.

[0012] In one possible embodiment, a voltage divider circuit includes a resistor string. The resistor string includes multiple equivalent resistors. The multiple equivalent resistors are connected in series. A first end of the resistor string is an input end of the voltage divider circuit. The multiple equivalent resistors are respectively coupled to multiple voltage divider output ends. In an embodiment of the present application, voltage division can be achieved through a resistor string. The resistor string includes multiple equivalent resistors connected in series. Each equivalent resistor can divide the input voltage. The multiple voltage divider output ends of the voltage divider circuit are coupled to the multiple equivalent resistors, thereby outputting first voltage signals with different voltage values ​​through the multiple voltage divider output ends.

[0013] In one possible implementation, the power amplifier further includes a first gating switch. Multiple voltage divider output terminals are coupled to the gate of at least one power transistor via the first gating switch. In this embodiment of the present application, the first gating switch can be used to achieve gating coupling of the multiple voltage divider output terminals, thereby outputting a first voltage signal of a certain voltage value to the gate of the power transistor.

[0014] In one possible implementation, when the first signal slice symbol does not carry valid data, or when no radio frequency signal is received, the first selection switch is directly connected to the output end of the second power supply interface. In an embodiment of the present application, when the gate of the power tube is coupled to the output end of the second power supply interface, the voltage divider circuit may divide the second voltage signal output by the second power supply interface, thereby raising the voltage of the rear stage of the voltage divider circuit. In this case, in the process of power amplification of the received radio frequency signal, more bottom noise may be generated on the output radio frequency signal, affecting the accuracy of the data, etc. By directly connecting the first selection switch to the second power supply interface, the generation of bottom noise, etc. can be avoided.

[0015] In one possible implementation, the gate bias circuit includes a first power supply. The output of the first power supply is coupled to the input of the first power supply interface. The voltage adjustment circuit includes multiple reference power supplies. The multiple reference outputs corresponding to the multiple reference power supplies are configured to output multiple reference voltages. The multiple reference voltages have different voltage values ​​and correspond to multiple data volume intervals. When the first signal slice symbol carries valid data and the amount of valid data is within the first data volume interval, the voltage input of the first power supply is coupled to the first reference output. The first reference output corresponds to the first data volume interval. In this embodiment of the present application, the first power supply is configured to provide a first voltage signal to the input of the first power supply interface. The first voltage signal output by the first power supply can be adjusted to obtain first voltage signals of different voltage values. In this case, the voltage adjustment circuit may include multiple reference power supplies. The multiple reference power supplies can output multiple reference voltages of different voltage values. Each reference voltage corresponds to a data volume interval of the signal slice symbol. In actual applications, the corresponding reference voltage is selected based on the data volume interval corresponding to the first signal slice symbol. The selected reference voltage is used as the operating voltage of the first power supply to control the first power supply to output a first voltage signal corresponding to a first voltage value. By adjusting the voltage value of the first voltage signal, the power consumption waste of the drain of the power tube is minimized under data load conditions.

[0016] Exemplarily, the first power supply may be a digital-to-analog converter, a charge pump voltage conversion circuit, a voltage source, or a low-dropout linear regulator.

[0017] In one possible implementation, the power amplifier further includes a first gating switch. Multiple reference output terminals corresponding to multiple reference power sources are coupled to a voltage input terminal of the first power source via the first gating switch. In this embodiment of the present application, the first gating switch can be used to select a reference voltage source to obtain reference voltages of different voltage values. The voltage value of the first voltage signal is adjusted based on the reference voltages of different voltage values.

[0018] In one possible implementation, the multiple reference power sources are multiple digital registers. In this embodiment of the present application, a constant reference voltage can be output by the digital registers. The multiple digital registers output reference voltages of different voltage values.

[0019] In a possible implementation, when multiple adjacent signal slice symbols are located in at least two data volume intervals, the second data volume interval is used as the actual data volume interval of the adjacent multiple slice symbols. The second data volume interval is the highest data volume interval among the at least two data volume intervals. In an embodiment of the present application, when switching and selecting first voltage signals of different voltage values, a certain switching time is required. When there are certain requirements for transmission accuracy, the operation of switching the first voltage signal will bring a certain delay, affecting the accuracy of data transmission. At this time, the voltage value of the first voltage signal may not be switched between multiple adjacent (for example, two, three, etc.) signal slice symbols. The voltage value corresponding to the highest data volume interval of multiple adjacent signal slice symbols can be used as the voltage value of the first voltage signal. This voltage value can ensure that multiple adjacent signal slice symbols achieve power amplification with higher accuracy.

[0020] In one possible implementation, the power amplifier further includes a second selection switch. The gate of at least one power transistor is coupled to the output of the first power supply interface, or to the output of the second power supply interface, via the second selection switch. In this embodiment of the present application, the second selection switch can be used to selectively connect to the output of the first power supply interface or the output of the second power supply interface to select between the first voltage signal and the second voltage signal.

[0021] In a second aspect, an embodiment of the present application further provides a control method based on a power amplifier. The power amplifier includes at least one power tube. The method includes: the gate of the at least one power tube is used to receive a radio frequency signal and a gate bias voltage signal. The drain of the at least one power tube receives a drain bias voltage signal. The radio frequency signal carries multiple signal slice symbols. When a first signal slice symbol carries valid data, the gate bias voltage signal is controlled to be a first voltage signal according to a control signal. When the first signal slice symbol does not carry valid data or does not receive a radio frequency signal, the gate bias voltage signal is controlled to be a second voltage signal according to the control signal. There is a certain voltage difference between the first voltage signal and the second voltage signal.

[0022] In one possible implementation, the method further includes: when the first signal slice symbol carries valid data, adjusting the magnitude of the first voltage signal to a first voltage value according to the control signal. The first voltage value corresponds to a data volume interval where the valid data carried by the first signal slice symbol is located.

[0023] In one possible implementation, adjusting the magnitude of the first voltage signal to the first voltage value based on the control signal further includes: when the adjacent plurality of signal slice symbols are located in at least two data volume intervals, setting the voltage value of the first voltage signal to a voltage value corresponding to a second data volume interval. The second data volume interval is a highest data volume interval among the at least two data volume intervals.

[0024] In a possible implementation, the method further includes: inputting a first indication signal, wherein the first indication signal is used to indicate the amount of valid data carried by the plurality of signal slice symbols, and obtaining the control signal according to the first indication signal.

[0025] In a third aspect, embodiments of the present application further provide a radio frequency processing system, comprising a radio frequency generation circuit and a power amplifier as described in the first aspect. The output of the radio frequency generation circuit is coupled to the input of the power amplifier. The radio frequency generation circuit is configured to output a radio frequency signal. The radio frequency signal carries multiple signal slice symbols. The power amplifier is configured to amplify the power of the radio frequency signal.

[0026] In one possible embodiment, the baseband processing circuit includes a controller. The controller is used to output a control signal to the radio frequency processing system. The control signal is used to adjust the magnitude of the gate bias voltage signal of the power tube of the radio frequency processing system. In an embodiment of the present application, when the baseband processing circuit generates a first baseband signal based on a plurality of signal slice symbols, it can generate a control signal and output the control signal to the power amplifier to adjust the gate bias voltage signal. The controller can be an existing component in the baseband processing circuit, and only the relevant software or hardware circuit needs to be modified in the controller to generate the control signal. By generating relevant control signals based on the process of the baseband processing circuit processing the signal slice symbol, the time delay of the control signal in adjusting the gate bias voltage signal can be reduced.

[0027] In one possible implementation, the second output terminal of the baseband processing circuit is coupled to the first input terminal of the RF processing system. The second output terminal of the baseband processing circuit is further configured to output a first indication signal. The first indication signal is configured to indicate the amount of valid data carried by the plurality of signal slice symbols. In an embodiment of the present application, a controller is provided in the power amplifier. The baseband processing circuit may generate the first indication signal during processing of the signal slice symbols. The controller in the power amplifier generates a control signal based on the first indication signal and outputs the control signal to the gate bias circuit to adjust the voltage value of the gate bias voltage signal.

[0028] In a fourth aspect, an embodiment of the present application further provides a chip system comprising at least one processor and at least one interface circuit. The at least one processor and the at least one interface circuit may be interconnected via lines. The processor is used to support the chip system to implement the various functions or steps described in the second aspect above, and the at least one interface circuit may be used to receive signals from other devices (such as communication interfaces, radio frequency processing systems, baseband processing circuits, power amplifiers, antennas, etc.), or to send signals to other devices (such as communication interfaces, radio frequency processing systems, baseband processing circuits, power amplifiers, antennas, etc.). The chip system may include chips and may also include other discrete devices.

[0029] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, the computer-readable storage medium comprising instructions. When the instructions are executed on a processor, the processor executes the control method described in the second aspect above.

[0030] Regarding the technical principles and beneficial effects of the second, third, fourth and fifth aspects, please refer to the relevant description of the first aspect above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic diagram of the structure of a power amplifier;

[0032] FIG2 is a schematic diagram of a working range and amplification gain coefficient of a power amplifier;

[0033] FIG3 is a structural diagram of a transmitting device according to an embodiment of the present application;

[0034] FIG4 is a schematic structural diagram of a radio frequency processing system provided in an embodiment of the present application;

[0035] FIG5 is a schematic structural diagram of a first power amplifier provided in an embodiment of the present application;

[0036] FIG6 is a schematic diagram of efficiency-power variation of a first power amplifier as shown in FIG5 provided in an embodiment of the present application;

[0037] FIG7 is a schematic structural diagram of a second power amplifier provided in an embodiment of the present application;

[0038] FIG8 is a schematic diagram of efficiency-power variation of a second power amplifier as shown in FIG7 provided in an embodiment of the present application;

[0039] FIG9 is a first structural diagram of a third power amplifier provided in an embodiment of the present application;

[0040] FIG10 is a second structural diagram of another third power amplifier provided in an embodiment of the present application;

[0041] FIG11 is a third structural diagram of another third power amplifier provided in an embodiment of the present application;

[0042] FIG12 is a fourth structural diagram of a third power amplifier provided in an embodiment of the present application;

[0043] FIG13 is a fifth structural diagram of a third power amplifier provided in an embodiment of the present application;

[0044] FIG14 is a second structural diagram of another transmitting device provided in an embodiment of the present application;

[0045] FIG15 is a third structural diagram of another transmitting device provided in an embodiment of the present application;

[0046] FIG16 is a fourth structural diagram of another transmitting device provided in an embodiment of the present application;

[0047] FIG17 is a flow chart of a control method provided in an embodiment of the present application;

[0048] FIG18 is a schematic diagram showing a correspondence between a data volume interval and a voltage value of a gate bias voltage signal provided by an embodiment of the present application;

[0049] FIG19 is a schematic diagram showing another correspondence between data volume intervals and voltage values ​​of gate bias voltage signals provided by an embodiment of the present application;

[0050] FIG20 is a schematic structural diagram of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0052] The terms "exemplary" or "for example" in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0053] The terms "coupling" and "connection" involved in the embodiments of this application should be understood in a broad sense. For example, they may refer to a physical direct connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0054] First, some basic concepts involved in this application are explained:

[0055] Power amplifiers: Power amplifiers can be categorized as power tube-type and switching-type amplifiers. Power tube-type amplifiers are further divided into Class A, Class B, Class AB, and Class C. Class A, Class B, and Class AB are linear amplifiers. Class C is nonlinear. Class A amplifiers offer the best linearity and are suitable for amplifying small DC signals. Class B amplifiers operate in a half-cycle configuration. Single-ended Class B amplifiers produce significant nonlinear distortion and are rarely used for RF power amplification. They are typically used for audio signal amplification, using a push-pull configuration of two Class B amplifiers to generate positive and negative half-cycles. Class AB amplifiers are a combination of Class A and Class B amplifiers. Their efficiency and linearity lie between Class A and Class B amplifiers, making them widely used for RF power amplification. Figure 1 shows the basic structure of a single power tube-type amplifier. In the figure, a gate bias circuit P1 is provided at the gate of the power tube M, and a drain bias circuit P2 is provided at the drain of the power tube M. The gate bias circuit P1 and the drain bias circuit P2 control the bias state between the electrodes of the power tube M, so that the power tube M is in a power amplification state. In the power amplification state, the power tube M can amplify the power of the received signal.

[0056] The efficiency of a power amplifier refers to the proportion of input power that can be converted into useful output power. In practical applications, the ratio of the power of the output signal of the power amplifier to the power supplied by the power supply is the efficiency of the power amplifier, represented by η, that is, η = Po / PE * 100%. By definition, power amplifier efficiency = (output power / supply power) × 100%. Taking Figure 1 as an example, the operating efficiency of the power amplifier can be reflected by the operating efficiency provided by the drain bias circuit P2 of the power tube M, that is, the proportion of the drain DC signal provided by the drain bias circuit P2 converted to the RF signal actually output by the power amplifier. The operating efficiency of the power amplifier will decrease as the output power decreases. The output power of the power amplifier is positively correlated with the input power of the power amplifier. The input power of the power amplifier is the power of the RF signal received by the gate of the power tube M as shown in Figure 1.

[0057] Power Back-off of a Power Amplifier: Figure 2 shows a schematic diagram of the power amplification of a single power amplifier. As can be seen, a power amplifier has a certain linear operating power range. Within this linear operating power range, the gain ratio between the input power and output power of the power amplifier is linear (i.e., a proportional, constant gain ratio). However, when the input power of the power amplifier exceeds this linear operating power range, the gain ratio between the input power and output power becomes nonlinear. Even when the input power reaches the power amplifier's saturation power range, the output power no longer increases with increasing input power. To ensure linear amplification of the RF signal output by the power amplifier, power back-off is required (i.e., backing off a certain amount from the maximum operating power point of the power amplifier). The RF signal received by the power amplifier is a modulated signal obtained by modulating data information onto a carrier signal. The amount of power back-off is related to the peak-to-average power ratio (PAPR) of the modulated signal. In wireless communications, the RF signal carries the data signal to be communicated. The greater the amount of data carried by the RF signal, the greater the power of the RF signal received by the power transistor M.

[0058] Quiescent current refers to the current flowing through an electronic device when there is no signal input, that is, the current consumed by the electronic device itself when it is not affected by external factors.

[0059] An embodiment of the present application provides a signal transmission device. As shown in Figure 3, the signal transmission device 1000 includes a baseband processing circuit 100 and a radio frequency processing system 200. A first output terminal of the baseband processing circuit 100 is coupled to a first input terminal of the radio frequency processing system 200. The baseband processing circuit 100 is configured to carry data information in the form of signal slice symbols on a first baseband signal and transmit the first baseband signal to the radio frequency processing system 200 via the first output terminal of the baseband processing circuit 100. The radio frequency processing system 200 is configured to generate a radio frequency signal based on the first baseband signal and transmit the radio frequency signal. The radio frequency signal carries multiple signal slice symbols.

[0060] As shown in Figure 4, the RF processing system 200 includes an RF generation circuit 10 and a power amplifier 20. The RF generation circuit 10 is configured to generate a first RF signal based on a first baseband signal. The first RF signal carries multiple signal slice symbols. The power amplifier 20 is configured to derive a second RF signal from the first RF signal. The second RF signal carries multiple signal slice symbols, and the signal power of the second RF signal has a gain-amplified relationship with the signal power of the first RF signal. In this embodiment of the present application, the RF generation circuit 10 processes the lower-frequency first baseband signal to generate a higher-frequency first RF signal. To ensure the quality of wireless communication, the power amplifier 20 includes at least one power transistor M. This at least one power transistor M generates a second RF signal with higher signal power based on the first RF signal. The RF processing system 200 transmits the second RF signal to perform wireless communication. During wireless communication, the amount of data on the first baseband signal is affected by factors such as time, service scenario, and the number of current users. The amount of data on the first baseband signal varies at different times. Similarly, the signal power of the first RF signal also varies with the amount of data. However, as shown in FIG1 , the drain bias circuit P2 outputs a constant drain DC signal (which can be a drain bias voltage signal or a drain bias current signal) to provide supply power to the power amplifier 20. The power tube M of the power amplifier 20 generates a second RF signal of corresponding signal power based on the drain DC signal as the supply power according to the signal power of the first RF signal received by the gate. In the design of the power amplifier 20, in order to ensure the signal power linearity of the second RF signal, the bandwidth and back-off amount of the power amplifier 20, etc., it is necessary to set the linear operating range of the power amplifier 20 as large as possible as shown in FIG2 , and make the signal power of the received first RF signal (i.e., the input power in FIG2 ) be located in the medium power region and low power region of the linear operating range under the data information of most services. For example, the amount of service data corresponds more to the area below the midpoint A of the linear operating range (i.e., the service load is 50%). In this case, when the power amplifier 20 is in an idle state (i.e., the signal slice symbol on the first RF signal does not carry valid data, or the power amplifier 20 is not receiving the first RF signal), and the data volume of the signal slice symbol on the first RF signal is small (e.g., less than 50% traffic load), the at least one power transistor M in the power amplifier 20 does not efficiently utilize the power supplied by the drain bias circuit P2, resulting in significant power waste. The power consumption of the power amplifier 20 is the main source of power consumption for the entire RF processing system 200. As wireless technology advances, the frequency bands of the first RF signal and the second RF signal are also increasing, and the power consumption problem of the power amplifier 20 is becoming increasingly serious.

[0061] In order to reduce the power consumption of the power amplifier 20, in some possible embodiments, the power amplifier 20 shown in Figure 4 can be a first power amplifier. As shown in Figure 5, the first power amplifier 20A includes a main amplifier circuit 21A and at least one slave amplifier circuit 22A. The main amplifier circuit 21A and the at least one slave amplifier circuit 22A form a Doherty structure amplifier through multiple impedance transformation lines ZL. Among them, the main amplifier circuit 21A is a class AB power amplifier. The at least one slave amplifier circuit 22A is typically a class C power amplifier. Depending on the signal power level of the received first RF signal, different numbers of amplifier circuits are turned on to achieve power amplification. Load pull is achieved through the impedance transformation line ZL to synthesize the RF signals output by different numbers of amplifier circuits to obtain a second RF signal. Figure 6 is a schematic diagram of the relationship between the power and efficiency of the second RF signal of the first power amplifier 20A. As shown in Figure 6, the first power amplifier 20A is taken as an example, including one main amplifier circuit 21A and two slave amplifier circuits 22A. When the signal power of the first or second RF signal is within the low-power range of the linear operating range of the first power amplifier 20A, the main amplifier circuit 21A of the first power amplifier 20A is turned on to generate the second RF signal based on the first RF signal. At the power saturation point in the low-power range, the first power amplifier 20A is guaranteed to have high efficiency, thereby reducing the power consumption of the first power amplifier 20A in the low-power range. When the signal power of the first or second RF signal is within the mid-power range of the linear operating range of the first power amplifier, the main amplifier circuit 21A and a slave amplifier circuit 22A of the first power amplifier 20A are turned on, and both amplifier circuits generate corresponding RF signals based on the first RF signal. When the two amplifier circuits are turned on, as their voltages and currents change, load pulling is achieved through the impedance transformation line ZL, thereby synthesizing the second RF signal. Similarly, at the power saturation point in the mid-power range, the first power amplifier 20A is guaranteed to have high efficiency. When the signal power of the first RF signal and the second RF signal is in the high power range of the linear operating range of the first power amplifier, the main amplifier circuit 21A and the two slave amplifier circuits 22A of the first power amplifier 20A are all turned on. When the three amplifier circuits are turned on, as the voltage and current of each other change, load pulling is also achieved through the impedance transformation line ZL, thereby synthesizing a high-power second RF signal. At the power saturation point in the high power range, high efficiency can also be maintained. In an embodiment of the present application, the first power amplifier 20A is obtained based on the Doherty structure, so that it can have high efficiency in different power ranges to avoid waste of power consumption. However, if you want to further reduce power consumption in the low-power linear operating range, you need to increase the number of slave amplifier circuits 22A as much as possible.However, as the number of slave amplifier circuits 22A increases, the design complexity, device area, and device cost of the first power amplifier 20A also increase significantly. Furthermore, if the number of slave amplifier circuits 22A increases excessively (e.g., if there are more than three slave amplifier circuits 22A), the gain factor of the first power amplifier 20A (i.e., the power amplification ratio between the second RF signal and the first RF signal) will also decrease significantly. In summary, while the Doherty-based first power amplifier 20A can reduce power consumption in the low-power range to a certain extent, the reduction in power consumption in the low-power range is limited, and the solution is difficult and complex to implement.

[0062] In some possible implementations, the power amplifier 20 shown in FIG4 may be a second power amplifier. As shown in FIG7 , the second power amplifier 20B includes at least one power transistor M, a gate bias circuit P1, a drain bias circuit P2, and a voltage follower (avarage power tracking) circuit T1. The output end of the gate bias circuit P1 is coupled to the gate of at least one power transistor M. The output end of the voltage follower circuit T1 is coupled to the input end of the drain bias circuit P2. The output end of the drain bias circuit P2 is coupled to the drain of at least one power transistor M. Exemplarily, as shown in FIG7 , VDD comes from an external power supply of the second power amplifier 20B or a secondary power supply within the second power amplifier 20B (i.e., a power supply that converts an external power supply within the second power amplifier 20B). The voltage follower circuit T1 controls the voltage output to the input end of the drain bias circuit P2 based on the average output power of the second RF signal output by the second power amplifier 20B. In some examples, a detection feedback circuit can be coupled to the output end of the second power amplifier 20B, and the average output power of the second RF signal can be obtained through the detection feedback circuit, and a voltage control signal is generated to the voltage follower circuit T1. The magnitude of the drain DC signal output by the drain bias circuit P2 is controlled by the voltage follower circuit T1. In an embodiment of the present application, as shown in Figure 8, lines ①, line ②, line ③, line ④ and line ⑤ are schematic diagrams of the relationship between the signal power of the second RF signal and the efficiency of the second power amplifier 20B under multiple drain DC signals from large to small. It can be seen from Figure 8 that when the signal power of the second RF signal is at the signal power point B, as the drain DC signal decreases, the efficiency of the second power amplifier 20B increases, thereby achieving the purpose of reducing power consumption. However, in the embodiment shown in Figure 7, there will be an equivalent capacitor at the power supply interface of the second power amplifier 20B, thereby presenting a capacitive load. During the power supply process, the equivalent capacitor will exhibit characteristics such as charging or discharging, which will affect the response speed of the power supply. Therefore, in the process of controlling the gate DC signal based on the voltage follower circuit T1, due to the limited response speed when adjusting the VDD voltage, the voltage follower circuit T1 can only perform feedback adjustment at a relatively slow speed, making it difficult to achieve accurate and fast average power tracking.

[0063] In some possible embodiments, the power amplifier 20 shown in FIG4 may be a third power amplifier. As shown in FIG9 , the third power amplifier 20C includes a gate bias circuit P1, a drain bias circuit P2, and at least one power transistor M. The drain bias circuit P2 is coupled to the drain of the at least one power transistor M. The gate bias circuit P1 includes a first power supply interface P11 and a second power supply interface P12. The first voltage signal received by the first power supply interface P11 is greater than the second voltage signal received by the second power supply interface P12. The gate of the at least one power transistor M is used to receive a first RF signal; the first RF signal carries multiple signal slice symbols. When the first signal slice symbol carries valid data, the gate of the at least one power transistor M is coupled to the first power supply interface P11. When the first signal slice symbol does not carry valid data, or when the first RF signal is not received, the gate of the at least one power transistor M is coupled to the output end of the second power supply interface P12.

[0064] For example, as shown in FIG9 , in a wireless communication application, the baseband processing circuit 100 slices the wireless communication interaction data based on at least one of the following factors: the number of users, the amount of service interaction data, and the network protocol used, and generates a first baseband signal carrying a signal slice symbol. The RF generation circuit 10 modulates the first baseband signal to obtain a first RF signal. The first RF signal also carries multiple signal slice symbols. The amount of data on each signal slice symbol may be the same or different. Furthermore, depending on the modulation method, the RF generation circuit 10 may not output the first RF signal when there are no signal slice symbols on the first baseband signal. For example, when modulating the first baseband signal into the first RF signal using amplitude shift keying (ASK) modulation, if the baseband processing circuit 100 does not output the first baseband signal carrying the signal slice symbol, the RF generation circuit 10 may output a RF signal with a signal amplitude of zero (i.e., not output the first RF signal). When the first signal slice symbol does not carry valid data, or the third power amplifier 20C does not receive the first RF signal, the third power amplifier 20C does not need to perform actual power amplification. This state can be referred to as the idle state of the third power amplifier 20C. When the third power amplifier 20C is in the idle state, the current flowing through the drain of at least one power tube M is the static bias current. The larger the static bias current of the drain of the power tube M, the higher the power consumption of the third power amplifier 20C. In the idle state, the power consumption of the third power amplifier 20C is the highest. However, in the process of power amplification of the first RF signal, the existing technology cannot accurately manage the idle state generated by the short period of time between multiple signal slice symbols. In an embodiment of the present application, a first power supply interface P11 and a second power supply interface P12 are provided in the gate bias circuit P1. A first voltage signal is received through the first power supply interface P11. A second voltage signal is received through the second power supply interface P12. The first voltage signal is greater than the second voltage signal. When the first signal slice symbol carries valid data, it indicates that the third power amplifier 20C needs to perform normal power amplification and couple the gate of at least one power transistor M to the output of the first power supply interface P11 to receive the first voltage signal. When the first signal slice symbol does not carry valid data or does not receive the first RF signal, the third power amplifier 20C is in an idle state and couples the gate of at least one power transistor M to the output of the second power supply interface P12.

[0065] In some examples, at least one power transistor M may be an enhancement-mode transistor or a depletion-mode transistor. Furthermore, the enhancement-mode transistor or the depletion-mode transistor may be a P-type metal-oxide-semiconductor (PMOS) transistor or an N-type metal-oxide-semiconductor (NMOS) transistor, respectively. In some possible examples, depending on the control type of at least one power transistor M, it may be classified as a voltage-controlled voltage-type amplifier power transistor or a voltage-controlled current-type amplifier power transistor. A voltage-controlled voltage-type amplifier power transistor refers to a power transistor M that controls the voltage between the drain and source of the power transistor M based on the gate voltage. A voltage-controlled current-type power transistor refers to a power transistor M that controls the current between the drain and source of the power transistor M based on the gate voltage. In some examples, at least one power transistor M may be based on gallium nitride (GaN) material, gallium arsenide (GaAS) material, or silicon (Si)-based material. In some examples, the first voltage signal and the second voltage signal may be positive or negative voltages depending on the actual transistor type of the at least one power transistor M (e.g., a P-type enhancement-type transistor, a P-type depletion-type transistor, an N-type enhancement-type transistor, an N-type depletion-type transistor, etc.). Furthermore, the first voltage signal may be greater than the second voltage signal, or the first voltage signal may be less than the second voltage signal.

[0066] Taking at least one power transistor M as a GaN-based P-type depletion-mode transistor as an example: when the gate of at least one power transistor M receives a negative voltage, the channel between the drain and source of the power transistor M is conductive. The larger the negative voltage (i.e., the closer it is to zero voltage), the wider the channel width between the drain and source of the power transistor M is, resulting in a larger current (or voltage) between the drain and source. In this case, the first voltage signal corresponding to the data load state is greater than the second voltage signal corresponding to the idle state. Taking at least one power transistor M as an N-type enhancement-mode transistor based on Si or GaN as an example: when the gate of at least one power transistor M receives a positive voltage, the channel between the drain and source of the power transistor M is conductive. The larger the positive voltage (i.e., greater than zero voltage), the wider the channel width between the drain and source of the power transistor M is, resulting in a larger current (or voltage) between the drain and source. In this case, the first voltage signal corresponding to the data load state is greater than the second voltage signal corresponding to the idle state.

[0067] In the embodiment of the present application, a certain voltage difference exists between the first voltage signal and the second voltage signal. When the third power amplifier 20C is in an idle state, the second voltage signal is used as the gate bias voltage signal for at least one power transistor M to reduce the channel conduction width between the drain and source of the power transistor M, thereby reducing the static bias DC signal of the power transistor M, thereby reducing power consumption in the idle state. The static bias DC signal can be a static bias current signal or a static bias voltage signal. When the third power amplifier 20C is in a data load state, the first voltage signal is used as the gate bias voltage signal for at least one power transistor M to increase the channel conduction width between the drain and source of the power transistor M, thereby increasing the operating bias DC signal of the power transistor M to meet normal power amplification requirements.

[0068] 9 , the third power amplifier 20C further includes a second selection switch S2 . The gate of at least one power transistor M is coupled to the output of the first power supply interface P11 or the output of the second power supply interface P12 via the second selection switch S2 .

[0069] In some possible implementations, the first voltage signal and the second voltage signal are external voltages received by the third power amplifier 20C. In this case, the first power supply interface P11 is coupled to the external power supply of the third power amplifier 20C to receive the first voltage signal; and / or the second power supply interface P12 is coupled to the external power supply of the third power amplifier 20C to receive the second voltage signal.

[0070] In some possible implementations, the first voltage signal and the second voltage signal are secondary power supplies generated internally by the third power amplifier 20C. In this case, as shown in FIG10 , the gate bias circuit P1 further includes a first power supply P13 and a second power supply P14. The output end of the first power supply P13 is coupled to the input end of the first power supply interface P11. The first power supply P13 is used to output the first voltage signal. The output end of the second power supply P14 is coupled to the input end of the second power supply interface P12. In some examples, the first power supply P13 and the second power supply P14 can be digital-to-analog converters (DACs). The first voltage signal and the second voltage signal are generated as positive or negative voltages by the DACs. In some examples, the first power supply P13 and the second power supply P14 can also be charge pump voltage conversion circuits, voltage sources, or low dropout regulators (LDOs).

[0071] In some possible implementations, when the third power amplifier 20C is in a data-loaded state, the voltage value of the first voltage signal can be adjusted based on the data volume of the current first signal slice symbol to reduce the power consumption of the third power amplifier 20C in this data-loaded state. In this case, the gate bias circuit P1 also includes a voltage adjustment circuit. The voltage adjustment circuit is configured to adjust the magnitude of the first voltage signal to a first voltage value when the first signal slice symbol carries valid data; the first voltage value corresponds to the data volume range of the valid data carried by the first signal slice symbol.

[0072] In an embodiment of the present application, the data volume of the signal slice symbol can be divided into multiple data volume intervals according to the data load state, and a first voltage signal with a corresponding voltage value is set for each data volume interval. The first voltage signal corresponding to a larger data volume interval can increase the channel conduction width between the drain and source of the power transistor M. The increase in the channel conduction width also increases the drain DC signal, thereby meeting the power amplification requirements under larger data volumes.

[0073] In one possible embodiment, the voltage output by the first power supply interface can be adjusted to obtain a first voltage signal of different voltage magnitudes. As shown in Figures 11 and 12, the voltage adjustment circuit is a voltage divider circuit D1. The voltage divider circuit D1 includes multiple voltage divider output terminals Dout. The multiple voltage divider output terminals Dout correspond one-to-one to multiple data volume intervals. Wherein: when the first signal slice symbol carries valid data and the data volume of the valid data is in the first data volume interval, the input terminal of the voltage divider circuit D1 is coupled to the first power supply interface P11, and the gate of at least one power tube M is connected to the first voltage divider output terminal; the first voltage divider output terminal is the voltage divider output terminal Dout corresponding to the first data volume interval. In some examples, as shown in Figure 11, the voltage divider circuit D1 can be coupled between the second selection switch S2 and the output terminal of the first power supply interface P12. In some examples, as shown in Figure 12, the voltage divider circuit D1 can be coupled to the subsequent stage of the second selection switch S2. In the embodiment of the present application, the gate bias voltage signal of the power tube M is adjusted at the signal slice symbol level to ensure that the efficiency of the third power amplifier 20C is dynamically improved as much as possible while meeting the normal power amplification of the third power amplifier 20C, and the power consumption caused by the drain DC signal is reduced.

[0074] For example, as shown in FIG12 , the voltage divider circuit D1 includes a resistor string RL. The resistor string RL includes multiple equivalent resistors R. The multiple equivalent resistors R are connected in series. A first end of the resistor string RL is an input end of the voltage divider circuit D1. A second end of the resistor string RL is grounded. The multiple equivalent resistors R are respectively coupled to multiple voltage divider output ends Dout. By connecting multiple equivalent resistors R in series, voltage division can be performed to obtain multiple different voltage values. The voltage divider output end Dout can be coupled to the first end or the second end of the equivalent resistor R. Each voltage value can correspond to a data volume interval.

[0075] Exemplarily, each equivalent resistor R may include one or more resistors. When the equivalent resistor R includes multiple resistors, the multiple resistors may be connected in series and / or in parallel.

[0076] For example, in an embodiment where the first voltage signal is greater than the second voltage signal, the greater the voltage value of the first voltage signal, the greater the channel conduction width between the drain and source of the power tube M. In this case, the closer the voltage divider output terminal Dout is to the first end of the resistor string RL (i.e., the output end of the first power supply interface P11), the larger the corresponding data volume interval. The closer the voltage divider output terminal Dout is to the second end of the resistor string RL (i.e., the ground end), the smaller the corresponding data volume interval.

[0077] For example, in an embodiment where the first voltage signal is smaller than the second voltage signal, the smaller the first voltage signal, the larger the channel conduction width between the drain and source of the power transistor M. In this case, the closer the voltage divider output terminal Dout is to the first end of the resistor string RL (i.e., the output end of the first power supply interface P11), the smaller the corresponding data volume interval. The closer the voltage divider output terminal Dout is to the second end of the resistor string RL (i.e., the ground end), the larger the corresponding data volume interval.

[0078] In this embodiment of the present application, when the data volume of the first signal slice symbol exceeds a preset maximum data volume, the first voltage signal corresponding to the maximum data volume interval is selected as the gate bias voltage signal to ensure power amplification. Similarly, as the data volume of the first signal slice symbol decreases, the first voltage signal corresponding to the smaller data volume interval is selected as the gate bias voltage signal to reduce the channel conduction width between the drain and source of the power transistor M, thereby achieving real-time dynamic reduction in the power consumption of the third power amplifier 20C.

[0079] In some possible implementations, as shown in FIG12 , the third power amplifier 20C further includes a first gate switch S1. Multiple voltage-dividing output terminals Dout are coupled to the gate of at least one power transistor M via the first gate switch S1. The first gate switch S1 can be used to select and switch first voltage signals of different voltage values.

[0080] In some possible implementations, when the first signal slice symbol does not carry valid data or the first RF signal is not received, the first selection switch S1 is directly connected to the output end of the second power supply interface P12. In an embodiment of the present application, as shown in FIG12 , when the first signal slice symbol does not carry valid data or the first RF signal is not received, the third power amplifier 20C is in an idle state. At this time, the gate of the power transistor M needs to receive the second voltage signal. However, the voltage divider circuit D is coupled between the output end of the second power supply interface P12 and the gate of the power transistor M. If the voltage divider circuit D divides the second voltage signal, the voltage of the subsequent stage of the voltage divider circuit D will be increased, thereby affecting the power transistor M and possibly generating more bottom noise on the generated second RF signal, affecting the data accuracy of the second RF signal. To this end, when the third power amplifier 20C is in an idle state, the first selection switch S1 can be connected to the voltage divider output end Dout corresponding to the first end of the resistor string RL to directly connect to the output end of the second power supply interface P12.

[0081] In some possible implementations, the magnitude of the first voltage signal received by the input of the first power supply interface can be adjusted to obtain first voltage signals of varying magnitudes. As shown in Figure 13, the voltage adjustment circuit includes multiple reference power sources D2. Multiple reference outputs corresponding to the multiple reference power sources D2 are configured to output multiple reference voltages. The multiple reference voltages have different voltage values ​​and correspond to multiple data volume intervals. When the first signal slice symbol carries valid data and the amount of valid data is within the first data volume interval, the voltage input of the first power source is coupled to the first reference output. The first reference output corresponds to the first data volume interval. In this embodiment of the present application, the multiple reference power sources D2 can output reference voltages of varying magnitudes, each corresponding to a different data volume interval of the signal slice symbol. The reference voltages of varying magnitudes are output to the first power source P13 as its operating voltage. Driven by the varying operating voltages, the first power source P13 can output first voltage signals of varying magnitudes.

[0082] For example, taking the first power supply P13 as a DAC, under different operating voltages, the first power supply can convert and generate first voltage signals of different voltage values. For example, as shown in FIG13 , different reference power supplies D2 can be selected and switched using a first selection switch S1. For example, the reference power supply D2 can be a digital register.

[0083] Regarding the correspondence between the first voltage signal and the data volume interval in the embodiment shown in FIG. 13 , reference may be made to the relevant description in the embodiment shown in FIG. 12 , which will not be repeated here.

[0084] In some possible implementations, the RF transmitting apparatus 1000 further includes a controller. The controller implements the operations of selecting and switching the first voltage signal and the second voltage signal in the data load state and the idle state in the embodiments of Figures 9 and 10. The controller may also implement the operations of adjusting the voltage value of the first voltage signal in the data load state in the embodiments of Figures 11, 12, and 13.

[0085] In some examples, the controller may be a first controller provided in the third power amplifier 20C. As shown in FIG14 , the third power amplifier 20C includes a first controller 21C. The second output terminal of the baseband processing circuit 100 is coupled to the input terminal of the first controller 21C. The output terminal of the first controller 21C is coupled to the controlled terminal of the gate bias circuit P1. The baseband processing circuit 100 outputs a first indication signal to the first controller 21C. The first indication signal is used to indicate the amount of valid data carried by the multiple signal slice symbols. Based on the first indication signal, the first controller 21C sends a control signal to the gate bias circuit P1 to select and switch between the first voltage signal and the second voltage signal, and to adjust the voltage value of the first voltage signal.

[0086] In some examples, the controller may be a second controller provided in the baseband processing circuit 100. As shown in FIG15 , the second controller C1 sends a control signal to the gate bias circuit P1 of the third power amplifier 20C to select and switch between the first voltage signal and the second voltage signal, and to adjust the voltage value of the first voltage signal.

[0087] In some possible implementations, the signal transmitting device 1000 may include multiple RF processing systems 200. The multiple RF processing systems 200 may receive the same first RF signal or different first RF signals. In some examples, when the multiple RF processing systems 200 receive the same first RF signal, the multiple RF processing systems 200 may implement power amplification based on independent gate bias circuits P1. In some examples, as shown in FIG16 , the same gate bias circuit P1 may be reused between the multiple RF processing systems 200. Similarly, when the RF processing system 200 includes a second controller C1 as shown in FIG15 , the multiple RF processing systems 200 may also reuse the same second controller C1.

[0088] In some possible implementations, the present application does not limit the type of the third power amplifier 20C formed by the at least one power transistor M. For example, the third power amplifier 20C may be a class AB power amplifier, a power amplifier based on a Doherty architecture, a power amplifier based on a Chireix architecture, a power amplifier based on out-phasing modulation, a sequential power amplifier, or a power amplifier based on envelope tracking technology, etc.

[0089] In some possible implementations, the baseband processing circuit 100 may be a baseband unit (BBU), and the radio frequency processing system 200 may be a remote radio unit (RRU), an active antenna unit (AAU), or the like.

[0090] In some possible implementations, the signal transmitting device 1000 may be a base station, a terminal device, a mobile phone, a laptop computer, a tablet computer, a smart watch, a smart home device, or a smart car.

[0091] Based on the structures shown in FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 and FIG. 16 , a control method including the following steps S100 to S200 as shown in FIG. 17 can be implemented:

[0092] S100: The gate of at least one power tube M receives a first radio frequency signal and a gate bias voltage signal.

[0093] Exemplarily, the transistor can be used as a switch and a power tube M. When the transistor needs to be used as a power tube M, as shown in FIG1 , it is necessary to set a gate DC signal at the gate of the power tube M, and set a drain DC signal to the drain of the power tube M. The biased gate DC signal and the drain DC signal are used to control the transistor bias in the amplification state to serve as the power tube M. Normally, the power tube M is a voltage-controlled voltage type or a voltage-controlled current type transistor. Therefore, the gate DC signal can be a gate bias voltage signal. When the power tube M performs power amplification, the gate of the power tube M receives a first radio frequency signal. The power tube M working in the amplification state outputs a second radio frequency signal from the drain based on the first radio frequency signal and the drain DC signal, which has a gain amplification relationship with the first radio frequency signal, thereby completing power amplification and outputting the second radio frequency signal.

[0094] S200 , adjusting the magnitude of the gate bias voltage signal.

[0095] Exemplarily, the size of the gate bias voltage signal is adjusted according to the amount of valid data carried by the signal slice symbol. For example, when the amount of valid data is zero, it means that the signal slice symbol does not carry valid data, or the first RF signal is not received. At this time, the third power amplifier 20C is in an idle state, and the second voltage signal corresponding to the idle state can be used as the gate bias voltage signal. The second voltage signal causes the channel conduction width of the power tube M to be in a lower state to reduce the current or voltage between the drain and the source, thereby reducing power consumption. When the signal slice symbol carries valid data, the third power amplifier 20C is in a data load state, and the first voltage signal corresponding to the data load state can be used as the gate bias voltage signal. The first voltage signal causes the channel conduction width of the power tube M to be in a higher state to increase the current or voltage between the drain and the source, thereby meeting normal power amplification in the data load state.

[0096] In some possible implementations, step S200 may include the following sub-operations:

[0097] S210: Generate a control signal.

[0098] In some possible implementations, as shown in FIG14 , the baseband processing circuit 100 generates a first indication signal based on the amount of data carried by the first signal symbol on the first baseband signal to be transmitted. The first indication signal indicates the amount of valid data carried by multiple signal slice symbols. Upon receiving the first indication signal, the first controller 21C of the third power amplifier 20C within the RF processing system 200 generates a control signal based on the first indication signal and sends the control signal to the gate bias circuit P1.

[0099] In some possible implementations, as shown in FIG15 , the second controller C1 within the baseband processing circuit 100 generates a control signal based on the amount of data in the first signal symbol carried by the first baseband signal to be transmitted, and outputs the control signal to the gate bias circuit P1 of the third power amplifier 20C within the RF processing system 200. In this embodiment of the present application, before the baseband processing circuit 100 outputs the first baseband signal, the internal second controller C1 has already performed relevant processing operations on the signal slice symbols. While processing the signal slice symbols internally, the second controller C1 can generate the control signal and output it to the gate bias circuit P1 of the third power amplifier 20C. The second controller C1 can utilize the relevant control components already within the baseband processing circuit 100. The solution described in this embodiment of the present application eliminates the need for additional control components, saving device costs. Furthermore, while the second controller C1 processes and generates the second baseband signal, it can also generate and send the relevant control signal to the gate bias circuit P1, enabling rapid, timely, and precise adjustment of the gate bias voltage signal, thereby achieving precise power consumption control of the third power amplifier 20C at the signal slice symbol level.

[0100] S220 , adjusting the gate bias voltage signal according to the control signal.

[0101] In some examples, control signals can be used to reduce the power consumption of the third power amplifier 20C in an idle state. As shown in FIG14 , the control signals include a first control signal. Based on the first control signal, the second selection switch S2 is controlled to select and switch between a first voltage signal and a second voltage signal. The first voltage signal and the second voltage signal have a certain voltage difference. When the first signal slice symbol of the first RF signal received by the gate of the power transistor M carries valid data, the third power amplifier 20C is in a data-carrying state. The first voltage signal is used to increase the channel conduction width between the drain and source of the power transistor M to ensure normal power amplification. When the first signal slice symbol of the first RF signal received by the gate of the power transistor M does not carry valid data, or the power transistor M is not receiving the first RF signal, the third power amplifier 20C is in an idle state. The second voltage signal is used to decrease the channel conduction width between the drain and source of the power transistor M to reduce the DC signal at the drain of the power transistor M, thereby reducing the power consumption of the third power amplifier 20C. In an embodiment of the present application, the selection state of the second selection switch S2 can be controlled by the first control signal to achieve precise control of the gate bias voltage signal at the signal slice level, thereby minimizing the power consumption of the third power amplifier 20C in the idle state.

[0102] In some examples, the power consumption of the third power amplifier 20C in a data-loaded state can be reduced by a control signal. As shown in Figures 11, 12, and 13, when the control gate bias circuit P1 outputs a first voltage signal to the power transistor M, the magnitude of the output first voltage signal is also controlled to be a first voltage value. The first voltage value corresponds to the data volume range within which valid data carried by the first signal slice symbol is located.

[0103] For example, the data volume of a signal slicer can be in different data volume intervals, and the signal power of the first RF signal corresponding to different data volume intervals is different. Under different signal powers, the channel conduction width between the drain and source of the power transistor M can be adjusted accordingly to achieve reduced power consumption while ensuring normal operation of the power amplifier. Therefore, for different data volume intervals, a first voltage signal with a corresponding voltage value can be set. In actual applications, based on the data volume interval in which the data volume of the first signal slicer is located, the channel conduction width between the drain and source of the power transistor M can be controlled based on a first voltage signal with a corresponding voltage value (e.g., the first voltage value). As shown in Figure 18, when the data volume of the signal slicer is in a higher data volume interval, the first voltage signal with a corresponding voltage value of V1 is used as the gate bias voltage signal. When in an idle state, the second voltage signal is used as the gate bias voltage signal. When the data volume of the signal slicer is in a lower data volume interval, the first voltage signal with a corresponding voltage value of V2 is used as the gate bias voltage signal.

[0104] In some examples, when multiple adjacent signal slice symbols are located in at least two data volume intervals, the voltage value of the first voltage signal is set to the voltage value corresponding to the second data volume interval; the second data volume interval is the highest data volume interval among the at least two data volume intervals. Exemplarily, as shown in FIG19 , for multiple adjacent signal slice symbols (for example, the two signal slice symbols shown in the dotted box in the figure). When multiple signal slice symbols are located in at least two data volume intervals, it means that in the process of power amplifying the first RF signal corresponding to the multiple adjacent signal slice symbols, at least one switching operation of the voltage value of the first voltage signal will be performed. In some application scenarios, switching selection for different voltage values ​​requires a certain switching time. When there are certain requirements for transmission accuracy, etc., it is possible not to switch between multiple adjacent (for example, two, three, etc.) signal slice symbols, and use the voltage value corresponding to the highest data volume interval of the multiple adjacent signal slice symbols as the voltage value of the first voltage signal.

[0105] Exemplarily, the control signal further includes a second control signal. The magnitude of the first voltage signal is controlled based on the second control signal. Exemplarily, as shown in FIG12 , the first selection switch S1 is turned on to the corresponding voltage divider output terminal Dout based on the second control signal to obtain a first voltage signal corresponding to the data volume interval within which the data on the first signal slice symbol resides. Exemplarily, as shown in FIG13 , the first selection switch S1 is turned on to the corresponding reference output terminal based on the second control signal to obtain a reference voltage corresponding to the data volume interval within which the data on the first signal slice symbol resides. The corresponding reference voltage causes the first power supply P13 to output a first voltage signal having a corresponding voltage value.

[0106] For example, as shown in FIG12 , when the third power amplifier 20C is in an idle state, the first control signal controls the second selection switch S2 to be coupled and turned on with the output end of the second power supply interface P12. In order to avoid the problem that the voltage divider circuit D divides the second voltage signal output by the second power supply interface P12, thereby causing the voltage of the rear stage of the voltage divider circuit D to be raised, in some examples, the first selection switch S1 can be parameter-configured so that the first selection switch S1 remains coupled with the input end of the voltage divider circuit D (i.e., directly connected to the output end of the second power supply interface P12) when no second control signal is input. In some examples, the first selection switch S1 can also be controlled by the second control signal to be coupled with the input end of the voltage divider circuit D when the third power amplifier 20C is in an idle state.

[0107] For example, as shown in FIG12 , when the power tube is a depletion-mode transistor based on GaN material. Taking the voltage output by the first power supply P13 as -2.8V and the voltage output by the second power supply P14 as -10V as an example, when the signal power of the first RF signal is 0 (that is, the first signal slice symbol does not carry valid data, or the first RF signal is not actually received), the second selection switch S2 is controlled by the first control signal to couple and conduct with the second power supply interface P12. When the first selection switch S1 is directly connected to the second power supply interface P12, the gate bias voltage signal of the power tube M is the second voltage signal (-10V). At this time, the static bias current corresponding to the drain of the power tube M is 30mA. The third power amplifier 20C is in a low-power state. When the valid data carried by the first signal slice symbol is in the highest data volume interval, the second selection switch S2 is controlled by the first control signal to couple and conduct with the first power supply interface P12. Based on the maximum data volume range of the valid data on the first signal slice symbol, the second control signal controls the first selection switch S1 to couple to the corresponding voltage divider output terminal Dout (e.g., the input terminal of the voltage divider circuit D). After the 2.8V voltage passes through the voltage divider circuit D, a 2.7V first voltage signal is generated. Under the 2.7V first voltage signal, the corresponding quiescent bias current of the drain of the power transistor M is 50mA. Taking a drain bias voltage signal with a 34V DC drain signal as an example, in the idle state (low power consumption), the power consumption of the third power amplifier 20C is 32.64W. In the fully loaded, high power consumption state (2.7V first voltage signal), the corresponding power consumption is 54.4W. This embodiment of the present application reduces power consumption by 21.76W compared to conventional solutions in the low-power idle state. Furthermore, when the data in the signal slice symbol is not in the maximum data volume range, the value of the first voltage signal can be adjusted to still reduce power consumption under data load conditions.

[0108] Embodiments of the present application provide a power amplifier, a control method, a radio frequency processing system, and a signal transmitter. The power amplifier includes a gate bias circuit, a drain bias circuit, and at least one power transistor. The gate bias circuit outputs a gate bias voltage signal to the gate of the power transistor. The drain bias voltage signal outputs a drain DC signal to the drain of the power transistor. The drain DC signal can be a drain bias voltage signal or a drain bias current signal. The gate bias voltage signal and the drain DC signal bias the power transistor M in an amplification state. Simultaneously, after receiving a first radio frequency signal, the power transistor M generates a second radio frequency signal of corresponding power based on the channel conduction level of the drain and source of the power transistor M. The first radio frequency signal carries multiple signal slice symbols. The power of the first radio frequency signal is positively correlated with the amount of data in the signal slice symbol. When the amount of data in the signal slice symbol is small or the first radio frequency signal is not received, the energy conversion efficiency of the power transistor is low, resulting in significant power waste. To this end, the embodiment of the present application adjusts the magnitude of the gate bias voltage signal of the power tube based on the amount of data in the signal slice symbol carried by the first RF signal. By adjusting the magnitude of the gate bias voltage signal, the power consumption of the power tube is reduced while ensuring normal operation of the power amplification of the power tube. The embodiment of the present application adjusts the gate bias voltage signal based on signal slice symbol-level accuracy, resulting in high adjustment accuracy, good timeliness, and a significant reduction in power consumption.

[0109] The embodiment of the present application also provides a chip system, as shown in Figure 20, the chip system 300 includes at least one processor 310 and at least one interface circuit 320. At least one processor 310 and at least one interface circuit 320 can be interconnected via lines. The processor 310 is used to support the chip system to implement the various functions or steps in the above method embodiment (such as the control method described in Figure 17), and at least one interface circuit 320 can be used to receive signals from other devices (such as communication interfaces, radio frequency processing systems, baseband processing circuits, power amplifiers, antennas, etc.), or to send signals to other devices (such as communication interfaces, radio frequency processing systems, baseband processing circuits, power amplifiers, antennas, etc.). The chip system 300 may include chips and may also include other discrete devices.

[0110] The present application also provides a computer-readable storage medium including instructions. When the instructions are executed on a processor, the processor executes the control method described in the above embodiment (e.g., the control method described in FIG17 ).

[0111] The processor and controller involved in the embodiments of the present application can be a chip. For example, it can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0112] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0113] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0116] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0117] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0118] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0119] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A power amplifier, characterized in that: It includes a gate bias circuit, a drain bias circuit and at least one power tube; the drain bias circuit is coupled with the drain of the at least one power tube; the gate bias circuit includes a first power supply interface and a second power supply interface; There is a certain voltage difference between a first voltage signal received at the input end of the first power supply interface and a second voltage signal received at the input end of the second power supply interface; the gate of the at least one power tube is used to receive a radio frequency signal; the radio frequency signal carries a plurality of signal slice symbols; wherein: When the first signal slice symbol carries valid data, the gate of the at least one power tube is coupled to the output end of the first power supply interface; When the first signal slice symbol does not carry valid data, or the radio frequency signal is not received, the gate of the at least one power tube is coupled to the output end of the second power supply interface.

2. The power amplifier according to claim 1, characterized in that: The gate bias circuit further includes a voltage adjustment circuit; the voltage adjustment circuit is used for: When the first signal slice symbol carries valid data, the magnitude of the first voltage signal is adjusted to a first voltage value; the first voltage value corresponds to a data volume interval where the valid data carried by the first signal slice symbol is located.

3. The power amplifier according to claim 2, characterized in that: The voltage adjustment circuit is a voltage divider circuit; the voltage divider circuit includes a plurality of voltage divider output terminals; the plurality of voltage divider output terminals correspond one to one with a plurality of data volume intervals; wherein: When the first signal slice symbol carries valid data and the amount of the valid data is in the first data amount interval, the input end of the voltage divider circuit is coupled to the output end of the first power supply interface, and the gate of the at least one power tube is connected to the first voltage divider output end; the first voltage divider output end is the voltage divider output end corresponding to the first data amount interval.

4. The power amplifier according to claim 3, characterized in that: The voltage divider circuit includes a resistor string; the resistor string includes a plurality of equivalent resistors; the plurality of equivalent resistors are connected in series; the first end of the resistor string is the input end of the voltage divider circuit; the plurality of equivalent resistors are respectively coupled to the plurality of voltage divider output ends.

5. The power amplifier according to claim 3 or 4, characterized in that: The power amplifier further includes a first gate switch; the plurality of voltage-dividing output terminals are coupled to the gate of the at least one power tube via the first gate switch.

6. The power amplifier according to claim 5, characterized in that: When the first signal slice symbol does not carry valid data, or the radio frequency signal is not received, the first selection switch is directly connected to the output end of the second power supply interface.

7. The power amplifier according to claim 2, characterized in that: The gate bias circuit includes a first power supply; the output end of the first power supply is coupled to the input end of the first power supply interface; the voltage adjustment circuit includes a plurality of reference power supplies; a plurality of reference output ends corresponding to the plurality of reference power supplies are used to output a plurality of reference voltages; the voltage values ​​of the plurality of reference voltages are different, and the plurality of reference voltages correspond to a plurality of data volume intervals; wherein: When the first signal slice symbol carries valid data and the amount of the valid data is in a first data amount interval, the voltage input end of the first power supply is coupled to the first reference output end; the first reference output end is the reference output end corresponding to the first data amount interval.

8. The power amplifier according to claim 7, characterized in that: The power amplifier further includes a first gating switch; the multiple reference output terminals corresponding to the multiple reference power sources are coupled to the voltage input terminal of the first power source through the first gating switch.

9. The power amplifier according to claim 7 or 8, characterized in that: The plurality of reference power sources are a plurality of digital registers.

10. The power amplifier according to any one of claims 2 to 9, characterized in that: When a plurality of adjacent signal slice symbols are located in at least two data volume intervals, a second data volume interval is used as an actual data volume interval of the plurality of adjacent signal slice symbols; the second data volume interval is a highest data volume interval among the at least two data volume intervals.

11. The power amplifier according to any one of claims 1 to 10, characterized in that: The power amplifier also includes a second gating switch; the gate of the at least one power tube is coupled to the output end of the first power supply interface through the second gating switch, or is coupled to the output end of the second power supply interface.

12. A control method, characterized in that: Based on a power amplifier; the power amplifier includes at least one power tube; the method includes: The gate of the at least one power tube receives a radio frequency signal and a gate bias voltage signal; the drain of the at least one power tube receives a drain bias voltage signal, and the radio frequency signal carries a plurality of signal slice symbols; When the first signal slice symbol carries valid data, controlling the gate bias voltage signal to be a first voltage signal according to a control signal; When the first signal slice symbol does not carry valid data, or the RF signal is not received, the gate bias voltage signal is controlled to be a second voltage signal according to the control signal; there is a certain voltage difference between the first voltage signal and the second voltage signal.

13. The control method according to claim 12, characterized in that: The method further comprises: When the first signal slice symbol carries valid data, the magnitude of the first voltage signal is adjusted to a first voltage value according to the control signal; the first voltage value corresponds to a data volume interval where the valid data carried by the first signal slice symbol is located.

14. The control method according to claim 13, characterized in that: The step of adjusting the magnitude of the first voltage signal to a first voltage value according to the control signal further includes: When a plurality of adjacent signal slice symbols are located in at least two data volume intervals, the voltage value of the first voltage signal is set to a voltage value corresponding to a second data volume interval; the second data volume interval is a highest data volume interval among the at least two data volume intervals.

15. The control method according to any one of claims 12 to 14, characterized in that: The method further comprises: Input a first indication signal; the first indication signal is used to indicate the amount of valid data carried by the multiple signal slice symbols; The control signal is obtained according to the first indication signal.

16. A radio frequency processing system, characterized in that: It comprises a radio frequency generating circuit and a power amplifier as described in any one of claims 1 to 11; the output end of the radio frequency generating circuit is coupled to the input end of the power amplifier; the radio frequency generating circuit is used to output a radio frequency signal; the radio frequency signal carries a plurality of signal slice symbols; and the power amplifier is used to amplify the power of the radio frequency signal.

17. A signal transmitting device, characterized in that: comprising a baseband processing circuit and a radio frequency processing system as claimed in claim 16; a first output terminal of the baseband processing circuit is coupled to a first input terminal of the radio frequency processing system; The first output terminal of the baseband processing circuit is used to output a first baseband signal; The first baseband signal includes a plurality of signal slice symbols; the radio frequency processing system is used for modulating the first baseband signal to obtain a radio frequency signal and outputting the radio frequency signal.

18. The signal transmitting device according to claim 17, characterized in that: The baseband processing circuit includes a controller; the controller is used to output a control signal to the radio frequency processing system; the control signal is used to adjust the magnitude of a gate bias voltage signal of a power tube of the radio frequency processing system.

19. The signal transmitting device according to claim 17, characterized in that: The second output end of the baseband processing circuit is coupled to the first input end of the radio frequency processing system; the second output end of the baseband processing circuit is also used to output a first indication signal; The first indication signal is used to indicate the amount of valid data carried by the multiple signal slice symbols.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes instructions; when the instructions are executed on a processor, the processor is caused to execute the control method according to any one of claims 12 to 15.

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