Capacitor, memory, and method for manufacturing memory

Abstract

The present application relates to a capacitor, a memory, and a method for manufacturing a memory. The capacitor may comprise: a first electrode layer; a second electrode layer; and a strontium titanate dielectric layer, which is formed between the first electrode layer and the second electrode layer, wherein the value of Sr / (Sr+Ti) in the strontium titanate dielectric layer is gradually reduced in the direction from the center of the strontium titanate dielectric layer towards two opposite sides of the strontium titanate dielectric layer, and one of the two opposite sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is close to the second electrode layer.

Description

Capacitor, memory, and method for manufacturing memory

[0001] Related applications

[0002] This application discloses and claims priority to Chinese patent application No. 2023109241479 filed on July 25, 2023, entitled “Capacitor, Memory and Method for Manufacturing Memory” and No. 2023219866424 filed on July 25, 2023, entitled “Capacitor, Memory and Method for Manufacturing Memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application belongs to the field of chips, and specifically relates to a capacitor, a memory, and a method for manufacturing the memory. Background Art

[0004] With the development of the chip industry, the market demand for DRAM (Dynamic Random Access Memory) chips with higher storage density is increasing. How to achieve higher storage density of DRAM chips is an important research topic for many chip industries.

[0005] For DRAM chips with a 1T1C (1 transistor + 1 capacitor) structure, the capacitor is an important factor that restricts the critical size of the DRAM chip. How to increase the DRAM storage density while reducing the critical size and ensure that the DRAM chip has sufficient signal resolution, that is, how to ensure that the capacitor achieves a higher dielectric constant (abbreviated as: K value) and a lower leakage density, has become an urgent problem that needs to be solved.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a capacitor, a memory, and a method for manufacturing the memory, which can achieve high K value and low leakage.

[0008] In a first aspect, the present application provides a capacitor, comprising:

[0009] a first electrode layer;

[0010] a second electrode layer; and

[0011] a strontium titanate dielectric layer formed between the first electrode layer and the second electrode layer, wherein:

[0012] From the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases,

[0013] One of the two opposite sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is close to the second electrode layer.

[0014] A second aspect of the present application provides a memory comprising a substrate and a capacitor as described in any one of the above items, wherein the capacitor is formed on the substrate.

[0015] A third aspect of the present application provides a method for manufacturing a memory, which may include:

[0016] providing a substrate;

[0017] forming a first electrode layer on the substrate;

[0018] forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate, wherein a ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases from a center of the strontium titanate dielectric layer to two opposite sides of the strontium titanate dielectric layer, and one side of the two opposite sides of the strontium titanate dielectric layer is closer to the first electrode layer and the other side is farther away from the first electrode layer;

[0019] A second electrode layer is formed on a side of the strontium titanate dielectric layer away from the first electrode layer to form a capacitor.

[0020] The technical solution provided by the embodiments of the present application has at least the following advantages: by gradually decreasing the Sr content ratio in the strontium titanate dielectric layer from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer, and gradually increasing the Ti content ratio from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer, while ensuring that the strontium titanate dielectric layer as a whole has a high Sr content so that it has a higher K value, it can also be beneficial to release or relax the stress caused by the high Sr content in the strontium titanate dielectric layer that is easy to crystallize. That is, the stress is gradually released from the center of the strontium titanate dielectric layer to its two sides. By reducing the internal stress of the strontium titanate dielectric layer, the occurrence of cracks in the strontium titanate dielectric layer can be reduced, and the surface uniformity of the strontium titanate dielectric layer is improved, thereby making it have low leakage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0022] 1 to 5 show schematic structural diagrams of memories corresponding to the various solutions mentioned in the first embodiment of the present application.

[0023] FIG6 shows a schematic diagram of the three-dimensional structure of the memory mentioned in the first embodiment of the present application.

[0024] FIG7 shows a schematic structural diagram of a capacitor according to a solution mentioned in the first embodiment of the present application.

[0025] 8 to 10 show schematic diagrams of the corresponding changes in the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer when different gradient designs are performed in Example 1 of the present application.

[0026] FIG11 shows a schematic structural diagram of a capacitor according to another solution mentioned in the first embodiment of the present application.

[0027] 12 to 14 show schematic structural diagrams of capacitors corresponding to various schemes in the second embodiment of the present application.

[0028] Figures 15 to 25 are structural schematic diagrams corresponding to each step in the memory manufacturing method provided in Example 3 of the present application.

[0029] Explanation of Reference Numerals: 10, substrate; 100, semiconductor base; 101, insulating isolation layer; 11, capacitor; 11a, ruthenium element film layer; 11b, titanium nitride film layer; 110, first electrode layer; 111, dielectric layer; 111a, dielectric material film; 112, second electrode layer; 112a, second electrode material film; 1110, strontium titanate dielectric layer; 11101, strontium titanate film layer; 1111, first titanium oxide dielectric layer; 1112, second titanium oxide dielectric layer; 1113, first aluminum titanate dielectric layer; 1114, second aluminum titanate dielectric layer; 12, insulating dielectric layer; 13, etch-stop layer; 14, measuring electrode material film; 14a, first measuring electrode; 14b, second measuring electrode; 140, via conductive portion; 141, measuring conductive portion; 15. Interlayer dielectric layer; 150. Through hole; 15a. Interlayer dielectric material film; 16. Transistor; 17. Word line; 18. Bit line; 19. First photoresist mask layer; 20. Second photoresist mask layer; 21. First via hole; 22. Second via hole; 23. Third photoresist mask layer; 24. Fourth photoresist mask layer. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0031] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0032] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0033] Example 1

[0034] An embodiment of the present application provides a memory, which may be a DRAM, for example, a three-dimensional DRAM, that is, a memory formed by stacking multiple layers of DRAM. However, it should be understood that the memory of this embodiment is not limited to DRAM, but may also be other types of memory, depending on the specific circumstances.

[0035] As shown in FIG. 1 , the memory of this embodiment may include a substrate 10 and a plurality of memory cells formed on the substrate 10 . The memory cell may include a capacitor 11 formed on the substrate 10 .

[0036] The capacitor 11 may include a first electrode layer 110 , a dielectric layer 111 , and a second electrode layer 112 sequentially stacked on a substrate 10 . That is, the dielectric layer 111 is formed between the first electrode layer 110 and the second electrode layer 112 .

[0037] For example, this capacitor 11 can be a MIM (Metal-Isolation-Metal) structure, that is, the first electrode layer 110 and the second electrode layer 112 include metal or metal compounds and have conductive properties, and the dielectric layer 111 is an insulator to isolate the first electrode layer 110 and the second electrode layer 112.

[0038] As shown in FIG2 , the substrate 10 may include a semiconductor base 100 , such as, but not limited to, a silicon substrate. It may also be a substrate formed of other semiconductor materials (e.g., silicon carbide, gallium compounds, or germanium compounds). To isolate the MIM structure from the effects of the semiconductor base 100 , the substrate 10 may further include an insulating isolation layer 101 formed between the first electrode layer 110 and the semiconductor base 100 . That is, before forming the first electrode layer 110 on the semiconductor base 100 , an insulating isolation layer 101 may be formed on the semiconductor base 100 , and then the first electrode layer 110 may be formed. The insulating isolation layer 101 insulates the semiconductor base 100 from the first electrode layer 110 .

[0039] For example, the insulating isolation layer 101 may be made of SiO 2 (silicon dioxide) material, but is not limited thereto and may also be made of other insulating materials, depending on the specific situation.

[0040] In order to measure the electrical properties of the dielectric layer 111 in the capacitor 11, a measuring electrode for measuring the capacitor 11 may also be fabricated during the process of fabricating the capacitor 11 on the substrate 10. The specific relationship between the capacitor 11 and the measuring electrode is as follows:

[0041] As shown in FIG3 , in the capacitor 11 , the orthographic projections of the second electrode layer 112 and the dielectric layer 111 on the substrate 10 are located in the middle area of ​​the orthographic projection of the first electrode layer 110 on the substrate 10 . That is, the edge area of ​​the first electrode layer 110 is not covered by the second electrode layer 112 and the dielectric layer 111 , so as to facilitate the contact between the subsequently manufactured measuring electrode and the first electrode layer 110 . The orthographic projection of the second electrode layer 112 on the first electrode layer 110 overlaps with the orthographic projection of the dielectric layer 111 on the first electrode layer 110 , so as to ensure the storage capacity of the capacitor 11 .

[0042] As shown in FIG4 , after the capacitor 11 is formed on the substrate 10 , the memory further includes an insulating dielectric layer 12 , an etch stop layer 13 , and a first measurement electrode 14 a and a second measurement electrode 14 b spaced apart from each other.

[0043] The insulating dielectric layer 12 covers the edge region of the first electrode layer 110 and the second electrode layer 112. The etch-stop layer 13 is formed on the side of the insulating dielectric layer 12 facing away from the substrate 10, and the etch-stop layer 13 completely covers the insulating dielectric layer 12. The first measuring electrode 14a and the second measuring electrode 14b each include a connected via conductive portion 140 and a measuring conductive portion 141. The measuring conductive portion 141 of the first measuring electrode 14a and the second measuring electrode 14b is formed on the side of the etch-stop layer 13 facing away from the substrate 10 and is configured to connect to an external measuring device for measuring the performance of the capacitor 11.

[0044] The orthographic projection of the via-hole conductive portion 140 of the first measuring electrode 14a on the substrate 10 is located within the orthographic projection of the edge area of ​​the first electrode layer 110 on the substrate 10. The via-hole conductive portion 140 of the first measuring electrode 14a sequentially penetrates the etch-stop layer 13 and the insulating dielectric layer 12 and contacts the edge area of ​​the first electrode layer 110, so that one pole of the measuring device contacts the first electrode layer 110 through the first measuring electrode 14a; the orthographic projection of the via-hole conductive portion 140 of the second measuring electrode 14b on the substrate 10 is located within the orthographic projection of the second electrode layer 112 on the substrate 10. The via-hole conductive portion 140 of the second measuring electrode 14b sequentially penetrates the etch-stop layer 13 and the insulating dielectric layer 12 and contacts the second electrode layer 112, so that the other pole of the measuring device contacts the second electrode layer 112 through the second measuring electrode 14b.

[0045] In this embodiment, the material of the first measuring electrode 14 a and the second measuring electrode 14 b may be TiN (titanium nitride), etc., but is not limited thereto, and may also be other conductive materials, depending on the specific situation.

[0046] Since the dielectric layer 111 in the capacitor 11 is very thin, usually only a few nanometers, the leakage at the edge of the dielectric layer 111 is very large. Edge leakage is not an intrinsic characteristic of the material and will interfere with the measurement results. Based on this, as shown in Figure 5, the memory of this embodiment may also include an interlayer dielectric layer 15 to increase the distance between the edge of the second electrode layer 112 and the first electrode layer 110.

[0047] Specifically, as shown in FIG5 , the interlayer dielectric layer 15 may be formed between the first electrode layer 110 and the insulating dielectric layer 12. It should be understood that the aforementioned via conductive portion 140 of the first sensing electrode 14a not only penetrates the etch-stop layer 13 and the insulating dielectric layer 12, but also penetrates the interlayer dielectric layer 15 to contact the edge region of the first electrode layer 110. Furthermore, the interlayer dielectric layer 15 further includes a through hole 150 to expose a portion of the first electrode layer 110.

[0048] As shown in FIG5 , the dielectric layer 111 has a middle portion and an edge portion disposed around the middle portion. The middle portion of the dielectric layer 111 is formed within the through-hole 150 and contacts the first electrode layer 110. The edge portion of the dielectric layer 111 overlaps the surface of the interlayer dielectric layer 15 away from the first electrode layer 110 to increase the distance between the edge of the second electrode layer 112 and the first electrode layer 110. The orthographic projection of the via-hole conductive portion 140 of the second measuring electrode 14 b on the substrate 10 is located within the orthographic projection of the through-hole conductive portion 140 on the substrate 10. In other words, the orthographic projection of the via-hole conductive portion 140 of the second measuring electrode 14 b on the substrate 10 is located within the orthographic projection of the middle portion of the dielectric layer 111 on the substrate 10, thereby accurately measuring the K value and leakage condition at the middle portion of the dielectric layer 111.

[0049] For example, as shown in Figures 4 and 5, multiple via conductive portions 140 are provided in the first measuring electrode 14a and the second measuring electrode 14b, and are arranged at equal intervals around the axis of the through hole 150. This can make the electric field distribution more uniform during the measurement process and the measurement effect more accurate.

[0050] It should be noted that when multiple via-hole conductive portions 140 are provided in the first measuring electrode 14a and the second measuring electrode 14b, there may be only one measuring conductive portion 141 in the first measuring electrode 14a and the second measuring electrode 14b, but is not limited thereto. Multiple measuring conductive portions 141 may be provided and arranged at equal intervals around the axis of the through hole 150. They may be connected to the via-hole conductive portions 140 one-to-one or one-to-many.

[0051] The first measuring electrode 14a and the second measuring electrode 14b mentioned in this embodiment are not limited to being retained in the memory finally produced, but may also be completely cut off or partially cut off during the die (crystal) cutting process after the test is completed, depending on the specific cutting situation, but it does not affect the final use of the product.

[0052] In this embodiment, as shown in Figure 6, in addition to the capacitor 11, the memory cell may also include a transistor 16, a word line 17 and a bit line 18. The transistor 16, the word line 17 and the bit line 18 can all be formed on the substrate 10. The gate of the transistor 16 can be connected to the word line 17, and one of the source and drain of the transistor 16 is connected to the bit line 18, and the other is connected to the capacitor 11; specifically, it can be connected to the first electrode layer 110 of the capacitor 11 to implement data reading and writing operations. That is, the memory cell can be a 1T1C structure.

[0053] For a memory including a 1T1C (1 transistor 16 + 1 capacitor 11) structure, capacitor 11 is an important factor restricting the critical size of the memory. How to increase the DRAM storage density while reducing the critical size and ensure that the DRAM chip has sufficient signal resolution has become a technical problem that needs to be solved urgently.

[0054] When the memory is a three-dimensional DRAM, as shown in FIG6 , the capacitor 11 can be placed horizontally. By reducing the lateral length of the capacitor 11, its storage density can be effectively increased. In addition, the first electrode layer 110, the second electrode layer 112, and the dielectric layer 111 of the capacitor 11 can be adjusted so that the capacitor 11 has a higher dielectric constant (abbreviated as: K value), that is, the storage density is increased and the leakage is reduced. In addition to being applicable to three-dimensional DRAM, this method can also be applied to other memories including capacitor structures. The structure of the capacitor 11 in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0055] In this embodiment, as shown in FIG. 7 , the dielectric layer 111 of the capacitor may include a strontium titanate dielectric layer 1110 (STO dielectric layer for short). The strontium titanate dielectric layer 1110 contains strontium (Sr) and titanium (Ti).

[0056] According to research, when the strontium titanate dielectric layer 1110 is designed to have a high Sr content, that is, when the Sr content is greater than the Ti content in the overall design of the strontium titanate dielectric layer 1110, and the strontium titanate dielectric layer 1110 is a strontium-rich layer (SrRich), the K value will be relatively large and the storage density will be high. However, the strontium titanate dielectric layer 1110 is prone to cracking, which will cause the formed capacitor to have an uneven electric field distribution, thereby causing the capacitor 11 to leak easily, and due to Since Sr is a heavy metal, it is easy to form oxygen vacancies, which further increases leakage current. When the strontium titanate dielectric layer 1110 is designed as a whole with a high Ti content, that is, when the Ti content in the overall design of the strontium titanate dielectric layer 1110 is greater than the Sr content, this strontium titanate dielectric layer 1110 is a titanium-rich layer (TiRich), it is not easy to crack and has a low leakage effect, but the K value will be relatively small, which is not conducive to reducing the size of the capacitor, and thus is not conducive to increasing the storage density of the DRAM chip.

[0057] Therefore, the embodiment of the present application implements a gradient design for the structure of the strontium titanate dielectric layer 1110. Specifically, in the direction from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases (that is, the proportion of Sr content in the strontium titanate dielectric layer 1110 gradually decreases, and the proportion of Ti content gradually increases); in other words, in the direction from the opposite sides of the strontium titanate dielectric layer 1110 to the center of the strontium titanate dielectric layer 1110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually increases (that is, the proportion of Sr content in the strontium titanate dielectric layer 1110 gradually increases, and the proportion of Ti content gradually decreases).

[0058] One of the two opposite sides of the aforementioned strontium titanate dielectric layer 1110 is close to the first electrode layer 110, and the other side is close to the second electrode layer 112. From the center of the strontium titanate dielectric layer 1110 to the direction of the first electrode layer 110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases, and from the center of the strontium titanate dielectric layer 1110 to the direction of the second electrode layer 112, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 also gradually decreases.

[0059] In the solution of this embodiment, compared with the technical solution that the strontium titanate dielectric layer 1110 is a titanium-rich layer or a strontium-rich layer as a whole, the Sr content ratio in the strontium titanate dielectric layer 1110 is gradually reduced from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110, and the Ti content ratio is gradually increased from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110. In this way, the strontium titanate dielectric layer 1110 is ensured to be a titanium-rich layer or a strontium-rich layer as a whole. While the high Sr content inside the strontium titanate dielectric layer 1110 gives it a higher K value, it is also beneficial to release or relax the stress caused by the easy crystallization due to the high Sr content. That is, the stress is gradually released from the center of the strontium titanate dielectric layer 1110 to its two sides. By reducing the internal stress of the strontium titanate dielectric layer 1110, the occurrence of cracks in the strontium titanate dielectric layer 1110 can be reduced, and the surface uniformity of the strontium titanate dielectric layer 1110 is improved, so that it has low leakage performance.

[0060] That is, this solution improves the K value of capacitor 11, that is, effectively improves the storage density of capacitor 11 while reducing its leakage, which is beneficial to reducing the key size in the 1T1C structure and improving the storage density of three-dimensional DRAM.

[0061] For example, in this embodiment, the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 is greater than 50%, that is, the Sr content at the center of the strontium titanate dielectric layer 1110 is greater than the Ti content. The center of the strontium titanate dielectric layer 1110 is in an Sr-rich state to ensure that the center of the strontium titanate dielectric layer 1110 has a higher K value, thereby ensuring that the strontium titanate dielectric layer 1110 as a whole has a good storage density.

[0062] It should be noted that the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 may be designed to be related to its thickness to ensure the overall performance of the strontium titanate dielectric layer 1110 .

[0063] The thickness of the strontium titanate dielectric layer 1110 can range from 5nm to 7nm, such as: 5nm, 5.5nm, 6nm, 6.5nm, 7nm, etc., and the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 can range from 60% to 65%, such as: 60%, 61%, 62%, 63%, 64%, 65%, etc.

[0064] For example, when the thickness of the strontium titanate dielectric layer 1110 is about 6 nm, the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 can substantially reach 62%, which enables the capacitor to achieve a high K value (>60) and a low leakage current (<10 -5 ) performance.

[0065] In one embodiment of the present application, as shown in Figure 7, the strontium titanate dielectric layer 1110 is a single-layer structure formed in one step. That is, when the strontium titanate dielectric layer 1110 is formed on the side of the first electrode layer 110 away from the substrate 10, a film forming process can be used. For example, the strontium titanate material can be deposited on the side of the first electrode layer 110 away from the substrate 10 using an atomic layer deposition (ALD) process to form the strontium titanate dielectric layer 1110.

[0066] In the atomic layer deposition process, the flow rate of the Sr precursor and / or the Ti precursor is adjusted so that the Sr content in the strontium titanate dielectric layer 1110 first gradually increases and then gradually decreases, thereby making the ratio of Sr / (Sr+Ti) in the strontium titanate material first gradually increase and then gradually decrease, to form the aforementioned strontium titanate dielectric layer 1110, that is: from the opposite sides of the strontium titanate dielectric layer 1110 to the center of the strontium titanate dielectric layer 1110: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually increases.

[0067] Furthermore, as shown in FIG7 , in the strontium titanate dielectric layer 1110: the surface close to the first electrode layer 110 is defined as the first boundary surface a1, and the surface close to the second electrode layer 112 is defined as the second boundary surface a2, and the Sr content at the first boundary surface a1 and the second boundary surface a2 can be 0; in other words, when the strontium titanate dielectric layer 1110 is produced, the initial strontium titanate material deposited at the beginning of an atomic layer deposition process does not contain Sr, or the Sr content is very, very small, approximately 0, and then the Sr content in the strontium titanate material is gradually increased. When the set amount is reached, the Sr content in the strontium titanate material is gradually reduced, so that the Sr content in the strontium titanate material at the end of the atomic layer deposition process is 0, or approximately 0.

[0068] It should be understood that when the Sr content at the first boundary surface a1 and the second boundary surface a2 in the strontium titanate dielectric layer 1110 is 0, the first boundary surface a1 and the second boundary surface a2 can be understood as the titanium dioxide (TiO2) surface. The use of TiO2 at the boundary surface can effectively reduce the oxygen vacancies in the strontium titanate dielectric layer 1110 and reduce the occurrence of leakage.

[0069] For example, when manufacturing a single-layer strontium titanate dielectric layer 1110, the strontium titanate material deposited at the beginning and end of an atomic layer deposition process, in addition to being free of Sr, may also be doped with Al (aluminum). That is, the first boundary surface a1 and the second boundary surface a2 may be ATO (aluminum titanate) boundary surfaces to increase CBO (conduction band offset) and further reduce leakage.

[0070] It should be understood that when semiconductors and semiconductors, or insulators and semiconductors contact to form an interface structure, due to the different band gap widths, discontinuous steps will be formed at the bottom of the conduction band and the top of the valence band of the materials on both sides, namely band offsets. The band step at the bottom of the conduction band is called the conduction band offset (CBO), and the band step at the top of the valence band is called the valence band offset (VBO).

[0071] In an optional embodiment, from the center of the strontium titanate dielectric layer 1110 (the center is passed through by the dotted line in Figure 7) to the opposite sides of the strontium titanate dielectric layer 1110 (the direction of the black bold arrows in Figure 7): the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases according to a linear relationship. In other words, from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 can decrease at a uniform rate to better balance the high K value and low leakage performance of the strontium titanate dielectric layer 1110.

[0072] For example, referring to FIG8 , the aforementioned linear relationship may be specifically:

[0073] Wherein, C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer 1110, D is the distance from the center of the strontium titanate dielectric layer 1110, H is the thickness of the strontium titanate dielectric layer 1110, and 0≤D≤H / 2.

[0074] For example, when C is 0.62 and H is 6 nm, the linear relationship can be:

[0075] Among them, when the distance from the center of the strontium titanate dielectric layer 1110 in the direction close to the first electrode layer 110 is 3 nm, the ratio of Sr / (Sr+Ti) here is 0, which can be understood as the first boundary surface a1 mentioned above. When the distance from the center of the strontium titanate dielectric layer 1110 in the direction close to the second electrode layer 112 is 3 nm, the ratio of Sr / (Sr+Ti) here is 0, which can be understood as the second boundary surface a2 mentioned above.

[0076] In another optional embodiment, as shown in Figure 9, the rate of decrease of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually increases in the direction from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110. In other words, the rate of increase of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases in the direction from the opposite sides of the strontium titanate dielectric layer 1110 to the center of the strontium titanate dielectric layer 1110. In other words, when the entire strontium titanate dielectric layer 1110 is manufactured, the Sr content is first increased rapidly, then the Sr content is slowly increased to a maximum value, and then the Sr content is first slowly decreased and then the Sr content is quickly decreased. In this way, while ensuring that the strontium titanate dielectric layer 1110 has low leakage performance, the K value of the strontium titanate dielectric layer 1110 can also be improved.

[0077] For example, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 may satisfy the following relationship:

[0078] Wherein, C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer 1110, D is the distance from the center of the strontium titanate dielectric layer 1110, H is the thickness of the strontium titanate dielectric layer 1110, and 0≤D≤H / 2.

[0079] For example, when C is 0.62 and H is 6 nm, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 satisfies the following relationship:

[0080] Among them, when the distance from the center of the strontium titanate dielectric layer 1110 in the direction close to the first electrode layer 110 is 3 nm, the ratio of Sr / (Sr+Ti) here is 0, which can be understood as the first boundary surface a1 mentioned above. When the distance from the center of the strontium titanate dielectric layer 1110 in the direction close to the second electrode layer 112 is 3 nm, the ratio of Sr / (Sr+Ti) here is 0, which can be understood as the second boundary surface a2 mentioned above.

[0081] In another optional embodiment, as shown in FIG10 , the rate of decrease of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases in the direction from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110. In other words, the rate of increase of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually increases in the direction from the opposite sides of the strontium titanate dielectric layer 1110 to the center of the strontium titanate dielectric layer 1110. That is, when the entire strontium titanate dielectric layer 1110 is manufactured, the Sr content is first slowly increased, then quickly increased to a maximum value, and then the Sr content is first quickly decreased, and then slowly decreased. In this way, while ensuring that the strontium titanate dielectric layer 1110 has a high K value, the surface uniformity of the opposite sides of the strontium titanate dielectric layer 1110 can also be improved, thereby making it have low leakage performance.

[0082] It should be understood that the X-axis in Figures 8 to 10 is used to represent the distance from the strontium titanate dielectric layer 1110, in units of nm (nanometers), the Y-axis is used to represent the ratio of Sr / (Sr+Ti), and the line on the left side of the Y-axis is used to represent the change in the ratio of Sr / (Sr+Ti) between the center of the strontium titanate dielectric layer 1110 and the first electrode layer 110, and the line on the right side of the Y-axis is used to represent the change in the ratio of Sr / (Sr+Ti) between the center of the strontium titanate dielectric layer 1110 and the second electrode layer 112.

[0083] In addition, in order to further improve the performance of the capacitor, as shown in Figure 9, the first electrode layer 110 and the second electrode layer 112 of this embodiment may include a ruthenium element film layer 11a. This ruthenium element film layer 11a is a metal ruthenium (Ru) film layer or a ruthenium oxide (RuO2) film layer with a high work function. The work function is also called the work function or the work function, and is defined in solid state physics as: the minimum energy required to move an electron from the inside of a solid to the surface of the object.

[0084] For example, the dielectric layer 111 of the capacitor may only include the strontium titanate dielectric layer 1110 mentioned above, and the first boundary surface a1 of the strontium titanate dielectric layer 1110 may contact the ruthenium element film layer 11a of the first electrode layer 110, and the second boundary surface a2 of the strontium titanate dielectric layer 1110 may contact the ruthenium element film layer 11a of the second electrode layer 112. When the first boundary surface a1 and the second boundary surface a2 of the strontium titanate dielectric layer 1110 are TiO2 surfaces, the ruthenium element film layer 11a can promote the formation of a rutile structure of TiO2 at the boundary surface, thereby reducing leakage and increasing the K value, so that the K value of the strontium titanate dielectric layer 1110 first decreases and then increases from the middle to both sides, the middle and the boundary mainly increase the dielectric constant, and the area between the middle and the boundary mainly provides the function of reducing leakage.

[0085] As shown in FIG9 , the first electrode layer 110 and the second electrode layer 112 further include a titanium nitride film layer 11b, which is formed on the side of the ruthenium element film layer 11a away from the strontium titanate dielectric layer 1110. In this way, while ensuring that the overall thickness and work function of the first electrode layer 110 and the second electrode layer 112 meet the requirements, the thickness of the ruthenium element film layer 11a can be appropriately reduced by providing the titanium nitride film layer 11b, so as to promote the formation of a rutile structure of TiO2 at the boundary surface, reduce leakage, increase the K value, and appropriately reduce the cost of the first electrode layer 110 and the second electrode layer 112.

[0086] Example 2

[0087] The main difference between the embodiment of the present application and the first embodiment is that the strontium titanate dielectric layer 1110 in the capacitor of the first embodiment is a single-layer structure, while the strontium titanate dielectric layer 1110 in the capacitor of the second embodiment can be a multi-layer stacked structure.

[0088] The structure of the capacitor according to the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0089] In this embodiment, as shown in reference figure 12, the strontium titanate dielectric layer 1110 may be a multi-layer stacked structure, and the strontium titanate dielectric layer 1110 may include N layers of strontium titanate film layers 11101 stacked in sequence, where N is a positive integer greater than or equal to 3; it should be understood that each molding process forms a film layer, that is, the strontium titanate dielectric layer 1110 is formed using multiple molding processes. For example, in the step of forming the strontium titanate dielectric layer 1110 on the side of the first electrode layer 110 away from the substrate 10, it may specifically include: using N atomic layer deposition processes to form N layers of strontium titanate film layers 11101 stacked in sequence on the side of the first electrode layer 110 away from the substrate 10 to form a stacked strontium titanate dielectric layer 1110.

[0090] It should be noted that the strontium titanate film layer 11101 of this embodiment contains both Sr and Ti. That is, the ratio of Sr / (Sr+Ti) in each strontium titanate film layer 11101 is greater than 0.

[0091] From the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 decreases layer by layer. As shown in FIG12 , taking N equal to 3 as an example, the strontium titanate dielectric layer 1110 may include a first strontium titanate film layer 11101, a second strontium titanate film layer 11101, and a third strontium titanate film layer 11101 stacked in sequence. The ratio of Sr / (Sr+Ti) in the second strontium titanate film layer 11101 is the largest, and the ratio of Sr / (Sr+Ti) in the first strontium titanate film layer 11101 is the largest. The ratio of Sr / (Sr+Ti) in the strontium titanate film layer 11101 and the third strontium titanate film layer 11101 is smaller than the ratio of Sr / (Sr+Ti) in the second strontium titanate film layer 11101. It should be noted that the strontium titanate dielectric layer 1110 is not limited to the three layers of strontium titanate film layers 11101 shown in FIG. 12 , but may also include four layers, five layers, etc., depending on the specific circumstances.

[0092] In this embodiment, the strontium titanate dielectric layer 1110 is designed to be a multi-layer stacked structure. In this way, the gradient design of the strontium titanate dielectric layer 1110 is realized to ensure that the strontium titanate dielectric layer 1110 has high K value and low leakage characteristics. At the same time, the manufacturing method is simple. While ensuring that the thickness of the strontium titanate dielectric layer 1110 remains unchanged, the thickness of each layer is reduced through layered manufacturing. This makes it easy to control the uniformity of film formation to improve product performance, and is also conducive to rapid commissioning. Existing equipment can be used to form each layer of the strontium titanate film 11101 in sequence, without the need to re-develop the equipment, thereby reducing research and development costs.

[0093] In addition, this embodiment designs the strontium titanate dielectric layer 1110 to be composed of at least three stacked layers of strontium titanate film layers 11101. This ensures that the area of ​​the strontium titanate dielectric layer 1110 close to the first electrode layer 110 and the area close to the second electrode layer 112 are both gradient-designed, ensuring that the strontium titanate dielectric layer 1110 and the first electrode layer 110 and the second electrode layer 112 have high K value and low leakage characteristics.

[0094] For example, N in this embodiment can be an odd number greater than or equal to 3, that is, the number of strontium titanate film layers 11101 in the strontium titanate dielectric layer 1110 is an odd number and greater than or equal to 3, such as: N = 3, 5, 7, 9, etc., depending on the specific situation.

[0095] In this embodiment, by designing the number of strontium titanate film layers 11101 in the strontium titanate dielectric layer 1110 to be an odd number, it is ensured that the number of film layers on the opposite sides of the strontium titanate film layer 11101 located in the middle is the same, so as to ensure that the area of ​​the strontium titanate dielectric layer 1110 close to the first electrode layer 110 and the area close to the second electrode layer 112 both achieve a balanced gradient design, thereby improving product quality.

[0096] The Sr / (Sr+Ti) ratio at each location in the strontium titanate film layer 11101 can be equal, that is, in each atomic layer deposition process, the flow rate of the Sr precursor and the Ti precursor remains constant. In this way, each layer of the strontium titanate film layer 11101 can be formed in sequence using existing equipment, without the need to re-develop the equipment, thereby reducing R&D costs.

[0097] It should be understood that the Sr / (Sr+Ti) ratio design between each strontium titanate film layer 11101 in the strontium titanate dielectric layer 1110 can be designed according to formula (1) and formula (2) mentioned in Example 1, wherein, in this Example 2, the parameter C mentioned in formula (1) and formula (2) is the ratio of Sr / (Sr+Ti) in the middle strontium titanate film layer 11101, and the parameter D is the distance between the center of the other film layers and the center of the middle strontium titanate film layer 11101.

[0098] In an optional embodiment, as shown in FIG13 , the dielectric layer 111 of the capacitor 11 may further include a first titanium oxide dielectric layer 1111 and a second titanium oxide dielectric layer 1112 in addition to the aforementioned strontium titanate dielectric layer 1110. The first titanium oxide dielectric layer 1111 is formed between the first electrode layer 110 and the strontium titanate dielectric layer 1110 and the strontium titanate film layer 11101, and the second titanium oxide dielectric layer 1112 is formed between the second electrode layer 112 and the strontium titanate dielectric layer 1110. A first titanium oxide dielectric layer 1111 and a second titanium oxide dielectric layer 1112 are formed on opposite sides of the layer 1110, and a gradient design of the dielectric layer 111 is further realized, that is, compared with the middle strontium titanate film layer 11101, the film layers located on the outermost sides of the dielectric layer 111 do not contain Sr, so as to form the first titanium oxide dielectric layer 1111 and the second titanium oxide dielectric layer 1112. This can ensure the uniformity of the outermost surfaces of the dielectric layer 111 in the capacitor 11, thereby making it have low leakage performance.

[0099] In addition, when the first electrode layer 110 and the second electrode layer 112 of this embodiment include the ruthenium element film layer 11a mentioned in the aforementioned embodiment 1, the first titanium oxide dielectric layer 1111 can be in contact with the ruthenium element film layer 11a of the first electrode layer 110, and the second titanium oxide dielectric layer 1112 can be in contact with the ruthenium element film layer 11a of the second electrode layer 112. The ruthenium element film layer 11a can promote the first titanium oxide dielectric layer 1111 and the second titanium oxide dielectric layer 1112 to contact with it to form a rutile structure, while reducing leakage, increasing the K value, so that the K value of the entire dielectric layer 111 in the first electrode layer 110 and the second electrode layer 112 first decreases and then increases from the middle to both sides, the middle and the boundary mainly increase the dielectric constant, and the area between the middle and the boundary mainly provides the function of reducing leakage.

[0100] In another optional embodiment, as shown in Figure 14, the dielectric layer 111 of the capacitor 11 may also include a first aluminum titanate dielectric layer 1113 and a second aluminum titanate dielectric layer 1114 in addition to the aforementioned strontium titanate dielectric layer 1110, the first aluminum titanate dielectric layer 1113 is formed between the first electrode layer 110 and the strontium titanate dielectric layer 1110, and the second aluminum titanate dielectric layer 1114 is formed between the second electrode layer 112 and the strontium titanate dielectric layer 1110.

[0101] For example, the first aluminum titanate dielectric layer 1113 can contact the ruthenium element film layer 11a of the first electrode layer 110, and the second aluminum titanate dielectric layer 1114 can contact the ruthenium element film layer 11a of the second electrode layer 112. This design can not only increase the K value, but also increase CBO (conduction band offset), further reducing leakage.

[0102] It should be noted that, apart from the aforementioned differences between the second embodiment and the first embodiment, the rest of the design of the second embodiment can refer to the contents of the first embodiment and will not be repeated here.

[0103] Example 3

[0104] An embodiment of the present application also provides a method for manufacturing a memory, which can be used to manufacture the memory provided by the aforementioned embodiment. For detailed descriptions of the memory, please refer to the aforementioned embodiment and will not be repeated here.

[0105] 1 to 25 , the memory manufacturing method may include at least step S100 , step S200 , step S300 , and step S400 .

[0106] In step S100, a substrate 10 is provided. For example, a semiconductor substrate 100 may be provided first, and then an insulating isolation layer 101 is formed on the semiconductor substrate 100, as shown in Figures 2 to 5. The semiconductor substrate 100 may be a silicon substrate, and the insulating isolation layer 101 may be SiO2, and the deposition thickness of the insulating isolation layer 101 may be (Amy).

[0107] In step S200, a first electrode layer 110 is formed on the substrate 10. For example, the first electrode layer 110 may be formed on a side of the insulating isolation layer 101 away from the semiconductor base 100. The first electrode layer 110 may include a TiN layer and a RuO2 layer sequentially formed on a side of the insulating isolation layer 101 away from the semiconductor base 100.

[0108] In step S300, a dielectric layer 111 is formed on a side of the first electrode layer 110 away from the substrate 10. The dielectric layer 111 includes at least a strontium titanate dielectric layer 1110. The ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110. For example, the strontium titanate dielectric layer 1110 can be formed on a side of the RuO2 layer away from the semiconductor substrate 100.

[0109] In an optional embodiment, step S300 specifically includes: using a single atomic layer deposition process to deposit strontium titanate material on the side of the first electrode layer 110 away from the substrate 10 to form the strontium titanate dielectric layer 1110, as shown in Figure 7; wherein, in the single atomic layer deposition process, by adjusting the flow rate of the Sr precursor and / or the Ti precursor, the ratio of Sr / (Sr+Ti) in the strontium titanate material gradually increases and then gradually decreases according to a set rule.

[0110] In another optional embodiment, step S300 specifically includes: using N atomic layer deposition processes to form N layers of strontium titanate film layers 11101 stacked in sequence on the side of the first electrode layer 110 away from the substrate 10 to form the strontium titanate dielectric layer 1110, N is a positive integer greater than or equal to 3, as shown in Figures 12 to 14; wherein, in each of the atomic layer deposition processes, the flow rates of the Sr precursor and the Ti precursor can be basically constant, that is, within the error range.

[0111] In step S400, a second electrode layer 112 may be formed on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110 to form a capacitor. The second electrode layer 112 may include a RuO2 layer and a TiN layer sequentially formed on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110.

[0112] In an optional embodiment, before step S300 and after step S200, the manufacturing method further includes: forming a first titanium oxide dielectric layer 1111 on a side of the first electrode layer 110 away from the substrate 10; and, after step S300 and before step S400, the manufacturing method may further include: forming a second titanium oxide dielectric layer 1112 on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110, as shown in Figure 13.

[0113] In another optional embodiment, before step S300 and after step S200, the manufacturing method further includes: forming a first aluminum titanate dielectric layer 1113 on a side of the first electrode layer 110 away from the substrate 10; and, after step S300 and before step S400, the manufacturing method further includes: forming a second aluminum titanate dielectric layer 1114 on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110, as shown in Figure 14.

[0114] The step of forming a first aluminum titanate dielectric layer 1113 on the side of the first electrode layer 110 away from the substrate 10 may specifically include: forming a first titanium oxide dielectric layer 1111 on the side of the first electrode layer 110 away from the substrate 10, and then doping aluminum elements into the first titanium oxide dielectric layer 1111 to form the first aluminum titanate dielectric layer 1113; and the step of forming a second aluminum titanate dielectric layer 1114 on the side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110, including forming a second titanium oxide dielectric layer 1112 on the side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110, and then doping aluminum elements into the second titanium oxide dielectric layer 1112 to form the second aluminum titanate dielectric layer 1114.

[0115] It should be understood that aluminum elements can be doped in the boundary surface of the first titanium oxide dielectric layer 1111 toward the first electrode layer 110 to form a first aluminum titanate dielectric layer 1113, and can also expand inward to a certain space. Similarly, aluminum elements can also be doped in the boundary surface of the second titanium oxide dielectric layer 1112 toward the second electrode layer 112 to form a second aluminum titanate dielectric layer 1114, and can also expand inward to a certain space.

[0116] Before step S300 and after step S200, the manufacturing method further includes: forming an interlayer dielectric material film 15a on a side of the first electrode layer 110 away from the substrate 10, as shown in Figure 15; and forming a through hole 150 on the interlayer dielectric material film 15a to expose a portion of the first electrode layer 110 using a patterning process to form an interlayer dielectric layer 15.

[0117] For example, a photoresist layer can be first formed on the side of the interlayer dielectric material film 15a away from the first electrode layer 110, and then the photoresist layer is exposed and developed to form a first photoresist mask layer 19, as shown in Figure 16; thereafter, the interlayer dielectric material film 15a is etched using the first photoresist mask layer 19 to form a through hole 150, and finally, the first photoresist mask layer 19 is removed, as shown in Figure 17.

[0118] It should be understood that at least a portion of the strontium titanate dielectric layer 1110 is located within the through hole 150 and contacts the first electrode layer 110 .

[0119] The step of sequentially forming a strontium titanate dielectric layer 1110 and a second electrode layer 112 on a side of the first electrode layer 110 away from the substrate 10 may specifically include:

[0120] After the interlayer dielectric layer 15 is formed, a dielectric material film (strontium titanate dielectric material film) 111a and a second electrode material film 112a are formed in sequence to be located in the through hole 150 and covering the interlayer dielectric layer 15, as shown in FIG18 ; thereafter, the portion of the dielectric material film (strontium titanate dielectric material film) 111a and the second electrode material film 112a covering the interlayer dielectric layer 15 is removed to form a strontium titanate dielectric layer 1110 and a second electrode layer 112, as shown in FIG20 .

[0121] For example, a photoresist layer can be first formed on the second electrode material film 112a, and the photoresist layer can be exposed and developed to form a second photoresist mask layer 20. Then, the second photoresist mask layer 20 is used to etch the dielectric material film (strontium titanate dielectric material film) 111a and the second electrode material film 112a to remove the portions of the dielectric material film (strontium titanate dielectric material film) 111a and the second electrode material film 112a covering the interlayer dielectric layer 15 to form a strontium titanate dielectric layer 1110 and a second electrode layer 112, as shown in Figure 19. Finally, the second photoresist mask layer 20 is removed, as shown in Figure 20.

[0122] After step S400 , the manufacturing method further includes steps S500 , S600 , S700 , and S800 .

[0123] In step S500, an insulating dielectric layer 12 and an etch-stop layer 13 are sequentially formed on the side of the interlayer dielectric layer 15 and the second electrode layer 112 away from the substrate 10, as shown in FIG21 . For example, the insulating dielectric layer 12 may be made of SiO2, and the etch-stop layer 13 may be made of SiN, but the present invention is not limited thereto. The materials of the insulating dielectric layer 12 and the etch-stop layer 13 may also be selected according to actual conditions.

[0124] In step S600, a first via 21 and a second via 22 are formed, which are spaced apart. As shown in FIG23 , the orthographic projection of the first via 21 on the substrate 10 is located within the orthographic projection of the first electrode layer 110 on the substrate 10, and does not overlap with the orthographic projections of the second electrode layer 112 and the strontium titanate dielectric layer 1110 on the substrate 10. The first via 21 sequentially penetrates the insulating dielectric layer 12, the etch stop layer 13 and the interlayer dielectric layer 15, and exposes a portion of the first electrode layer 110. The orthographic projection of the second via 22 on the substrate 10 is located within the orthographic projection of the through hole 150 on the substrate 10. The second via 22 sequentially penetrates the insulating dielectric layer 12 and the etch stop layer 13, and exposes a portion of the second electrode layer 112.

[0125] For example, a photoresist layer can be first formed on the side of the etch stop layer 13 away from the insulating dielectric layer 12, and then the photoresist layer is exposed and developed to form a third photoresist mask layer 23, as shown in Figure 22. Then, the third photoresist mask layer 23 is etched to form the first via 21 and the second via 22 mentioned above. Finally, the third photoresist mask layer 23 is removed, as shown in Figure 23.

[0126] In step S700, a measuring electrode material film 14 is formed. The measuring electrode material film 14 covers the surface of the etch-stop layer 13 away from the insulating dielectric layer 12 and fills the first via hole 21 and the second via hole 22, as shown in FIG24 . For example, the material of the measuring electrode material film 14 can be TiN, but is not limited thereto and can also be other conductive materials.

[0127] In step S800, the measuring electrode material film 14 is patterned to form a first measuring electrode 14a and a second measuring electrode 14b. The first measuring electrode 14a and the second measuring electrode 14b both include a via conductive portion 140 and a measuring conductive portion 141. The measuring conductive portions 141 of the first measuring electrode 14a and the second measuring electrode 14b are spaced apart and are both formed on a side of the etch stop layer 13 away from the substrate 10. The measuring conductive portion 141 of the first measuring electrode 14a is the measuring electrode material film 14 filled in the first via hole 21, and the measuring conductive portion 141 of the second measuring electrode 14b is the measuring electrode material film 14 filled in the second via hole 22, as shown in FIG5 .

[0128] For example, a photoresist layer can be first formed on the side of the measuring electrode material film 14 away from the etch stop layer 13, and then the photoresist layer is exposed and developed to form a fourth photoresist mask layer 24. Then, the fourth photoresist mask layer 24 is used to etch the measuring electrode material film 14 on the surface of the etch stop layer 13, as shown in Figure 25, to form the measuring conductive parts 141 of the first measuring electrode 14a and the second measuring electrode 14b. Finally, the fourth photoresist mask layer 24 is removed, as shown in Figure 25.

[0129] After the first measurement electrode 14 a and the second measurement electrode 14 b are formed, an external measurement device may be connected to the first measurement electrode 14 a and the second measurement electrode 14 b to measure the performance of the capacitor.

[0130] It should be understood that after the performance of the capacitor is tested using the first and second measuring electrodes 14a and 14b, the first and second measuring electrodes 14a and 14b may be cut off when cutting the die, or may remain on the substrate 10, depending on the specific situation.

[0131] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0132] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0133] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A capacitor, comprising: a first electrode layer; a second electrode layer; as well as A strontium titanate dielectric layer is formed between the first electrode layer and the second electrode layer, wherein: In the direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases, One of the two opposite sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is close to the second electrode layer.

2. The capacitor according to claim 1, wherein: The strontium titanate dielectric layer is a single-layer structure.

3. The capacitor according to claim 2, wherein: In the strontium titanate dielectric layer: a surface close to the first electrode layer is defined as a first boundary surface, a surface close to the second electrode layer is defined as a second boundary surface, and the Sr content at the first boundary surface and the second boundary surface is 0.

4. The capacitor according to claim 1, wherein The strontium titanate dielectric layer is a multi-layer stacked structure, and the strontium titanate dielectric layer includes N layers of strontium titanate film layers stacked in sequence, where N is a positive integer greater than or equal to 3; Wherein, in a direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer decreases layer by layer.

5. The capacitor according to claim 4, wherein: The Sr / (Sr+Ti) ratio is equal at every location in the strontium titanate film layer.

6. The capacitor according to claim 1, wherein In the direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases according to a linear relationship.

7. The capacitor according to claim 6, wherein: The linear relationship is specifically: Wherein, C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer, D is the distance in the strontium titanate dielectric layer away from the center of the strontium titanate dielectric layer, H is the thickness of the strontium titanate dielectric layer, and 0≤D≤H / 2.

8. The capacitor according to claim 1, wherein In the direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the reduction rate of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually increases.

9. The capacitor according to claim 8, wherein: The ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer satisfies the following relationship: Wherein, C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer, D is the distance from the center of the strontium titanate dielectric layer, H is the thickness of the strontium titanate dielectric layer, and 0≤D≤H / 2.

10. The capacitor according to claim 1, wherein In the direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the reduction rate of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases.

11. The capacitor according to claim 1, wherein The Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer is greater than 50%.

12. The capacitor according to claim 11, wherein The thickness of the strontium titanate dielectric layer ranges from 5 nm to 7 nm, and the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer ranges from 60% to 65%.

13. The capacitor according to claim 1, wherein The capacitor further comprises: a first titanium oxide dielectric layer formed between the first electrode layer and the strontium titanate dielectric layer; A second titanium oxide dielectric layer is formed between the second electrode layer and the strontium titanate dielectric layer.

14. The capacitor according to claim 1, wherein The capacitor further comprises: a first aluminum titanate dielectric layer formed between the first electrode layer and the strontium titanate dielectric layer; A second aluminum titanate dielectric layer is formed between the second electrode layer and the strontium titanate dielectric layer.

15. The capacitor according to any one of claims 1 to 14, wherein: The first electrode layer and the second electrode layer include a ruthenium element film layer, and the ruthenium element film layer is a metal ruthenium film layer or a ruthenium oxide film layer.

16. The capacitor according to claim 15, wherein The first electrode layer and the second electrode layer further include a titanium nitride film layer, and the titanium nitride film layer is formed on a side of the ruthenium element film layer away from the strontium titanate dielectric layer.

17. A memory, wherein: The invention comprises a substrate and the capacitor according to any one of claims 1 to 16, wherein the capacitor is formed on the substrate.

18. The memory according to claim 17, wherein: The orthographic projection of the second electrode layer on the first electrode layer overlaps with the orthographic projection of the strontium titanate dielectric layer on the first electrode layer, and the orthographic projections of the second electrode layer and the strontium titanate dielectric layer on the substrate are located in the middle area of ​​the orthographic projection of the first electrode layer on the substrate, and the memory further includes: an insulating dielectric layer, covering an edge region of the first electrode layer and the second electrode layer; an etch stop layer, formed on a side of the insulating dielectric layer away from the substrate; and A first measuring electrode and a second measuring electrode are arranged at intervals, and the first measuring electrode and the second measuring electrode both include a via conductive portion and a measuring conductive portion connected to each other, wherein: The measurement conductive parts of the first measurement electrode and the second measurement electrode are formed on a side of the etch stop layer away from the substrate. The orthographic projection of the via conductive portion of the first measuring electrode on the substrate is located within the orthographic projection of the edge region of the first electrode layer on the substrate, and the via conductive portion of the first measuring electrode sequentially penetrates the etching stop layer and the insulating dielectric layer and contacts the edge region of the first electrode layer; The orthographic projection of the via conductive portion of the second measuring electrode on the substrate is located within the orthographic projection of the second electrode layer on the substrate. The via conductive portion of the second measuring electrode sequentially penetrates the etching stop layer and the insulating dielectric layer and contacts the second electrode layer.

19. The memory according to claim 18, wherein: The memory further includes an interlayer dielectric layer, the interlayer dielectric layer is formed between the first electrode layer and the insulating dielectric layer, and the interlayer dielectric layer has a through hole to expose a portion of the first electrode layer; wherein, The strontium titanate dielectric layer comprises a middle portion and an edge portion arranged around the middle portion, wherein the middle portion is formed in the through hole and contacts the first electrode layer, and the edge portion overlaps a surface of the interlayer dielectric layer away from the first electrode layer; The via conductive portion of the first measuring electrode penetrates the etching stop layer and the insulating dielectric layer, and also penetrates the interlayer dielectric layer to contact the edge region of the first electrode layer; The orthographic projection of the via-hole conductive portion of the second measuring electrode on the substrate is located within the orthographic projection of the through hole on the substrate.

20. The memory according to claim 19, wherein: A plurality of via conductive portions are provided in the first measuring electrode and the second measuring electrode, and are arranged at equal intervals around the axis of the through hole.

21. The memory according to claim 17, wherein: The substrate includes a semiconductor base and an insulating isolation layer, and the insulating isolation layer is formed between the first electrode layer and the semiconductor base.

22. A method for manufacturing a memory, the method comprising: providing a substrate; forming a first electrode layer on the substrate; A strontium titanate dielectric layer is formed on a side of the first electrode layer away from the substrate, and in a direction from the center of the strontium titanate dielectric layer to two opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases, and one of the two opposite sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is away from the first electrode layer; A second electrode layer is formed on a side of the strontium titanate dielectric layer away from the first electrode layer to form a capacitor.

23. The manufacturing method according to claim 22, wherein: The step of forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate comprises: Depositing a strontium titanate material on a side of the first electrode layer away from the substrate using a primary atomic layer deposition process to form the strontium titanate dielectric layer; In the primary atomic layer deposition process, the flow rate of the Sr precursor and / or the Ti precursor is adjusted so that the ratio of Sr / (Sr+Ti) in the strontium titanate material gradually increases and then gradually decreases according to a set rule.

24. The manufacturing method according to claim 22, wherein: The step of forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate comprises: N layers of strontium titanate film layers stacked in sequence are formed on a side of the first electrode layer away from the substrate by using N atomic layer deposition processes to form the strontium titanate dielectric layer, where N is a positive integer greater than or equal to 3.

25. The manufacturing method according to claim 22, wherein: Before the step of forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate, the manufacturing method further comprises: forming a first titanium oxide dielectric layer on a side of the first electrode layer away from the substrate; and Before the step of forming the second electrode layer on the side of the strontium titanate dielectric layer away from the first electrode layer, the manufacturing method further comprises: forming a second titanium oxide dielectric layer on the side of the strontium titanate dielectric layer away from the first electrode layer.

26. The manufacturing method according to claim 22, wherein: Before the step of forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate, the manufacturing method further comprises: forming a first aluminum titanate dielectric layer on a side of the first electrode layer away from the substrate; and Before the step of forming the second electrode layer on the side of the strontium titanate dielectric layer away from the first electrode layer, the manufacturing method further comprises: forming a second aluminum titanate dielectric layer on the side of the strontium titanate dielectric layer away from the first electrode layer.

27. The manufacturing method according to claim 26, wherein: The step of forming a first aluminum titanate dielectric layer on a side of the first electrode layer away from the substrate comprises: forming a first titanium oxide dielectric layer on a side of the first electrode layer away from the substrate, and then doping aluminum into the first titanium oxide dielectric layer to form the first aluminum titanate dielectric layer; and The step of forming a second aluminum titanate dielectric layer on a side of the strontium titanate dielectric layer away from the first electrode layer includes forming a second titanium oxide dielectric layer on a side of the strontium titanate dielectric layer away from the first electrode layer, and then doping aluminum elements into the second titanium oxide dielectric layer to form the second aluminum titanate dielectric layer.

28. The manufacturing method according to claim 22, wherein: Before the step of forming a strontium titanate dielectric layer on the side of the first electrode layer away from the substrate, the manufacturing method further comprises: forming an interlayer dielectric material film on the side of the first electrode layer away from the substrate; A through hole exposing the middle area of ​​the first electrode layer is formed on the interlayer dielectric material film by a patterning process, To form an interlayer dielectric layer; Wherein, at least a portion of the strontium titanate dielectric layer is located in the through hole and contacts the first electrode layer.

29. The manufacturing method according to claim 28, wherein: The step of sequentially forming a strontium titanate dielectric layer and a second electrode layer on a side of the first electrode layer away from the substrate comprises: After forming the interlayer dielectric layer, sequentially forming a strontium titanate dielectric material film and a second electrode material film located in the through hole and covering the interlayer dielectric layer; The portions of the strontium titanate dielectric material film and the second electrode material film covering the interlayer dielectric layer are removed to form a strontium titanate dielectric layer and a second electrode layer.

30. The manufacturing method according to claim 29, wherein: After the step of sequentially forming a strontium titanate dielectric layer and a second electrode layer on a side of the first electrode layer away from the substrate, the manufacturing method further comprises: forming an insulating dielectric layer and an etching stop layer in sequence on the side of the interlayer dielectric layer and the second electrode layer away from the substrate; A first via hole and a second via hole are formed, wherein the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the edge region of the first electrode layer on the substrate, and does not overlap with the orthographic projections of the second electrode layer and the strontium titanate dielectric layer on the substrate, the first via hole sequentially penetrates the insulating dielectric layer, the etch stop layer and the interlayer dielectric layer, and exposes a portion of the first electrode layer, the orthographic projection of the second via hole on the substrate is located within the orthographic projection of the through hole on the substrate, the second via hole sequentially penetrates the insulating dielectric layer and the etch stop layer, and exposes a portion of the second electrode layer; forming a measuring electrode material film, wherein the measuring electrode material film covers the surface of the etching stop layer away from the insulating dielectric layer and fills the first via hole and the second via hole; The measuring electrode material film is patterned to form a first measuring electrode and a second measuring electrode, wherein the first measuring electrode and the second measuring electrode both include a via conductive portion and a measuring conductive portion, the measuring conductive portions of the first measuring electrode and the second measuring electrode are spaced apart and are both formed on a side of the etch stop layer away from the substrate, the measuring conductive portion of the first measuring electrode is a measuring electrode material film filled in the first via hole, and the measuring conductive portion of the second measuring electrode is a measuring electrode material film filled in the second via hole.

Images