Baseboard management controller, and basic input / output system debugging method and apparatus

Abstract

Disclosed in the present application are a baseboard management controller, and a basic input / output system debugging method and apparatus, which are applied to the technical field of basic input / output system debugging. The baseboard management controller comprises: a target bus connected to a central processing unit and used for acquiring an access request sent by the central processing unit; a system bus, and a dynamic random access memory mounted on the system bus and used for storing a first basic input / output system image; a bus agent mounted on the system bus and used for configuring a first address range for a preset register and, on the basis of the first address range, forwarding the access request to a memory controller mounted on the system bus, the first address range being an address range in a bus address space of the system bus; and a memory controller, used for accessing the first basic input / output system image in the dynamic random access memory. The present application avoids the problem of lengthy time consumption of basic input / output system refreshing, thereby improving the efficiency of basic input / output system debugging.

Description

Baseboard management controller, basic input and output system debugging method and device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 26, 2023, with application number 202310923265.8, and application name “Baseboard management controller, basic input and output system debugging method and device”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of basic input / output system debugging, and in particular to a baseboard management controller, a basic input / output system debugging method, and a basic input / output system debugging device. Background Art

[0004] During the development phase of server BIOS (Basic Input / Output System), new versions of the BIOS need to be frequently debugged to develop new features and analyze issues. Currently, debugging under common BIOS storage architectures sometimes requires removing the flash memory, inserting a burner, or using a special fixture to refresh the BIOS, resulting in significant inefficiency. Other issues also result in slow BIOS refresh speeds, reducing debugging efficiency.

[0005] Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a baseboard management controller, a basic input and output system debugging method and device, which can improve the efficiency of basic input and output system debugging. The specific solution is as follows:

[0007] In a first aspect, the present application discloses a baseboard management controller, comprising:

[0008] A target bus connected to the central processing unit, for obtaining access requests sent by the central processing unit;

[0009] A system bus, and a dynamic random access memory connected to the system bus, wherein the dynamic random access memory is used to store a first basic input and output system image;

[0010] A bus agent attached to the system bus, configured to allocate a first address range to a preset register and forward an access request based on the first address range to a memory controller attached to the system bus; the first address range being an address range of a first basic input / output system image in a bus address space of the system bus;

[0011] The memory controller is used for accessing the first basic input and output system image in the dynamic random access memory.

[0012] In some embodiments, further comprising:

[0013] A network controller connected to the system bus, configured to obtain a first basic input / output system image based on an out-of-band interface of a baseboard management controller;

[0014] The core component connected to the system bus is used to store the first basic input and output system image in the dynamic random access memory.

[0015] In some embodiments, further comprising:

[0016] The core component connected to the system bus is used to create a virtual basic input and output system image in the dynamic random access memory as a first basic input and output system image.

[0017] In some embodiments, the bus agent is further configured to:

[0018] When the access request is a read request, an interrupt notification is sent to the preset service in the core component, and a data request is sent to the user terminal through the preset service;

[0019] The baseboard management controller also includes: a network controller mounted on the system bus, used to obtain read data returned by the user terminal; accordingly, the core component is also used to write the read data to the first basic input and output system image; wherein the read data is data read from the second basic input and output system image, and the second basic input and output system image is an image pre-loaded into the memory by the user terminal.

[0020] In some embodiments, the bus agent is further configured to:

[0021] When the access request is a write request, the write data carried by the write request is written into the first basic input / output system image, and an interrupt notification is sent to a preset service in the core component. The write data is read from the first basic input / output system image through the preset service and sent to the user terminal, so that the user terminal writes the write data into the second basic input / output system image pre-loaded into its own memory.

[0022] In some embodiments, further comprising:

[0023] The flash memory controller connected to the system bus is used to access the basic input and output system flash memory connected to the flash memory controller.

[0024] In some embodiments, the core component is further configured to program the flash memory controller to write the first BIOS image from the dynamic random access memory to the BIOS flash memory.

[0025] In some embodiments, the core component is further configured to read data from the BIOS flash memory into the dynamic random access memory, and to create a third BIOS image in the dynamic random access memory based on the data;

[0026] Allocate a second address range of the third basic input and output system image in the bus address space to a preset register;

[0027] When an access request for the basic input and output system flash memory sent by the central processing unit is obtained, the third basic input and output system image in the dynamic random access memory is accessed based on the second address range.

[0028] In a second aspect, the present application discloses a basic input / output system debugging method, which is applied to a baseboard management controller, wherein the baseboard management controller is connected to a central processing unit via a target bus, and a basic input / output system flash memory and a dynamic random access memory are mounted on the system bus of the baseboard management controller. The method comprises:

[0029] Allocating a first address range to a preset register; the first address range is an address range of a first basic input / output system image in the dynamic random access memory in a bus address space of a system bus;

[0030] When an access request for the BIOS flash memory sent by the CPU is obtained through the target bus, the first BIOS image in the DRAM is accessed based on the first address range to implement debugging of the BIOS.

[0031] In some embodiments, before allocating the first address range to the preset register, the method further includes:

[0032] A first basic input / output system image is acquired based on an out-of-band interface of a baseboard management controller, and the first basic input / output system image is stored in a dynamic random access memory.

[0033] In some embodiments, after obtaining the first basic input and output system image, the method further includes:

[0034] Parsing layout information of the first basic input / output system image; the layout information includes location and size information of the non-volatile data segment;

[0035] Backing up data in the non-volatile data section of the first basic input / output system image based on the layout information to obtain backup data;

[0036] When a default value restoration request is obtained, the data in the non-volatile data section in the current first basic input / output system image is overwritten based on the backup data.

[0037] In some embodiments, further comprising:

[0038] Obtaining a signature of the first basic input / output system image uploaded by the user terminal; the signature is obtained by encrypting a hash value of the first basic input / output system image using an encryption private key;

[0039] Use the public key to decrypt the signature and obtain the decrypted data;

[0040] Obtain a hash value of the first basic input / output system image uploaded by the user terminal, verify the hash value using the decrypted data, and if the verification passes, trigger a step of obtaining the first basic input / output system image based on the out-of-band interface of the baseboard management controller.

[0041] In some embodiments, further comprising:

[0042] If the dynamic random access memory includes different first basic input and output system images;

[0043] configuring a plurality of groups of preset registers in an address range of a bus address space based on different first basic input / output system images;

[0044] Based on the chip select signal enabled by the central processing unit, the preset register corresponding to the chip select signal is set to be valid;

[0045] An access request sent by the central processing unit is obtained, and a corresponding first basic input / output system image in the dynamic random access memory is accessed based on a valid preset register.

[0046] In some embodiments, before allocating the first address range to the preset register, the method further includes:

[0047] A virtual BIOS image is created in the dynamic random access memory as a first BIOS image.

[0048] In some embodiments, if the access request is a read request, the method further includes:

[0049] Sending an interrupt notification to a preset service, sending a data request to a user terminal through the preset service, obtaining read data returned by the user terminal, and writing the read data to the first basic input / output system image;

[0050] The read data is data read from the second basic input / output system image, and the second basic input / output system image is an image pre-loaded into the memory of the user terminal.

[0051] In some embodiments, if the access request is a write request, the method further includes:

[0052] The write data carried in the write request is written into the first basic input / output system image, and an interrupt notification is sent to the preset service. The write data is read from the first basic input / output system image through the preset service and sent to the user terminal, so that the user terminal writes the write data into the second basic input / output system image pre-loaded into its own memory.

[0053] In some embodiments, further comprising:

[0054] All access requests are collected through a preset service and sent to the user terminal so that the user terminal can perform log recording based on the access requests.

[0055] In some embodiments, further comprising:

[0056] Obtaining a signature of the second basic input / output system image uploaded by the user terminal; the signature is obtained by encrypting a hash value of the second basic input / output system image using an encryption private key;

[0057] Use the public key to decrypt the signature and obtain the decrypted data;

[0058] A hash value of the second BIOS image uploaded by the user terminal is obtained, and the hash value is verified using the decrypted data. If the verification passes, a step of creating a virtual BIOS image in the dynamic random access memory is triggered.

[0059] In some embodiments, further comprising:

[0060] Receive a client program download request sent by a user terminal, respond to the client program download request, and return the client program;

[0061] Accordingly, obtaining the signature of the second basic input and output system image uploaded by the user terminal includes:

[0062] The signature of the second basic input / output system image uploaded by the client is obtained based on the preset service; the client is a client started by the user terminal based on the client program.

[0063] In some embodiments, a memory controller is mounted on a system bus, a dynamic random access memory is mounted on the memory controller, and accessing a first basic input / output system image in the dynamic random access memory based on a first address range includes:

[0064] An access request is sent to a memory controller, and the first basic input / output system image in the dynamic random access memory is accessed through the memory controller.

[0065] In some embodiments, further comprising:

[0066] If the preset register is in the default configuration, an access request for the basic input and output system flash memory sent by the central processing unit is obtained through the target bus, and the basic input and output system flash memory is accessed.

[0067] In some embodiments, a flash memory controller is mounted on the system bus, a basic input / output system flash memory is mounted on the flash memory controller, and accessing the basic input / output system flash memory includes:

[0068] The access request is sent to the flash memory controller, and the basic input and output system flash memory is accessed through the flash memory controller.

[0069] In some embodiments, further comprising:

[0070] Acquire a first basic input / output system image based on an out-of-band interface of a baseboard management controller, and store the first basic input / output system image in a dynamic random access memory;

[0071] The flash memory controller is programmed to write the first basic input and output system image from the dynamic random access memory into the basic input and output system flash memory.

[0072] In some embodiments, further comprising:

[0073] Reading data from the BIOS flash memory into the dynamic random access memory, and creating a third BIOS image in the dynamic random access memory based on the data;

[0074] Allocate a second address range of the third basic input and output system image in the bus address space to a preset register;

[0075] When an access request for the basic input and output system flash memory sent by the central processing unit is obtained, the third basic input and output system image in the dynamic random access memory is accessed based on the second address range.

[0076] In some embodiments, further comprising:

[0077] Mapping different basic input and output system flash memories to a bus address space of a system bus, wherein different basic input and output system flash memories have different address ranges in the bus address space;

[0078] configuring a plurality of preset registers in an address range of a bus address space based on different basic input and output system flash memories;

[0079] Based on the chip select signal enabled by the central processing unit, the preset register corresponding to the chip select signal is set to be valid;

[0080] The access request sent by the central processing unit is obtained, and the corresponding basic input and output system flash memory is accessed based on the valid preset register.

[0081] In some embodiments, a network controller is connected to the system bus for interconnection with an external network.

[0082] In some embodiments, a bus agent is further connected to the system bus, and the bus agent is connected to the central processing unit based on the target bus. Accordingly, the method further includes:

[0083] The bus agent configures the preset register and obtains the access request sent by the central processing unit, and forwards the access request to the corresponding component connected to the system bus based on the configuration of the preset register.

[0084] In a third aspect, the present application discloses a basic input / output system debugging device, which is applied to a baseboard management controller. The baseboard management controller is connected to a central processing unit via a target bus, and a basic input / output system flash memory and a dynamic random access memory are mounted on the system bus of the baseboard management controller. The device includes:

[0085] A register configuration module, configured to configure a first address range to a preset register; the first address range is an address range of a first basic input / output system image in the dynamic random access memory in a bus address space of a system bus;

[0086] An access request obtaining module, configured to obtain an access request for a basic input / output system flash memory sent by a central processing unit via a target bus;

[0087] The image access module is used to access the first basic input and output system image in the dynamic random access memory based on the first address range to implement debugging of the basic input and output system.

[0088] It can be seen that the baseboard management controller provided by the present application includes a target bus connected to the central processing unit, which is used to obtain access requests sent by the central processing unit; a system bus, and a dynamic random access memory mounted on the system bus, which is used to store a first basic input and output system image; a bus agent mounted on the system bus, which is used to configure a first address range to a preset register and forward the access request to a memory controller mounted on the system bus based on the first address range; the first address range is the address range of the first basic input and output system image in the bus address space of the system bus; and the memory controller is used to access the first basic input and output system image in the dynamic random access memory.

[0089] The beneficial effect of the present application is that: the baseboard management controller controls the data bus of the central processing unit connected to the basic input and output system flash memory, maps the access request of the central processing unit to the dynamic random access memory, and realizes the debugging of the basic input and output system. In this way, there is no need to remove the flash memory or plug in a burner or use a special fixture to refresh the basic input and output system, and there is no need to erase the flash memory before writing it, thereby avoiding the problem of long time spent on refreshing the basic input and output system, and can improve the efficiency of basic input and output system debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] In order to more clearly illustrate some embodiments of the present application or the technical solutions in related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0091] FIG1 is a schematic diagram of a first BIOS storage architecture in the related art;

[0092] FIG2 is a schematic diagram of a second BIOS storage architecture in the related art;

[0093] FIG3 is a schematic diagram of a third BIOS storage architecture in the related art;

[0094] FIG4 is a schematic diagram of a fourth BIOS storage architecture in the related art;

[0095] FIG5 is a schematic diagram of the structure of a baseboard management controller disclosed in some embodiments of the present application;

[0096] FIG6 is a schematic diagram of the internal structure of a bus agent disclosed in some embodiments of the present application;

[0097] FIG7 is a flow chart of a basic input / output system debugging method disclosed in some embodiments of the present application;

[0098] FIG8 is a schematic diagram of a basic BIOS Flash access function disclosed in some embodiments of the present application;

[0099] FIG9 is a schematic diagram of an out-of-band BIOS Flash refresh function disclosed in some embodiments of the present application;

[0100] FIG10 is a schematic diagram of a memory-based BIOS debugging solution disclosed in some embodiments of the present application;

[0101] FIG11 is a schematic diagram of a network-based BIOS debugging solution disclosed in some embodiments of the present application;

[0102] FIG12 is a schematic diagram of a BIOS Flash access log format disclosed in some embodiments of the present application;

[0103] FIG13 is a schematic diagram of accelerating BIOS Flash access disclosed in some embodiments of the present application;

[0104] FIG14 is a schematic diagram of a dual BIOS Flash disclosed in some embodiments of the present application;

[0105] FIG15 is a schematic diagram of a bus agent disclosed in some embodiments of the present application;

[0106] FIG16 is a schematic diagram of another dual BIOS Flash disclosed in some embodiments of the present application;

[0107] FIG17 is a schematic diagram of a security mechanism disclosed in some embodiments of the present application;

[0108] FIG18 is a schematic structural diagram of a basic input / output system debugging device disclosed in some embodiments of the present application. DETAILED DESCRIPTION

[0109] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on some embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0110] During the research and development phase of server product BIOS, new versions of BIOS need to be debugged frequently due to the development of new functions and analysis of problems. The storage architecture and update method of BIOS have a great impact on the debugging efficiency of BIOS. BIOS must be stored in a non-volatile readable storage medium that can be directly accessed when the CPU (Central Processing Unit) is powered on. It is usually stored in Flash, and the CPU reads and writes Flash through the LPC (Low Pin Count), SPI (Serial Peripheral Interface) or eSPI (Enhanced SPI) interface. When testing a new version of BIOS, the new BIOS generally needs to be written to Flash before it can be run. The speed of updating BIOS affects the efficiency of BIOS development and debugging. There are four types of existing BIOS storage architectures, corresponding to different update methods:

[0111] Type 1: See Figure 1, which is a schematic diagram of the first BIOS storage architecture in the related art. The BIOS is directly connected to the CPU or chipset via the SPI bus. Taking CPU 0 and CPU 1 as examples, this architecture supports three BIOS update methods: 1) Remove the BIOS Flash (Basic Input / Output System Flash) from the motherboard slot and use a Flash writer to refresh it offline; 2) Plug a writer into a reserved socket on the motherboard to burn the BIOS Flash; 3) After the host boots, the BIOS Flash is refreshed in-band by programming the SPI bus controller.

[0112] Type 2: See Figure 2, which is a schematic diagram of the second BIOS storage architecture in the related art. Based on the Type 1 solution, a MUX (multiplexer) chip is added between the CPU and the BIOS Flash. The MUX chip's selection signal is used to control whether the SPI bus of the BIOS Flash is connected to the CPU or the BMC. The selection signal of the MUX chip is controlled by the GPIO (General Purpose Input Output) of the BMC (Baseboard Management Controller). The buses in Figure 2 all refer to the SPI bus. Under this architecture, in addition to supporting the three BIOS update solutions supported by Type 1, it also supports refreshing the BIOS Flash through the BMC, that is, it supports the out-of-band BIOS refresh function.

[0113] Category 3: See Figure 3, which is a schematic diagram of the third BIOS storage architecture in the related art. This architecture features a PFR (Platform Firmware Resilience) architecture with an independent PRoT (Platform Root of Trust). The buses in Figure 3 all refer to SPI buses. Under this architecture, the supported BIOS refresh methods are the same as those in Category 2, with only some differences in the process details when performing an out-of-band refresh: When performing an out-of-band refresh through the BMC, due to PFR architecture requirements, the BMC does not directly write the new version of the BIOS to the BIOS Flash. Instead, it temporarily stores the file in the reserved space of the BMC Flash. The BMC then notifies the PRoT of the BIOS update task. When the system restarts, the PRoT reads the new version of the BIOS file from the BMC Flash and updates it to the BIOS Flash.

[0114] Type 4: See Figure 4, which illustrates the fourth BIOS storage architecture in the related art. This architecture uses a PFR architecture with the BMC acting as a PRoT. This architecture supports all update methods in Type 2 and, because the BMC itself is a PRoT, avoids the intermediate storage required in Type 3 when performing out-of-band updates.

[0115] Among them, the disadvantage of type 1 architecture is that when a BIOS failure causes the system to fail to boot, the in-band refresh method cannot be used. The only option is to use a burner to refresh the BIOS. This requires the developer to be on-site at the machine, remove the Flash, plug in a burner, or use a special fixture to refresh, which is very inefficient. The main disadvantage of types 2, 3, and 4 architectures is slow update speed. As BIOS functions become increasingly complex, the capacity of BIOS Flash has become larger. The typical capacity of BIOS Flash on current servers is 64MB (megabytes) or 128MB. Furthermore, due to the inherent erase-before-write nature of Flash, a complete update takes several minutes. In applications requiring rapid BIOS iteration and verification, this cannot meet the time requirements of project development. In particular, the PFR architecture, due to the presence of intermediate temporary storage, takes longer to refresh the BIOS. In other words, the current problem of low efficiency in BIOS debugging exists. To this end, this application provides a BIOS debugging solution that can improve the efficiency of BIOS debugging.

[0116] As shown in FIG5 , some embodiments of the present application disclose a baseboard management controller, including:

[0117] A target bus 11 connected to the central processing unit, for obtaining access requests sent by the central processing unit;

[0118] A system bus 12, and a dynamic random access memory 13 connected to the system bus, the dynamic random access memory being used to store a first basic input / output system image;

[0119] A bus agent 14 mounted on the system bus is configured to allocate a first address range to a preset register and forward an access request based on the first address range to a memory controller 15 mounted on the system bus; the first address range is an address range of a first basic input / output system image in a bus address space of the system bus;

[0120] The memory controller 15 is configured to access the first basic input / output system image in the dynamic random access memory.

[0121] It can be seen that some embodiments of the present application control the data bus of the central processing unit connected to the basic input and output system flash memory through the baseboard management controller, and map the access request of the central processing unit to the dynamic random access memory to realize the debugging of the basic input and output system. In this way, there is no need to remove the flash memory or plug in a burner or use a special fixture to refresh the basic input and output system, nor is there any need to erase the flash memory before writing it, thereby avoiding the problem of long time spent on refreshing the basic input and output system and improving the efficiency of debugging the basic input and output system.

[0122] Furthermore, the baseboard management controller further includes:

[0123] A network controller connected to the system bus, configured to obtain a first basic input / output system image based on an out-of-band interface of a baseboard management controller;

[0124] The core component connected to the system bus is used to store the first basic input and output system image in the dynamic random access memory.

[0125] It is understandable that the present application can map the address range of the dynamic random access memory to the bus address space. When the basic input and output system image is stored in the dynamic random access memory, the address range of the image in the bus address space can be determined.

[0126] Furthermore, in one embodiment, the core component connected to the system bus is further configured to create a virtual BIOS image in the dynamic random access memory as the first BIOS image. Accordingly, the bus agent is further configured to:

[0127] When the access request is a read request, an interrupt notification is sent to the preset service in the core component, and a data request is sent to the user terminal through the preset service;

[0128] The network controller connected to the system bus is also used to obtain read data returned by the user terminal; accordingly, the core component is also used to write the read data to the first basic input and output system image; wherein the read data is data read from the second basic input and output system image, and the second basic input and output system image is an image pre-loaded into the memory by the user terminal.

[0129] In addition, the bus agent is further configured to: when the access request is a write request, write the write data carried by the write request into the first basic input / output system image, and send an interrupt notification to a preset service in the core component, read the write data from the first basic input / output system image through the preset service and send the data to the user terminal, so that the user terminal writes the write data into the second basic input / output system image pre-loaded into its own memory.

[0130] Furthermore, the baseboard management controller further includes:

[0131] The flash memory controller connected to the system bus is used to access the BIOS flash memory connected to the flash memory controller. That is, some embodiments of the present application provide access functions for the BIOS flash memory.

[0132] Accordingly, the core component is further configured to program the flash memory controller to write the first BIOS image from the dynamic random access memory to the BIOS flash memory, that is, to provide an out-of-band refresh function for the BIOS flash memory.

[0133] In addition, the core component is further configured to read data from the basic input and output system flash memory into the dynamic random access memory, and to create a third basic input and output system image in the dynamic random access memory based on the data;

[0134] Allocate a second address range of the third basic input and output system image in the bus address space to a preset register;

[0135] When an access request for the BIOS flash memory is received from the CPU, the third BIOS image in the DRAM is accessed based on the second address range. That is, some embodiments of the present application can achieve fast access to the BIOS flash memory.

[0136] It is understood that in some embodiments of the present application, the BMC is connected to the CPU via an SPI or eSPI bus (i.e., the target bus), acting as a slave device of the SPI or eSPI. The BIOS Flash is mounted under the BMC, taking CPU 0 and CPU 1 as an example. In addition, the BMC chip also has memory and network peripherals. The BMC includes the following components:

[0137] System bus: It is the internal system bus of the BMC chip. All functional components in the BMC are connected to this bus. Some components can initiate system bus access as bus masters, while some components can only accept access from other components as bus slaves.

[0138] Bus Agent: See Figure 6, which is a schematic diagram of the internal structure of a bus agent provided in some embodiments of the present application. The bus agent is composed of three modules. The target bus is an SPI / eSPI bus. The target bus slave module is responsible for connecting to the external target bus master and converting SPI / eSPI bus access requests into BMC system bus access requests, which are then forwarded to the system bus master module. The configuration module provides a software programming interface that can be used to influence how the system bus master operates. The system bus master module is responsible for initiating BMC system bus accesses and, based on the information provided by the configuration module, can forward requests from the target bus slave module to different components within the BMC. The configuration module can map BIOS Flash access requests to the BMC address space. The BMC distinguishes between accesses to flash memory and accesses to memory by mapping the BIOS Flash and the BIOS image in memory to different address spaces.

[0139] Flash memory controller: This is a controller with an SPI or eSPI interface, attached to the BMC system bus and connected to the BIOS Flash. Memory controller: This is the controller used by the BMC to access memory, capable of accessing dynamic random access memory (DDR) at double data rate. Network controller: The BMC connects to the external network through the network controller, providing an out-of-band access interface. The network can be a LAN (Local Area Network).

[0140] As shown in FIG7 , some embodiments of the present application disclose a basic input / output system debugging method, which is applied to a baseboard management controller (BMC). The BMC is connected to a central processing unit (CPU) via a target bus, and a basic input / output system flash memory and a dynamic random access memory (DRAM) are connected to the BMC's system bus. The method includes:

[0141] Step S11: Allocate a first address range to a preset register; the first address range is an address range of a first basic input / output system image in the dynamic random access memory in the bus address space of the system bus.

[0142] In some embodiments of the present application, the target bus may be an SPI bus or an eSPI bus.

[0143] In a specific implementation, a network controller is mounted on the system bus for interconnecting with an external network and providing an out-of-band interface.

[0144] In one embodiment, before allocating the first address range to the preset register, the first BIOS image can be obtained via an out-of-band interface of the baseboard management controller and stored in the dynamic random access memory. In other words, the first BIOS image can be obtained via an out-of-band interface provided by the network controller.

[0145] In addition, a signature of the first basic input / output system image uploaded by the user terminal can be obtained; the signature is obtained by encrypting the hash value of the first basic input / output system image using the encryption private key; the signature is decrypted using the public key to obtain decrypted data; the hash value of the first basic input / output system image uploaded by the user terminal is obtained, and the hash value is verified using the decrypted data. If the verification passes, the step of obtaining the first basic input / output system image based on the out-of-band interface of the baseboard management controller is triggered.

[0146] In addition, some embodiments of the present application, after obtaining the first BIOS image, further include: parsing layout information of the first BIOS image; the layout information includes location and size information of non-volatile data segments; backing up data in the non-volatile data segments in the first BIOS image based on the layout information to obtain backup data; and, upon receiving a default value restore request, overwriting data in the non-volatile data segments in the current first BIOS image with the backup data. The non-volatile data segments are used to store data such as user-configured options.

[0147] In another implementation, before allocating the first address range to the preset register, some embodiments of the present application may create a virtual BIOS image in the dynamic random access memory as the first BIOS image.

[0148] In addition, some embodiments of the present application can also obtain a signature of the second basic input and output system image uploaded by the user terminal; the signature is obtained by encrypting the hash value of the second basic input and output system image using an encryption private key; the signature is decrypted using a public key to obtain decrypted data; the hash value of the second basic input and output system image uploaded by the user terminal is obtained, and the hash value is verified using the decrypted data. If the verification passes, the step of creating a virtual basic input and output system image in the dynamic random access memory is triggered.

[0149] Among them, some embodiments of the present application can receive a client program download request sent by a user terminal, and respond to the client program download request and return the client program; accordingly, the signature of the second basic input and output system image uploaded by the client is obtained based on the preset service; the client is a client started by the user terminal based on the client program.

[0150] In a specific implementation, two preset registers, ie, a group of preset registers, may be configured, wherein one is a base register for configuring the starting address of the first address range, and the other is a range register for configuring the range size of the first address range.

[0151] Step S13: when an access request for the BIOS flash memory sent by the CPU is obtained through the target bus, the first BIOS image in the DRAM is accessed based on the first address range to implement debugging of the BIOS.

[0152] In a specific implementation, the access request may be sent to a memory controller, and the first basic input / output system image in the dynamic random access memory may be accessed through the memory controller.

[0153] Furthermore, when the image in the dynamic random access memory is a virtual BIOS image, if the access request is a read request, some embodiments of the present application can send an interrupt notification to a preset service, send a data request to the user terminal via the preset service, obtain the read data returned by the user terminal, and write the read data to the first BIOS image; wherein the read data is data read from the second BIOS image, and the second BIOS image is an image preloaded into the memory of the user terminal. If the access request is a write request, some embodiments of the present application can write the write data carried by the write request to the first BIOS image, send an interrupt notification to the preset service, read the write data from the first BIOS image via the preset service, and send it to the user terminal, so that the user terminal can write the write data to the second BIOS image preloaded into its own memory.

[0154] Furthermore, some embodiments of the present application may collect all access requests through a preset service and send the access requests to the user terminal so that the user terminal performs log recording based on the access requests.

[0155] In addition, in some embodiments of the present application, if the dynamic random access memory includes different first basic input and output system images, the different first basic input and output system images have different address ranges in the bus address space; multiple sets of preset registers are configured based on the address ranges of the different first basic input and output system images in the bus address space; based on the chip select signal enabled by the central processing unit, the preset register corresponding to the chip select signal is set to be valid; the access request sent by the central processing unit is obtained, and the corresponding first basic input and output system image in the dynamic random access memory is accessed based on the valid preset register. That is, the present application can obtain multiple different first basic input and output system images based on the out-of-band interface of the baseboard management controller, and store the multiple different first basic input and output system images in the dynamic random access memory. In addition, multiple virtual basic input and output system images can also be created in the dynamic random access memory, and multiple sets of preset registers can be configured for multiple first basic input and output system images.

[0156] Furthermore, in some embodiments of the present application, if the preset register is in the default configuration, an access request for the BIOS flash memory sent by the CPU is obtained via the target bus, and the BIOS flash memory is accessed. That is, some embodiments of the present application provide access functionality to the BIOS flash memory. Furthermore, a flash memory controller is connected to the system bus, and the access request can be sent to the flash memory controller, and the BIOS flash memory can be accessed via the flash memory controller.

[0157] Furthermore, some embodiments of the present application can obtain a first BIOS image based on an out-of-band interface of a baseboard management controller and store the first BIOS image in a dynamic random access memory (DRAM); and program a flash memory controller to write the first BIOS image from the dynamic random access memory to the BIOS flash memory. This provides an out-of-band BIOS flash memory refresh function.

[0158] Furthermore, data in the BIOS flash memory can be read into the dynamic random access memory, and a third BIOS image can be created in the dynamic random access memory based on the data; a second address range of the third BIOS image in the bus address space can be allocated to a preset register; when an access request for the BIOS flash memory is received from the central processing unit, the third BIOS image in the dynamic random access memory is accessed based on the second address range; and when booting is complete, the current third BIOS image is synchronized with the BIOS flash memory. In other words, some embodiments of the present application can achieve fast access to the BIOS flash memory.

[0159] Furthermore, some embodiments of the present application can map different BIOS flash memories to the bus address space of the system bus, with different BIOS flash memories having different address ranges in the bus address space; configure multiple sets of preset registers based on the address ranges of the different BIOS flash memories in the bus address space; set the preset register corresponding to the chip select signal to be valid based on a chip select signal enabled by the central processing unit; obtain an access request sent by the central processing unit, and access the corresponding BIOS flash memory based on the valid preset register. In other words, some embodiments of the present application support multiple BIOS flash memories.

[0160] Furthermore, the system bus is also connected to a bus agent, which is connected to the central processing unit based on the target bus. Accordingly, some embodiments of the present application configure preset registers through the bus agent and obtain access requests sent by the central processing unit, and forward the access requests to the corresponding components connected to the system bus based on the configuration of the preset registers.

[0161] Further, referring to Figure 8, Figure 8 is a schematic diagram of a basic BIOS Flash access function disclosed in some embodiments of the present application. This function implements the most basic CPU access to BIOS Flash function, that is, the SPI / eSPI agent (i.e., bus agent) initiates a system bus request and forwards the BIOS Flash access request sent by the CPU to the flash controller; the working method is as follows: 8.1. The BIOS Flash access issued by the CPU will be received by the SPI / eSPI agent; 8.2. The SPI / eSPI agent (under the default configuration) will initiate a BMC system bus request and send the BIOS Flash access request to the flash controller; 8.3. The flash controller executes a specific Flash access and returns the data according to the original path. This embodiment has no effect on the original BIOS Flash update function, and offline burning and in-band refresh can work normally.

[0162] Referring to Figure 9, Figure 9 is a schematic diagram of an out-of-band BIOS Flash refresh function disclosed in some embodiments of the present application. Specifically, the BIOS image is uploaded to the BMC memory via an out-of-band interface, and the BMC firmware executes a refresh process to write the BIOS image to the BIOS Flash. The operation is as follows: 9.1. The user uses a terminal device to access the Web (i.e., World Wide Web) service running on the BMC and calls the out-of-band refresh interface to initiate the BIOS Flash refresh process; 9.2. After the user uploads the new version of the BIOS image file, it is stored in the BMC memory; 9.3. The refresh program runs on the BMC core to program the flash memory controller; 9.4. The BIOS image is written from the memory to the BIOS Flash.

[0163] Referring to Figure 10, Figure 10 is a schematic diagram of a memory-based BIOS debugging solution disclosed in some embodiments of this application. Specifically, the BIOS image is uploaded out-of-band to a certain area in the BMC memory, and the SPI / eSPI proxy is configured to enable the execution of the BIOS image in memory. The operation is as follows: 10.1. The memory-based BIOS debugging process is initiated through the out-of-band interface provided by the BMC; 10.2. After the new version of the BIOS image file is uploaded, it is stored in a certain area in the memory; 10.3. The configuration module configures the base address and size information of the BIOS image in memory into the registers of the SPI / eSPI proxy, thereby forwarding BIOS Flash access requests to the memory controller; 10.4. The user starts the server to debug the new BIOS image. During this process, the BIOS Flash access request sent by the CPU is forwarded by the SPI / eSPI proxy to the memory controller, directly accessing the BIOS image stored in memory; 10.5. After the BIOS debugging is completed, the user downloads the final state of the BIOS image through the BMC out-of-band interface, making it easier to locate problems by checking the image changes.

[0164] Furthermore, the process of BIOS default values ​​in some embodiments of the present application may include: 1) the user establishes a connection with the service process on the BMC through a browser on the terminal to start the memory-based BIOS debugging process; 2) the user loads the BIOS file, fills in the BIOS layout information (including the location and size of the NVRAM (i.e., Non-Volatile RAM) segment), uploads it, and the BIOS image is uploaded to the BMC; 3) the BMC creates a BIOS image in the memory, parses the BIOS layout information, and backs up the NVRAM area data for use when restoring the default values; 4) the user initiates a request through the terminal to restore the default values; 5) the BMC uses the previous original NVRAM area data backup to overwrite part of the BIOS image.

[0165] Refer to Figure 11, which is a schematic diagram of a network-based BIOS debugging solution disclosed in some embodiments of the present application. The working method is as follows: 11.1. The user starts the client process on the BIOS development machine (i.e., the user terminal) and establishes a connection with the preset service process on the BMC; 11.2. The user selects the BIOS file to be debugged on the disk through the client process and loads it into the memory; 11.3. The preset service process creates a virtual BIOS image in the BMC's memory and configures the starting address and range to the configuration module of the SPI / eSPI agent, so that it forwards the BIOS Flash access to the memory; 11.4. Flash read and write requests are handled differently: For read requests, the SPI / eSPI proxy sends an interrupt to notify the preset service process. The preset service process requests data from the client and fills it into the corresponding location in the virtual BIOS image. After the interrupt returns, the memory controller returns the data from the corresponding location in the virtual BIOS image to the SPI / eSPI proxy. For write requests, the SPI / eSPI proxy writes the data to the corresponding location in the virtual BIOS image and sends an interrupt to notify the preset service process. The preset service process reads the data from the corresponding location in the virtual BIOS image and sends it to the client. 11.5. The interrupt handler in the preset service process collects all access requests from the SPI / eSPI proxy to the virtual BIOS image. 11.6. The preset service process sends all access requests to the BIOS image to the client process via the network. 11.7. The client logs all read requests and, in addition to logging write requests, synchronizes them to the BIOS image in the memory of the BIOS development machine. See Figure 12, which is a schematic diagram of a BIOS Flash access log format disclosed in some embodiments of the present application. It includes the operation type, starting address, size, and data. 11.8. The client process writes the updated BIOS image in the memory to the disk file at any time.

[0166] Furthermore, the process of BIOS default values ​​in some embodiments of the present application may include: 1) the user establishes a secure connection with the preset service on the BMC through a browser on the BIOS development machine, downloads the client program, and executes it; 2) the user loads the BIOS file through the client process, fills in the BIOS layout information (including the location and size of the NVRAM segment), and backs up the NVRAM area data for use when restoring the default values; 3) the BMC creates a virtual BIOS image in the memory and configures the SPI / eSPI agent to start debugging; 4) the user initiates a request through the client to restore the default values; 5) the client uses the previous original NVRAM area data backup to overwrite the corresponding part in the BIOS image.

[0167] Referring to Figure 13, Figure 13 is a schematic diagram of an accelerated BIOS Flash access provided by some embodiments of the present application. The operation method is as follows: 13.1. When the BMC boots up, the BMC firmware creates a BIOS image in the BMC's memory and configures the starting address and range in the SPI / eSPI agent's configuration module, causing it to forward BIOS Flash access to the memory; 13.2. The BMC firmware reads data from the BIOS Flash and synchronizes it to the BIOS image; 13.3. The SPI / eSPI agent forwards the BIOS Flash access request sent by the CPU to the specified memory area and accesses the BIOS image in the memory; 13.4. After the boot is complete, the BIOS firmware synchronizes the BIOS image in the memory to the BIOS Flash.

[0168] Referring to FIG14 , FIG14 is a schematic diagram of a dual BIOS Flash provided by some embodiments of the present application. The working method is as follows: 1) The BMC maps different BIOS Flashes to different address spaces, and the two BIOS images in the memory are also in different address spaces; 2) The internal configuration module of the SPI / eSPI agent sets two sets of base address / range registers to record the address base and range of the two BIOS Flashes (or the two BIOS images in the memory) in the BMC address space; 3) When the CPU enables CS0 (chip select signal 0), the configuration module sets CS0_BASE (base address register 0) / CS0_LIMIT (range register 0) to valid, and maps access initiated by the BMC Bus Master (bus master device) to BIOS Flash 0 (or BIOS image 0 in the memory); when the CPU enables CS1 (chip select signal 1), the configuration module sets CS1_BASE (base address register 1) / CS1_LIMIT (range register 1) to valid, and maps access initiated by the BMC Bus Master to BIOS Flash 1 (or BIOS image 1 in the memory). Referring to FIG15 , FIG15 is a schematic diagram of a bus agent disclosed in some embodiments of the present application. 15.1. Configure two groups of registers. 15.2. Enable the registers via a chip select signal.

[0169] Refer to Figure 16, which is another dual BIOS Flash schematic diagram provided by some embodiments of the present application. Relative to the scheme in Figure 11, the specific working method can refer to the scheme corresponding to Figure 11. Some embodiments of the present application have the following changes: 1) The client process on the BIOS development machine needs to load two BIOS files: BIOS file 0 and BIOS file 1, and create BIOS images 0 and 1 in the memory respectively; 2) The preset service process on the BMC creates BIOS images 0 and 1 in the BMC memory, and configures the CS0_BASE / CS0_LIMIT and CS1_BASE / CS1_LIMIT registers in the SPI / eSPI agent; 3) The preset service process on the BMC monitors all operations of the two BIOS images and synchronizes them to the client process; 4) After the startup is completed, the client process synchronizes the two BIOS images in the memory to the disk file.

[0170] Refer to Figure 17, which is a schematic diagram of a security mechanism provided by some embodiments of the present application. It works as follows: 1) The user establishes a secure connection with the preset service on the BMC through a browser on the BIOS development machine, downloads the client program, and executes it; 2) The user loads the signed BIOS file through the client process; 3) The client process uploads the BIOS image signature to the preset service process on the BMC; 4) The preset service process uses the public key to decrypt the signature; 5) The client process calculates the hash (an algorithm) of the BIOS image data in the BIOS file; 6) The client uploads the hash to the preset service process on the BMC for verification to obtain the verification result; 7) If the verification passes, the subsequent BIOS image mounting process is executed.

[0171] It can be seen that this application solves the problem of low efficiency of debugging BIOS in the original solution by implementing a new BMC chip architecture, and supports remote, convenient and efficient debugging of BIOS. The BMC fully controls the data bus connecting the Host to the Flash, and can flexibly map the Host's Flash request to multiple targets, including DRAM (a computer memory technology) and the network. When mapped to the BIOS area of ​​DRAM, the development and debugging of BIOS can quickly deploy a new BIOS over the network. Moreover, it is transparent to the CPU side and does not require any changes on the CPU side. It is transparent to the BIOS firmware code and does not require any changes to the BIOS code. In addition, this application can be used in scenarios where the BMC is used as the system's trusted root to achieve the purpose of the BMC monitoring and controlling the Host Flash bus. It can also be used to debug scenarios with dual BIOS Flash solutions. All BIOS Flash access logs can be recorded.

[0172] As shown in FIG18 , some embodiments of the present application disclose a basic input / output system debugging device, which is applied to a baseboard management controller (BMC). The BMC is connected to a central processing unit (CPU) via a target bus, and a basic input / output system flash memory and a dynamic random access memory (DRAM) are connected to the BMC's system bus. The device includes:

[0173] The register configuration module 21 is configured to configure a first address range to a preset register; the first address range is an address range of a first basic input / output system image in the dynamic random access memory in the bus address space of the system bus;

[0174] An access request obtaining module 22 is configured to obtain an access request for a basic input / output system flash memory sent by a central processing unit via a target bus;

[0175] The image access module 23 is configured to access the first BIOS image in the dynamic random access memory based on the first address range to implement debugging of the BIOS.

[0176] It can be seen that some embodiments of the present application

[0177] The baseboard management controller controls the data bus connecting the central processing unit to the basic input and output system flash memory, maps the central processing unit's access request to the dynamic random access memory, and realizes the debugging of the basic input and output system. In this way, there is no need to remove the flash memory or plug in a burner or use a special fixture to refresh the basic input and output system, nor is there a need to erase the flash memory before writing it, avoiding the problem of long refresh time of the basic input and output system and improving the efficiency of basic input and output system debugging.

[0178] In one embodiment, the apparatus further comprises:

[0179] The first basic input / output system image creation module is configured to obtain the first basic input / output system image based on the out-of-band interface of the baseboard management controller, and store the first basic input / output system image in the dynamic random access memory.

[0180] Furthermore, the device also includes:

[0181] A layout information parsing module, configured to parse layout information of the first basic input / output system image; the layout information includes location and size information of the non-volatile data segment;

[0182] a data backup module, configured to back up data in the non-volatile data section of the first basic input / output system image based on the layout information to obtain backup data;

[0183] The default value restoration module is configured to overwrite the data in the non-volatile data section in the current first basic input / output system image based on the backup data when a default value restoration request is obtained.

[0184] Furthermore, the device also includes:

[0185] The first security verification module is configured to obtain a signature of a first basic input / output system image uploaded by a user terminal; the signature is obtained by encrypting a hash value of the first basic input / output system image using an encryption private key; the signature is decrypted using a public key to obtain decrypted data; the hash value of the first basic input / output system image uploaded by the user terminal is obtained, the hash value is verified using the decrypted data, and if the verification passes, a step of obtaining the first basic input / output system image via an out-of-band interface of a baseboard management controller is triggered.

[0186] If the dynamic random access memory includes different first basic input and output system image register configuration modules 21, the module is further configured to configure multiple sets of preset registers in the address range of the bus address space based on the different first basic input and output system images; based on the chip select signal enabled by the central processing unit, the preset register corresponding to the chip select signal is set to be valid; the access request acquisition module 22 is used to acquire the access request sent by the central processing unit; and the image access module 23 is used to access the corresponding first basic input and output system image in the dynamic random access memory based on the valid preset register.

[0187] In another embodiment, the apparatus further comprises:

[0188] The virtual image creation module is used to create a virtual basic input and output system image in the dynamic random access memory as a first basic input and output system image.

[0189] Accordingly, the apparatus is further configured to: if the access request is a read request, send an interrupt notification to a preset service, send a data request to a user terminal via the preset service, obtain read data returned by the user terminal, and write the read data to the first BIOS image; wherein the read data is data read from the second BIOS image, which is an image preloaded into the memory of the user terminal. If the access request is a write request, write the write data carried in the write request to the first BIOS image, send an interrupt notification to the preset service, read the write data from the first BIOS image via the preset service, and send the data to the user terminal, so that the user terminal can write the write data to the second BIOS image preloaded into its own memory.

[0190] Furthermore, the device also includes an access request collection module, which is used to collect all access requests through a preset service and send the access requests to the user terminal so that the user terminal can perform log recording based on the access requests.

[0191] Furthermore, the device also includes:

[0192] The second security verification module is configured to obtain a signature of a second BIOS image uploaded by a user terminal; the signature is obtained by encrypting a hash value of the second BIOS image using a private encryption key; the signature is decrypted using a public key to obtain decrypted data; the hash value of the second BIOS image uploaded by the user terminal is obtained, the hash value is verified using the decrypted data, and if the verification passes, a step of creating a virtual BIOS image in a dynamic random access memory is triggered.

[0193] Furthermore, the second security verification module is also used to: receive a client program download request sent by the user terminal, and respond to the client program download request and return the client program; obtain the signature of the second basic input and output system image uploaded by the client based on the preset service; the client is a client started by the user terminal based on the client program.

[0194] In a specific implementation, a memory controller is mounted on the system bus, the dynamic random access memory is mounted on the memory controller, and the mirror access module 23 is specifically used to send an access request to the memory controller and access the first basic input and output system mirror in the dynamic random access memory through the memory controller.

[0195] Furthermore, the device is further configured to obtain an access request for the basic input and output system flash memory sent by the central processing unit through the target bus if the preset register is in a default configuration, and access the basic input and output system flash memory.

[0196] In a specific implementation, a flash memory controller is mounted on the system bus, and the basic input and output system flash memory is mounted on the flash memory controller. The device is specifically used to send an access request to the flash memory controller and access the basic input and output system flash memory through the flash memory controller.

[0197] Furthermore, the device also includes: an out-of-band refresh module, which is used to obtain the first basic input and output system image based on the out-of-band interface of the baseboard management controller and store the first basic input and output system image in the dynamic random access memory; programming the flash memory controller to write the first basic input and output system image from the dynamic random access memory to the basic input and output system flash memory.

[0198] Furthermore, the device also includes: a flash memory fast access module, which is used to read data from the basic input and output system flash memory into the dynamic random access memory, and establish a third basic input and output system image in the dynamic random access memory based on the data; configure the second address range of the third basic input and output system image in the bus address space to a preset register; and when an access request for the basic input and output system flash memory sent by the central processing unit is obtained, access the third basic input and output system image in the dynamic random access memory based on the second address range.

[0199] Furthermore, the device is also used to: map different basic input and output system flash memories to the bus address space of the system bus, and different basic input and output system flash memories have different address ranges in the bus address space; configure multiple groups of preset registers based on the address ranges of different basic input and output system flash memories in the bus address space; set the preset register corresponding to the chip select signal to be valid based on the chip select signal enabled by the central processing unit; obtain the access request sent by the central processing unit, and access the corresponding basic input and output system flash memory based on the valid preset register.

[0200] In addition, the system bus is connected to a network controller for interconnection with an external network.

[0201] Furthermore, the system bus is also connected to a bus agent, which is connected to the central processing unit based on the target bus. The bus agent is used to configure preset registers and obtain access requests sent by the central processing unit, and forward the access requests to the corresponding components connected to the system bus based on the configuration of the preset registers.

[0202] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0203] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM (Compact Disc Read Only Memory), or any other form of non-volatile readable storage medium known in the art.

[0204] The above is a detailed introduction to the baseboard management controller, basic input and output system debugging method, and device provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A baseboard management controller, characterized in that: include: A target bus connected to the central processing unit, configured to obtain an access request sent by the central processing unit; A system bus, and a dynamic random access memory connected to the system bus, wherein the dynamic random access memory is configured to store a first basic input / output system image; A bus agent attached to the system bus is configured to configure a first address range to a preset register and forward the access request to a memory controller attached to the system bus based on the first address range; the first address range is an address range of the first basic input / output system mirror in a bus address space of the system bus; The memory controller is configured to access the first basic input / output system image in the dynamic random access memory.

2. The baseboard management controller according to claim 1, characterized in that: Also includes: A network controller connected to the system bus is configured to obtain the first basic input / output system image based on an out-of-band interface of the baseboard management controller; The core component mounted on the system bus is configured to store the first basic input / output system image in the dynamic random access memory.

3. The baseboard management controller according to claim 1, characterized in that: Also includes: The core component mounted on the system bus is configured to create a virtual basic input / output system image in the dynamic random access memory as the first basic input / output system image.

4. The baseboard management controller according to claim 3, characterized in that: The bus agent is also configured to: When the access request is a read request, an interrupt notification is sent to a preset service in the core component, and a data request is sent to the user terminal through the preset service; The baseboard management controller also includes: a network controller mounted on the system bus, configured to obtain read data returned by the user terminal; correspondingly, the core component is also configured to write the read data into the first basic input / output system image; wherein the read data is data read from a second basic input / output system image, and the second basic input / output system image is an image pre-loaded into the memory by the user terminal.

5. The baseboard management controller according to claim 4, characterized in that: The bus agent is also configured to: When the access request is a write request, write data carried by the write request is written into the first basic input / output system image, and an interrupt notification is sent to a preset service in the core component. The write data is read from the first basic input / output system image through the preset service and sent to a user terminal, so that the user terminal writes the write data into a second basic input / output system image pre-loaded into its own memory.

6. The baseboard management controller according to claim 2, characterized in that: Also includes: The flash memory controller connected to the system bus is configured to access the basic input / output system flash memory connected to the flash memory controller.

7. The baseboard management controller according to claim 6, characterized in that: The core component is further configured to program the flash memory controller to write the first BIOS image from the dynamic random access memory to the BIOS flash memory.

8. The baseboard management controller according to claim 6, characterized in that: The core component is further configured to read data in the basic input and output system flash memory into the dynamic random access memory, and to establish a third basic input and output system image in the dynamic random access memory based on the data; Allocate the second address range of the third basic input and output system image in the bus address space to a preset register; When an access request for the BIOS flash memory sent by the central processing unit is obtained, the third BIOS image in the dynamic random access memory is accessed based on the second address range.

9. A basic input and output system debugging method, characterized in that: It should be set as a baseboard management controller, the baseboard management controller is connected to the central processing unit through a target bus, and the system bus of the baseboard management controller is connected with a basic input and output system flash memory and a dynamic random access memory, and the method includes: Allocate a first address range to a preset register; the first address range is an address range of a first basic input / output system image in the dynamic random access memory in a bus address space of the system bus; When the access request for the BIOS flash memory sent by the CPU is obtained through the target bus, the first BIOS image in the dynamic random access memory is accessed based on the first address range to implement debugging of the BIOS.

10. The basic input and output system debugging method according to claim 9, characterized in that: Before configuring the first address range to the preset register, the method further includes: The first basic input / output system image is acquired based on the out-of-band interface of the baseboard management controller, and the first basic input / output system image is stored in the dynamic random access memory.

11. The basic input and output system debugging method according to claim 10, characterized in that: After obtaining the first basic input and output system image, the method further includes: Parsing layout information of the first basic input / output system image; the layout information includes location and size information of the non-volatile data segment; Backing up the data of the non-volatile data section in the first basic input / output system image based on the layout information to obtain backup data; When a default value restoration request is obtained, the data in the non-volatile data section in the current first basic input / output system image is overwritten based on the backup data.

12. The basic input and output system debugging method according to claim 10, characterized in that: Also includes: Obtaining a signature of the first basic input / output system image uploaded by the user terminal; The signature is obtained by encrypting the hash value of the first basic input / output system image using an encryption private key; Decrypt the signature using the public key to obtain decrypted data; Obtain a hash value of the first basic input / output system image uploaded by the user terminal, verify the hash value using the decrypted data, and if the verification passes, trigger a step of obtaining the first basic input / output system image based on the out-of-band interface of the baseboard management controller.

13. The basic input and output system debugging method according to claim 9, characterized in that: Also includes: If the dynamic random access memory includes different first basic input and output system images; configuring a plurality of groups of preset registers in the address range of the bus address space based on different first basic input and output system images; Based on the chip select signal enabled by the central processing unit, setting the preset register corresponding to the chip select signal to be valid; An access request sent by the central processing unit is obtained, and a corresponding first basic input / output system image in the dynamic random access memory is accessed based on a valid preset register.

14. The basic input and output system debugging method according to claim 9, characterized in that: Before configuring the first address range to the preset register, the method further includes: A virtual basic input / output system image is created in the dynamic random access memory as the first basic input / output system image.

15. The basic input and output system debugging method according to claim 14, characterized in that: If the access request is a read request, the method further includes: Sending an interrupt notification to a preset service, sending a data request to a user terminal through the preset service, acquiring read data returned by the user terminal and writing the read data to the first basic input / output system image; The read data is data read from a second basic input / output system image, and the second basic input / output system image is an image pre-loaded into a memory of the user terminal.

16. The basic input and output system debugging method according to claim 14, characterized in that: If the access request is a write request, the method further includes: The write data carried by the write request is written into the first basic input / output system image, and an interrupt notification is sent to a preset service. The write data is read from the first basic input / output system image through the preset service and sent to a user terminal, so that the user terminal writes the write data into a second basic input / output system image pre-loaded into its own memory.

17. The basic input and output system debugging method according to claim 14, characterized in that: Also includes: All the access requests are collected through a preset service, and the access requests are sent to a user terminal so that the user terminal performs log recording based on the access requests.

18. The basic input and output system debugging method according to claim 15, characterized in that: Also includes: Obtaining a signature of a second basic input / output system image uploaded by the user terminal; The signature is obtained by encrypting the hash value of the second basic input and output system image using an encryption private key; Decrypt the signature using the public key to obtain decrypted data; A hash value of the second basic input / output system image uploaded by the user terminal is obtained, and the hash value is verified using the decrypted data. If the verification passes, a step of creating a virtual basic input / output system image in the dynamic random access memory is triggered.

19. The basic input and output system debugging method according to claim 18, characterized in that: Also includes: receiving a client program download request sent by the user terminal, responding to the client program download request, and returning the client program; Correspondingly, the step of obtaining the signature of the second basic input / output system image uploaded by the user terminal includes: Acquire a signature of a second basic input / output system image uploaded by the client based on the preset service; The client is a client started by the user terminal based on the client program.

20. The basic input and output system debugging method according to claim 9, characterized in that: The system bus is connected to a memory controller, the dynamic random access memory is connected to the memory controller, and the first basic input / output system image in the dynamic random access memory is accessed based on the first address range, including: The access request is sent to the memory controller, and the dynamic random The first basic input and output system image in the memory is accessed.

21. The basic input and output system debugging method according to claim 9, characterized in that: Also includes: If the preset register is in a default configuration, an access request for the basic input / output system flash memory sent by the central processing unit is obtained through the target bus, and the basic input / output system flash memory is accessed.

22. The basic input and output system debugging method according to claim 21, characterized in that: The system bus is connected to a flash memory controller, the basic input and output system flash memory is connected to the flash memory controller, and the accessing of the basic input and output system flash memory includes: The access request is sent to a flash memory controller, and the basic input and output system flash memory is accessed through the flash memory controller.

23. The basic input and output system debugging method according to claim 22, characterized in that: Also includes: Acquire the first basic input / output system image based on the out-of-band interface of the baseboard management controller, and store the first basic input / output system image in the dynamic random access memory; The flash memory controller is programmed to write the first BIOS image from the dynamic random access memory to the BIOS flash memory.

24. The basic input and output system debugging method according to claim 9, characterized in that: Also includes: Reading data in the basic input and output system flash memory into the dynamic random access memory, and establishing a third basic input and output system image in the dynamic random access memory based on the data; Allocate the second address range of the third basic input and output system image in the bus address space to a preset register; When an access request for the BIOS flash memory sent by the central processing unit is obtained, the third BIOS image in the dynamic random access memory is accessed based on the second address range.

25. The basic input and output system debugging method according to claim 9, characterized in that: Also includes: Mapping different basic input and output system flash memories to the bus address space of the system bus, wherein different basic input and output system flash memories have different address ranges in the bus address space; configuring a plurality of groups of preset registers in the address range of the bus address space based on different basic input and output system flash memories; Based on the chip select signal enabled by the central processing unit, setting the preset register corresponding to the chip select signal to be valid; An access request sent by the central processing unit is obtained, and a corresponding basic input / output system flash memory is accessed based on a valid preset register.

26. The basic input and output system debugging method according to claim 9, characterized in that: The system bus is connected with a network controller and is configured to be interconnected with an external network.

27. The basic input and output system debugging method according to claim 9, characterized in that: The system bus is also connected to a bus agent, and the bus agent is connected to the central processing unit based on the target bus. Accordingly, the method further includes: The bus agent configures a preset register and obtains an access request sent by the central processing unit, and forwards the access request to a corresponding component connected to the system bus based on the configuration of the preset register.

28. A basic input and output system debugging device, characterized in that: It should be set as a baseboard management controller, the baseboard management controller is connected to the central processing unit through a target bus, and the system bus of the baseboard management controller is connected with a basic input and output system flash memory and a dynamic random access memory, and the device includes: A register configuration module is configured to configure a first address range to a preset register; the first address range is an address range of a first basic input / output system image in the dynamic random access memory in a bus address space of the system bus; an access request acquisition module, configured to acquire, via the target bus, an access request for the basic input and output system flash memory sent by the central processing unit; The image access module is configured to access the first basic input / output system image in the dynamic random access memory based on the first address range to implement debugging of the basic input / output system.

Images