Semiconductor device

Abstract

The present invention prevents decreases in heat dissipation.　A semiconductor device (1) includes: an insulating circuit board (20) having a lower surface (23a); a heat dissipation base plate (40) including a front surface (40a), and having a placement region (40b) where the lower surface (23a) of the insulating circuit board (20) is placed on the front surface (40a) via a solder (27); a plating film (41) which is formed on the front surface (40a) of the heat dissipation base plate (40) except for at a solder region where the solder (27) is spread over the placement region (40b) of the front surface (40a); and an alloy layer which is included between the solder (27) and the placement region (40b) of the heat dissipation base plate (40), and contains solder components contained in the solder (27). In particular, in the semiconductor device (1), the plating film (41) is formed on the entire surface of the heat dissipation base plate (40) excluding an open region (41a) that surrounds the outer perimeter of the periphery of the placement region (40b) where the insulating circuit board (20) is placed via the solder (27).

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A semiconductor device includes a metal base and an insulating substrate mounted on the metal base via solder (see, for example, Patent Document 1). Another example includes a collector lead frame and a semiconductor element mounted on the collector lead frame via solder (see, for example, Patent Document 2). Alternatively, a concave depression is formed on the upper surface of a base material, a plating layer is formed on the upper surface including the depression, and the lower surface of the base material and the upper surface on which the plating layer is formed are polished. As a result, the plating layer filling the depression of the base material functions as a through electrode (see, for example, Patent Document 3). Furthermore, a copper plating film can be formed in the pattern formation area by electroless reduction plating using a resist pattern formed on a base substrate as a plating prevention film (see, for example, Patent Document 4). Furthermore, the plating film can be removed by laser irradiation (see, for example, Patent Document 5).

[0003] JP 2019-080014 A JP 2018-085360 A JP 2013-055114 A JP 2012-140705 A JP 10-183382 A

[0004] An object of the present invention is to provide a semiconductor device in which a decrease in heat dissipation performance is prevented.

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising: a substrate including a lower surface; a heat dissipation base plate including a main surface and having an arrangement area on the main surface where the lower surface of the substrate is arranged via solder; a first plating film formed on the main surface of the heat dissipation base plate except for a solder area where the solder has spread over the arrangement area on the main surface; and an alloy layer included between the solder and the arrangement area of ​​the heat dissipation base plate, the alloy layer including solder components contained in the solder.

[0006] The alloy layer may further contain, in addition to the solder component, a first metal material contained in the heat dissipation base plate, and the first metal material may include copper.

[0007] The first plating film may be primarily composed of nickel. The periphery of the placement area may be located inside the periphery of the substrate in a plan view. The first plating film may be formed on the main surface of the heat dissipation base plate, excluding an opening area that surrounds the entire periphery of the solder area.

[0008] The placement area may be recessed relative to the main surface excluding the placement area. The solder may include a fillet portion extending outward from the lower surface of the substrate in a plan view. An outer periphery of the fillet portion of the solder may be located outside the placement area in a plan view.

[0009] The substrate may include an insulating plate, a conductive pattern formed on the front surface of the insulating plate, and a metal plate formed on the back surface of the insulating plate and including the lower surface, and a second plating film may be formed on the side of the metal plate, surrounding the entire outer periphery of the lower surface except for the lower surface.

[0010] The metal plate may be primarily composed of copper, the second plating film may be primarily composed of nickel, and a resist material may be formed to surround the entire periphery of an opening edge portion of the first plating film formed on the front surface of the heat dissipation base plate.

[0011] The alloy layer may further include a second metal material that constitutes the first plating film together with the solder component and the first metal material, and the second metal material may include nickel.

[0012] The first plating film may be formed on a surface of the heat dissipation base plate excluding the main surface, and the thickness of the first plating film formed on the main surface may be thinner than the thickness of the first plating film formed on the surface excluding the main surface. The thickness of the first plating film formed on the main surface may be less than 0.2 μm.

[0013] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0014] According to the disclosed technology, the deterioration of heat dissipation can be prevented, and the deterioration of reliability can be suppressed. The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings which show preferred embodiments of the present invention as examples.

[0015] 1 is a cross-sectional view of a semiconductor device according to a first embodiment; FIG. 2 is a plan view of a main part of the semiconductor device according to the first embodiment (without a sealing member); FIG. 3 is a flowchart showing a manufacturing method of a semiconductor device according to the first embodiment; FIG. 4 is a plan view showing a manufacturing process of a heat dissipation unit (preparation of a heat dissipation base plate) included in the manufacturing method of a semiconductor device according to the first embodiment; FIG. 5 is a plan view showing a manufacturing process of a heat dissipation unit (plating treatment) included in the manufacturing method of a semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a manufacturing process of a heat dissipation unit (grinding treatment) included in the manufacturing method of a semiconductor device according to the first embodiment; FIG. 7 is a cross-sectional view showing a manufacturing process of a heat dissipation unit (setting of a mask) included in the manufacturing method of a semiconductor device according to the first embodiment; FIG. 8 is a plan view showing a manufacturing process of a heat dissipation unit (plating treatment) included in the manufacturing method of a semiconductor device according to the first embodiment; FIG. 9 is a cross-sectional view showing a manufacturing process of a heat dissipation unit (removal of a mask) included in the manufacturing method of a semiconductor device according to the first embodiment; FIG. 1 is a cross-sectional view showing a bonding step included in the manufacturing method of a semiconductor device of a first embodiment; FIG. 2 is a cross-sectional view showing a schematic cross-sectional view showing the arrangement of atoms in the bonding step included in the manufacturing method of a semiconductor device of a first embodiment; FIG. 3 is a cross-sectional view showing a placement step included in the manufacturing method of a semiconductor device of a reference example; FIG. 4 is a cross-sectional view showing a schematic cross-sectional view showing the arrangement of atoms in the placement step included in the manufacturing method of a semiconductor device of a reference example; FIG. 5 is a first cross-sectional view showing the arrangement of atoms in the bonding step (during heating) included in the manufacturing method of a semiconductor device of a reference example; FIG. 6 is a second cross-sectional view showing the arrangement of atoms in the bonding step (during heating) included in the manufacturing method of a semiconductor device of a reference example; FIG. 7 is a cross-sectional view showing the arrangement of atoms in the bonding step (during heating) included in the manufacturing method of a semiconductor device of a reference example;1 is a rear perspective view of an insulating circuit board included in a semiconductor device of a second embodiment; FIG. 2 is a plan view of a main part of a semiconductor device of a third embodiment (without a sealing member); FIG. 3 is a cross-sectional view of a semiconductor device of a fourth embodiment; FIG. 4 is a flowchart showing a method for manufacturing a semiconductor device of a fourth embodiment; FIG. 5 is a cross-sectional view showing a manufacturing process (plating process) of a heat dissipation unit included in a method for manufacturing a semiconductor device of a fourth embodiment; FIG. 6 is a cross-sectional view showing a manufacturing process (thinning process) of a heat dissipation unit included in a method for manufacturing a semiconductor device of a fourth embodiment; FIG. 7 is a cross-sectional view showing a placement process included in a method for manufacturing a semiconductor device of a fourth embodiment; FIG. 8 is a cross-sectional view showing an arrangement of atoms in a placement process included in a method for manufacturing a semiconductor device of a fourth embodiment; FIG. 9 is a cross-sectional view showing a bonding process included in a method for manufacturing a semiconductor device of a fourth embodiment;

[0016] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the X-Y plane facing upward (+Z direction) in the semiconductor device 1 of FIG. 1. Similarly, "top" refers to the upward direction (+Z direction) in the semiconductor device 1 of FIG. 1. The terms "back surface" and "bottom surface" refer to the X-Y plane facing downward (-Z direction) in the semiconductor device 1 of FIG. 1. Similarly, "bottom" refers to the downward direction (-Z direction) in the semiconductor device 1 of FIG. 1. Similar orientations will be used in other drawings as necessary. The terms "higher" and "upper" refer to the upper side (+Z direction) in the semiconductor device 1 of FIG. 1. Similarly, the terms "lower" and "lower" refer to the lower side (-Z direction) in the semiconductor device 1 of the drawings. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean a vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. In the following description, "main component" refers to a component containing 80 vol% or more (if a filler is included, this is the proportion excluding the filler). Furthermore, "substantially the same" may be within a range of ±10%. Furthermore, "perpendicular," "orthogonal," and "parallel" may be within a range of ±10°.

[0017] [First embodiment] A semiconductor device will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view of the semiconductor device of the first embodiment. FIG. 2 is a plan view of the essential parts of the semiconductor device of the first embodiment (without a sealing member). Note that FIG. 2 shows an enlarged view of a region including a semiconductor chip 25, excluding a sealing member 50 and wires 51 from the semiconductor device 1 of FIG. 1. Therefore, FIG. 2 shows an enlarged view of the essential parts inside the case 3 of FIG. 1, and therefore the case 3 is not shown. FIG. 1 is a cross-sectional view taken along the dashed dotted line Y-Y in FIG. 2 when the case 3 is included.

[0018] 1, the semiconductor device 1 includes a semiconductor unit 2, a heat dissipation unit 4 having the semiconductor unit 2 disposed on its front surface, and a case 3 provided on the outer edge of the heat dissipation unit 4 and housing the semiconductor unit 2. The interior of the case 3 of the semiconductor device 1 is sealed with a sealing member 50.

[0019] The sealing member 50 may be made of, for example, silicone gel. Alternatively, the sealing member 50 may be made of a thermosetting resin mixed with a filler. In this case, the thermosetting resin may be, for example, an epoxy resin, a phenolic resin, a maleimide resin, or a polyester resin. The filler is an insulating ceramic having high thermal conductivity. Examples of such fillers include silicon oxide, aluminum oxide, boron nitride, and aluminum nitride. The filler content may be 10% by volume or more and 70% by volume or less of the entire sealing member 50.

[0020] The semiconductor unit 2 includes an insulating circuit board 20 and a semiconductor chip 25 arranged on the front surface of the insulating circuit board 20 via solder 26. The insulating circuit board 20 includes an insulating plate 21, a plurality of conductive patterns 22 provided on the front surface of the insulating plate 21, and a metal plate 23 provided on the back surface of the insulating plate 21. The insulating plate 21 and the metal plate 23 are rectangular in plan view. The corners of the insulating plate 21 and the metal plate 23 may be round-chamfered or C-chamfered. The size of the metal plate 23 is smaller than the size of the insulating plate 21 in plan view, and is formed inside the insulating plate 21.

[0021] The insulating plate 21 may be, for example, a ceramic substrate. The ceramic substrate is made of ceramics with good thermal conductivity. The ceramics is made of a material containing aluminum oxide, aluminum nitride, or silicon nitride as its main components, for example. The insulating plate 21 has a rectangular shape in plan view.

[0022] The conductive pattern 22 has a semiconductor chip 25 disposed on its upper surface 22a. The conductive pattern 22 is formed over the entire surface of the insulating plate 21 except for the edges. Preferably, in a plan view, the end of the conductive pattern 22 facing the outer periphery of the insulating plate 21 overlaps the outer periphery of the metal plate 23. This maintains a stress balance between the conductive pattern 22 and the metal plate 23 on the back surface of the insulating plate 21 in the insulating circuit board 20. Damage to the insulating plate 21, such as excessive warping or cracking, is suppressed. The conductive pattern 22 is made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The conductive pattern 22 can also be plated with a material with excellent corrosion resistance. Examples of such materials include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. The thickness of the plating film is 10 μm or less. The conductive pattern 22 for the insulating plate 21 is obtained by forming a metal plate on the front surface of the insulating plate 21 and then performing a process such as etching on the metal plate. Alternatively, the conductive pattern 22 may be cut out in advance from a metal plate and bonded to the front surface of the insulating plate 21. Note that the conductive pattern 22 included in the semiconductor device 1 of this embodiment is merely an example. The number, shape, size, etc. of the conductive patterns may be selected appropriately as needed. Note that the top surface 22a of the conductive pattern 22 is also the top surface 22a of the insulating circuit board 20.

[0023] The lower surface 23a of the metal plate 23 is disposed on the heat dissipation unit 4. The metal plate 23 is made of a metal with excellent thermal conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. Here, copper is included. Furthermore, to improve corrosion resistance, the surface of the metal plate 23 may be plated. In this case, the plating material includes nickel. Examples of such plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The thickness of the plating film is 3 μm or more and 7 μm or less. The lower surface 23a of the metal plate 23 is also the lower surface 23a of the insulating circuit board 20. Another form of the plating film formed on the metal plate 23 will be described in the second embodiment.

[0024] For example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used as the insulating circuit board 20 having such a configuration. Alternatively, a resin insulating substrate may be used. The insulating circuit board 20 dissipates heat generated by a semiconductor chip 25 (described later) by conducting it to the back side of the insulating circuit board 20 via the conductive pattern 22, the insulating plate 21, and the metal plate 23.

[0025] The semiconductor chip 25 includes a switching element made primarily of silicon, for example. The switching element is, for example, an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT is a semiconductor element in which an IGBT and an FWD (Free Wheeling Diode) are arranged in anti-parallel within a single chip.

[0026] The semiconductor chip 25 has a collector electrode as an input electrode on its back surface, and a gate electrode as a control electrode and an emitter electrode as an output electrode on its front surface. The control electrode may be provided at the center of one side of the front surface of the semiconductor chip 25. Alternatively, the control electrode does not necessarily have to be provided at the center of one side of the front surface of the semiconductor chip 25, and may be shifted from the center in the ±X direction.

[0027] Another switching element may be a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) primarily made of silicon carbide. In the power MOSFET, the body diode may function as the FWD. The semiconductor chip 25 has, for example, an input electrode (drain electrode) as a main electrode on its back surface, and an output electrode (source electrode) and a control electrode (gate electrode) as main electrodes on its front surface.

[0028] Alternatively, instead of the semiconductor chip 25, a semiconductor chip mainly composed of silicon and including a pair of switching elements and diode elements may be used. The switching elements are, for example, power MOSFETs or IGBTs. The semiconductor chip including the switching elements includes, for example, an input electrode (a drain electrode in a power MOSFET or a collector electrode in an IGBT) as a main electrode on the back surface, and a gate electrode (a source electrode in a power MOSFET or an emitter electrode in an IGBT) as a control electrode and an output electrode (a source electrode in a power MOSFET or an emitter electrode in an IGBT) as a main electrode on the front surface. The diode elements include, for example, Schottky Barrier Diodes (SBDs) and P-intrinsic-N (PiN) diodes used as FWDs. The semiconductor chip including the diode elements includes an output electrode (cathode electrode) as a main electrode on the back surface, and an input electrode (anode electrode) as a main electrode on the front surface.

[0029] The back side of the semiconductor chip 25 is bonded to the conductive pattern 22 by solder 26. The solder 26 is composed of solder components. The solder components are materials that constitute solder, including lead-free solder primarily composed of a predetermined alloy. The predetermined alloy includes tin. Such alloys include, for example, at least one of a tin-silver alloy, a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, a tin-silver-indium-bismuth alloy, and a tin-antimony alloy. Furthermore, such solder components may include additives. Examples of additives include nickel, germanium, cobalt, or silicon. Therefore, examples of the solder components include, for example, tin and at least one of silver, zinc, copper, bismuth, indium, and antimony. Furthermore, the solder components may include, for example, at least one of nickel, germanium, cobalt, and silicon. Note that the solder components in the following embodiments are similar to those in the first embodiment. Furthermore, a sintered body may be used instead of the solder 26. When joining is performed using a sintered body, the sintered material is, for example, a powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum. Note that the solder 26 here is made of the same solder as the solder 27 described later.

[0030] The case 3 includes a frame portion 31 and external connection terminals 32 embedded in the frame portion 31. The frame portion 31 is rectangular in plan view and forms a frame shape surrounding a storage area 31f. The storage area 31f is an area extending from an upper opening 31a on the front surface of the case 3 to a lower opening 31b on the back surface. The area of ​​the upper opening 31a may be larger than the area of ​​the lower opening 31b. A heat dissipation unit 4 (described later) is attached to a step on the back surface of the frame portion 31 to cover the storage area 31f.

[0031] Furthermore, the upper inner wall 31c of the frame 31 surrounds the upper four sides of the storage area 31f, forming an upper opening 31a that leads to the storage area 31f. The lower inner wall 31e of the frame 31 surrounds the lower four sides of the storage area 31f, forming a lower opening 31b that leads to the storage area 31f. In plan view, the frame 31 has steps 31d formed between the upper inner wall 31c and the lower inner wall 31e on the short sides. The upper inner wall 31c is disposed approximately perpendicular to the front surface of the frame 31. The step 31d is disposed approximately perpendicular to the upper inner wall 31c. The lower inner wall 31e is disposed approximately perpendicular to the step 31d. From the above, in plan view, the lower inner wall 31e on the short side protrudes by the amount of the step 31d toward the storage area 31f beyond the upper inner wall 31c.

[0032] The frame 31 is formed by injection molding using a thermoplastic resin containing a filler, such as polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), or polyamide (PA). The filler may be, for example, glass fiber, glass beads, calcium carbide, talc, magnesium oxide, or aluminum hydroxide.

[0033] The external connection terminal 32 is flat and L-shaped in side view. The external connection terminal 32 is integrally molded with the frame 31. The external connection terminal 32 includes an internal wiring portion 32a and an external wiring portion 32b disposed substantially perpendicular to the internal wiring portion 32a. The internal wiring portion 32a is included in the frame 31 and parallel to the front surface of the frame 31. One end of the internal wiring portion 32a extends substantially perpendicularly from the upper inner wall 31c toward the storage area 31f, and the front surface of the one end is exposed through the step 31d. The external wiring portion 32b is included in the frame 31 and parallel to the upper inner wall 31c of the frame 31. The other end of the external wiring portion 32b extends substantially perpendicular to the front surface of the frame 31. One end of the external wiring portion 32b is integrally connected to the other end of the internal wiring portion 32a within the frame 31.

[0034] The external connection terminals 32 are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The external connection terminals 32 have a uniform thickness throughout. The external connection terminals 32 can also be plated with a material with excellent corrosion resistance. Examples of such materials include aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, or an alloy containing at least one of these.

[0035] The frame 31 of this case 3 has the outer periphery of the front surface of the heat dissipation unit 4, to which the semiconductor unit 2 is bonded, bonded with an adhesive (not shown) to the back surface of the frame 31 on the side of the lower opening 31b. This allows the semiconductor unit 2 to be housed in the housing region 31f of the frame 31. Although not shown, a lid (not shown) may be bonded with an adhesive to the front surface of the frame 31 on the side of the upper opening 31a. The adhesive may be, for example, a thermosetting resin adhesive or an elastomer adhesive. The thermosetting resin adhesive is primarily composed of, for example, epoxy resin or phenolic resin. The elastomer adhesive is primarily composed of, for example, silicone rubber or chloroprene rubber.

[0036] The bonding area exposed from the step 31d of the internal wiring portion 32a is electrically connected to the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25 by wiring members. An example of the wiring member is the wire 51 shown in FIG. 1 . The wire 51 is made of a material with excellent conductivity. Such a material may be, for example, gold, silver, copper, aluminum, or an alloy containing at least one of these. Note that such wiring members are not limited to the wire 51, and a lead frame may also be used.

[0037] The heat dissipation unit 4 includes a heat dissipation base plate 40 and a plating film 41. The heat dissipation base plate 40 is primarily composed of copper. The heat dissipation base plate 40 includes an arrangement region 40b on its front surface 40a, where the underside 23a of the insulating circuit board 20 is arranged via solder 27. The arrangement region 40b is the area where the metal plate 23 of the insulating circuit board 20 is arranged on the heat dissipation base plate 40. The arrangement region 40b has a rectangular shape in plan view, similar to the insulating circuit board 20. The size of the arrangement region 40b may be equal to or smaller than the size of the insulating plate 21 and equal to or larger than the size of the metal plate 23 in plan view. Note that the example shown here shows a case where the size of the arrangement region 40b is the same as the size of the metal plate 23. The thickness of the heat dissipation base plate 40 depends on the size of the semiconductor device 1, but may be, for example, 2.5 mm or more and 3.5 mm or less. The plating film 41 is formed on the front surface 40a of the heat dissipation base plate 40, excluding an opening region 41a that surrounds the entire periphery of the arrangement region 40b. The thickness of the plating film 41 excluding the opening region 41a may be, for example, a commonly used thickness, and may be, for example, 1 μm or more and 10 μm or less.

[0038] The placement area 40b may be rectangular in plan view, similar to the insulating circuit board 20, but is larger in size than the insulating circuit board 20. The placement area 40b does not necessarily have to be rectangular as long as it includes the insulating circuit board 20 in plan view. Furthermore, the corners of the placement area 40b do not necessarily have to be right angles in plan view, and may form rounded surfaces.

[0039] The placement region 40b may be recessed in the -Z direction relative to the front surface 40a of the heat dissipating base plate 40 excluding the placement region 40b. Here, the placement region 40b is smoothly connected to the front surface 40a of the heat dissipating base plate 40 excluding the placement region 40b. In this case, the depth of the deepest position of the placement region 40b may be deeper than the thickness of the plating film 24 described below. Note that the placement region 40b may be flush with the front surface 40a of the heat dissipating base plate 40 excluding the placement region 40b.

[0040] 1 and 2, solder 27 is provided in arrangement region 40b and joins insulating circuit board 20 to front surface 40a of heat dissipating base plate 40. The thickness of solder 27 is 100 μm or more and 500 μm or less. In plan view, solder 27 includes fillet portion 27b that extends outside lower surface 23a of insulating circuit board 20 (metal plate 23) and is provided outside arrangement region 40b.

[0041] This fillet portion 27b (the outer edge of the solder 27) may extend outward beyond the outer edge of the insulating circuit board 20 (insulating plate 21) in a plan view. However, it is preferable that the fillet portion 27b be located inside the outer edge of the insulating plate 21. Note that FIG. 2 merely illustrates a case in which the outer edge of the solder 27 extends outward beyond the outer edge of the insulating circuit board 20 (insulating plate 21) so as to clarify the position of the solder 27 relative to the insulating circuit board 20 and the plating film 41. Note that the region in which the solder 27 extends over the arrangement region 40b on the front surface 40a of the heat dissipation base plate 40 is the solder region (reference numeral omitted here; see solder region 41b in FIG. 25). The size of the solder region may be wider than the size of the arrangement region 40b in a plan view and may include the arrangement region 40b.

[0042] The opening region 41a of the plating film 41 around the placement region 40b includes an area where the plating film 41 is not provided, in case the solder 27 spreads outward beyond the placement region 40b. The opening region 41a may be rectangular like the placement region 40b, but is wider than the placement region 40b. It is desirable that the opening region 41a be at least 1 mm away from the placement region 40b, for example. The opening region 41a may also coincide with the solder region or may spread outward beyond the solder region.

[0043] The plating film 41 is formed by plating on the surface of the heat dissipating base plate 40 excluding the placement region 40b. The plating film 41 improves the corrosion resistance of the heat dissipating base plate 40. The plating material of the plating film 41 contains nickel. Examples of such plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0044] Alternatively, a cooling unit (not shown) may be attached to the back surface of the case 3 containing the heat dissipation unit 4 via a thermally conductive member. The thermally conductive member is a thermal interface material (TIM). TIM is a general term for various materials, such as thermally conductive grease, elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, phase change material, solder, and silver brazing. This improves the heat dissipation performance of the semiconductor device 1. In this case, the cooling unit is made of, for example, a metal with excellent thermal conductivity. The metal may be, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. The cooling unit may be, for example, a heat sink with one or more fins or a water-cooled cooling device.

[0045] Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIG. 3. FIG. 3 is a flowchart showing the method for manufacturing the semiconductor device of the first embodiment. Note that the flowchart showing the manufacturing method in FIG. 3 is merely an example. The semiconductor device 1 can be manufactured using methods other than the flowchart in FIG. 3 as long as it includes the heat dissipation unit 4 to which the semiconductor unit 2 is bonded.

[0046] First, a preparation step is performed to prepare the components of the semiconductor device 1 (step S1 in FIG. 3). The components prepared at this time include, for example, the insulating circuit board 20, the semiconductor chip 25, the case 3, and the heat dissipation unit 4. Other components necessary for the semiconductor device 1 may also be prepared. Manufacturing equipment used to manufacture the semiconductor device 1 may also be prepared.

[0047] There are, for example, two possible manufacturing methods for the heat dissipation unit 4. First, a manufacturing method for the heat dissipation unit 4 included in the semiconductor device 1 shown in FIG. 1 (steps S10, S11a, S12a, and S14 in FIG. 3) will be described with reference to FIGS. 4 to 7. FIG. 4 is a plan view showing a manufacturing process for the heat dissipation unit (preparation of a heat dissipation base plate) included in the manufacturing method for a semiconductor device according to the first embodiment. FIG. 5 is a plan view showing a manufacturing process for the heat dissipation unit (plating process) included in the manufacturing method for a semiconductor device according to the first embodiment. FIG. 6 is a plan view showing a manufacturing process for the heat dissipation unit (grinding process) included in the manufacturing method for a semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process for the heat dissipation unit (grinding process) included in the manufacturing method for a semiconductor device according to the first embodiment. Note that FIG. 7 is a cross-sectional view taken along the dashed dotted line X-X in FIG. 6. FIG. 1 also shows the heat dissipation base plate 40 (heat dissipation unit 4) of FIGS. 4 to 7 as viewed in the +Y direction.

[0048] First, a heat dissipating base plate 40 is prepared (step S10 in FIG. 3 ). For example, a metal plate is sheared to obtain a heat dissipating base plate 40 of a size corresponding to the heat dissipating unit 4 of the semiconductor device 1, as shown in FIG. 4 . Shearing may be performed using, for example, a press or a blade. Such a heat dissipating base plate 40 has a flat, rectangular shape in a plan view. The front surface 40a of the heat dissipating base plate 40 is substantially smooth. Furthermore, placement areas 40b are defined on the front surface 40a of the heat dissipating base plate 40. The placement areas 40b are placement areas where the metal plates 23 of the insulating circuit boards 20 are to be placed. The placement areas 40b are defined according to the number of insulating circuit boards 20 included in the semiconductor device 1. In this example, two placement areas 40b are defined side by side on the front surface 40a of the heat dissipating base plate 40.

[0049] Next, the heat dissipating base plate 40 is plated (step S11a in FIG. 3). As shown in FIG. 5, the entire surface of the heat dissipating base plate 40, including the front surface 40a, is plated to form a plating film 41. The plating is a commonly known method, and may be, for example, electrolytic plating or electroless plating.

[0050] Next, a grinding process is performed on the heat dissipating base plate 40 on which the plating film 41 is formed (step S12a in FIG. 3 ). The plating film 41 corresponding to the opening region 41a, including the placement region 40b, of the heat dissipating base plate 40 on which the plating film 41 is formed is removed by grinding. As shown in FIG. 6 , the plating film 41 is removed to form the opening region 41a, which is wider than the placement region 40b. Note that the plating film 41 is formed on the heat dissipating base plate 40 in areas other than the opening region 41a. When the plating film 41 corresponding to the opening region 41a, including the placement region 40b of the heat dissipating base plate 40, is removed by grinding, the plating film 41 on the placement region 40b is removed, and the front surface 40a of the heat dissipating base plate 40 in the placement region 40b is also ground. Therefore, as shown in FIG. 7 , the placement region 40b is recessed from the front surface 40a excluding the placement region 40b. Furthermore, when the front surface 40a of the heat dissipating base plate 40 is ground, the bottom surface of the recess and the front surface 40a are connected by a smooth surface. In this manner, the heat dissipating unit 4 shown in FIG. 1 can be prepared (step S14 in FIG. 3).

[0051] The heat dissipation unit 4 can also be manufactured by the following manufacturing method. The manufacturing method in this case (steps S10, S11b, S12b, S13b, and S14 in FIG. 3 ) will be described with reference to FIGS. 8 to 11 , along with FIG. 4 . FIG. 8 is a plan view showing a manufacturing process (mask setting) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment. FIG. 9 is a plan view showing a manufacturing process (plating) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment. FIG. 10 is a plan view showing a manufacturing process (mask removal) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment, and FIG. 11 is a cross-sectional view showing a manufacturing process (mask removal) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment. Note that FIG. 11 is a cross-sectional view taken along the dashed dotted line X-X in FIG. 10 .

[0052] Here, too, first, the heat dissipating base plate 40 is prepared (step S10 in FIG. 3). Step S10 is as described above. Next, a mask is set on the heat dissipating base plate 40 (step S11b in FIG. 3). As shown in FIG. 8, a mask 42 is set in the placement area 40b on the front surface 40a of the heat dissipating base plate 40. The mask 42 to be set has the same shape as the placement area 40b in a plan view, but is slightly larger than the placement area 40b.

[0053] Next, the heat dissipating base plate 40 is plated (step S12b in FIG. 3). Similar to step S11a, the entire surface of the heat dissipating base plate 40, including the front surface 40a, is plated to form a plating film 41. After the plating process, the plating film 41 is formed on the front surface 40a of the heat dissipating base plate 40 except for the area covered by the mask 42.

[0054] Next, the mask 42 is removed (step S13b in FIG. 3). After step S12b, the mask 42 is removed. As shown in FIG. 10, the plating film 41 is formed on the front surface 40a of the heat dissipating base plate 40 except for the opening region 41a including the placement region 40b. Also, as shown in FIG. 11, the placement region 40b on the front surface 40a of the heat dissipating base plate 40 is not removed, and the placement region 40b forms the same plane as the front surface 40a. In this way, the heat dissipating unit 4 shown in FIG. 1 can be prepared (step S14 in FIG. 3).

[0055] Next, an arrangement process is performed in which the heat dissipation unit 4, the insulating circuit board 20, and the semiconductor chip 25 are arranged in this order (step S2 in FIG. 3 ). The arrangement process will be described with reference to FIGS. 12 and 13 . FIG. 12 is a cross-sectional view showing the arrangement process included in the semiconductor device manufacturing method of the first embodiment. FIG. 13 is a schematic cross-sectional view showing the atomic arrangement in the arrangement process included in the semiconductor device manufacturing method of the first embodiment. Note that FIG. 13 also schematically shows the atomic arrangement in the area B surrounded by the dashed line in FIG. 12 . Also, FIG. 13 merely shows the atomic arrangement, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer. Furthermore, FIG. 13 only shows tin, which is a constituent element of the solder component. The solder component may contain elements other than tin, and these elements are not shown. Also, not only FIG. 13 but also subsequent schematic cross-sectional views showing atomic arrangements only show tin, which is a constituent element of the solder component. In these schematic cross-sectional views, the solder components may also contain elements other than tin, and the illustration of these elements is omitted.

[0056] The insulating circuit boards 20 are placed in the placement areas 40b within the opening areas 41a of the plating film 41 formed on the heat dissipation units 4 via solder plates 27a. The solder plates 27a are formed by hardening solder 27 in the shape of a plate. The solder plates 27a are placed at the bottom of the recesses in the placement areas 40b of the heat dissipation units 4. The solder plates 27a may have the same size as the lower surface 23a of the metal plate 23 of the insulating circuit board 20 in a plan view, for example.

[0057] The semiconductor chip 25 is placed on the upper surface 22a of the conductive pattern 22 of the insulating circuit board 20 via a solder plate 26a. The solder plate 26a is formed by hardening the solder 26 in a plate shape. The solder plate 26a may be, for example, the same size as the semiconductor chip 25 in a plan view.

[0058] By this placement process, as shown in Figure 12, the insulating circuit board 20 is placed in the placement area 40b of the heat dissipation unit 4 via the solder plate 27a, and the semiconductor chip 25 is placed on the conductive pattern 22 of the insulating circuit board 20 via the solder plate 26a.

[0059] 12 is near the boundary between the heat dissipation base plate 40 and the solder plate 27a in the heat dissipation unit 4. At the boundary in this range B, as shown in FIG. 13 , copper atoms contained in the heat dissipation base plate 40 and tin atoms contained in the solder plate 27a are regularly arranged on either side of the boundary L. This boundary L corresponds to the boundary between the solder plate 27a and the placement region 40b of the heat dissipation base plate 40 when the solder plate 27a is placed in the placement region 40b of the heat dissipation unit 4 (heat dissipation base plate 40). Note that because the solder plate 27a is not bonded when placed on the heat dissipation base plate 40, air spaces contained in the unevenness of the solder plate 27a exist between the solder plate 27a and the metal plate 23 and between the solder plate 27a and the heat dissipation base plate 40, but these will not be described.

[0060] Next, a bonding process is performed between the heat dissipation unit 4 and the insulating circuit board 20, and between the insulating circuit board 20 and the semiconductor chip 25 (step S3 in FIG. 3). The bonding process will be described with reference to FIGS. 14 and 15. FIG. 14 is a cross-sectional view showing the bonding process included in the manufacturing method of the semiconductor device of the first embodiment. FIG. 15 is a schematic cross-sectional view showing the arrangement of atoms in the bonding process included in the manufacturing method of the semiconductor device of the first embodiment. Note that FIG. 15 schematically shows the atomic arrangement in area B surrounded by a dashed line in FIG. 14. Also, FIG. 15 merely shows the arrangement of atoms schematically, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0061] The solder plate 27a between the heat dissipation unit 4 and the insulating circuit board 20 arranged in step S2, and the solder plate 26a between the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25 are heated. The solder plates 26a and 27a melt and turn into solders 26 and 27, respectively.

[0062] When heated in this manner, as shown in Figure 15, the copper atoms of the heat dissipating base plate 40 migrate and diffuse across the boundary L into the tin atoms of the solder 27. Furthermore, as the copper atoms diffuse, the tin atoms of the solder 27 diffuse across the boundary L into the copper atoms of the heat dissipating base plate 40. In this manner, an alloy layer 44 is generated near the boundary L. The alloy layer 44 contains copper atoms and tin atoms. Such alloy layer 44 is included in the boundary between the solder 27 and the heat dissipating base plate 40, not limited to the area indicated by range B.

[0063] The solders 26, 27 melted from the solder plates 26a, 27a are cooled and hardened. As a result, as shown in Fig. 14, the insulating circuit boards 20 are bonded to the placement areas 40b of the heat dissipation units 4 via the hardened solder 27. Similarly, the semiconductor chip 25 is bonded to the upper surface 22a of the insulating circuit board 20 via the hardened solder 26.

[0064] Thus, the semiconductor unit 2 is formed, including the insulating circuit board 20 and the semiconductor chip 25. The semiconductor unit 2 is also joined to the placement area 40b of the heat dissipation unit 4 with solder 27.

[0065] Next, the heat dissipation unit 4 is attached to the lower opening 31b of the case 3, and the semiconductor unit 2 is housed in the case 3 (step S4 in FIG. 3). The outer periphery of the heat dissipation unit 4 is attached to the step on the back surface of the case 3 (frame portion 31) via an adhesive (not shown). This allows the semiconductor unit 2 to be housed in the housing region 31f of the case 3.

[0066] Next, a wiring process is performed to wire the semiconductor unit 2 housed in the case 3 (step S5 in FIG. 3). The internal wiring portions 32a of the external connection terminals 32 exposed from the upper opening 31a of the case 3 are connected to the conductive patterns 22 by wires 51. The output electrodes of the semiconductor chip 25 are also connected to the internal wiring portions 32a of the external connection terminals 32 by wires 51.

[0067] Next, a sealing step is performed to seal the storage area 31f of the case 3 with a sealing member 50 (step S6 in FIG. 3). The sealing member 50 is filled from the upper opening 31a of the case 3 to seal the semiconductor unit 2 on the heat dissipation unit 4 in the storage area 31f. In this way, the semiconductor device 1 shown in FIG. 1 is obtained.

[0068] Here, a semiconductor device (not shown) of a reference example compared to the semiconductor device 1 of the first embodiment will be described with reference to FIG. 3 (as well as FIGS. 16 and 17 described later). The semiconductor device of the reference example (not shown) also includes a heat dissipation unit 4a. The heat dissipation base plate 40 included in the heat dissipation unit 4a of the reference example has a plating film 41 formed on the entire surface, including the placement area 40b. In other words, the plating film 41 in the placement area 40b of the heat dissipation unit 4a is not removed. A semiconductor device including such a heat dissipation unit 4a is also manufactured according to the flowchart of FIG. 3.

[0069] First, a preparation step is performed to prepare components of the semiconductor device (step S1 in FIG. 3). The heat dissipation unit 4a prepared here is manufactured through steps S10, S11a, and S14 in FIG. 3. Alternatively, it is manufactured through steps S10, S12b, and S14 in FIG. 3.

[0070] Next, an arrangement step is performed in which the heat dissipation unit 4, the insulating circuit board 20, and the semiconductor chip 25 are sequentially arranged (step S2 in FIG. 3 ). The arrangement step will be described with reference to FIGS. 16 and 17 . FIG. 16 is a cross-sectional view illustrating the arrangement step included in the semiconductor device manufacturing method of the reference example. FIG. 17 is a schematic cross-sectional view illustrating the atomic arrangement in the area B surrounded by the dashed line in FIG. 16 . FIG. 17 merely illustrates the atomic arrangement, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer. Also, in this case, since the solder plate 27 a is not bonded to the heat dissipation base plate 40 (plating film 41) when it is placed on it, air spaces contained in the unevenness of the solder plate 27 a exist between the solder plate 27 a and the metal plate 23 and between the solder plate 27 a and the plating film 41, but these will not be described.

[0071] 16 , insulating circuit boards 20 are placed via solder plates 27a in placement areas 40b where plating film 41 of heat dissipation units 4a is formed. Semiconductor chips 25 are placed via solder plates 26a on top surfaces 22a of conductive patterns 22 of insulating circuit boards 20. The thickness of plating film 41 formed over the entire surface of heat dissipation base plate 40 may be a commonly used thickness, for example, not less than 1 μm and not more than 10 μm, as in the first embodiment.

[0072] 16 is near the boundary between the heat dissipation base plate 40 on which the plating film 41 is formed and the solder plate 27a in the heat dissipation unit 4a. At the boundary in this region B, as shown in FIG. 17 , copper atoms contained in the heat dissipation base plate 40, nickel atoms contained in the plating film 41, and tin atoms contained in the solder plate 27a are regularly arranged on either side of boundaries L1 and L2, respectively. Boundary L1 corresponds to the boundary between the solder plate 27a and the plating film 41 when the solder plate 27a is placed in the placement area 40b of the heat dissipation unit 4a (heat dissipation base plate 40). Similarly, boundary L2 corresponds to the boundary between the heat dissipation base plate 40 and the plating film 41.

[0073] Next, a bonding process is performed between the heat dissipation unit 4a and the insulating circuit board 20, and between the insulating circuit board 20 and the semiconductor chip 25 (step S3 in FIG. 3). The bonding process will be described with reference to FIGS. 18 to 20. FIG. 18 is a first schematic cross-sectional view showing the atomic arrangement during the bonding process (during heating) included in the semiconductor device manufacturing method of the reference example. FIG. 19 is a second schematic cross-sectional view showing the atomic arrangement during the bonding process (during heating) included in the semiconductor device manufacturing method of the reference example. FIG. 20 is a third schematic cross-sectional view showing the atomic arrangement during the bonding process (during heating) included in the semiconductor device manufacturing method of the reference example. Note that FIGS. 18 to 20 show the atomic arrangement in the area B enclosed by the dashed line in FIG. 16, and are a schematic representation of a change from FIG. 17. Also, FIGS. 18 to 20 merely show the atomic arrangements, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0074] The solder plate 27a between the heat dissipation unit 4a and the insulating circuit board 20 arranged in step S2, and the solder plate 26a between the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25 are heated. The solder plates 26a and 27a melt and turn into solders 26 and 27, respectively.

[0075] 18, when heated in this manner, nickel atoms in any part of the plating film 41 migrate and diffuse across the boundary L1 into the tin atoms of the molten solder 27. Meanwhile, tin atoms in any part of the solder 27 diffuse across the boundary L1 into the nickel atoms of the plating film 41. Therefore, an alloy layer containing nickel atoms and tin atoms begins to form near the boundary L1.

[0076] As heating continues, the nickel atoms of the plating film 41 diffuse into the solder 27, and the tin atoms of the solder 27 diffuse into the plating film 41, further promoting the formation of an alloy layer containing nickel and tin atoms near the boundary L1, as shown in FIG. 19 . The plating film 41 is thinner than the solder 27. As a result, the nickel atoms in the plating film 41 decrease in some areas, while the tin atoms increase in others. In this way, the nickel atoms in the plating film 41 are partially replaced by tin atoms, resulting in solder erosion. Note that if the plating film 41 is sufficiently thin, the plating film 41 will disappear if all of the nickel atoms in the plating film 41 are replaced by tin atoms.

[0077] As heating continues, copper atoms, which have a high diffusion rate in the heatsink base plate 40, cross the boundary L2, migrate to the solder-eaten portion of the plating film 41, and diffuse into the solder 27. Furthermore, tin atoms in the solder plate 27a near the boundary L1 cross the boundary L2 and diffuse into the heatsink base plate 40. At this time, as shown in Figure 20, the traces of the migration of copper atoms in the heatsink base plate 40 become voids (Kirkendall voids). Kirkendall voids often occur in the portion of the heatsink base plate 40 below the remaining plating film 41.

[0078] The joining of heat dissipation unit 4 and insulating circuit board 20, and insulating circuit board 20 and semiconductor chip 25, respectively, which is performed by cooling and hardening molten solder 26, 27 after heating, will be described with reference to Fig. 21. Fig. 21 is a cross-sectional view showing the joining step (after joining) included in the manufacturing method of a semiconductor device of the reference example.

[0079] The molten solders 26 and 27 are cooled and hardened. Then, as shown in Figure 21, the insulating circuit boards 20 are joined to the placement areas 40b of the heat dissipation units 4a via the hardened solder 27. Similarly, the semiconductor chip 25 is joined to the upper surface 22a of the insulating circuit board 20 via the hardened solder 26. However, the heat dissipation base plate 40 contains a plurality of Kirkendall voids (vacant holes V).

[0080] Next, the heat dissipation unit 4 is attached to the lower opening 31b of the case 3, and an accommodation step (step S4 in FIG. 3) of accommodating the semiconductor unit 2 in the case 3 is performed, followed by a wiring step (step S5 in FIG. 3) of wiring the semiconductor unit 2 accommodated in the case 3. Finally, a sealing step (step S6 in FIG. 3) of sealing the accommodation region 31f of the case 3 with a sealing member 50 is performed. In this manner, a semiconductor device including the heat dissipation unit 4a is manufactured.

[0081] In this heat dissipation unit 4a, as described in FIG. 20 , the plating film 41 directly below the solder 27 is partially eroded by the solder 27. Furthermore, as shown in FIG. 21 , multiple Kirkendall voids (vacancy V) are generated below the partially remaining plating film 41 on the heat dissipation base plate 40. When multiple Kirkendall voids (vacancy V) are present in the heat dissipation base plate 40, the thermal resistance of the heat dissipation base plate 40 increases. This example illustrates the generation of Kirkendall voids in the heat dissipation unit 4a (heat dissipation base plate 40) due to heating during the bonding process. This is not limited to this case; Kirkendall voids can also occur due to heat generated by long-term operation of the semiconductor device 1. A semiconductor device including such a heat dissipation unit 4a has reduced heat dissipation performance.

[0082] The semiconductor device 1 includes an insulating circuit board 20 including a lower surface 23a, a heat dissipating base plate 40 including a front surface 40a and having an arrangement region 40b on the front surface 40a where the lower surface 23a of the insulating circuit board 20 is arranged via solder 27, a plating film 41 formed on the front surface 40a of the heat dissipating base plate 40 except for a solder region 41b where the solder 27 spreads over the arrangement region 40b of the front surface 40a, and an alloy layer 44 included between the solder 27 and the arrangement region 40b of the heat dissipating base plate 40 and containing the solder components of the solder 27. In particular, in the semiconductor device 1, the plating film 41 is formed on the entire surface of the heat dissipating base plate 40 except for an opening region 41a surrounding the outer periphery of the arrangement region 40b where the insulating circuit board 20 is arranged via the solder 27. In other words, the solder 27 that joins the insulating circuit board 20 is joined to the heat dissipating base plate 40 without the plating film 41 being interposed therebetween. Therefore, the plating film 41 is not eroded by the solder 27 in the placement region 40b of the heat dissipating base plate 40. Therefore, the atoms constituting the heat dissipating base plate 40 do not move, and the generation of voids in the heat dissipating base plate 40 is suppressed. Furthermore, the generation of voids is similarly suppressed even when heat is generated due to long-term operation of the semiconductor device 1. As a result, an increase in the thermal resistance of the heat dissipating base plate 40 is suppressed, and a decrease in the heat dissipation performance of the semiconductor device 1 including the heat dissipating base plate 40 is suppressed. Furthermore, a decrease in the reliability of the semiconductor device 1 is prevented.

[0083] Second Embodiment In a second embodiment, a case in which a plating film is not provided on the lower surface 23a of the insulating circuit board 20 in contact with the solder 27 in the semiconductor device 1 will be described with reference to Figures 22 and 23. Figure 22 is a cross-sectional view of the semiconductor device of the second embodiment. Figure 23 is a rear perspective view of the insulating circuit board included in the semiconductor device of the second embodiment.

[0084] As described in the first embodiment, the surface of the metal plate 23 of the insulating circuit board 20 of the semiconductor device 1 may be plated to improve corrosion resistance. The insulating circuit board 20 is joined to the placement area 40b of the heat dissipation unit 4 via solder 27. The plated metal plate 23 comes into contact with the solder 27 via the plating film. As a result, the plating film on the metal plate 23 is also susceptible to solder erosion.

[0085] 22 and 23, metal plate 23 of insulating circuit board 20 of the second embodiment has plating film 24 formed on the surfaces thereof except for bottom surface 23a. That is, metal plate 23 does not have plating film 24 on bottom surface 23a, which is disposed in placement area 40b of heat dissipation base plate 40 via solder 27, but has plating film 24 formed on the side surfaces surrounding the entire periphery of bottom surface 23a except for bottom surface 23a.

[0086] Therefore, the solder 27 that joins the heat dissipation unit 4 is joined to the metal plate 23 of the insulating circuit board 20 without the plating film 24 therebetween. Therefore, the plating film 24 is not eroded by the solder 27 on the underside 23a of the metal plate 23. Therefore, the atoms that make up the metal plate 23 do not move, and the generation of voids in the metal plate 23 is suppressed. Furthermore, the generation of voids is similarly suppressed even when the semiconductor device 1 generates heat during long-term operation. As a result, an increase in the thermal resistance of the metal plate 23 as well as the heat dissipation unit 4 is suppressed, and a decrease in the heat dissipation performance of the semiconductor device 1 including the heat dissipation unit 4 and the metal plate 23 is suppressed, and a decrease in the reliability of the semiconductor device 1 is also prevented.

[0087] [Third Embodiment] A heat dissipation unit 4 according to a third embodiment will be described with reference to Fig. 24. Fig. 24 is a plan view of a main part of a semiconductor device according to the third embodiment (without a sealing member). Note that the heat dissipation unit 4 according to the third embodiment is included in the semiconductor device 1 according to the first embodiment.

[0088] A resist film 43 is continuously formed in a ring shape along the edge of the opening region 41a of the plating film 41 included in the heat dissipation unit 4 of the third embodiment. The resist film 43 may be made of, for example, epoxy resin or acrylic resin.

[0089] The solder 27 provided between the placement area 40b of the heat dissipating base plate 40 and the insulating circuit board 20 may spread outside the placement area 40b, but the presence of the resist film 43 prevents the solder 27 from spreading beyond the placement area 40b. Without the resist film 43, the solder 27 may spread beyond the placement area 40b, potentially reaching the plating film 41 around the placement area 40b. As previously mentioned, contact between the solder 27 and the plating film 41 would result in voids forming in the heat dissipating base plate 40 below the plating film 41. By providing the resist film 43 on the edge of the opening area 41a of the plating film 41, the formation of voids in the heat dissipating base plate 40 can be prevented. Furthermore, the resist film 43 can narrow the opening area 41a. This allows the area on the heat dissipating base plate 40 without the plating film 41 or solder 27 to be reduced or eliminated.

[0090] 3, the resist film 43 for the opening region 41a of the plating film 41 may be formed by applying the resist film 43 along the opening edge of the opening region 41a of the plating film 41. Alternatively, after step S11a, the resist film 43 may be formed for the opening region 41a of the plating film 41, and then step S12a may be performed.

[0091] The resist film 43 may be formed by being applied along the opening edge of the opening region 41a of the plating film 41 after steps S10, S11b, S12b, and S13b of FIG. 3 are performed.

[0092] [Fourth Embodiment] A semiconductor device according to a fourth embodiment has the same configuration as the semiconductor device 1 according to the first embodiment, except for the heat dissipation unit 4. Such a semiconductor device according to the fourth embodiment will be described with reference to Fig. 25. Fig. 25 is a cross-sectional view of the semiconductor device according to the fourth embodiment. Note that Fig. 25 corresponds to Fig. 1 of the first embodiment.

[0093] 25 , the semiconductor device 1a includes a semiconductor unit 2, a heat dissipation unit 4a on the front surface of which the semiconductor unit 2 is disposed, and a case 3 provided on the outer edge of the heat dissipation unit 4a and housing the semiconductor unit 2. The interior of the case 3 of the semiconductor device 1a is sealed with a sealing member 50. The semiconductor unit 2, the case 3, and the sealing member 50 have the same configuration as in the first embodiment. Furthermore, the solders 26, 27 provided on the upper surface 22a and the lower surface 23a of the semiconductor unit 2 are also as described in the first embodiment.

[0094] The heat dissipation unit 4a includes a heat dissipation base plate 40 and a plating film 41. The heat dissipation base plate 40 is made of the same material and has the same size as in the first embodiment. The front surface 40a of the heat dissipation base plate 40 also includes an arrangement region 40b, similar to the first embodiment, to which the lower surface 23a of the insulating circuit board 20 is joined via solder 27. However, unlike the first embodiment, the arrangement region 40b on the front surface 40a of the heat dissipation base plate 40 in the fourth embodiment is not recessed in the -Z direction relative to the front surface 40a of the heat dissipation base plate 40 excluding the arrangement region 40b. In other words, the entire front surface 40a of the heat dissipation base plate 40 in the fourth embodiment is substantially smooth. The front surface 40a of the heat dissipation base plate 40 includes a solder region 41b in which the solder 27 is spread over the arrangement region 40b.

[0095] The plating film 41 is made of the same material as in the first embodiment. The plating film 41 is formed on the front surface 40a of the heat dissipating base plate 40, excluding the solder regions 41b. Furthermore, the plating film 41 is also formed on the entire surface of the heat dissipating base plate 40, excluding the front surface 40a. That is, the plating film 41 is formed on the front surface 40a, excluding the solder regions 41b of the heat dissipating base plate 40, the back surface 40c opposite the front surface 40a, and four side surfaces 40d surrounding the front surface 40a and the back surface 40c.

[0096] The thickness of the plating film 41 formed on the front surface 40 a is thinner than the thickness of the plating film 41 formed on the back surface 40 c and the side surface 40 d. The thickness of the plating film 41 formed on the front surface 40 a is, for example, 0.2 μm or less.

[0097] The insulating circuit board 20 is joined to the solder area 41b of the heat dissipating base plate 40 included in this heat dissipating unit 4a via the solder 27. The plating film 41 is formed on the surface of the heat dissipating base plate 40 excluding the solder 27 (solder area 41b). Furthermore, an alloy layer containing the solder components contained in the solder 27 is included between the solder 27 and the front surface 40a of the heat dissipating base plate 40. Details of this alloy layer will be described later.

[0098] Next, a method for manufacturing such a semiconductor device 1a will be described with reference to FIG. 26. FIG. 26 is a flowchart showing a method for manufacturing a semiconductor device according to the fourth embodiment. Note that the flowchart showing the manufacturing method in FIG. 26 is merely an example. The semiconductor device 1a can be manufactured by methods other than the flowchart in FIG. 26 as long as it includes a heat dissipation unit 4a to which a semiconductor unit 2 is bonded. Furthermore, the processes from step S2 onward in the flowchart in FIG. 26 are the same as the processes from step S2 onward in the flowchart in FIG. 3. For this reason, the description of the processes from step S2 onward may be simplified here.

[0099] First, a preparation step is performed to prepare the components of the semiconductor device 1a (step S1a in FIG. 26). The prepared components include, for example, an insulating circuit board 20, a semiconductor chip 25, a case 3, and a heat dissipation unit 4a. Other components necessary for the semiconductor device 1a may also be prepared. Manufacturing equipment used to manufacture the semiconductor device 1a may also be prepared.

[0100] Here, a manufacturing method of the heat dissipation unit 4a included in the semiconductor device 1a shown in FIG. 25 (steps S10, S11c, S12c, and S14 in FIG. 26) will be described with reference to FIG. 5, as well as FIGS. 27 and 28. FIG. 27 is a cross-sectional view showing a manufacturing process (plating process) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the fourth embodiment. FIG. 28 is a cross-sectional view showing a manufacturing process (thinning process) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the fourth embodiment. Note that FIGS. 27 and 28 correspond to the cross-sectional portion taken along dashed line X-X in FIG. 6.

[0101] First, as in the first embodiment, a heat dissipating base plate 40 is prepared (step S10 in FIG. 26 ). Next, a plating process is performed on the entire surface of the heat dissipating base plate 40 to form a plating film 41 (step S11c in FIG. 26 ). For example, as shown in FIG. 27 , a plating process is performed on the front surface 40a, back surface 40c, and side surface 40d of the heat dissipating base plate 40 to form the plating film 41. The plating process may be a commonly known method, such as electrolytic plating or electroless plating. The plating films 41 thus formed on the entire surface of the heat dissipating base plate 40 may each have the same thickness. In this case, the thickness may be, for example, 1 μm or more and 10 μm or less.

[0102] Next, the plating film 41 on the front surface 40a of the heat dissipating base plate 40 is thinned by a thinning process (step S12c in FIG. 26). The plating film 41 on the front surface 40a of the heat dissipating base plate 40 is uniformly ground away from the entire surface. As shown in FIG. 28, the plating film 41 on the front surface 40a of the heat dissipating base plate 40 is made thinner than the other surfaces, and its thickness is 0.2 μm or less. This completes the preparation of the heat dissipating unit 4a (step S14 in FIG. 26).

[0103] The heat dissipation unit 4a may also be manufactured by the following manufacturing method. For example, during the plating process in step S11c of Fig. 26, the plating process may be performed so that the thickness of the plating film 41 formed on the front surface 40a of the heat dissipation base plate 40 is thinner than the thickness of the plating film 41 formed on the other surfaces.

[0104] The above example shows a case where the entire plating film 41 on the front surface 40a of the heat dissipating base plate 40 is made thinner than the other surfaces. However, this is not limited to this case, and only the solder regions 41b of the plating film 41 formed on the front surface 40a of the heat dissipating base plate 40 may be made thinner. Such plating film 41 may be formed by forming the plating film 41 on the entire surface of the heat dissipating base plate 40, as in step S11c above, and then grinding and thinning only the plating film 41 in the solder regions 41b in step S12c.

[0105] Alternatively, the plating film 41 may be formed on the entire surface of the heat dissipating base plate 40 to a thickness of at least 0.2 μm, the solder regions 41 b of the plating film 41 may be masked, and the plating film 41 may be further formed and the masking removed. In this case, the plating film 41 is also formed on the heat dissipating base plate 40 using electrolytic plating or electroless plating to the desired thickness. As a result, only the solder regions 41 b of the plating film 41 formed on the front surface 40 a of the heat dissipating base plate 40 can be made thinner than the other portions.

[0106] Alternatively, the thickness of the plating film 41 formed on the entire surface, including the solder regions 41b, of the heat dissipating base plate 40 may be set to 0.2 μm or less. In this case, the plating film 41 is also formed on the heat dissipating base plate 40 using an electrolytic plating method or an electroless plating method until the plating film 41 reaches the desired thickness.

[0107] Next, an arrangement step is performed in which the heat dissipation unit 4a, the insulating circuit board 20, and the semiconductor chip 25 are arranged in this order (step S2 in FIG. 26 ). The arrangement step will be described with reference to FIGS. 29 and 30 . FIG. 29 is a cross-sectional view showing the arrangement step included in the manufacturing method of a semiconductor device according to the fourth embodiment. FIG. 30 is a schematic cross-sectional view showing the arrangement of atoms in the arrangement step included in the manufacturing method of a semiconductor device according to the fourth embodiment. Note that FIG. 30 schematically shows the atomic arrangement in area B surrounded by a dashed line in FIG. 29 . Also, FIG. 30 merely shows the arrangement of atoms schematically, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0108] The insulating circuit boards 20 are placed in the placement areas 40b of the plating films 41 formed on the heat dissipation units 4a via solder plates 27a. The solder plates 27a are formed by hardening the solder 27 in a plate shape. In this case, as in the first embodiment, the solder plates 27a may have the same size as the lower surface 23a of the metal plate 23 of the insulating circuit board 20 in a plan view.

[0109] The semiconductor chip 25 is placed on the upper surface 22a of the conductive pattern 22 of the insulating circuit board 20 via a solder plate 26a. The solder plate 26a is formed by hardening the solder 26 in a plate shape. The solder plate 26a may be, for example, the same size as the semiconductor chip 25 in a plan view.

[0110] By this placement process, as shown in Figure 29, the insulating circuit board 20 is placed in the placement area 40b of the heat dissipation unit 4a via the solder plate 27a, and the semiconductor chip 25 is placed on the conductive pattern 22 of the insulating circuit board 20 via the solder plate 26a.

[0111] 29 is near the boundary between the heat dissipation base plate 40 and the solder plate 27a in the heat dissipation unit 4a. At the boundary in this region B, as shown in FIG. 30, tin atoms, which are a solder component contained in the solder plate 27a, and nickel atoms contained in the plating film 41 are regularly arranged on either side of the boundary L1. This boundary L1 corresponds to the boundary between the solder plate 27a and the plating film 41 when the solder plate 27a is placed on the plating film 41. The boundary may contain solder components other than tin, such as silver and zinc. While only tin, a typical solder component, will be described below, other solder components may also be included.

[0112] Furthermore, nickel atoms contained in the plating film 41 and copper atoms contained in the heat dissipation base plate 40 are regularly arranged across a boundary L2. This boundary L2 corresponds to the boundary between the plating film 41 and the placement region 40b of the heat dissipation base plate 40 when the plating film 41 is formed in the placement region 40b of the heat dissipation unit 4a (heat dissipation base plate 40).

[0113] Since the solder plate 27a is not bonded when it is placed on the heat dissipation base plate 40 (plating film 41), air layers contained in the unevenness of the solder plate 27a exist between the solder plate 27a and the metal plate 23, and between the solder plate 27a and the heat dissipation base plate 40 (plating film 41), but this description is omitted.

[0114] Next, a bonding step is performed between the heat dissipation unit 4a and the insulating circuit board 20, and between the insulating circuit board 20 and the semiconductor chip 25 (step S3 in FIG. 26). The bonding step will be described with reference to FIGS. 31 and 32. FIG. 31 is a cross-sectional view showing the bonding step included in the manufacturing method of a semiconductor device according to the fourth embodiment. FIG. 32 is a schematic cross-sectional view showing the arrangement of atoms in the bonding step included in the manufacturing method of a semiconductor device according to the fourth embodiment. Note that FIG. 32 schematically shows the atomic arrangement in area B surrounded by a dashed line in FIG. 31. Also, FIG. 32 merely shows the arrangement of atoms schematically, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0115] The solder plate 27a between the heat dissipation unit 4a and the insulating circuit board 20 arranged in step S2, and the solder plate 26a between the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25 are heated. The solder plates 26a and 27a melt and turn into solders 26 and 27, respectively.

[0116] When heated in this manner, the tin atoms of the molten solder 27 and the nickel atoms of the plating film 41 migrate and diffuse beyond the boundary L1. Furthermore, the copper atoms of the heat dissipating base plate 40 and the nickel atoms of the plating film 41 migrate and diffuse beyond the boundary L2. Furthermore, the tin atoms of the molten solder 27 further migrate and diffuse beyond the boundary L2 into the copper atoms of the heat dissipating base plate 40. Furthermore, the copper atoms of the heat dissipating base plate 40 further migrate and diffuse beyond the boundary L1 into the tin atoms of the molten solder 27.

[0117] The plating film 41 on the front surface 40a of the heat dissipating base plate 40 is formed sufficiently thin. Therefore, nickel atoms in the plating film 41 are replaced by tin and copper atoms, resulting in plating erosion. As a result, as shown in FIG. 32 , the plating film 41 is eroded between the solder 27 and the heat dissipating base plate 40 near the boundaries L1 and L2, forming an alloy layer 44. In this case, traces of copper atoms moving within the heat dissipating base plate 40, as shown in FIG. 20 , do not become voids (Kirkendall voids). This alloy layer 44 contains copper atoms, tin atoms, and nickel atoms. Such an alloy layer 44 may be included in the boundary between the solder 27 and the heat dissipating base plate 40, not limited to the area indicated by area B.

[0118] The molten solders 26 and 27 are cooled and hardened, and the insulating circuit board 20 is bonded to the placement area 40b of the heat dissipation unit 4a (front surface 40a of heat dissipation base plate 40) via the hardened solder 27. Similarly, the semiconductor chip 25 is bonded to the upper surface 22a of the insulating circuit board 20 via the hardened solder 26.

[0119] Thus, the semiconductor unit 2 is formed, including the insulating circuit board 20 and the semiconductor chip 25. The semiconductor unit 2 is also joined with solder 27 to the placement area 40b of the heat dissipation unit 4a.

[0120] Thereafter, similarly to the first embodiment, the steps of the enclosing step (step S4 in FIG. 26), the wiring step (step S5 in FIG. 26), and the sealing step (step S6 in FIG. 26) are performed in order. By the above steps, the semiconductor device 1a shown in FIG. 25 is obtained.

[0121] In the semiconductor device 1a described above, the insulating circuit board 20 and the heat dissipating base plate 40 having the plating film 41 on the front surface 40a are also joined by the solder plate 27a. Therefore, the plating film 41 is eroded in the placement area 40b of the heat dissipating base plate 40. That is, the thickness of the plating film 41 on the front surface 40a of the heat dissipating base plate 40 of the semiconductor device 1a is significantly thinner than that of the reference example shown in FIG. 16 , and disappears during joining. Therefore, an alloy layer 44 containing atoms constituting the heat dissipating base plate 40, tin atoms constituting the solder 27, and nickel atoms constituting the plating film 41 is formed, thereby suppressing the generation of voids in the heat dissipating base plate 40. Furthermore, the generation of voids is similarly suppressed even when the semiconductor device 1a generates heat due to long-term operation. As a result, an increase in the thermal resistance of the heat dissipating base plate 40 is suppressed, and a decrease in the heat dissipation performance of the semiconductor device 1a including the heat dissipating base plate 40 is suppressed. This also prevents a decrease in the reliability of the semiconductor device 1a.

[0122] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0123] REFERENCE SIGNS LIST 1, 1a Semiconductor device 2 Semiconductor unit 3 Case 4, 4a Heat dissipation unit 20 Insulated circuit board 21 Insulating plate 22 Conductive pattern 22a Upper surface 23 Metal plate 23a Lower surface 24 Plating film 25 Semiconductor chip 26, 27 Solder 26a, 27a Solder plate 27b Fillet portion 31 Frame portion 31a Upper opening 31b Lower opening 31c Upper inner wall 31d Step 31e Lower inner wall 31f Storage area 32 External connection terminal 32a Internal wiring portion 32b External wiring portion 40 Heat dissipation base plate 40a Front surface 40b Arrangement area 40c Back surface 40d Side surface 41 Plating film 41a Opening area 41b Solder area 42 Mask 43 Resist film 44 Alloy layer 50 Sealing member 51 Wire

Claims

1. A semiconductor device comprising: a substrate including an underside; a heat dissipating base plate including a main surface and having an arrangement area on the main surface where the underside of the substrate is arranged via solder; a first plating film formed on the main surface of the heat dissipating base plate, excluding a solder area on the arrangement area of ​​the main surface where the solder has spread; and an alloy layer included between the solder and the arrangement area of ​​the heat dissipating base plate, the alloy layer including a solder component contained in the solder.

2. The semiconductor device according to claim 1, wherein the alloy layer further contains, in addition to the solder component, a first metal material contained in the heat dissipating base plate.

3. The semiconductor device according to claim 2, wherein the first metal material includes copper.

4. The semiconductor device according to claim 1, wherein the first plating film is composed mainly of nickel.

5. The semiconductor device according to claim 1, wherein the outer periphery of the placement region is located inside the outer periphery of the substrate in a plan view.

6. The semiconductor device according to claim 1, wherein the first plating film is formed on the main surface of the heat dissipating base plate, excluding an opening area surrounding the entire periphery of the solder area.

7. The semiconductor device according to claim 6, wherein the placement region is recessed relative to the main surface excluding the placement region.

8. The semiconductor device according to claim 7, wherein the solder includes a fillet portion that extends outward from the lower surface of the substrate in a plan view.

9. The semiconductor device according to claim 8, wherein an outer periphery of the fillet portion of the solder is located outside the placement area in a plan view.

10. The semiconductor device described in claim 6, wherein the substrate includes an insulating plate, a conductive pattern formed on the front surface of the insulating plate, and a metal plate formed on the back surface of the insulating plate and including the underside, and a second plating film is formed on a side surface of the metal plate surrounding the entire outer periphery of the underside except for the underside.

11. The semiconductor device according to claim 10, wherein the metal plate is mainly composed of copper.

12. The semiconductor device according to claim 10, wherein the second plating film is composed mainly of nickel.

13. The semiconductor device according to claim 6, further comprising a resist material formed so as to surround the entire periphery of an opening edge portion of the first plating film formed on the front surface of the heat dissipating base plate.

14. The semiconductor device according to claim 2, wherein the alloy layer further includes a second metal material that constitutes the first plating film together with the solder component and the first metal material.

15. The semiconductor device according to claim 14, wherein the second metallic material includes nickel.

16. The semiconductor device described in claim 14, wherein the first plating film is further formed on a surface of the heat dissipation base plate other than the main surface, and the thickness of the first plating film formed on the main surface is thinner than the thickness of the first plating film formed on the surface other than the main surface.

17. The semiconductor device according to claim 14, wherein the first plating film formed on the main surface has a thickness of less than 0.2 μm.

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