Method for manufacturing ceramic circuit board by using light sintering, ceramic circuit board, and double-sided cooling power module

Abstract

The present invention provides a method for manufacturing a ceramic circuit board by using light sintering, and a conductive layer formed using same. The method for manufacturing a ceramic circuit board by using light sintering, according to one embodiment of the present invention, comprises: a conductive paste layer formation step of forming, on a substrate, a conductive paste layer including conductive powder; a mask arrangement step of arranging a mask on the conductive paste layer; a main light irradiation step of irradiating the conductive paste layer with light by using the mask, thereby forming a light-sintered region in which the conductive powder is light-sintered; and a conductive layer formation step of removing a non-sintered region of the conductive paste layer in which light sintering has not been performed, such that a conductive layer is formed in the light-sintered region.

Description

Method for manufacturing a ceramic circuit board using optical sintering, ceramic circuit board, and double-sided cooling power module

[0001] The technical idea of ​​the present invention relates to a ceramic circuit board, and more specifically, to a method for manufacturing a ceramic circuit board using photo-sintering, a ceramic circuit board, and a double-sided cooling power module.

[0002] The present invention relates to the development of advanced compound power semiconductor technology (R&D) (Project No. RS-2024-00405131) supported by the Korea Institute of Industrial Technology Planning and Evaluation with funding from the Ministry of Trade, Industry and Energy.

[0003] Power semiconductor devices, widely used in mobile devices, home appliances, and automobiles, play a role in converting, processing, and controlling power. Power semiconductor devices, which require high current and voltage for power supply, generate a significant amount of heat, and therefore use ceramic circuit boards made of ceramic materials such as Al2O3, AlN, Zirconia Toughened Alumina (ZTA), and Si3N4. Ceramics have high insulation, mechanical strength, and relatively high heat dissipation performance, making them suitable as substrates for high-power power semiconductor devices. In addition, ceramic circuit boards may include conductive patterns made of aluminum (Al) or copper (Cu), which have high thermal conductivity, on the ceramic material.

[0004] In order to easily dissipate heat generated from power semiconductor devices, a double-sided cooling type power module is being used, which can cool both sides by placing ceramic circuit boards on both sides of the power semiconductor devices. In addition, to dissipate heat from the power module, cooling fins are placed on the outside of the ceramic circuit board, and heat can be transferred to a water cooler installed externally through the cooling fins.

[0005] Wiring in power semiconductor devices is typically formed through photolithography or damascene processes, which involve deposition, exposure, and development. Consequently, these processes require expensive equipment, such as deposition equipment, and additional materials, such as photoresist.

[0006] Alternatively, methods have been proposed to form wiring by performing high-temperature metallization using metal foil or conductive powder. In this case, the metallization process requires a specific energy source, and the process of metallizing the pattern is performed separately after forming the conductive powder pattern in the shape of the wiring. Furthermore, numerous processes, such as bonding, photolithography, and etching, are required, requiring additional equipment, requiring significant processing time and costs, and causing physical, chemical, and environmental problems. Furthermore, the metallization of the conductive powder requires high temperatures exceeding 600°C, which can lead to issues such as migration and diffusion to the substrate, and the generation of carbon dioxide during the process, which can cause environmental problems.

[0007] The technical problem to be achieved by the technical idea of ​​the present invention is to provide a method for manufacturing a ceramic circuit board using low-temperature optical sintering, a ceramic circuit board, and a double-sided cooling power module.

[0008] However, these tasks are exemplary and the technical idea of ​​the present invention is not limited thereto.

[0009] According to one aspect of the present invention, a method for manufacturing a ceramic circuit board using optical sintering, a ceramic circuit board, and a double-sided cooling type power module are provided.

[0010] According to one embodiment of the present invention, the method for manufacturing the ceramic circuit board may include a conductive paste layer forming step of forming a conductive paste layer including conductive powder on a substrate; a mask placing step of placing a mask on the conductive paste layer; a main light irradiation step of irradiating light using the mask to the conductive paste layer to form a photo-sintered region in which the conductive powder is photo-sintered; and a conductive layer forming step of removing a non-photo-sintered unsintered region of the conductive paste layer so that a conductive layer is formed in the photo-sintered region.

[0011] According to one embodiment of the present invention, after performing the step of forming the conductive paste layer, a preliminary drying step of drying the conductive paste layer may be further included.

[0012] According to one embodiment of the present invention, after performing the step of forming the conductive paste layer, a pressing step of pressing the conductive paste layer may be further included.

[0013] According to one embodiment of the present invention, after performing the step of placing the mask, a preliminary light irradiation step of irradiating light to the conductive paste layer using the mask to dry the conductive paste layer may be further included.

[0014] According to one embodiment of the present invention, a drying step of drying the conductive layer may be further included.

[0015] According to one embodiment of the present invention, the step of forming the conductive paste layer may form the conductive paste on the substrate using screen printing, inkjet printing, gravure printing, or flexography.

[0016] According to one embodiment of the present invention, the main light irradiation step is 1 J / cm 2 30 J / cm 2It can be performed using light having a pulse intensity in the range of 0.1 ms to 60 ms, a pulse gap in the range of 0.1 ms to 60 ms, and a pulse number in the range of 1 to 100.

[0017] According to one embodiment of the present invention, the main light irradiation step can be performed by at least one of a single shot irradiating light once, a multi-shot irradiating the same light multiple times, and a step shot irradiating light multiple times while changing the light.

[0018] According to one embodiment of the present invention, the step shot can be performed while changing the pulse intensity of the light.

[0019] According to one embodiment of the present invention, in the conductive layer forming step, the removal of the unsintered region can be performed using distilled water or a basic solution containing sodium hydroxide, potassium hydroxide, sodium carbonate, potassium carbonate or a mixture thereof as a developing solution.

[0020] According to one embodiment of the present invention, the conductive powder may include copper (Cu), silver (Ag), gold (Au), aluminum (Al), nickel (Ni), palladium (Pd), titanium oxide (TiO), or a combination thereof.

[0021] According to one embodiment of the present invention, the conductive powder may include a first powder having a first diameter in the range of 1 μm to 10 μm in an amount of 50 wt% to 90 wt%, and a second powder having a second diameter in the range of 20 nm to 1000 nm in an amount of 10 wt% to 50 wt%.

[0022] According to one embodiment of the present invention, the conductive powder may have at least one shape among a spherical shape, a square shape, a wire shape, a plate shape, a nanotube shape, a rod shape, and a whisker shape.

[0023] According to one embodiment of the present invention, the substrate may include a silicon substrate, a wafer, a glass substrate, a metal substrate, a ceramic substrate, a polymer substrate, a rigid substrate, a flexible substrate, a low-k film substrate, or a ceramic sheet substrate.

[0024] According to one embodiment of the present invention, the substrate may include at least one of Al2O3, AlN, ZTA (Zirconia Toughened Alumina), and Si3N4.

[0025] According to one embodiment of the present invention, the ceramic circuit board includes a ceramic layer, a base copper layer, and a copper structure, and the conductive layer may be at least one of the base copper layer and the copper structure.

[0026] According to one embodiment of the present invention, the copper structure may include a region on the upper side having the differential porosity and having a lower porosity than a lower side relatively adjacent to the first base copper layer.

[0027] According to one embodiment of the present invention, a method for manufacturing a ceramic circuit board using the above-described optical sintering may include: forming a conductive paste layer including a conductive powder on a substrate; placing a mask on the conductive paste layer; irradiating light to the conductive paste layer using the mask to harden a portion of the conductive paste layer; removing an uncured region of the conductive paste layer; drying a cured region of the conductive paste layer; and sintering the cured region to form a conductive layer.

[0028] According to one embodiment of the present invention, the sintering may be performed by thermal sintering or light sintering.

[0029] According to one embodiment of the present invention, the ceramic circuit board can be formed using the method for manufacturing a ceramic circuit board using the above-described optical sintering.

[0030] According to the technical idea of ​​the present invention, the method for manufacturing a ceramic circuit board using optical sintering allows the use of substrates that may be damaged at high temperatures, since the formation of the conductive layer is performed at low temperatures rather than through high-temperature metallization. In addition, since a conductive paste layer is formed over the entire substrate and then metallization by optical sintering is used to form a pattern, the fixation and stability of the pattern can be superior compared to a method in which the pattern itself is screen-printed. In addition, since optical sintering is possible at a low temperature of 300°C or less for a short time, it is efficient and can reduce process time and cost. In addition, the conductive layer has excellent straightness and surface roughness, so that the resistance of the layer can be reduced and the skin effect can be minimized, and therefore, it can be applied to high-frequency circuits such as millimeter waves.

[0031] The method for manufacturing a ceramic circuit board using optical sintering according to the present invention can be applied to various electronic industries, including displays, lighting, energy, and sensors. Furthermore, it can be applied to existing rigid substrates, as well as flexible substrates that can be bent, folded, or rolled. This allows for the creation of practical and portable electronic products. In particular, since optical sintering is possible at temperatures of approximately 300°C, it can be applied to polymer-based substrates that can be deformed at temperatures exceeding 300°C.

[0032] The method for manufacturing a ceramic circuit board using optical sintering according to the present invention can be applied to radio frequency identification tags (RFID tags), near field communication (NFC) devices, solar cells, etc., and can be applied to disposable electronics, wearable electronics, deformable batteries, etc.

[0033] The ceramic circuit board according to the present invention can form a three-dimensional pattern on a ceramic substrate by using a copper structure formed by printing, pressing, and sintering as a spacer, so as to be compatible with various types of semiconductor devices mounted on the substrate. Furthermore, the use of the copper structure improves electrical and thermal conductivity, and enhances durability against thermal cycles.

[0034] In addition, since the above copper structure is a sintered material rather than a rolled material, there are differences in the microstructure, such as not having the directionality that appears in a rolled material, and there are differences in the degree of inclusion and distribution of pores.

[0035] While the Mo-Cu spacer according to the prior art has a porosity of about 0% and thus has high thermal stress and low thermal fatigue characteristics, the copper structure according to the present invention includes a lower layer having a high porosity, thereby providing low thermal stress and improved resistance to thermal fatigue destruction, and further includes an upper layer having a low porosity, thereby preventing bonding defects in power semiconductor devices.

[0036] In addition, since the copper structure has a pyramidal shape, a power semiconductor element can be stably mounted.

[0037] The method for manufacturing a ceramic circuit board according to the present invention can prevent the formation of defects due to heat by performing sintering of a copper structure at a temperature ranging from 500°C to 800°C. In addition, by performing surface blasting treatment, copper oxide formed on the surface of the copper structure during sintering can be removed to provide a smooth surface, thereby ensuring stable bonding of power semiconductor devices mounted on the copper structure.

[0038] The effects of the present invention described above are illustrative, and the scope of the present invention is not limited by these effects.

[0039] FIG. 1 is a flowchart illustrating a method for manufacturing a ceramic circuit board using optical sintering according to one embodiment of the present invention.

[0040] Figures 2 to 7 are cross-sectional views illustrating a method for manufacturing a ceramic circuit board using optical sintering according to one embodiment of the present invention, step by step.

[0041] FIG. 8 is a schematic diagram illustrating optical sintering of conductive powder in a method for manufacturing a ceramic circuit board using optical sintering according to one embodiment of the present invention.

[0042] FIG. 9 is a photograph of the surface of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to an embodiment of the present invention.

[0043] FIG. 10 is a scanning electron microscope photograph of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to an embodiment of the present invention.

[0044] Fig. 11 is a graph showing the surface roughness of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to one embodiment of the present invention.

[0045] FIG. 12 is a photograph of the surface according to the process steps of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to an embodiment of the present invention.

[0046] Fig. 13 is a scanning electron microscope photograph of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to one embodiment of the present invention.

[0047] Figures 14 to 17 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.

[0048] FIGS. 18 and 19 are cross-sectional views illustrating a base copper layer and a copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0049] FIG. 20 is a photograph showing the microstructure of a copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0050] FIG. 21 and FIG. 22 are cross-sectional views and photographs showing a pyramid-shaped copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0051] Figure 23 is a flowchart illustrating a method for manufacturing a ceramic circuit board according to one embodiment of the present invention.

[0052] Figure 24 is an ultrasonic inspection result showing whether a defect occurs depending on the sintering temperature of a ceramic circuit board according to an embodiment of the present invention.

[0053] FIG. 25 is a photograph showing the surface state of a copper structure of a ceramic circuit board before and after blasting treatment according to an embodiment of the present invention.

[0054] FIG. 26 is a perspective view illustrating a pair of ceramic circuit boards for forming a double-sided cooling power module according to one embodiment of the present invention.

[0055] Figures 27 to 30 are cross-sectional views illustrating a double-sided cooling power module according to one embodiment of the present invention.

[0056] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Embodiments of the present invention are provided to more completely explain the technical idea of ​​the present invention to those skilled in the art. The following embodiments may be modified in various different forms, and the scope of the technical idea of ​​the present invention is not limited to the following embodiments. Rather, these embodiments are provided to more faithfully and completely convey the technical idea of ​​the present invention to those skilled in the art. Like reference numerals throughout this specification denote like elements. Furthermore, various elements and areas in the drawings are schematically drawn. Therefore, the technical idea of ​​the present invention is not limited by the relative sizes or intervals drawn in the attached drawings.

[0057] In this specification, a layer formed "on" another layer may refer to a layer formed directly above the other layer, or may refer to an intermediate layer or layers formed on another layer. It should be noted that the meanings of "upper" and "lower" in this specification are relative, and the direction upward from the substrate is described as "upper", and the direction downward is described as "lower."

[0058] Due to the trend of industrial diversification, printing technology is evolving with a variety of materials. Research is underway on photonics sintering, a method capable of forming circuit wiring without substrate deformation or deterioration. This photonics sintering method has been commercialized in some processes in the flexible electronics industry, and active research is underway in applications that can leverage the benefits of rapid sintering.

[0059] The optical sintering method can form a highly conductive wiring by sintering ink or paste containing conductive powder at a high speed ranging from several ms to tens of ms by irradiating it with strong pulsed light, which is different from the conventional high-temperature and long-time sintering.

[0060] The present invention relates to optical sintering of inorganic and organic materials, and studies the changes in the electrical and physical properties of inorganic and organic materials due to optical sintering. Furthermore, when optically sintering printed compositions, process variables such as the intensity, amount, and time of optical energy, as well as differences in the degree of sintering, were analyzed. Accordingly, the influence of optical energy on the composition of inorganic and organic materials was analyzed, and an appropriate paste composition was derived. These results of the present invention can be applied to various electronic components, such as high-frequency band communication components. Furthermore, they can be applied to ceramic substrates or spacers of power semiconductor devices.

[0061] Optical sintering offers the following advantages: Because it utilizes light for sintering, it enables high-speed, large-area sintering. It also allows for effective, selective sintering of required areas. It also allows for sintering at relatively low temperatures. Furthermore, the process is simple and ensures product uniformity.

[0062] Heat dissipation substrates for power modules require a flat surface and a three-dimensional structure when power semiconductor devices are mounted. Conventional screen printing methods, however, require a compression process due to the uneven surface, and the screen mask's manufacturing resolution affects the patterning resolution, limiting high-precision patterning. Furthermore, after screen printing, the friction between the screen mask mesh and the emulsion during plate-release causes the outer edge to rise, requiring a compression process to flatten the substrate to reduce this height difference. Conventional screen printing has limitations, with a line width of 50 μm or more and a deviation of ±5% or more.

[0063] The technical idea of ​​the present invention can be applied to micro-patterning, whereby only a portion corresponding to a circuit area is locally exposed to light using a mask, the uncured area is removed with a developer, and sintered to metallize. Alternatively, sintering can be performed by exposure.

[0064] The method for manufacturing a ceramic circuit board using optical sintering according to the technical concept of the present invention involves performing optical sintering locally on a conductive layer using a mask to metallize the conductive layer, and removing the areas covered by the mask and not subjected to optical sintering using a developer. Therefore, the patterning process and the metallization process can be performed in a single process.

[0065] FIG. 1 is a flowchart illustrating a method for manufacturing a ceramic circuit board using optical sintering according to one embodiment of the present invention.

[0066] Referring to FIG. 1, a method for manufacturing a ceramic circuit board using photo-sintering (S1) includes a conductive paste layer forming step (S10) of forming a conductive paste layer including conductive powder on a substrate; a preliminary drying step (S20) of drying the conductive paste layer; a pressing step (S30) of pressing the conductive paste layer; a mask placing step (S40) of placing a mask having a pattern formed on the conductive paste layer; a preliminary light irradiation step (S50) of irradiating light onto the conductive paste layer using the mask to dry the conductive paste layer; a main light irradiation step (S60) of irradiating light onto the conductive paste layer using the mask to form a photo-sintered region in which the conductive powder is photo-sintered; a conductive layer forming step (S70) of removing an unphoto-sintered region of the conductive paste layer so that a conductive layer is formed in the photo-sintered region; and a drying step (S80) of drying the conductive layer.

[0067] At least one of the above-mentioned preliminary drying step (S20), the above-mentioned pressing step (S30), the above-mentioned preliminary light irradiation step (S50), and the above-mentioned drying step (S80) is optional and may be omitted.

[0068] Figures 2 to 7 are cross-sectional views illustrating a method for manufacturing a ceramic circuit board using optical sintering according to one embodiment of the present invention, step by step.

[0069] Referring to FIGS. 1 and 2, the conductive paste layer forming step (S10) can be performed by forming a conductive paste layer (20) including conductive powder on a substrate (10).

[0070] The conductive paste layer (20) can be formed on the substrate (10) using screen printing, inkjet printing, gravuring, or flexography. However, this is exemplary and the technical idea of ​​the present invention is not limited thereto.

[0071] The conductive paste layer (20) can be formed over the entire surface of the substrate (10) or locally.

[0072] The substrate (10) may include various substrates, and since the light sintering has a low process temperature of about 300°C or a high process temperature of about 1000°C, the light application time is very short, on the order of milliseconds, so it may include a substrate that is weak to high temperatures or a temperature-sensitive substrate. The substrate (10) may include, for example, a silicon substrate, a wafer, a glass substrate, a metal substrate, a ceramic substrate, a polymer substrate, a rigid substrate, a flexible substrate, a low-k film substrate, or a ceramic sheet substrate. However, this is an example, and the technical idea of ​​the present invention is not limited thereto.

[0073] The conductive paste forming the conductive paste layer (20) may include a conductive powder, a dispersant, and a solvent. The conductive paste may further include a polymer resin.

[0074] The conductive powder may include a metal or an oxide, for example, copper (Cu), silver (Ag), gold (Au), aluminum (Al), nickel (Ni), palladium (Pd), titanium oxide (TiO), or a combination thereof. The combination may include simple mixtures and alloys of the above-described metal materials. In addition, the conductive powder may include a core-shell material in which another metal has a core-shell structure, for example, a silver core-copper shell material, or a copper core-silver shell material.

[0075] The conductive powder may have a diameter capable of being photo-sintered, and for this purpose, it is preferable to have a diameter in the nano-millimeter range. The conductive powder may have a diameter in the range of, for example, 20 nm to 10 μm. The conductive powder may have a micro-sized diameter of, for example, 10 μm or less, and may have a first diameter in the range of, for example, 1 μm to 10 μm. Alternatively, the conductive powder may have a nano-sized diameter of, for example, 1000 nm or less, and may have a second diameter in the range of, for example, 20 nm to 1000 nm.

[0076] The conductive powder may be a mixed powder in which a first powder having a first diameter in the range of 1 μm to 10 μm and a second powder having a second diameter in the range of 20 nm to 1000 nm are mixed. The conductive powder may contain the first powder in the range of 50 wt% to 90 wt% and the second powder in the range of 10 wt% to 50 wt%.

[0077] The conductive powder may be a mixed powder comprising three or more powders having different diameters. In this way, by using a conductive powder comprising a mixture of powders having different diameters, the density of the formed conductive layer can be increased.

[0078] The conductive powder may have various shapes, for example, at least one of a spherical type, an angular type, a wire type, a flake type, a nano tube type, a rod type, and a whisker type.

[0079] The dispersant can perform the function of uniformly dispersing solid particles such as the conductive powder in a solvent and preventing the solid particles from separating, agglomerating, or precipitating. The dispersant can reduce the interfacial tension between the inorganic powder and the polymer resin solution and can act through electrostatic repulsion or a steric effect. In particular, when the conductive powder has a diameter of nano-millimeters, it is preferable to include the dispersant. The dispersant can include various surfactants, and can include, for example, a saturated fatty acid or an unsaturated fatty acid, and can include, for example, a polycarboxylic acid-based material, an alkylamine-based material, a silicone-based material, and the like. The dispersant may include, for example, 2-Ethylhexyl 2-propenoate reaction products with ethylenediamine-ethylenimine polymer, a compound with polyethylene-polypropylene glycol monobutyl etherphosphate, a mixture of quaternary ammonium hydroxide, and the like.

[0080] The solvent may include an alcohol-based substance, an ether-based substance, or an ester-based substance, and may be polar or nonpolar. For example, the solvent may include a substance having a mean boiling point of 150°C or higher, such as diethylene glycol monoethyl ether acetate (ECA), ethylene glycol monobutyl ether acetate (BCA), alpha-terpineol, or hexylene glycol (HG).

[0081] The polymer resin may be added to improve at least one of the following properties: adhesion to the substrate of the conductive paste layer, shape retention, viscosity control, leveling, and photosensitivity. The polymer resin may include various polymer materials, such as high-polymer and synthetic polymer compound forms.

[0082] The polymer resin may include, for example, at least one of polyvinyl butyral (PVB), polyvinyl pyrrolidone (PVP), ethylene carbonate (EC), polyvinyl alcohol (PVA), polyvinyl chloride (PVC), polyethylene (PE), and polypropylene (PP). Such a polymer resin may implement improved properties for adhesion of the conductive paste layer to the substrate, shape retention, viscosity control, and leveling.

[0083] Additionally, the polymer resin may include a photopolymer resin. The photopolymer resin may include various photosensitive materials and may include at least one of an oligomer, a monomer, and a photoinitiator.

[0084] The above oligomer may include, for example, at least one of an epoxy resin, an acrylate resin, a polyurethane resin, and a polyester resin.

[0085] The epoxy resin may include, for example, bisphenol A type epoxy, bisphenol F type epoxy, phenol novolac type epoxy, cresol novolac type epoxy, trisphenol methane type epoxy, biphenyl type epoxy, aliphatic type glycidyl ether, alicyclic epoxy, etc.

[0086] The above acrylate resin may include a resin synthesized using acrylate or methacrylate as a main monomer, may include acrylic acid and methacrylic acid or derivatives thereof, such as esters, nitriles, amides, etc., and may include various resins obtained by polymerizing olefin monomers. The above acrylate resin may include, for example, polymethyl methacrylate (PMMA), polyacrylic acid (PAA), polyacrylamide, polyacrylonitrile (PAN), butyl acrylate, 2-chloroethyl vinyl ether, etc.

[0087] The polyurethane resin may include, for example, ethylene glycol, propylene glycol, diethylene glycol, neopentyl glycol, 1,6-hexanediol, 1,4-butanediol, polytetramethylene glycol, polybutadiene diol, bisphenol A polyethoxydiol, triethylene propane, and the like.

[0088] The polyester resin may include, for example, carboxylated polyester acrylate, polyester triacrylate oligomer, polyester hexaacrylate oligomer, acid modified polyester acrylate, chlorinated polyester acrylate, etc.

[0089] The above monomer can react with other monomer molecules to form larger polymer chains or three-dimensional networks through a polymerization process. The above monomer has a molecular weight of 1,000 or less, and acts as a cross-linking agent and diluent for the oligomer, and can adjust the working viscosity while participating in the UV curing reaction to form part of the layer.

[0090] The above monomer may include various monomer materials and may include a material having a functional group in the range of 1 to 3.

[0091] The above monofunctional monomers include, for example, N-methoxymethyl methacrylamide, N-ethoxymethyl methacrylamide, N-alkoxymethyl methacrylamide, 2-hydroxyethyl methacrylate, 2-hydroxypropyl methacrylate, 4-hydroxybutyl methacrylate, 2-ethylhexyl methacrylate, 2-ethylhexyl polyethoxy methacrylate, ethylcarbitol methacrylate, carbitol methacrylate, Tetrahydropropryl methacrylate, N,N-dimethylaminoethyl methacrylate, N,N-diethylaminoethyl methacrylate, 3-(N,N-dimethylamino)propyl methacrylate, 3-(N,N-dimethylamino)propyl methacrylamide, N,N-diethylaminoethyl vinylether, 4-vinylpyridine methacrylamide, N-vinylpyrrolidone, N-vinyl caprolactam, acrylic morpholino morpholino), N,N,N-dimethylamino methacrylate, N,N-dimethyl methacrylamide, dicyclopentenyl methacrylate, dicyclopentenyloxyethyl methacrylate, hydrogenated dicyclopentenyl methacrylate, isobornyl methacrylate, cyclohexane-1,4-dimethylolmono methacrylate, o-phenyl·phenyloxyethyl methacrylate, o-phenyl·phenyloxyethyloxyethyl(meth) acrylate, phenyloxyethyl It may include phenyloxyethyl methacrylate, tribromphenyloxyethyl methacrylate, phenoxyethyl methacrylate, etc.

[0092] The above bifunctional monomers include, for example, 1,6-hexanediol dimethacrylate, neopentyl glycol dimethacrylate, 1,9-Nomendiol dimethacrylate, neopentyl glycol polypropoxy dimethacrylate, hydroxypivalic acid neopentyl glycol dimethacrylate, bisphenyl A polyethoxy dimethacrylate, bisphenol F polyethoxy dimethacrylate, polyethylene glycol dimethacrylate, It may include bis[methacryloyloxyethyl]hydroxyethyl isocyanurate, etc.

[0093] The above three functional monomers may include, for example, trimethylolpropane triacrylate (TMPTA), trimethylolpropane ethoxylate triacrylate (TMP3EOTA), ethoxylated trimethylolpropane triacrylate (TMP6EOTA), glyceryl propoxy triacrylate (G3POTA), and the like.

[0094] The photoinitiator can absorb energy from a light source, thereby inducing a photopolymerization reaction in the oligomer and the monomer. The photoinitiator can include various photoinitiators depending on the light used, such as short-wavelength light or long-wavelength light. For example, the photoinitiator can include, for example, an ultraviolet photoinitiator, a visible light photoinitiator, a near-infrared photoinitiator, a two-photon absorbing photoinitiator, a cationic photoinitiator, etc.The photoinitiator may be, for example, 4-methylbenzophenone, 4,4'-bis(diethylamino) benzophenone, 4-benzoyl-4'-methyldiphenylsulfide, ethyl phenlglyoxylate, ethyl o-benzoylbenzoate, 4-phenyl benzophenone, benzil dimethylketal, 2-ethylhexyl-4-dimethyl aminobenzoate, ethyl-4-dimethyl aminobenzoate, Hydroxy-2-methylphayl-propane-1-one, 1-hydroxycyclohexylphenylketone, sopropyl thioxanthone, 2,4-diethyl thioxanthone, 2,4,6-trimethylbenzoyl-diphenyl phosphine oxide, ethyl(2,4,6-trimethylbenzoyl)phenyl phosphinate It may include 2-benzyl-2-(dimethylamino)-1-[4-(morpholinyl)phenyl]-1-butanone, bis(2,4,6-trimethylbenzoyl)-phenylphosphineoxide, etc.

[0095] The proportions of the materials constituting the conductive paste may vary depending on the desired purpose. For example, in the conductive paste, the conductive powder may be 50 wt% to 90 wt%, the polymer resin may be 1 wt% to 10 wt%, the dispersant may be 0.1 wt% to 1 wt%, and the remainder may be the solvent. In addition, the oligomer may be 1 wt% to 10 wt%, the monomer may be 0.1 wt% to 1 wt%, and the photoinitiator may be 0.1 wt% to 1 wt%. However, this is merely exemplary and the technical idea of ​​the present invention is not limited thereto.

[0096] Referring to FIGS. 1 and 3, the preliminary drying step (S20) can be performed by drying the conductive paste layer (20).

[0097] In the above-described preliminary drying step (S20), the conductive paste layer (20) may be heated to a temperature ranging from 50°C to 100°C using a heater or the like to remove the solvent contained in the conductive paste layer (20). By this preliminary drying, the conductive paste layer (20) may be solidified. The preliminary drying may be performed by heat drying, and may be performed, for example, at a temperature ranging from 60°C to 100°C for 1 minute to 10 minutes. The preliminary drying may be performed, for example, by indirect hot air drying, direct hot air drying, far infrared drying, high-frequency heating, etc. However, this is merely exemplary, and the technical idea of ​​the present invention is not limited thereto. The above-described preliminary drying step (S20) is optional and may be omitted.

[0098] Referring to FIGS. 1 and 4, the pressing step (S30) can be performed by pressing the conductive paste layer (20) by using air pressure or a load.

[0099] By the above pressing step (S30), the internal pores of the conductive paste layer (20) can be reduced, the uniformity of height can be secured, and the thickness of the conductive paste layer (20) can be reduced. The pressing step (S30) is optional and can be omitted.

[0100] The conductive paste layer (20) can be physically flattened by the pressing described above. Alternatively, the conductive paste layer (20) can be physically flattened by dry leveling even when pressing is not performed.

[0101] The conductive paste layer (20) after performing the above pressing step (S30) may have various thicknesses that allow for photo-sintering, for example, may have a thickness of 20 μm or less, or may have a thickness in the range of 1 μm to 20 μm. However, this is exemplary and the technical idea of ​​the present invention is not limited thereto.

[0102] Referring to FIG. 1 and FIG. 5, the mask placement step (S40) can be performed by placing a mask (90) on a conductive paste layer (20).

[0103] The mask (90) may be placed in contact with the conductive paste layer (20) or may be placed spaced apart from it and not in contact. A pattern is formed on the mask (90), and the pattern can block light in a subsequent light irradiation step.

[0104] The mask (90) may be composed of glass, plastic, metal, paper, fiber, etc. The mask (90) may be a perforated type formed by forming an opening through which a material is removed, or a non-perforated type formed by forming a transparent area in the mask.

[0105] The above non-penetrating mask may be made of a transparent material, for example, a soda lime glass-based chrome (Cr) pattern mask, a quartz glass-based chrome pattern mask, a positive film patterning mask, etc.

[0106] The above-mentioned penetrating mask may be made of an opaque material, for example, a metal mask, a stainless steel mask, a ceramic sheet patterning mask, a film patterning mask, a paper patterning mask, etc.

[0107] However, this is exemplary and the technical idea of ​​the present invention is not limited thereto.

[0108] In addition, in the step of placing the mask (S30), the conductive paste layer (20) can be preheated to a temperature in the range of about 80°C to 120°C by being placed on a hot plate or the like.

[0109] Referring to FIG. 1 and FIG. 6, the preliminary light irradiation step (S50) and the main light irradiation step (S60) can be performed by irradiating light to the conductive paste layer (20) using a mask (90).

[0110] The above preliminary light irradiation step (S50) can be performed by irradiating light onto the conductive paste layer (20) using a mask (90) to dry the conductive paste layer (20). Accordingly, organic substances not removed from the conductive paste layer (20) in the preliminary drying step (S20) can be volatilized and removed. The light used in the preliminary light irradiation step (S50) can have a condition in which the conductive powder of the conductive paste layer (20) is not photo-sintered. The preliminary light irradiation step (S50) is optional and can be omitted.

[0111] The above main light irradiation step (S60) can be performed by irradiating light to the conductive paste layer (20) using a mask (90) to form a light-sintered area (22) in which the conductive powder is light-sintered.

[0112] The area of ​​the conductive paste layer (20) irradiated with light by the above-described photosintering can form a photosintered area (22). The area where light is blocked by the pattern of the mask (90) and not irradiated can form an unsintered area (24).

[0113] The above light can be obtained from various light sources, for example, an intense pulsed light (IPL) source can be used, and for example, a xenon flash lamp can be used.

[0114] For example, in the high-density pulse light source, some wavelength bands within the range of 100 nm to 1500 nm can be blocked, or only some wavelength bands can be selectively irradiated. In addition, selective light sources can be irradiated by cutting off / band passing through optical pulse filtering.

[0115] The above light is, for example, 1 J / cm 2 30 J / cm 2 It may have a pulse intensity in the range of 0.1 ms to 60 ms, a pulse gap in the range of 0.1 ms to 60 ms, and a pulse number in the range of 1 to 100 times. However, this is exemplary and the technical idea of ​​the present invention is not limited thereto.

[0116] The above light irradiation can be performed by at least one of a single shot in which light is irradiated once, a multi shot in which the same light is irradiated multiple times, and a step shot in which light is irradiated multiple times while changing the light. The step shot can be performed by changing the pulse intensity of the light, such as by increasing or decreasing it.

[0117] Referring to FIGS. 1 and 7, the conductive layer forming step (S70) may be performed by removing the non-photosintered unsintered region (24) of the conductive paste layer (20) to form the conductive layer (30). The non-sintered region (24) may be removed so that the substrate (10) is exposed. Accordingly, the remaining photosintered region (22) may form the conductive layer (30).

[0118] The removal of the above-mentioned non-sintered region (24) can be performed using a developer, and this can be referred to as a development process. At this time, the photo-sintered region (22) is not removed by the developer.

[0119] The developer may be distilled water or an alkaline solution. The developer may include a metal salt, an alkaline rare earth metal salt, or a mixture thereof, for example, sodium hydroxide (NaOH), potassium hydroxide (KOH), sodium carbonate (Na2CO3), potassium carbonate (K2CO3), or a mixture thereof. The developer may have a concentration in the range of 1 g / L to 10 g / L and a temperature in the range of 25°C to 40°C.

[0120] The above phenomenon can be performed using a wet method, for example, by applying, dipping, spraying, or puddle method. However, these are exemplary and the technical idea of ​​the present invention is not limited thereto.

[0121] The above application method can be performed by applying a developer on the conductive paste layer (20), developing it, and then removing the unsintered area (24) by washing it with distilled water or the like.

[0122] The above immersion method can be performed by immersing the structure of the substrate (10) and the conductive paste layer (20) in a container containing a developer, developing the structure, and then washing and removing the unsintered region (24) with distilled water or the like. Specifically, the immersion method can be performed by placing a developer containing only distilled water or a developer containing an alkaline substance in a container, and immersing the structure in the container. The cleaning can utilize ultrasonic cleaning, and the ultrasonic frequency can be in the range of 28 kHz to 300 kHz, the ultrasonic power can be in the range of 100 W to 1000 W, the temperature can be in the range of 25°C to 40°C, and the ultrasonic operating time can be in the range of 1 second to 5 minutes.

[0123] The spray method can be performed by spraying a developer through a nozzle onto the conductive paste layer (20) to develop it, and then washing and removing the unsintered region (24) with distilled water or the like. Specifically, the spray method can be performed by directly spraying a developer containing only distilled water or a developer containing an alkaline substance onto the structure using a nozzle. The nozzle can be flat or full cone, the temperature can range from 25°C to 40°C, the developing time can be 5 minutes or less, and the distilled water washing time can be 5 minutes or less. In addition, air drying to remove moisture can be performed within 5 minutes.

[0124] The above puddle method can be performed by providing a developer on a conductive paste layer (20), developing using surface tension, and then removing the unsintered area (24) by washing it with distilled water or the like.

[0125] However, this is exemplary and the technical idea of ​​the present invention is not limited thereto.

[0126] The above drying step (S80) can be performed by drying the conductive layer (30). By drying, the developer remaining from the conductive layer can be removed. The drying can be performed by heat drying, and can be performed, for example, at a temperature ranging from 60°C to 100°C for 1 to 10 minutes. The drying can be performed, for example, by indirect hot air drying, direct hot air drying, far infrared drying, high-frequency heating, etc. However, this is merely exemplary, and the technical idea of ​​the present invention is not limited thereto. The drying step (S80) is optional and can be omitted.

[0127] The conductive layer (30) formed using the method for manufacturing a ceramic circuit board using optical sintering according to the technical concept of the present invention can be applied to various fields requiring wiring. For example, it can be applied to mobile communication components, mobile communication modules, electrical devices, electronic devices, semiconductor devices, etc. In particular, the conductive layer (30) can be applied as a wiring layer in a substrate that can be destroyed at high temperatures, such as a flexible printed circuit board.

[0128] FIG. 8 is a schematic diagram illustrating optical sintering of conductive powder in a method for manufacturing a ceramic circuit board using optical sintering according to one embodiment of the present invention.

[0129] Referring to Fig. 8, the conductive powder (26) included in the conductive paste layer is individually separated before photo-sintering.

[0130] On the other hand, after performing photo-sintering, the conductive powders (26) undergo a sintering phenomenon on the surface to form a photo-sintered conductive powder sintered body (28). The light used in the photo-sintering can be used as metallization energy for the conductive powder (26). A conductive layer (30) can be formed by the conductive powder sintered body (28).

[0131] Experimental example

[0132] Below, preferred experimental examples are presented to aid understanding of the present invention. However, the following experimental examples are provided solely to aid understanding of the present invention, and the present invention is not limited to the following experimental examples.

[0133] A conductive paste containing conductive powder, dispersant, and solvent was prepared.

[0134] In the above conductive paste, the conductive powder is silver (Ag) powder, and flake silver powder with a diameter of 7 μm or less, spherical silver powder with a diameter of 7 μm or less, and nano silver powder with a diameter of 300 nm or less were prepared.

[0135] The solvent was diethylene glycol monoethyl ether (ECA).

[0136] The dispersants were 2-propenoate reaction products with ethylenediamine-ethylenimine polymer and a compound with polyethylene-polypropylene glycol monobutyl etherphosphate.

[0137] Polyvinyl butyral (PVB) or polyvinyl pyrrolidone (PVP) was added as a polymer resin to some of the above conductive paste.

[0138] Epoxy or acrylate was added as a photosensitive polymer resin to some of the above conductive paste.

[0139] Table 1 is a table showing the materials and contents (weight%) constituting the conductive paste.

[0140] Separator plate type silver powder (7 μm or less) Spherical silver powder (7 μm or less) Nano silver powder (300 nm or less) Polymer resin solvent dispersant Experimental example 19000091 Experimental example 20900091 Experimental example 30090091 Experimental example 463270091 Experimental example 563027091 Experimental example 663027 Epoxy 4.54.51 Experimental example 763027 Acrylate 4.54.51 Experimental example 863027 PVB 4.54.51 Experimental example 963027 PVP 4.54.51

[0141] The above conductive paste was formed by mixing the above-described materials, then mixing at high speed and then mixing with a 3-roll mixer.

[0142] The above conductive paste was screen-printed onto a glass substrate to form a square conductive paste layer. The scraper speed was 50 mm / sec, the squeegee speed was 50 mm / sec, and the gap between the substrate and the screen was 1.2 mm.

[0143] The conductive paste layer was irradiated with light to perform photosintering. The light was irradiated with pulse intensities shown in the table below. The light was irradiated with single shots, multi-shots, and step shots.

[0144] The resistivity of the photo-sintered structure was measured using a four-point probe. The microstructure was observed using a scanning electron microscope. In addition, a cross-cut adhesion test was performed on the structure.

[0145] Results and Analysis

[0146] Hereinafter, with reference to Tables 2 to 5 and FIGS. 9 to 11, the characteristics of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to an embodiment of the present invention will be examined.

[0147] Table 2 shows the results of a cross-cut adhesion test of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to one embodiment of the present invention.

[0148] Tables 3 to 5 show the results of resistivity measurements of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to an embodiment of the present invention. Table 3 shows the single-shot results, Table 4 shows the multi-shot results, and Table 5 shows the step-shot results.

[0149] Classification Results Experimental Example 14B Experimental Example 24B Experimental Example 34B Experimental Example 45B Experimental Example 55B Experimental Example 64B Experimental Example 74B Experimental Example 85B Experimental Example 94B

[0150] Resistivity (μΩ cm) 5.5 J / cm 2 6.0 J / cm 2 6.5 J / cm 2 7.0 J / cm 2 Experimental Example 110.59.57.56.5 Experimental Example 219.017.515.5-Experimental Example 310.09.0--Experimental Example 420.016.514.011.0 Experimental Example 511.510.08.07.0 Experimental Example 611.58.57.0-Experimental Example 78.57.55.5-Experimental Example 811.59.58.57.5 Experimental Example 914.012.010.58.5

[0151] Resistivity (μΩ cm) 3.0 J / cm 2 3.0 J / cm per session 2 2 times 3.0 J / cm 2 3rd Experiment Example 1 - 8.09.0 Experiment Example 2 17.511.0 - Experiment Example 3 - 79.080.0 Experiment Example 4 13.511.5 Experiment Example 5 12.510.011.0 Experiment Example 6 80.0 - Experiment Example 7 80.080.0 - Experiment Example 8 19.014.014.0 Experiment Example 9 - 22.015.5

[0152] Resistivity (μΩ cm) 1.5 => 2.5 => 3.5 J / cm 2 3.0 => 3.25 => 3.5 J / cm 2 Experimental Example 17.57.0 Experimental Example 226.030.0 Experimental Example 319.519.0 Experimental Example 416.513.0 Experimental Example 510.511.5 Experimental Example 612.07.5 Experimental Example 718.510.0 Experimental Example 88.57.5 Experimental Example 99.59.5

[0153] FIG. 9 is a photograph of the surface of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to an embodiment of the present invention.

[0154] FIG. 10 is a scanning electron microscope photograph of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to an embodiment of the present invention.

[0155] Figures 9 and 10 show photographs of the structure of Experimental Example 5. Surface photographs of after printing, single shot, multi shot, and step shot, as well as surface microstructure observed with a scanning electron microscope, are shown. Here, the single shot was 7.0 J / cm 2 and the multi-shot was 3.0 J / cm 2 It was 3 times, and the step shot was 3.0 => 3.25 => 3.5 J / cm 2 was the condition.

[0156] Fig. 11 is a graph showing the surface roughness of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to one embodiment of the present invention.

[0157] Analysis of the cross-cut adhesion test results shows that all cases exhibit 4B or higher. In addition, the mixed powder of Experimental Example 4 exhibited the greatest adhesion, followed by the polymer-mixed cases of Experimental Examples 5 and 8, and then the single powder.

[0158] The resistivity varied depending on the shape, size, and mixing of the silver powder, and it was found that in order to implement a resistivity of less than 30 μΩ cm, it was possible for the silver powder to be in the form of a plate, nanopowder, spherical, and mixed form. The resistivity increased in the order of the plate, nanopowder, and spherical form of the silver powder. That is, since the plate-shaped silver powder of Experimental Example 1 showed the lowest resistivity, it is analyzed that the conductivity of the conductive layer will be the highest. In addition, the plate-shaped and nano silver powder-mixed form of Experimental Example 5 also showed a relatively low resistivity.

[0159] Additionally, the resistivity varied depending on the light irradiation conditions, and it was found that single-shot, multi-shot, and step-shot were all possible to achieve a resistivity of less than 30 μΩ cm. Overall, low resistivity was observed in single-shot, and the resistivity decreased as the light pulse intensity increased.

[0160] Analysis of the microstructure shows that the particle size changes due to photo-sintering by single shot, multi-shot, and step shot, and that larger bonds are formed between particles.

[0161] When examining the surface roughness, Experimental Example 1 had a centerline average roughness (Ra) of 0.83 μm and a ten-point average roughness (Rz) of 3.68 μm, and Experimental Example 5 had a centerline average roughness (Ra) of 0.77 μm and a ten-point average roughness (Rz) of 1.03 μm. Therefore, Experimental Example 5 exhibited more uniform surface roughness. Therefore, the case where nano silver powder is mixed can exhibit better surface characteristics.

[0162] For reference, in the graph of Fig. 11, the X-axis represents the distance in one direction of the experimental specimen on which surface roughness was performed, and there were a total of 2500 points. The total measured length was approximately 770 μm, and 1 point was approximately 0.3 μm.

[0163] FIG. 12 is a photograph of the surface according to the process steps of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to an embodiment of the present invention.

[0164] Fig. 13 is a scanning electron microscope photograph of a photo-sintered structure formed using a method for manufacturing a ceramic circuit board using photo-sintering according to one embodiment of the present invention.

[0165] In Figures 12 and 13, the surface shape and microstructure of the structure of Experimental Example 5 are shown. In addition, similar results to Experimental Example 5 were observed in other experimental examples.

[0166] Referring to Fig. 12, the surface topography immediately after printing, immediately after photo sintering, and immediately after developing of a conductive paste layer formed over the entire substrate is shown. After photo sintering of the conductive paste layer formed over the entire substrate, it can be seen that a relatively bright photo sintered region (22) and a relatively dark unsintered region (24) are formed. Immediately after developing, i.e., after removing the unsintered region, an exemplary conductive layer composed of patterned photo sintered regions can be formed.

[0167] Referring to Figure 13, the microstructure of the surface and cross section of the photo-sintered structure immediately after printing and immediately after photo-sintering are shown. Immediately after printing, individualized silver powders were observed on the surface and cross section, and immediately after photo-sintering, it was observed that the silver powders formed a sintered body through photo-sintering.

[0168] In 5G applications utilizing high-frequency bands, controlling the roughness of the electrode surface is crucial. As the current frequency increases, most of the current flows closer to the conductor surface, resulting in transmission loss. This is known as the skin effect and skin depth. When verifying the controllability of surface roughness related to the transmission loss required in high-frequency bands, surface conditions can vary depending on the powder mixture.

[0169] As described above, the conductive layer formed using optical sintering can be applied to at least one of the first base copper layer (130) and the second base copper layer (140) described below. The first base copper layer (130) and the second base copper layer (140) can be patterned to function as wiring.

[0170] Additionally, the conductive layer can be applied to the first copper structure (150) and the second copper structure (160) that function as spacers described below.

[0171] The conductive layer may be formed by other methods in addition to the above-described method. After forming a conductive paste layer on a substrate, ultraviolet pulsed light is irradiated using a mask layer to cure a portion of the conductive paste layer. Subsequently, a development process is performed to remove uncured areas and form a cured area. After drying the cured area, the conductive powder in the cured area may be thermally or optically sintered to form the conductive layer.

[0172] According to the technical idea of ​​the present invention, after full-surface printing of a substrate using an optimized paste for photosintering, the paste layer can be flattened by dry leveling using the fluidity of the paste.

[0173] Additionally, a mask patterned with a light-blocking material on glass or a transparent film is placed on top of the paste layer, and ultraviolet rays or light are irradiated so that the light source passing through the mask is used as photoreaction energy to form radicals, thereby hardening or sintering the paste layer.

[0174] Patterning is performed by wet removing the uncured portion with a developer containing water or an alkaline component, and then drying and evaporating the remaining developer.

[0175] The pattern formed in this way is metallized by heating and sintering under a nitrogen atmosphere, and the process can be repeated to form a three-dimensional structure. In addition, within a certain thickness range, three-dimensionalization can be achieved by repeating only the printing exposure and development process.

[0176] The present invention enables patterning with a line width of 50 μm or less and a precision of ±5% or less. Furthermore, the surface planarization process can be omitted, enabling three-dimensional fine patterning. Furthermore, compared to conventional screen printing, the use of pulses enables high-definition (fine pitch) printing.

[0177] In this specification, power semiconductor devices are exemplary, and cases composed of other semiconductor devices are also included in the technical concept of the present invention.

[0178] Figures 14 to 17 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.

[0179] Referring to FIGS. 14 to 17, the ceramic circuit board (1) may include a ceramic substrate (110) and a first copper structure (150). The ceramic circuit board (1a) may include a ceramic substrate (110a) and a first copper structure (150). The ceramic circuit board (100) may include a ceramic substrate (110), a first copper structure (150), and a second copper structure (160). The ceramic circuit board (100a) may include a ceramic substrate (110a), a first copper structure (150), and a second copper structure (160).

[0180] Hereinafter, components of the ceramic circuit board will be described in detail with reference to FIGS. 14 to 17.

[0181] The ceramic substrate (110) may include a ceramic layer (120), a first base copper layer (130), and a second base copper layer (140).

[0182] The ceramic substrate (110a) may include a ceramic layer (120), a first active metal brazing layer (125), a second active metal brazing layer (126), a first base copper layer (130), and a second base copper layer (140). Compared to the ceramic substrate (110), the ceramic substrate (110a) has a difference in that it further includes a first active metal brazing layer (125) and a second active metal brazing layer (126).

[0183] The ceramic layer (120) may have a first surface (121) and a second surface (122) that face each other. In FIGS. 1 to 4, the first surface (121) is illustrated as the upper surface and the second surface (122) is illustrated as the lower surface with respect to the ceramic layer (120). The ceramic layer (120) may have excellent thermal conductivity and electrical insulation. The ceramic layer (120) may be formed of a ceramic material, and may include, for example, at least one of Al2O3, AlN, Zirconia Toughened Alumina (ZTA), and Si3N4.

[0184] At least one of the first base copper layer (130) and the second base copper layer (140) may be formed as a conductive layer formed using optical sintering as described above.

[0185] A first base copper layer (130) may be disposed on a first surface (121) of a ceramic layer (120). The first base copper layer (130) may be formed using TPC technology, DBC technology, DPC technology, or AMB technology. The first base copper layer (130) may have a total thickness in the range of, for example, 100 μm to 1000 μm, and may have a total thickness of, for example, about 300 μm.

[0186] The second base copper layer (140) may be disposed on the second surface (122) opposite to the first surface (121) of the ceramic layer (120). The second base copper layer (140) may function as a warpage prevention layer that prevents the ceramic layer (120) from warping during the sintering process for forming the first base copper layer (130) and the sintering process for forming the first copper structure (150) and the second copper structure (160). In addition, the second base copper layer (140) may provide a path for dissipating heat generated from the power semiconductor device to the outside. For this purpose, a heat dissipation structure (not shown) may be attached to the second base copper layer (140). The second base copper layer (140) may be formed as a single layer or as a plurality of layers.

[0187] The second base copper layer (140) can be formed in the same manner as the first base copper layer (130). The second base copper layer (140) can be formed using the above-described TPC technology, DBC technology, DPC technology, or AMB technology. The second base copper layer (140) can include the same material as the first base copper layer (130) and can be formed simultaneously.

[0188] The first base copper layer (130) and the second base copper layer (140) may be formed as TPC (thick printed copper) copper layers using TPC technology. The TPC technology may refer to a technology of forming a copper layer having a predetermined thickness by printing, pressing, and sintering using a copper-containing paste. The TPC copper layer may be formed by printing a copper-containing paste on one or both sides of a ceramic layer (120) to form a paste layer, and pressing and sintering the paste layer. Since the TPC technology forms the TPC copper layer using a screen printing method, it does not require an additional etching process and can freely implement various patterning shapes. In addition, the TPC technology may allow a layer formed in one process cycle of printing, pressing, and sintering to have a very small thickness, and the layer may have a thickness in the range of, for example, 10 μm to 100 μm. In addition, since the thickness of the TPC copper layer can be increased by repeatedly performing the above process cycle to form multiple layers, thickness control can be facilitated. In addition, the TPC copper layer can secure overall uniformity in thickness, surface quality, etc. In addition, nickel (Ni), silver (Ag), gold (Au), etc. can be plated on the TPC copper layer.

[0189] In addition, the first base copper layer (130) and the second base copper layer (140) may be formed as DBC copper layers formed using DBC (direct bonded copper) technology. The DBC technology may refer to a technology of forming a copper layer by directly attaching a copper foil to a ceramic layer. The DBC copper layer may be formed by placing a copper foil on one or both sides of a ceramic layer (120), performing a high-temperature oxidation process at a temperature in the range of 1000°C to 1080°C, and bonding the copper foil to the ceramic layer using a copper-oxygen eutectic liquid. The bonding may be performed in a nitrogen atmosphere containing about 30 ppm of oxygen at a temperature lower than 1083°C, which is the melting point of copper, and a copper oxide layer may be formed on the surface of the copper foil to implement bonding with the ceramic layer (120). Subsequently, if necessary, the DBC copper layer may be patterned using an etching process. Additionally, nickel (Ni), silver (Ag), gold (Au), etc. can be plated on the DBC copper layer.

[0190] In addition, the first base copper layer (130) and the second base copper layer (140) may be formed as DPC copper layers formed using DPC (direct plating copper) technology. The DPC technology may refer to a technology for forming a copper layer by using a thin film process, an etching process, and a plating process. The DPC copper layer may be formed by forming a seed layer of titanium (Ti), titanium-tungsten (TiW), or the like on one or both sides of a ceramic layer (120), and then plating copper (Cu) on the seed layer. In addition, a photoresist pattern may be formed on the seed layer, and then copper (Cu) may be plated on the photoresist pattern, and the photoresist pattern may be removed to form the DPC copper layer having a desired pattern. Subsequently, if necessary, the DPC copper layer may be patterned using an etching process.

[0191] In addition, the first base copper layer (130) and the second base copper layer (140) may be formed as active metal brazing (AMB) copper layers formed using an AMB technology. The AMB technology may refer to a technology for bonding a ceramic layer and a copper layer using an active metal foil. An active metal foil and a copper foil are sequentially placed on one or both sides of a ceramic layer (120), and heated to melt the active metal foil. As illustrated in FIG. 15, by forming a first active metal brazing layer (125) and a second active metal brazing layer (126), the ceramic layer (120) and the copper foil are bonded to each other. Therefore, the first active metal brazing layer (125) may serve to bond the ceramic layer (120) and the first base copper layer (130). The second active metal brazing layer (126) may serve to bond the ceramic layer (120) and the second base copper layer (140). Next, if necessary, the AMB copper layer can be patterned using an etching process.

[0192] The first active metal brazing layer (125) and the second active metal brazing layer (126) may include a metal or metal alloy having a lower melting point than the copper constituting the copper foil, and may include, for example, an active metal alloy in which copper, aluminum, nickel, or silver is added to titanium, hafnium, nickel, molybdenum, or zirconium, which are active against oxygen, to lower the melting point. The first active metal brazing layer (125) and the second active metal brazing layer (126) may include, for example, an alloy including at least one of silver (Ag), copper (Cu), and titanium (Ti). However, this is exemplary, and the first active metal brazing layer (125) and the second active metal brazing layer (126) may include at least one of aluminum (Al), titanium (Ti), nickel (Ni), niobium (Nb), and molybdenum (Mo).

[0193] As illustrated in FIG. 15, the first active metal brazing layer (125) may be disposed on the first surface (121) of the ceramic layer (120). The first base copper layer (130) may be disposed on the first active metal brazing layer (125). That is, the first active metal brazing layer (125) may be interposed between the ceramic layer (120) and the first base copper layer (130), thereby bonding the ceramic layer (120) and the first base copper layer (130) to each other.

[0194] The second active metal brazing layer (126) may be disposed on the second surface (122) of the ceramic layer (120). The second base copper layer (140) may be disposed on the second active metal brazing layer (126). That is, the second active metal brazing layer (126) may be interposed between the ceramic layer (120) and the second base copper layer (140), thereby bonding the ceramic layer (120) and the second base copper layer (140) to each other.

[0195] In order to form a pattern on the first base copper layer (130), an additional etching process may be required when applying the DBC technology, DPC technology, or AMB technology. Therefore, when using such an etching process, there is a limitation in that there is a limitation in the pattern shape, and it may be difficult to make a difference in thickness between patterns or to form secondary and tertiary patterns on the pattern in order to respond to various types of semiconductor devices. On the other hand, when applying the TPC technology to form the first base copper layer (130), the pattern can be easily formed during printing, and an additional etching process may not be required.

[0196] Referring to FIGS. 14 to 17, the first copper structure (150) may be disposed on a portion of the ceramic substrate (110), for example, on a portion of the first base copper layer (130). The first copper structures (150) may all have substantially the same height. The height may refer to the height from the ceramic substrate (110).

[0197] Referring to FIGS. 16 and 17, the second copper structure (160) may be disposed on at least a portion of the first copper structure (150). As the second copper structure (160) is formed on at least a portion of the first copper structure (150), the portion where the second copper structure (160) is additionally formed may have a higher height than the portion where only the first copper structure (150) is formed.

[0198] At least one of the first copper structure (150) and the second copper structure (160) may be formed of a conductive layer formed using optical sintering as described above.

[0199] The first copper structure (150) and the second copper structure (160) can be formed using the above-described TPC technology that forms copper layers by printing, pressing, and sintering. Therefore, the first structure (150) and the second copper structure (160) can be sintered bodies made of substantially the same material. The second copper structure (160) can be laminated one or more times on the first copper structure (150). As an example, in FIGS. 3 and 4, a single layer of the second copper structure (160) is laminated on a portion of the first copper structure (150). However, the present invention is not limited thereto, and the second copper structure (160) can be formed in two or more layers in order to adjust the height of the copper structure as needed.

[0200] The first copper structure (150) and the second copper structure (160) can provide a space in which the power semiconductor element is mounted, and can function as a spacer that corrects a thickness deviation of the power semiconductor element. The height at which the power semiconductor element is disposed can be changed by the arrangement of the first copper structure (150) and the second copper structure (160). That is, as the second copper structure (160) is selectively formed on a portion of the first copper structure (150), the height provided when the first copper structure (150) and the second copper structure (160) are included can be greater than the height provided when only the first copper structure (150) is included. The height can refer to the height from the ceramic substrate (110). Copper structures having different heights are formed, and thus, the thickness deviation of power semiconductor elements having different thicknesses can be corrected.

[0201] The first copper structure (150) and the second copper structure (160) may have the same planar area, or the second copper structure (160) may have a smaller planar area than the first copper structure (150).

[0202] In addition, the first copper structure (150) and the second copper structure (160) can additionally perform the function of wiring that provides an electrical passage. The first copper structure (150) and the second copper structure (160) can be applied with a high current or high voltage from the power semiconductor element.

[0203] The first copper structure (150) and the second copper structure (160) can be integrated by sintering.

[0204] At least one of the first copper structure (150) and the second copper structure (160) may have a surface from which oxides have been removed by blasting treatment.

[0205] FIGS. 18 and 19 are cross-sectional views illustrating a base copper layer and a copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0206] Referring to Fig. 18, the first base copper layer (130) may be a copper foil formed by DBC technology or AMB technology, or a copper plating layer formed by DPC technology. The first copper structure (150) and the second copper structure (160) may be sintered bodies of copper-containing paste formed by TPC technology.

[0207] Hereinafter, the first base copper layer (130), the first copper structure (150), and the second copper structure (160) formed using TPC (thick printed copper) technology will be described in detail.

[0208] Referring to FIG. 19, the first base copper layer (130) may be a sintered body of a copper-containing paste formed by TPC technology. The first copper structure (150) and the second copper structure (160) may be sintered bodies of a copper-containing paste formed by TPC technology.

[0209] The first base copper layer (130), the first copper structure (150), and the second copper structure (160) can be formed by commonly printing a copper-containing paste to form a paste layer and pressing and sintering the paste layer.

[0210] The first base copper layer (130) may be disposed on a portion of the ceramic layer (120). The first base copper layer (130) may be formed using the TPC technology described above.

[0211] The first base copper layer (130) may be composed of a plurality of layers. The first base copper layer (130) may include, for example, at least one of a bonding copper layer (131), a laminated copper layer (132), and a surface copper layer (133).

[0212] The thickness of the first base copper layer (130) can be varied by controlling the thickness of the relatively thick laminated copper layer (132). The laminated copper layer (132) can have a greater thickness than the bonded copper layer (131) and the surface copper layer (133). The bonded copper layer (131) and the surface copper layer (133) can have the same thickness or different thicknesses. The bonded copper layer (131) can have a thickness in the range of, for example, 1 μm to 100 μm, for example, about 20 μm. The laminated copper layer (132) can have a thickness in the range of, for example, 100 μm to 1000 μm. The surface copper layer (133) can have a thickness in the range of, for example, 1 μm to 100 μm, for example, about 30 μm.

[0213] The bonding copper layer (131) may be disposed on at least a portion of the ceramic layer (120). The laminated copper layer (132) may be disposed on the bonding copper layer (131). The surface copper layer (133) may be disposed on the laminated copper layer (132). However, this is exemplary and the technical idea of ​​the present invention is not limited thereto. For example, when the thickness of the first base copper layer (130) is not thick, the first base copper layer (130) may be configured to include the bonding copper layer (131) and the surface copper layer (133), excluding the laminated copper layer (132). Alternatively, when a power semiconductor element is not bonded on the base copper layer (140), the first base copper layer (130) may be configured to include the bonding copper layer (131) and the laminated copper layer (132), excluding the surface copper layer (133).

[0214] The bonding copper layer (131) can be formed by forming a bonding paste layer by printing a copper-containing bonding paste on the ceramic layer (120) using a screen printing method or the like, drying to remove the solvent, pressing the dried bonding paste layer, and then heating to sinter it.

[0215] The laminated copper layer (132) can be formed by printing a copper-containing laminated paste on the bonding copper layer (131) using a screen printing method or the like to form a laminated paste layer, then drying to remove the solvent, pressing the dried laminated paste layer, and then heating to sinter it.

[0216] The surface copper layer (133) can be formed by printing a copper-containing surface paste on the laminated copper layer (132) using a screen printing method or the like to form a surface paste layer, then drying to remove the solvent, pressing the dried surface paste layer, and then heating to sinter it.

[0217] By the above pressing, the internal pores of the bonding paste layer, the laminated paste layer, and the surface paste layer can be reduced and the uniformity of height can be secured.

[0218] The above-described printing, pressing, and sintering steps can be performed repeatedly. For example, after forming one paste layer in one cycle of the printing and pressing, the printing and pressing can be performed again to form one more subsequent paste layer on the previously formed paste layer, and this can be repeated to form multiple paste layers. The multiple paste layers can be sintered together. In addition, by repeatedly performing the sintering, the copper layer can be formed. That is, sintering can be performed once or more times for one copper layer constituting the first base copper layer (130). The number of times of the printing, pressing, and sintering can be varied.

[0219] Below, the materials constituting the above-described paste forming the first base copper layer (130) will be described.

[0220] The copper-containing bonding paste may include, for example, copper particles, glass frit, inorganic particles, copper oxide particles, a solvent, and a binder.

[0221] The copper-containing laminate paste may include, for example, copper particles, inorganic particles, a solvent, and a binder. Compared to the copper-containing bonding paste, the copper-containing laminate paste may not include glass frit and copper oxide particles.

[0222] The copper-containing surface paste may include copper particles, copper oxide particles, a solvent, and a binder. Compared to the copper-containing bonding paste, the copper-containing surface paste may not include glass frit and inorganic particles.

[0223] The above glass frit is a sintering aid that helps sintering of copper (Cu) particles and can provide better bonding between the ceramic layer (120) and the bonding copper layer (131).

[0224] The above inorganic particles may include powder of at least one of Al2O3, CaO, and ZrO2. The above inorganic particles may function to reduce the shrinkage rate of the paste. For reference, the shrinkage rate can be measured by printing the paste into a disk shape, drying and sintering it, and comparing the diameter of the disk after drying and after sintering.

[0225] The above copper oxide particles may include at least one of CuO and Cu2O, and may perform a function of improving bonding properties with the components to be bonded. The above copper oxide particles may form a process liquid phase during the sintering process. For example, when the ceramic layer (120) includes alumina (Al2O3), the copper oxide may react with alumina to form CuAlO2, CuAl2O4, etc., thereby improving bonding properties.

[0226] The above copper particles may be composed of copper and may be a main component constituting the first base copper layer (130). The copper particles may include fine copper particles having an average particle diameter in the range of 1 μm to 10 μm and may be included in an amount of 60 wt% to 95 wt% of the paste.

[0227] The shrinkage rate of the copper-containing laminate paste may be higher than the shrinkage rate of the copper-containing bonding paste. The shrinkage rate of the copper-containing surface paste may be higher than the shrinkage rate of the copper-containing bonding paste and the shrinkage rate of the copper-containing bonding paste. The shrinkage rate of the copper-containing bonding paste may be, for example, 0% to 3%. The shrinkage rate of the copper-containing laminate paste may be, for example, 3% to 9%. The shrinkage rate of the copper-containing surface paste may be, for example, 10% to 15%.

[0228] The copper-containing bonding paste, the copper-containing laminate paste, and the copper-containing surface paste can change the types and contents of glass frit, inorganic particles, copper oxide particles, copper particles, solvent, and binder in order to achieve a desired thermal expansion coefficient and shrinkage rate.

[0229] The description of the composition and paste for the first base copper layer (130) described above can be equally applied to the second base copper layer (140).

[0230] The first copper structure (150) may be placed on a portion of the first base copper layer (130). The first copper structure (150) may be placed on a portion of the first base copper layer (130) to reduce the difference in thermal expansion coefficient with respect to the power semiconductor element mounted thereon, for example, 5 x 10 -6 / ℃ to 20 x 10 -6 / ℃ can have a coefficient of thermal expansion in the range.

[0231] The first copper structure (150) may be a porous structure having pores within it. The first copper structure (150) may have a differential porosity. This means that the first copper structure (150) includes a region on the upper side having a lower porosity than the lower side that is relatively adjacent to the first base copper layer (130).

[0232] For example, the porosity of the first copper structure (150) may decrease from the lower side relatively adjacent to the first base copper layer (130) toward the upper side.

[0233] For example, the first copper structure (150) may be composed of a plurality of layers and may include a first base portion (151) and a first surface portion (152) disposed on the first base portion (151) and having a lower porosity than the first base portion (151). The first base portion (151) may have a porosity in a range of, for example, more than 5% by volume and less than or equal to 20% by volume. The first surface portion (152) may have a porosity in a range of, for example, more than 0% by volume and less than or equal to 5% by volume.

[0234] Since the first base (151) has a relatively high porosity, the pores perform a buffer function against thermal shock, thereby reducing thermal stress and increasing resistance to thermal fatigue destruction due to thermal stress under repeated thermal history.

[0235] On the other hand, since the first surface portion (152) has a relatively low porosity, it can have a smooth surface, and thus the bonding of the power semiconductor element mounted thereon can be improved. If the first surface portion (152) has a high porosity, void defects may remain on the bonding surface due to the pores, which may result in poor bonding of the power semiconductor element. Therefore, it is preferable to control the first surface portion (152) so that there are no pores or the porosity is low.

[0236] To control this porosity, the particle size and fraction of copper particles included in the paste can be controlled. If the particle size of the copper particles is large or the fraction is low, the porosity can increase, and if the particle size of the copper particles is small or the fraction is large, the porosity can decrease.

[0237] The first paste forming the first base portion (151) may include copper particles having an average particle diameter in a range of more than 3 μm and less than or equal to 10 μm. The second paste forming the first surface portion (152) may include copper particles having an average particle diameter in a range of 100 nm to 3 μm. That is, the average particle diameter of the copper particles included in the second paste may be smaller than the average particle diameter of the copper particles included in the first paste. Due to this difference in the average particle diameter of the copper particles, the first surface portion (152) may have a denser microstructure and a lower porosity than the first base portion (151).

[0238] The first copper structure (150) may have an overall thickness in the range of, for example, 100 μm to 2000 μm. The first base portion (151) may have a greater thickness than the first surface portion (152). The first base portion (151) may have a thickness in the range of, for example, 100 μm to 1900 μm. The first surface portion (152) may have a thickness in the range of, for example, 1 μm to 100 μm, for example, about 20 μm.

[0239] The first copper structure (150) can be formed using the TPC technology described above. The first copper structure (150) can be formed using a copper-containing paste including copper particles, inorganic particles, a solvent, and a binder. The copper-containing paste may further include copper oxide particles. The first copper structure (150) can be formed by printing the copper-containing paste using a screen printing method or the like to form a paste layer, then drying to remove the solvent, pressing the dried paste layer, and then heating to sinter it.

[0240] The above-described printing, pressing, and sintering steps can be performed repeatedly. For example, after forming one paste layer in one cycle of the printing and pressing, the printing and pressing can be performed again to form one more subsequent paste layer on the previously formed paste layer, and this can be repeated a plurality of times to form a plurality of paste layers. The plurality of paste layers can be sintered together. In addition, by repeatedly performing the sintering, the copper layer can be formed. That is, sintering can be performed one or more times for one copper layer constituting the first copper structure (150). The number of times of the printing, pressing, and sintering can be varied.

[0241] The second copper structure (160) may be disposed on at least a portion of the first copper structure (150). The second copper structure (160) may be formed using the TPC technology described above. The second copper structure (160) may be formed to reduce the difference in thermal expansion coefficient with respect to the power semiconductor element mounted thereon, for example, by 5 x 10 -6 / ℃ to 20 x 10 -6 / ℃ can have a coefficient of thermal expansion in the range.

[0242] The second copper structure (160) may be a porous structure having pores within it. The second copper structure (160) may have a differential porosity. This means that the second copper structure (160) includes a region on the upper side having a lower porosity than the lower side that is relatively adjacent to the first copper structure (150).

[0243] For example, the porosity of the second copper structure (160) may decrease from the lower side relatively adjacent to the first copper structure (150) toward the upper side.

[0244] For example, the second copper structure (160) may be composed of a plurality of layers and may include a second base portion (161) and a second surface portion (162) disposed on the second base portion (161) and having a lower porosity than the second base portion (161). The second base portion (161) may have a porosity in a range of, for example, more than 5% by volume and less than or equal to 20% by volume. The second surface portion (162) may have a porosity in a range of, for example, more than 0% by volume and less than or equal to 5% by volume.

[0245] The first paste forming the second base portion (161) may include copper particles having an average particle diameter in the range of more than 3 μm and less than or equal to 10 μm. The second paste forming the second surface portion (162) may include copper particles having an average particle diameter in the range of 100 nm to 3 μm.

[0246] The second copper structure (160) may have an overall thickness in the range of, for example, 100 μm to 2000 μm. The second base portion (161) may have a greater thickness than the second surface portion (162). The second base portion (161) may have a thickness in the range of, for example, 100 μm to 1900 μm. The second surface portion (162) may have a thickness in the range of, for example, 1 μm to 100 μm, for example, about 20 μm.

[0247] The second copper structure (160) can be formed using the TPC technology described above. The second copper structure (160) can be formed using a copper-containing paste including copper particles, inorganic particles, a solvent, and a binder.

[0248] The second base portion (161) may be identical or similar to the first base portion (151), and the second surface portion (162) may be identical or similar to the first surface portion (152).

[0249] However, this is exemplary, and the technical idea of ​​the present invention also includes cases where the second copper structure (160) has a different structure than the first copper structure (150), has a different constituent material, or is formed by a different manufacturing method.

[0250] FIG. 20 is a photograph showing the microstructure of a copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0251] Referring to Fig. 20, the internal pores of the first base portion (151) and the first surface portion (152) of the first copper structure (150) are shown. Compared to the first base portion (151), the first surface portion (152) has a low porosity, and the size of each pore is also small. That is, the first surface portion (152) has a dense microstructure.

[0252] When the porosity was 0%, it exhibited a high thermal stress of 220 MPa, whereas when the porosity was 7.7%, it exhibited a thermal stress of 136 MPa, and when the porosity was 17.2%, it exhibited a thermal stress of 114 MPa. In other words, it can be seen that as the porosity increases, the thermal stress decreases. In addition, when the porosity was 7.7%, it exhibited thermal fatigue failure characteristics of 1000 cycles, and when the porosity was 17.2%, it exhibited improved thermal fatigue failure characteristics of 2000 cycles. In other words, it can be seen that as the porosity increases, the resistance to thermal fatigue failure improves.

[0253] The Mo-Cu spacer according to the prior art is a metalworking material that substantially does not contain pores inside and has a porosity of approximately 0%, thereby exhibiting high thermal stress and low thermal fatigue fracture characteristics. In contrast, the copper structure according to the present invention comprises a lower layer having a high porosity, thereby providing low thermal stress and improved resistance to thermal fatigue fracture, and further comprises an upper layer having a low porosity, thereby preventing bonding defects in power semiconductor devices.

[0254] FIG. 21 and FIG. 22 are cross-sectional views and photographs showing a pyramid-shaped copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0255] Referring to FIG. 21, the first copper structure (150) may have a truncated pyramid shape in which the planar area of ​​the upper side is smaller than that of the lower side as the planar area decreases from the lower side relatively adjacent to the first base copper layer (130) toward the upper side. That is, the first copper structure (150) may have a trapezoidal vertical cross-sectional shape. In addition, the first copper structure (150) may have a horizontal cross-sectional shape that is a polygon such as a triangle, a square, a pentagon, a hexagon, or a circle such as a square, an ellipse, a semicircle, or the like.

[0256] Since the first copper structure (150) has a pyramidal shape, it can stably mount a power semiconductor element. In addition, it can prevent an undercut phenomenon formed by etching.

[0257] These pyramidal shapes can be formed as follows.

[0258] After printing and pressing the first layer (151_1) of the first base portion (151) and then sintering, it can naturally shrink due to volume reduction caused by evaporation of the solvent and sintering of the copper particles. At this time, the lower side of the first layer (151_1) is attached to the first base copper layer (130), so the shrinkage is small, whereas the upper side shrinks greatly. Then, when the second layer (151_2) is printed, the area of ​​the upper side that has shrunk corresponds to the area of ​​the upper side, so the lower area of ​​the second layer (150_2) is reduced. When the second layer (151_2) is sintered, the upper side shrinks more than the lower side, similar to the first layer (150_1). In this manner, a plurality of layers having an upper side having a smaller area than the lower side are formed. Next, a first surface portion (152) having an upper side having a smaller area than a lower side is formed on the n-th layer (150_n). Accordingly, a first copper structure (150) having a pyramidal shape can be formed.

[0259] In addition, in the step of forming the first copper structure (150), the application area of ​​the paste applied during printing can be reduced from the bottom to the top using TPC technology to implement the pyramidal shape. When forming a subsequent layer based on the first layer formed first, for example, a second layer (151_2) based on the first layer (151_1), the application area can be reduced to 1 area% to 10 area%, for example, 3 area% to 5 area%.

[0260] Additionally, similar to the first copper structure (150), the second copper structure (160) may have a pyramidal shape in which the planar area decreases from the lower side relatively adjacent to the first copper structure (150) toward the upper side.

[0261] Referring to Figure 22, there are photographs showing the actual implementation of such a pyramid-shaped copper structure.

[0262] Hereinafter, a method for manufacturing a ceramic circuit board according to one embodiment of the present invention will be described.

[0263] Figure 23 is a flowchart illustrating a method for manufacturing a ceramic circuit board according to one embodiment of the present invention.

[0264] Referring to FIG. 23, a method for manufacturing a ceramic circuit board (S100) may include a step of providing a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer (S110); a step of forming a first copper structure on a portion of the ceramic substrate (S120); and a step of forming one or more second copper structures on at least a portion of the first copper structure (S130).

[0265] In addition, the method for manufacturing a ceramic circuit board (S100) may further include a step (S140) of blasting the surface of at least one of the first copper structure and the second copper structure.

[0266] The step of providing the ceramic substrate (S110) may be performed by providing a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer. In addition, the ceramic substrate may further include a second base copper layer disposed on a second surface of the ceramic layer opposite to the first surface.

[0267] Hereinafter, the base copper layer should be understood to mean the first base copper layer and the second base copper layer.

[0268] In the step (S110) of providing the above ceramic substrate, the first base copper layer may be a TPC copper layer, a DBC copper layer, a DPC copper layer, or an AMB copper layer.

[0269] The step (S120) of forming the first copper structure may include a printing step of forming a paste layer by printing a copper-containing paste on a portion of the first base copper layer; a pressing step of pressing the paste layer; and a sintering step of forming the first copper structure by sintering the paste layer.

[0270] In the above printing step, a copper-containing paste may be screen-printed onto the ceramic layer to form a paste layer. The printing step may include a drying step that is intentionally performed to remove all or part of the solvent contained in the paste layer by maintaining the temperature in the air at a range of 10°C to 100°C. Alternatively, the drying may be performed unintentionally through natural drying.

[0271] In the above pressing step, the paste layer can be pressed to form a uniform thickness. The boundary of the paste layer may have a higher viscosity than the center due to a reduced flow rate of the copper-containing paste, and may be formed to a thicker thickness. By pressing the paste layer, this thickness variation can be reduced. In addition, internal pores in the paste layer can be eliminated or reduced.

[0272] In the above sintering step, the copper particles contained in the paste layer can be sintered. The sintering step can be performed in an inert atmosphere, such as a nitrogen atmosphere or an argon atmosphere, or can be performed in an air atmosphere. The sintering step can be performed in a continuous heat treatment furnace, such as a muffle-type heat treatment furnace, or in a batch-type heat treatment furnace, such as a box oven.

[0273] The step (S130) of forming the second copper structure may include a printing step of forming a paste layer by printing a copper-containing paste on a portion of the first copper structure; a pressing step of pressing the paste layer; and a sintering step of forming the second copper structure by sintering the paste layer.

[0274] At least one of the sintering step for forming the first copper structure and the sintering step for forming the second copper structure may be performed at a temperature of, for example, less than 900°C, and may be performed at a temperature in the range of, for example, 500°C to 800°C for 10 minutes to 120 minutes.

[0275] For example, when the ceramic substrate includes an active metal brazing layer, it is important to prevent the active metal brazing layer from melting during the sintering step of forming the first copper structure or the second copper structure, and therefore, the sintering temperature is preferably lower than the melting temperature of the active metal brazing layer, and is preferably lower, for example, in the range of 50°C to 100°C.

[0276] In addition, the sintering may be performed by including a bake out step at a temperature ranging from 300°C to 500°C by supplying a small amount of water vapor or oxygen in a nitrogen atmosphere to remove the binder contained in the paste layer, and a liquid phase sintering step of the copper particles contained in the paste layer. However, this is exemplary and the technical idea of ​​the present invention is not limited thereto, and the bake out step may be omitted.

[0277] The step (S120) of forming the first copper structure may be performed so that the first copper structure has a differential porosity. The first copper structure may include a region on the upper side having a lower porosity than a region on the lower side that is relatively adjacent to the first base copper layer.

[0278] The step of forming the first copper structure (S120) may include: forming a first base portion; and forming a first surface portion having a lower porosity than the first base portion on the first base portion. The step of forming the first base portion may be performed using a paste including copper particles having an average particle diameter in a range of more than 3 μm and less than or equal to 10 μm. The step of forming the first surface portion may be performed using a paste including copper particles having an average particle diameter in a range of 100 nm to 3 μm on the first base portion. The first base portion may have a porosity in a range of more than 5 vol% and less than or equal to 20 vol%. The first surface portion may have a porosity in a range of more than 0 vol% and less than or equal to 5 vol%.

[0279] The step (S130) of forming the second copper structure may be performed so that the second copper structure has a differential porosity. The second copper structure may include a region on the upper side having a lower porosity than the lower side relatively adjacent to the first copper structure.

[0280] The step of forming the second copper structure (S130) may include: forming a second base portion; and forming a second surface portion having a lower porosity than the second base portion on the second base portion. The step of forming the second base portion may be performed using a paste including copper particles having an average particle diameter in a range of more than 3 μm and less than or equal to 10 μm. The step of forming the second surface portion may be performed using a paste including copper particles having an average particle diameter in a range of 100 nm to 3 μm on the second base portion. The second base portion may have a porosity in a range of more than 5 vol% and less than or equal to 20 vol%. The second surface portion may have a porosity in a range of more than 0 vol% and less than or equal to 5 vol%.

[0281] The printing step, the pressing step, and the sintering step for forming the first copper structure and the second copper structure may be performed repeatedly. For example, after the printing step and the pressing step are performed in one cycle to form one paste layer, the printing step and the pressing step are performed again to further form a subsequent paste layer on the previously formed paste layer, thereby forming a plurality of paste layers. The plurality of paste layers may be sintered together. In addition, by repeatedly performing the sintering step, the copper layer can be formed. That is, the sintering step may be performed one or more times for one copper layer constituting the first copper structure and the second copper structure. The number of times of the printing step, the pressing step, and the sintering step may be varied.

[0282] In addition, if a paste layer is formed on only one side of the ceramic layer and sintered, the ceramic layer may warp during sintering. To prevent this, paste layers may be formed on both sides of the ceramic layer and sintered together to form the first base copper layer and the second base copper layer simultaneously. In addition, the second base copper layer may be additionally formed simultaneously with the first copper structure and the second copper structure. It is preferable that the paste layers formed on both sides of the ceramic layer and sintered simultaneously have the same volume, or the volume ratio may be, for example, 90% to 100%. The volume ratio may be a percentage obtained by dividing the volume of the paste layer having a small volume by the volume of the paste layer having a large volume. In addition, the volume may be calculated from the weight of the paste layer.

[0283] The step (S120) of forming the first copper structure can cause the first copper structure to have a pyramidal shape by reducing the application area of ​​the copper-containing paste from the lower side relatively adjacent to the first base copper layer toward the upper side when performing the printing step.

[0284] In the step (S130) of forming the second copper structure, when performing the printing step, the application area of ​​the copper-containing paste is reduced from the lower side relatively adjacent to the first copper structure toward the upper side, thereby allowing the second copper structure to have a pyramidal shape.

[0285] The above blasting treatment step (S140) can treat the surface of at least one of the base copper layer, the first copper structure, and the second copper structure by blasting it with ceramic particles such as sand.

[0286] Solder is applied to the first copper structure and the second copper structure, and a power semiconductor element is mounted on the first copper structure and the second copper structure. The process of sintering the first copper structure and the second copper structure is heat-treated at a high temperature in the air, so a copper oxide layer may be formed on the surface. In addition, even when the sintering is performed in an inert atmosphere, oxidation by oxygen may occur. The copper oxide layer may reduce the adhesion of the power semiconductor element to the first copper structure and the second copper structure. Therefore, after forming the first copper structure and the second copper structure, the copper oxide layer may be removed by blasting fine-diameter ceramic particles on the surfaces of the first copper structure and the second copper structure. The blasting may be referred to as sandblasting. In addition, a case of blasting a base copper layer is also included in the technical concept of the present invention.

[0287] Alternatively, at least one of the first base copper layer and the second base copper layer may be formed as a conductive layer using optical sintering as described above, and a method for forming the conductive layer may be applied.

[0288] Alternatively, at least one of the first copper structure and the second copper structure may be formed of a conductive layer formed using photo-sintering as described above, and a method for forming the conductive layer may be applied.

[0289] Figure 24 is an ultrasonic inspection result showing whether a defect occurs depending on the sintering temperature of a ceramic circuit board according to an embodiment of the present invention.

[0290] Referring to Fig. 24, when the sintering of the copper structure was performed at 900°C to form a ceramic circuit board, an adhesion defect occurred between the ceramic layer and the base copper layer, as indicated by the arrow. It is analyzed that the adhesion defect occurred due to exposure to a high temperature of 900°C during the sintering process of the copper structure, and the occurrence became more pronounced as this high-temperature exposure was repeated. In particular, when the ceramic circuit board includes an active metal brazing layer, since the sintering temperature of 900°C approaches or exceeds the melting point of the active metal brazing layer, the adhesion defect occurs more as the active metal brazing layer melts.

[0291] On the other hand, when the sintering of the copper structures was performed at 600°C, the above-mentioned adhesion defect did not occur. Therefore, the sintering temperature of the base copper layer, the first copper structure, and the second copper structure is preferably lower than 900°C, and for example, a temperature in the range of 500°C to 800°C is preferable.

[0292] FIG. 25 is a photograph showing the surface state of a copper structure of a ceramic circuit board before and after blasting treatment according to an embodiment of the present invention.

[0293] Referring to Figure 25, the surface condition of a copper structure before and after blasting treatment is shown. When blasting treatment is not performed, it can be seen that copper oxide exists on the surface of the copper structure, resulting in a rough surface. On the other hand, it can be seen that the copper oxide is removed by blasting treatment, resulting in a smooth surface, and that the surface becomes even smoother as the number of blasting cycles increases. Therefore, after blasting treatment, power semiconductor devices mounted on the copper structure can be more stably bonded.

[0294] FIG. 26 is a perspective view illustrating a pair of ceramic circuit boards for forming a double-sided cooling power module according to one embodiment of the present invention.

[0295] Referring to FIG. 26, a lower ceramic circuit board (100_D) and an upper ceramic circuit board (100_U) forming a double-sided cooling power module are illustrated.

[0296] The lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first copper structure (150_D), and a lower second copper structure (160_D). The lower ceramic substrate (110_D) may include a lower ceramic layer (120_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0297] The upper ceramic circuit board (100_U) may include an upper ceramic substrate (110_U), an upper first copper structure (150_U), and an upper second copper structure (160_U). The upper ceramic substrate (110_U) may include an upper ceramic layer (120_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).

[0298] Figures 27 to 30 are cross-sectional views illustrating a double-sided cooling power module according to one embodiment of the present invention.

[0299] Referring to FIG. 27, a double-sided cooling power module (1000) may include a lower ceramic circuit board (100_D), an upper ceramic circuit board (100_U), a first power semiconductor element (200), a second power semiconductor element (300), an element attachment layer (400), and a mold layer (500).

[0300] The lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first copper structure (150_D), and a lower second copper structure (160_D). The lower ceramic substrate (110_D) may include a lower ceramic layer (120_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0301] The upper ceramic circuit board (100_U) may include an upper ceramic substrate (110_U), an upper first copper structure (150_U), and an upper second copper structure (160_U). The upper ceramic substrate (110_U) may include an upper ceramic layer (120_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).

[0302] The lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U) can be placed facing each other.

[0303] A first power semiconductor element (200) and a second power semiconductor element (300) may be disposed between a lower ceramic circuit board (100_D) and an upper ceramic circuit board (100_U). The lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U) may perform a function of dissipating heat generated in the first power semiconductor element (200) and the second power semiconductor element (300) to the outside. For such heat dissipation, a heat dissipation structure (not shown) may be disposed on the outer surface of at least one of the lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U).

[0304] The first power semiconductor element (200) and the second power semiconductor element (300) may be, for example, a GTO (gate turn-off thyristor) semiconductor element or an IGBT (insulated gate bipolar mode transistor) semiconductor element, and may perform an operation of converting power supplied from a power supply unit such as a battery into power for driving a motor through a switching operation and supplying the converted power. In addition, the first power semiconductor element (200) and the second power semiconductor element (300) may include electrode members formed on the upper or lower portions.

[0305] The first power semiconductor element (200) may be placed between the lower first copper structure (150_D) and the upper first copper structure (150_U). One side of the first power semiconductor element (200) may be attached to the lower first copper structure (150_D) by the element attachment layer (400), and the other side may be attached to the upper first copper structure (150_U) by the element attachment layer (400).

[0306] The second power semiconductor element (300) may be placed between the lower second copper structure (160_D) and the upper second copper structure (160_U). One side of the second power semiconductor element (300) may be attached to the lower second copper structure (160_D) by means of an element attachment layer (400), and the other side may be attached to the upper second copper structure (160_U) by means of an element attachment layer (400).

[0307] The second power semiconductor element (300) may have a smaller thickness than the first power semiconductor element (200). Therefore, by further arranging a second copper structure (160) on the upper and lower sides of the second power semiconductor element (300), the thickness difference between the second power semiconductor element (300) and the first power semiconductor element (200) can be corrected.

[0308] The component attachment layer (400) may be a solder layer or an adhesive layer, which is exemplary and the technical idea of ​​the present invention is not limited thereto.

[0309] The mold layer (500) can fill the space between the lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U). Accordingly, the first power semiconductor element (200) and the second power semiconductor element (300) can be covered by the mold layer (500). The mold layer (500) can insulate the first power semiconductor element (200) and the second power semiconductor element (300). The mold layer (500) can be composed of, for example, EMC (epoxy molding compound).

[0310] At least one of the lower first copper structure (150_D), the upper first copper structure (150_U), the lower second copper structure (160_D) and the upper second copper structure (160_U) may have a differential porosity and include a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer (130_D) or the upper first base copper layer (130_U).

[0311] The double-sided cooling power module (1000) may have a symmetrical structure based on the first power semiconductor element (200) and the second power semiconductor element (300). That is, the lower first copper structure (150_D), the lower second copper structure (160_D), the upper first copper structure (150_U), and the upper second copper structure (160_U) may be symmetrically arranged. However, this is merely exemplary, and the technical idea of ​​the present invention is not limited thereto. For example, the lower first copper structure (150_D) and the upper first copper structure (150_U) may have different heights. In addition, the lower second copper structure (160_D) and the upper second copper structure (160_U) may have different heights.

[0312] Hereinafter, descriptions of components identical or similar to those in the embodiment of Fig. 27 will be omitted.

[0313] Referring to FIG. 28, a double-sided cooling power module (1000a) may include a lower ceramic circuit board (100a_D), an upper ceramic circuit board (100a_U), a first power semiconductor element (200), a second power semiconductor element (300), an element attachment layer (400), and a mold layer (500).

[0314] The lower ceramic circuit board (100a_D) may include a lower ceramic substrate (110a_D), a lower first copper structure (150_D), and a lower second copper structure (160_D). The lower ceramic substrate (110a_D) may include a lower ceramic layer (120_D), a lower first active metal brazing layer (125_D), a lower second active metal brazing layer (126_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0315] The upper ceramic circuit board (100a_U) may include an upper ceramic substrate (110a_U), an upper first copper structure (150_U), and an upper second copper structure (160_U). The upper ceramic substrate (110a_U) may include an upper ceramic layer (120_U), an upper first active metal brazing layer (125_U), an upper second active metal brazing layer (126_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).

[0316] The lower ceramic circuit board (100a_D) and the upper ceramic circuit board (100a_U) may be arranged to face each other. The first power semiconductor element (200) may be arranged between the lower first copper structure (150_D) and the upper first copper structure (150_U). The second power semiconductor element (300) may be arranged between the lower second copper structure (160_D) and the upper second copper structure (160_U). The second power semiconductor element (300) may have a smaller thickness than the first power semiconductor element (200).

[0317] At least one of the lower first copper structure (150_D), the upper first copper structure (150_U), the lower second copper structure (160_D) and the upper second copper structure (160_U) may have a differential porosity and include a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer (130_D) or the upper first base copper layer (130_U).

[0318] The double-sided cooling power module (1000a) may have a symmetrical structure based on the first power semiconductor element (200) and the second power semiconductor element (300). That is, the lower first copper structure (150_D), the lower second copper structure (160_D), the upper first copper structure (150_U), and the upper second copper structure (160_U) may be symmetrically arranged. However, this is merely exemplary, and the technical idea of ​​the present invention is not limited thereto. For example, the lower first copper structure (150_D) and the upper first copper structure (150_U) may have different heights. In addition, the lower second copper structure (160_D) and the upper second copper structure (160_U) may have different heights.

[0319] Compared with the double-sided cooling power module (1000) of FIG. 27, the double-sided cooling power module (1000a) of FIG. 28 has a difference in that it further includes a lower first active metal brazing layer (125_D) interposed between the lower ceramic layer (120_D) and the lower first base copper layer (130_D), a lower second active metal brazing layer (126_D) interposed between the lower ceramic layer (120_D) and the lower second base copper layer (140_D), an upper first active metal brazing layer (125_U) interposed between the upper ceramic layer (120_U) and the upper first base copper layer (130_U), and an upper second active metal brazing layer (126_U) interposed between the upper ceramic layer (120_U) and the upper second base copper layer (140_U).

[0320] Referring to FIG. 29, a double-sided cooling power module (1000b) may include a lower ceramic circuit board (100_D), an upper ceramic board (110_U), a first power semiconductor element (200), a second power semiconductor element (30), an element attachment layer (400), and a mold layer (500).

[0321] The lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first copper structure (150_D), and a lower second copper structure (160_D). The lower ceramic substrate (110_D) may include a lower ceramic layer (120_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0322] The upper ceramic substrate (110_U) may include an upper ceramic layer (120_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).

[0323] The lower ceramic circuit board (100_D) and the upper ceramic board (110_U) can be placed facing each other.

[0324] The first power semiconductor element (200) may be disposed between the lower first copper structure (150_D) and the upper first base copper layer (130_U). The second power semiconductor element (300) may be disposed between the lower second copper structure (160_D) and the upper first base copper layer (130_U). The second power semiconductor element (300) may have a smaller thickness than the first power semiconductor element (200).

[0325] At least one of the lower first copper structure (150_D) and the lower second copper structure (160_D) may have a differential porosity and may include a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer (130_D).

[0326] Compared with the double-sided cooling power module (1000) of FIG. 27, the double-sided cooling power module (1000b) of FIG. 29 has a difference in that it includes an upper ceramic substrate (110_U) instead of an upper ceramic circuit substrate (100_U). That is, the double-sided cooling power module (1000b) does not include an upper first copper structure (150_U) and an upper second copper structure (160_U). Therefore, the double-sided cooling power module (1000b) may have an asymmetrical structure with respect to the first power semiconductor element (200) and the second power semiconductor element (300).

[0327] Referring to FIG. 30, a double-sided cooling power module (1000c) may include a lower ceramic circuit board (100a_D), an upper ceramic board (110a_U), a first power semiconductor element (200), a second power semiconductor element (30), an element attachment layer (400), and a mold layer (500).

[0328] The lower ceramic circuit board (100a_D) may include a lower ceramic substrate (110a_D), a lower first copper structure (150_D), and a lower second copper structure (160_D). The lower ceramic substrate (110a_D) may include a lower ceramic layer (120_D), a lower first active metal brazing layer (125_D), a lower second active metal brazing layer (126_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0329] The upper ceramic substrate (110a_U) may include an upper ceramic layer (120_U), an upper first active metal brazing layer (125_U), an upper second active metal brazing layer (126_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).

[0330] The lower ceramic circuit board (100a_D) and the upper ceramic board (110a_U) can be placed facing each other.

[0331] The first power semiconductor element (200) may be disposed between the lower first copper structure (150_D) and the upper first base copper layer (130_U). The second power semiconductor element (300) may be disposed between the lower second copper structure (160_D) and the upper first base copper layer (130_U). The second power semiconductor element (300) may have a smaller thickness than the first power semiconductor element (200).

[0332] At least one of the lower first copper structure (150_D) and the lower second copper structure (160_D) may have a differential porosity and may include a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer (130_D).

[0333] Compared with the double-sided cooling power module (1000b) of FIG. 29, the double-sided cooling power module (1000c) of FIG. 30 has a difference in that it further includes a lower first active metal brazing layer (125_D) interposed between the lower ceramic layer (120_D) and the lower first base copper layer (130_D), a lower second active metal brazing layer (126_D) interposed between the lower ceramic layer (120_D) and the lower second base copper layer (140_D), an upper first active metal brazing layer (125_U) interposed between the upper ceramic layer (120_U) and the upper first base copper layer (130_U), and an upper second active metal brazing layer (126_U) interposed between the upper ceramic layer (120_U) and the upper second base copper layer (140_U).

[0334] Compared with the double-sided cooling power module (1000a) of FIG. 28, the double-sided cooling power module (1000c) of FIG. 30 has a difference in that it includes an upper ceramic substrate (110a_U) instead of an upper ceramic circuit substrate (100a_U). That is, the double-sided cooling power module (1000c) does not include an upper first copper structure (150_U) and an upper second copper structure (160_U). Therefore, the double-sided cooling power module (1000c) may have an asymmetrical structure with respect to the first power semiconductor element (200) and the second power semiconductor element (300).

[0335] According to one embodiment of the present invention, a method for manufacturing a double-sided cooling power module comprises the steps of: providing a lower ceramic circuit board comprising: a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; and one or more lower second copper structures disposed on at least a portion of the lower first copper structure; mounting a first power semiconductor device on the lower first copper structure; mounting a second power semiconductor device having a smaller thickness than the first power semiconductor device on the lower second copper structure; disposing an upper ceramic circuit board on the lower ceramic circuit board, the upper ceramic substrate including an upper ceramic layer and an upper first base copper layer; an upper first copper structure disposed on a portion of the upper ceramic substrate; and one or more upper second copper structures disposed on at least a portion of the upper first copper structure, so as to face the lower ceramic circuit board; and a step of forming a mold layer covering the first power semiconductor element and the second power semiconductor element by filling the space between the lower ceramic circuit board and the upper ceramic circuit board.

[0336] According to one embodiment of the present invention, a method for manufacturing a double-sided cooling power module may include the steps of: providing a lower ceramic circuit board including a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; and one or more lower second copper structures disposed on at least a portion of the lower first copper structure; mounting a first power semiconductor element on the lower first copper structure; mounting a second power semiconductor element having a smaller thickness than the first power semiconductor element on the lower second copper structure; arranging an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer on the lower ceramic circuit board so as to face the lower ceramic circuit board; and forming a mold layer that fills a space between the lower ceramic circuit board and the upper ceramic substrate to cover the first power semiconductor element and the second power semiconductor element.

[0337] At least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure can be formed by printing, pressing, and sintering of a copper-containing paste at a temperature ranging from 500°C to 800°C.

[0338] The surface of at least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure can be blasted.

[0339] At least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure may have a differential porosity, and may include a region on the upper side having a lower porosity than a lower side relatively adjacent to the upper first base copper layer or the lower first base copper layer.

[0340] It will be apparent to a person skilled in the art to which the technical idea of ​​the present invention pertains that the technical idea of ​​the present invention described above is not limited to the above-described embodiments and the attached drawings, and that various substitutions, modifications, and changes are possible within a scope that does not depart from the technical idea of ​​the present invention.

Claims

1. A conductive paste layer forming step of forming a conductive paste layer containing conductive powder on a substrate; A mask placement step of placing a mask on the conductive paste layer; A main light irradiation step of irradiating light onto the conductive paste layer using the mask to form a light-sintered region in which the conductive powder is light-sintered; and Including a conductive layer forming step of removing the non-photosintered unsintered area of ​​the conductive paste layer so that a conductive layer is formed in the photosintered area. Method for manufacturing ceramic circuit board using optical sintering.

2. In paragraph 1, After performing the step of forming the conductive paste layer, Further comprising a pre-drying step of drying the conductive paste layer, Method for manufacturing ceramic circuit board using optical sintering.

3. In paragraph 1, After performing the step of forming the conductive paste layer, Further comprising a pressing step of pressing the conductive paste layer, Method for manufacturing ceramic circuit board using optical sintering.

4. In paragraph 1, After performing the steps of placing the above mask, Further comprising a preliminary light irradiation step of drying the conductive paste layer by irradiating light onto the conductive paste layer using the mask. Method for manufacturing ceramic circuit board using optical sintering.

5. In paragraph 1, Further comprising a drying step of drying the conductive layer, Method for manufacturing ceramic circuit board using optical sintering.

6. In paragraph 1, The step of forming the conductive paste layer is: Forming a conductive paste on the substrate using screen printing, inkjet printing, gravure printing, or flexography, Method for manufacturing ceramic circuit board using optical sintering.

7. In paragraph 1, The above main light irradiation step is, 1 J / cm 2 30 J / cm 2 Performed using light having a pulse intensity in the range of 0.1 ms to 60 ms, a pulse gap in the range of 0.1 ms to 60 ms, and a pulse number in the range of 1 to 100. Method for manufacturing ceramic circuit board using optical sintering.

8. In paragraph 1, The above main light irradiation step is, Performed with at least one of a single shot that irradiates light once, a multi-shot that irradiates the same light multiple times, and a step shot that irradiates light multiple times while changing it. Method for manufacturing ceramic circuit board using optical sintering.

9. In paragraph 8, The above step shot is, Performed while changing the pulse intensity of the above light, Method for manufacturing ceramic circuit board using optical sintering.

10. In paragraph 1, In the above conductive layer formation step, The removal of the above-mentioned unsintered area is performed by using a basic solution containing distilled water or sodium hydroxide, potassium hydroxide, sodium carbonate, potassium carbonate or a mixture thereof as a developing solution. Method for manufacturing ceramic circuit board using optical sintering.

11. In paragraph 1, The above conductive powder is, Containing copper (Cu), silver (Ag), gold (Au), aluminum (Al), nickel (Ni), palladium (Pd), titanium oxide (TiO), or a combination thereof. Method for manufacturing ceramic circuit board using optical sintering.

12. In paragraph 1, The above conductive powder is, A first powder having a first diameter in the range of 1 μm to 10 μm is included in an amount of 50 wt% to 90 wt%, A second powder having a second diameter ranging from 20 nm to 1000 nm, comprising from 10 wt% to 50 wt%, Method for manufacturing ceramic circuit board using optical sintering.

13. In paragraph 11, The above conductive powder is, Having at least one shape among spherical, square, wire-like, plate-like, nano-tubular, rod-like, and whisker-like, Method for manufacturing ceramic circuit board using optical sintering.

14. In paragraph 1, The above substrate is, Including a silicon substrate, wafer, glass substrate, metal substrate, ceramic substrate, polymer substrate, rigid substrate, flexible substrate, low-k film substrate, or ceramic sheet substrate, Method for manufacturing ceramic circuit board using optical sintering.

15. In paragraph 1, The above substrate is, Containing at least one of Al2O3, AlN, ZTA (Zirconia Toughened Alumina), and Si3N4, Method for manufacturing ceramic circuit board using optical sintering.

16. In paragraph 1, The above ceramic circuit board includes a ceramic layer, a base copper layer, and a copper structure, The conductive layer is at least one of the base copper layer or the copper structure, Method for manufacturing ceramic circuit board using optical sintering.

17. In paragraph 16, The above copper structure is, Having the above differential porosity, including a region on the upper side having a lower porosity than the lower side relatively adjacent to the first base copper layer, Method for manufacturing ceramic circuit board using optical sintering.

18. A step of forming a conductive paste layer containing conductive powder on a substrate; A step of placing a mask on the conductive paste layer; A step of irradiating light onto the conductive paste layer using the mask to harden a portion of the conductive paste layer; A step of removing an uncured area of ​​the conductive paste layer; A step of drying the cured area of ​​the conductive paste layer; and A step of forming a conductive layer by sintering the above-mentioned hardening region, Method for manufacturing ceramic circuit board using optical sintering.

19. In paragraph 18, The above sintering is performed by thermal sintering or light sintering. Method for manufacturing ceramic circuit board using optical sintering.

20. A ceramic circuit board formed using a method for manufacturing a ceramic circuit board using photo-sintering according to Article 1. Ceramic circuit board.

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