Semiconductor structure and formation method therefor

Abstract

Disclosed are a semiconductor structure and a formation method therefor. The semiconductor structure comprises a substrate, word line structures, a plurality of active column structures, and isolation structures. A plurality of word line structures are located on the substrate and are arranged at intervals in a first direction. Each word line structure comprises a plurality of gate structures sequentially arranged at intervals in a third direction. The active column structures are disposed on outer walls of the gate structures. At least one end of each active column structure in a second direction is provided with a trench having an opening facing the second direction, a portion of the active column structure surrounding the gate structure forms a channel structure, and a portion of the active column structure located on two sides of the channel structure in the second direction and disposed adjacent to the trench form a source / drain. The isolation structures are located in the trenches and on inner walls adjacent to the gate structures.

Description

Semiconductor structure and method for forming the same

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on Chinese patent application number 202310966093.2, application date July 31, 2023, and invention name “Semiconductor structure and formation method thereof”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to, but not limited to, a semiconductor structure and a method for forming the same. Background Art

[0004] Currently, in order to achieve the miniaturization of semiconductor structure size, a channel-all-around (CAA) structure is generally used as the channel structure of indium gallium zinc oxide (IGZO) transistors. However, in the CAA structure based on IGZO devices, the distance between the gate structure and the source and drain is relatively close, which makes it easy for gate-induced drain leakage (GIDL) to occur between the gate structure and the source and drain.

[0005] Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0007] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising:

[0008] substrate;

[0009] word line structures arranged on the substrate at intervals along a first direction, each of the word line structures comprising a plurality of gate structures sequentially arranged at intervals along a third direction;

[0010] A plurality of active pillar structures are disposed on an outer wall of each gate structure; at least one end of the active pillar structure along the second direction has a trench opening toward the second direction; a portion of the active pillar structure surrounding the gate structure constitutes a channel structure, and portions of the active pillar structure located on both sides of the channel structure along the second direction and adjacent to the trench constitute a source and drain;

[0011] an isolation structure located in the trench adjacent to an inner wall of the gate structure;

[0012] The first direction intersects with the second direction and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located.

[0013] In some embodiments, the trench includes a first trench and a second trench respectively located at two ends of the active pillar structure along the second direction;

[0014] The isolation structure includes: a first isolation structure and a second isolation structure;

[0015] The first isolation structure is located in the first trench adjacent to an inner wall of the gate structure, and the second isolation structure is located in the second trench adjacent to an inner wall of the gate structure.

[0016] In some embodiments, the sidewalls of the word line structure along the cross-section of the third direction are sawtooth-shaped, and the word line structure includes gate structures and recessed portions alternately arranged in sequence along the third direction, the size of the gate structure along the second direction is larger than the size of the recessed portion along the second direction, and the size of the gate structure along the first direction is larger than the size of the recessed portion along the first direction.

[0017] In some embodiments, the source and drain electrodes include a first source and drain electrode and a second source and drain electrode located at two ends of the active pillar structure along the second direction;

[0018] The portion of the active pillar structure adjacent to the first trench constitutes the first source and drain, and the portion of the active pillar structure adjacent to the second trench constitutes the second source and drain.

[0019] In some embodiments, further comprising: a bit line and a capacitor structure;

[0020] The bit line is connected to the first source and drain, and is embedded in the first trench and connected to the first isolation structure;

[0021] The capacitor structure is connected to the second source and drain, and is embedded in the second trench and connected to the second isolation structure.

[0022] In some embodiments, further comprising: a spacer layer;

[0023] The spacer layer is located between the plurality of bit lines arranged along the third direction, between the plurality of capacitor structures arranged along the third direction, and between the plurality of active pillar structures arranged along the third direction.

[0024] In some embodiments, the bit lines extend along the first direction, and a row of the bit lines arranged along the first direction are connected to each other;

[0025] A plurality of bit lines arranged along the third direction form a stepped structure.

[0026] In a second aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method comprising:

[0027] A substrate is provided, on which a stacked structure is formed; the stacked structure is projected on the substrate in a comb-tooth shape; the stacked structure includes a first region and a second region arranged along a second direction; the second region includes a plurality of sub-regions arranged at intervals along the first direction;

[0028] forming a word line structure extending along a third direction and penetrating the sub-region, wherein each word line structure includes a plurality of gate structures sequentially spaced apart along the third direction;

[0029] forming a plurality of active pillar structures surrounding the gate structure and spaced apart; wherein at least one end of the active pillar structure along the second direction has a trench opening toward the second direction; a portion of the active pillar structure surrounding the gate structure constitutes a channel structure, and a portion of the active pillar structure located on both sides of the channel structure along the second direction and adjacent to the trench constitutes a source and a drain;

[0030] forming an isolation structure in the trench adjacent to an inner wall of the gate structure;

[0031] The first direction intersects with the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

[0032] In some embodiments, the stacked structure includes a spacer layer, a first sacrificial layer, a second sacrificial layer, and the first sacrificial layer that are cyclically and alternately arranged along the third direction; and forming a word line structure extending through the sub-region along the third direction includes:

[0033] Etching the sub-region to form a third trench extending along the third direction; the third trench exposes the bottommost spacer layer;

[0034] forming a first initial active pillar structure on a portion of the inner wall of the third trench; wherein the first initial active pillar structure is partially or entirely embedded in the first sacrificial layer;

[0035] The word line structure is formed in the third trench having the first preliminary active pillar structure.

[0036] In some embodiments, forming a plurality of active pillar structures surrounding the gate structure and spaced apart includes:

[0037] removing a portion of the first initial active pillar structure extending in the first direction into between the second sacrificial layer and the spacer layer to form the active pillar structure;

[0038] The remaining portion of the first initial active pillar structure embedded between the second sacrificial layer and the spacer layer constitutes the source and drain;

[0039] The remaining portion of the first initial active pillar structure extending into between the second sacrificial layer and the spacer layer and the region between the first initial active pillar structure located on the sidewall of the second sacrificial layer form the trench.

[0040] In some embodiments, the trench includes a first trench and a second trench respectively located at both ends of the active pillar structure along the second direction; the isolation structure includes a first isolation structure located in the first trench adjacent to an inner wall of the gate structure, and a second isolation structure located in the second trench adjacent to an inner wall of the gate structure; forming the isolation structure in the trench adjacent to the inner wall of the gate structure includes:

[0041] removing the second sacrificial layer between the channel structures to form the first trench and the second trench;

[0042] The first isolation structure and the second isolation structure are formed adjacent to inner walls of the gate structure in the first trench and the second trench, respectively.

[0043] In some embodiments, the source and drain include a first source and drain and a second source and drain located at two ends of the active pillar structure along the second direction, and a portion of the active pillar structure adjacent to the first trench constitutes the first source and drain; the method further includes:

[0044] While forming the first trench and the second trench, removing the second sacrificial layer in the stacked structure to form a fourth trench and a fifth trench; the fourth trench wraps around the first trench; and the fifth trench wraps around the second trench;

[0045] After or simultaneously with forming the first isolation structure and the second isolation structure, removing the first sacrificial layer in the first region and the second region on a side close to the first region along the first direction to form a sixth trench; the sixth trench wraps the fourth trench;

[0046] A bit line connected to the first source and drain is formed in the sixth trench.

[0047] In some embodiments, a portion of the active pillar structure adjacent to the second trench constitutes the second source and drain; and the method further includes:

[0048] Removing the remaining first sacrificial layer in the stacked structure to form a seventh trench; the seventh trench wraps the fifth trench;

[0049] A capacitor structure connected to the second source and drain is formed in the seventh trench.

[0050] In some embodiments, forming a first initial active pillar structure on a portion of an inner wall of the third trench includes:

[0051] forming a second initial active pillar structure on the inner wall and bottom of the third trench;

[0052] The second initial active pillar structure at the bottom of the third trench and the sidewall of the spacer layer is removed to form the first initial active pillar structure.

[0053] In some embodiments, etching the sub-region to form a third trench extending along the third direction includes:

[0054] Etching the sub-region until the bottommost spacer layer is exposed to form an eighth trench extending along the third direction;

[0055] Through the eighth groove, part of the first sacrificial layer and part of the second sacrificial layer are removed by side etching to form the third groove; the third groove wraps the eighth groove and is zigzag-shaped; the size of the third groove located between the first sacrificial layers is larger than the size of the third groove located between the second sacrificial layers.

[0056] An embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate; word line structures arranged at intervals along a first direction on the substrate, each word line structure including a plurality of gate structures arranged in sequence at intervals along a third direction; a plurality of active pillar structures arranged on the outer wall of each gate structure; at least one end of the active pillar structure along a second direction having a groove opening toward the second direction; a portion of the active pillar structure surrounding the gate structure constitutes a channel structure, and a portion of the active pillar structure located on both sides of the channel structure along the second direction and adjacent to the trench constitutes a source and a drain; and an isolation structure located on the inner wall of the trench adjacent to the gate structure. Since at least one end of the active pillar structure along the second direction has a trench opening toward the second direction, and a portion of the active pillar structure adjacent to the trench constitutes a source and drain, this not only increases the distance between the gate structure and the drain, thereby reducing the generation of GIDL, but also increases the contact area between the capacitor structure and the source and drain, as well as the contact area between the bit line and the source and drain, thereby reducing the contact resistance and improving the response speed of the semiconductor structure. In addition, since the inner wall adjacent to the gate structure in the trench has an isolation structure, not only can the GIDL be further reduced, but also the parasitic capacitance between the gate structure and the capacitor structure, and between the gate structure and the bit line, can be reduced, thereby reducing the power consumption of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0058] 1 to 3 are schematic structural diagrams of semiconductor structures provided by embodiments of the present disclosure;

[0059] FIG4 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0060] 5 to 20 are schematic structural diagrams of the semiconductor structure during formation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0062] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0063] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0064] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0065] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0066] At present, six times the square of the characteristic size (6F 2 ) and buried word lines to manufacture small-sized dynamic random access memory (DRAM). However, further scaling of such small-sized DRAM would significantly damage its electrical performance, making DRAM scaling very difficult. To achieve the miniaturization of semiconductor structures, a CAA structure is commonly used as the channel structure of IGZO transistors. However, in the CAA structure based on IGZO devices, the distance between the gate structure and the source and drain is relatively close, which makes it easy to generate GIDL between the gate structure and the source and drain.

[0067] Based on this, an embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate; word line structures arranged at intervals along a first direction on the substrate, each word line structure including a plurality of gate structures arranged in sequence along a third direction; a plurality of active pillar structures arranged on the outer wall of each gate structure; at least one end of the active pillar structure along the second direction has a groove opening toward the second direction; part of the active pillar structure surrounding the gate structure constitutes a channel structure, and part of the active pillar structure located on both sides of the channel structure along the second direction and adjacent to the trench constitutes a source and a drain; an isolation structure located on the inner wall of the trench adjacent to the gate structure. Since at least one end of the active pillar structure along the second direction has a trench opening toward the second direction, and a portion of the active pillar structure adjacent to the trench constitutes a source and drain, this not only increases the distance between the gate structure and the drain, thereby reducing the generation of GIDL, but also increases the contact area between the capacitor structure and the source and drain, as well as the contact area between the bit line and the source and drain, thereby reducing the contact resistance and improving the response speed of the semiconductor structure. In addition, since the inner wall adjacent to the gate structure in the trench has an isolation structure, not only can the GIDL be further reduced, but also the parasitic capacitance between the gate structure and the capacitor structure, and between the gate structure and the bit line, can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0068] The semiconductor structure and the method for forming the same in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0069] Before introducing the embodiments of the present disclosure, the three directions that may be used to describe the three-dimensional structure in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular) with the top and bottom surfaces of the substrate is defined as the third direction. In the directions of the top and bottom surfaces of the substrate (i.e., the plane where the base is located), two directions intersecting (e.g., perpendicular to each other) are defined. For example, the direction in which the word line structure is arranged may be defined as the first direction, and the plane direction of the substrate may be determined based on the first and second directions. In the embodiments of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular. In the embodiments of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0070] 1 to 3 are schematic structural diagrams of a semiconductor structure 100 provided in an embodiment of the present disclosure. As shown in FIG1 to 3 , the semiconductor structure 100 includes: a substrate 110; word line structures 120 arranged on the substrate 110 along the X-axis, each word line structure 120 including a plurality of gate structures 130 arranged in sequence along the Z-axis; a plurality of active pillar structures 140 arranged on the outer wall of each gate structure 130; at least one end of the active pillar structure 140 along the Y-axis has a trench 170 opening toward the Y-axis; a portion of the active pillar structure 140 surrounding the gate structure 130 constitutes a channel structure 150, and a portion of the active pillar structure 140 located on both sides of the channel structure 150 along the Y-axis and adjacent to the trench constitutes a source and drain (i.e., 181 and 182 in the figure); an isolation structure 160; and an inner wall located in the trench adjacent to the gate structure 130.

[0071] It should be noted that FIG2 is a top view and a cross-sectional view along line a-a' of the semiconductor structure 100 in FIG1 according to an embodiment of the present disclosure, and FIG3 is a schematic structural diagram of a memory cell in the semiconductor structure 100. Furthermore, the substrate 110 and the gate structure 130 are not shown in FIG1 . For details on the positions of the substrate 110 and the gate structure 130, please refer to FIG2 .

[0072] In the disclosed embodiment, substrate 110 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. Substrate 110 may also include other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. In other embodiments, substrate 110 may also be an ion-doped substrate, such as a P-type doped substrate or an N-type doped substrate.

[0073] Continuing to refer to FIG. 1 to FIG. 3 , the word line structure 120 extends along the Z-axis direction. This, on the one hand, can reduce the distance between a column of memory cells arranged along the Z-axis direction, thereby effectively reducing signal delay and improving signal transmission speed. On the other hand, it can improve the integration of the stacked structure of the semiconductor structure 100 and enhance the storage density of the semiconductor structure 100, thereby effectively utilizing the space in the semiconductor structure and realizing miniaturization of the semiconductor structure.

[0074] Further, referring to Figures 1 to 3 , the word line structure 120 can include at least one gate structure 130 (i.e., a raised portion on the word line structure 120) and at least one recessed portion, with the gate structure 130 and the recessed portion arranged alternately along the Z-axis. The size of the gate structure 130 along the Y-axis is larger than the size of the recessed portion along the Y-axis, and the size of the gate structure 130 along the X-axis is larger than the size of the recessed portion along the X-axis. This increases the contact area between the gate structure 130 and the channel structure (i.e., the active pillar structure 140), improving the control capability of the gate structure 130.

[0075] In the embodiment of the present disclosure, the gate structure 130 can be axisymmetric along the Z axis (please refer to Figure 2), or mirror-symmetrical along the XZ plane. In this way, the gate structure 130 can uniformly control the channel structure, thereby making signal transmission more stable and uniform.

[0076] In the embodiment of the present disclosure, please continue to refer to Figures 1 to 3. Each word line structure 120 includes a plurality of gate structures 130 arranged in sequence along the Z-axis direction, and the gate structure 130 includes a gate insulating layer 131 and a gate conductive layer. The material of the word line structure 120 can be any one of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt) and palladium (Pd). The gate insulating layer 131 can be composed of a high dielectric constant (HK) material or other suitable materials such as silicon oxide. The high dielectric constant material can include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), zirconium oxide (ZrO2) and aluminum oxide (Al2O3).

[0077] In the embodiment of the present disclosure, please continue to refer to Figures 1 to 3. The multiple active pillar structures 140 are arranged on the outer wall of each gate structure 130, which means that each active pillar structure 140 is arranged around the outer side of the corresponding gate structure 130, or in other words, each word line structure 120 passes through the multiple active pillar structures 140 arranged along the Z-axis direction.

[0078] In the disclosed embodiment, the active pillar structure 140 has grooves opening toward the Y-axis at both ends along the Y-axis (see Figures 1 to 3), i.e., two grooves. Alternatively, the active pillar structure 140 has a groove opening toward the Y-axis at either end along the Y-axis, i.e., one groove. The number of grooves on the active pillar structure 140 can be set according to actual needs.

[0079] It should be noted that the transistors of the semiconductor structure 100 are oxide thin-film transistors. It is understood that the material of the active pillar structure 140 (i.e., the channel structure 150) may include an oxide semiconductor, such as indium gallium zinc oxide. Due to the inherent characteristics of oxide semiconductors (low electron mobility), the use of an oxide semiconductor as the material of the active pillar structure 140 can reduce the leakage current of the transistor located on the surface of the active pillar structure 140, thereby reducing the rate of charge loss on the capacitor structure 190, thereby extending the data retention time of the semiconductor structure 100 and reducing the power consumption of the semiconductor structure. In other embodiments, the transistors of the semiconductor structure 100 may also be ordinary silicon-based transistors or other types of transistors.

[0080] In the embodiment of the present disclosure, since at least one end of the active pillar structure along the Y-axis direction has a groove opening toward the Y-axis direction, and part of the active pillar structure adjacent to the groove constitutes the source and drain, this can not only increase the distance between the gate structure and the drain and reduce the generation of GIDL; it can also increase the contact area between the capacitor structure and the source and drain, as well as the contact area between the bit line and the source and drain, thereby reducing the contact resistance and improving the response speed of the semiconductor structure; in addition, since the inner wall adjacent to the gate structure in the trench has an isolation structure, not only can GIDL be further reduced, but also the parasitic capacitance between the gate structure and the capacitor structure, and the gate structure and the bit line can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0081] In some embodiments, please continue to refer to Figures 1 to 3, the groove 170 includes a first trench 171 and a second trench 172 respectively located at both ends of the active pillar structure 140 along the Y-axis direction; the isolation structure 160 includes: a first isolation structure 161 and a second isolation structure 162; the first isolation structure 161 is located in the first trench 171 adjacent to the inner wall of the gate structure 130, and the second isolation structure 162 is located in the second trench 172 adjacent to the inner wall of the gate structure 130.

[0082] In the disclosed embodiment, the first isolation structure 161 and the second isolation structure 162 may be any insulating material, such as silicon oxide or silicon oxynitride. The first isolation structure 161 and the second isolation structure 162 may also be air gaps. Since the dielectric constant of air is relatively low, setting the first isolation structure 161 and the second isolation structure 162 as air gaps can reduce the parasitic capacitance of structures in contact with the channel structure 150 (e.g., the bit line 200 and the capacitor structure 190), thereby improving the read and write performance of the semiconductor structure.

[0083] Here, the materials of the first isolation structure 161 and the second isolation structure 162 can be the same or different. For example, the materials of the first isolation structure 161 and the second isolation structure 162 are both silicon oxide. For another example, the material of the first isolation structure 161 is silicon oxynitride, and the second isolation structure 162 is an air gap. The thickness of the first isolation structure 161 and the second isolation structure 162 is greater than the thickness of the gate insulating layer 131.

[0084] In the embodiment of the present disclosure, since the first isolation structure 161 is located in the first trench 171 adjacent to the inner wall of the gate structure 130, and the second isolation structure 162 is located in the second trench 172 adjacent to the inner wall of the gate structure 130, not only can the GIDL be further reduced, but the parasitic capacitance between the gate structure and the capacitor structure, as well as the gate structure and the bit line can also be reduced, thereby reducing the power consumption of the semiconductor structure.

[0085] In some embodiments, referring to FIG. 2 , the sidewalls of the wordline structure 120 along the Z-axis are sawtooth-shaped. In other words, the sidewalls of the gate structure 130 along the Z-axis are sawtooth-shaped. This increases the contact area between the gate structure 130 and the channel structure (i.e., the active pillar structure 140 ), thereby improving the control capability of the gate structure 130 .

[0086] In some embodiments, please continue to refer to Figures 1 to 3, the source and drain include a first source and drain 181 and a second source and drain 182 located at both ends of the active column structure 140 along the Y-axis direction; wherein, the portion of the active column structure 140 adjacent to the first trench 171 constitutes the first source and drain 181, and the portion of the active column structure 140 adjacent to the second trench 172 constitutes the second source and drain 182.

[0087] In the embodiment of the present disclosure, the first source drain 181 and the second source drain 182 can be doped with atoms, ions or plasma of group III elements such as boron, gallium, and indium; they can also be doped with atoms, ions or plasma of group V elements such as phosphorus, antimony, and arsenic; the embodiment of the present disclosure is not limited to this.

[0088] In the embodiment of the present disclosure, since the active pillar structure has a first trench 171 and a second trench 172 with an opening facing the Y-axis direction at at least one end along the Y-axis direction, and the portion of the active pillar structure 140 adjacent to the first trench 171 constitutes the first source and drain 181, and the portion of the active pillar structure 140 adjacent to the second trench 172 constitutes the second source and drain 182; in this way, not only can the distance between the gate structure and the drain be increased, reducing the generation of GIDL; the contact area between the capacitor structure and the second source and drain 182, as well as the contact area between the bit line and the first source and drain 181 are increased, thereby reducing the contact resistance and thereby improving the response speed of the semiconductor structure.

[0089] In some embodiments, please continue to refer to Figures 1 to 3, the semiconductor structure 100 also includes: a bit line 200 and a capacitor structure 190; the bit line 200 is connected to the first source and drain 181, and is embedded in the first trench 171 and connected to the first isolation structure 161; the capacitor structure 190 is connected to the second source and drain 182, and is embedded in the second trench 172 and connected to the second isolation structure 162.

[0090] In the embodiment of the present disclosure, please continue to refer to FIG2 , the capacitor structure 190 includes a first electrode layer 191, a dielectric layer 192, and a second electrode layer 193; wherein the materials of the first electrode layer 191 and the second electrode layer 193 may include metal nitrides or metal silicides, such as titanium nitride. The material of the dielectric layer 192 may include a high-K dielectric material, such as lanthanum oxide (La2O3), aluminum oxide, hafnium oxide, hafnium oxynitride (HfON), hafnium silicate (HfSiO x ) or zirconium oxide or any combination thereof. In other embodiments, the material of the first electrode layer 191 and the second electrode layer 193 may also be polysilicon.

[0091] In the embodiment of the present disclosure, the capacitor structure 190 is horizontal and arranged in an array along the X-axis and Z-axis directions. The horizontal capacitor structure 190 can reduce the possibility of tipping over or breaking. The stacked structure formed by stacking multiple capacitor structures 190 in the Z-axis direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure 100 and achieving miniaturization.

[0092] In the embodiment of the present disclosure, the material of the bit line 200 includes tungsten, cobalt, copper (Cu), aluminum (Al), titanium nitride (TiN), polysilicon, or any combination thereof.

[0093] In some embodiments, referring to FIG. 1 to FIG. 3 , the bit lines 200 extend along the X-axis direction, and a row of bit lines 200 arranged along the X-axis direction are connected to each other; a plurality of bit lines 200 arranged along the Z-axis direction form a stepped structure.

[0094] In some embodiments, please continue to refer to Figures 1 to 3, the semiconductor structure 100 also includes: a spacer layer 210; the spacer layer 210 is located between multiple bit lines 200 arranged along the Z-axis direction, between multiple capacitor structures 190 arranged along the Z-axis direction, and between multiple active pillar structures 140 arranged along the Z-axis direction.

[0095] In the embodiment of the present disclosure, the material of the spacer layer 210 can be silicon nitride or silicon carbonitride; on the one hand, the spacer layer 210 can be used to support the formed capacitor structure to reduce the collapse of the capacitor structure and improve the stability of the formed semiconductor structure; on the other hand, the spacer layer 210 can also isolate adjacent capacitor structures, as well as the capacitor structure and the bit line structure, to reduce the generation of leakage current.

[0096] It should be noted that, referring to FIG. 2 , the spacer layer 210 is also located between the substrate 110 and the memory cell.

[0097] In the disclosed embodiment, referring again to FIG. 2 , the semiconductor structure 100 further includes a second insulating structure 111 located between the substrate 110 and the spacer layer 210. The material of the second insulating structure 111 can be any insulating material, such as silicon oxide. The second insulating structure 111 and the spacer layer 210 together isolate the memory cell from the substrate 110, thereby reducing leakage in the memory cell and improving the performance of the semiconductor structure.

[0098] In the disclosed embodiment, referring to FIG. 2 , the semiconductor structure 100 further includes a first insulating structure 220. The first insulating structure 220 is located between adjacent memory cells along the X-axis to prevent leakage from the memory cells. Furthermore, a low-k (low dielectric constant) material can be used as the material for the first insulating structure 220. This can reduce the parasitic capacitance of the semiconductor structure, thereby reducing capacitance-resistance delay and improving the response time of the semiconductor structure.

[0099] In addition, the present disclosure also provides a method for forming a semiconductor structure. FIG4 is a schematic flow chart of the method for forming a semiconductor structure according to the present disclosure. FIG5 through FIG20 are schematic diagrams of the structure during the formation of the semiconductor structure according to the present disclosure. FIG5 through FIG7 are three-dimensional views; FIG8 through FIG20 are top views of the semiconductor structure during the formation process, as well as cross-sectional views along lines a-a' and b-b'. As shown in FIG4, the method for forming a semiconductor structure includes steps S101 through S104.

[0100] First, referring to Figures 4 to 7, step S101 is performed to provide a substrate 110, on which a stacking structure 300 is formed; the projection of the stacking structure 300 on the substrate 110 is comb-shaped; the stacking structure 300 includes a first region A and a second region B arranged along the Y-axis direction; the second region B includes a plurality of sub-regions b arranged at intervals along the X-axis direction.

[0101] In some embodiments, the stack structure 300 can be formed by the following steps S1011 and S1012:

[0102] In step S1011 , an initial spacer layer 210 a , an initial first sacrificial layer 211 a , an initial second sacrificial layer 212 a and an initial first sacrificial layer 211 a are cyclically and alternately stacked on the surface of the substrate 110 to form an initial stack structure 300 a as shown in FIG. 5 .

[0103] Here, please continue to refer to FIG. 5 . Before forming the initial stacking structure 300 a , the method for forming the semiconductor structure 100 further includes: forming an initial second insulating structure 111 a between the initial spacer layer 210 a and the substrate 110 .

[0104] During implementation, the second insulating material can be deposited in sequence on the surface of the substrate 110 to form the initial second insulating structure 111a as shown in Figure 5; the spacer material, the first sacrificial material, and the second sacrificial material can be cyclically deposited in sequence on the surface of the initial second insulating structure 111a to form a cyclically alternating stack of the initial spacer layer 210a, the initial first sacrificial layer 211a, the initial second sacrificial layer 212a, and the initial first sacrificial layer 211a as shown in Figure 5.

[0105] In the embodiment of the present disclosure, the number of layers of the initial spacer layer 210a, the initial first sacrificial layer 211a, and the initial second sacrificial layer 212a in the initial stacked structure 300a can be set according to the required capacitance density (or storage density). The more layers of the initial spacer layer 210a, the initial first sacrificial layer 211a, and the initial second sacrificial layer 212a, the higher the integration of the formed semiconductor structure 100 and the greater the density of the capacitor structure 190. In implementation, the initial spacer layer 210a can be three layers, the initial first sacrificial layer 211a can be five layers, and the initial second sacrificial layer 212a can be two layers.

[0106] In the disclosed embodiments, the second insulating material can be any insulating material, such as silicon oxide; the spacer material can be silicon nitride or silicon carbonitride. The first sacrificial material can be, for example, silicon oxide, and the second sacrificial material can be, for example, polysilicon. Thus, under the same etching conditions, the first sacrificial material is more easily removed than the second sacrificial material.

[0107] In the embodiment of the present disclosure, the initial second insulating structure 111a, the initial spacer layer 210a, the initial first sacrificial layer 211a and the initial second sacrificial layer 212a can be formed by any of the following deposition processes: Chemical Vapor Deposition (CVD) process, Physical Vapor Deposition (PVD) process, Atomic Layer Deposition (ALD) process or other suitable processes.

[0108] Step S1012 , etching the initial stack structure 300 a to form a stack structure 300 .

[0109] During implementation, for example, the initial stacking structure 300a can be etched by a dry etching process or a wet etching process to form a stacking structure 300 as shown in Figure 6; the stacking structure 300 includes a spacer layer 210, a first sacrificial layer 211, a second sacrificial layer 212 and a first sacrificial layer 211 that are cyclically arranged alternately along the Z-axis direction.

[0110] It should be noted that, referring to FIG. 6 , while etching the initial stacked structure 300 a , the initial second insulating structure 111 a is also etched to form the second insulating structure 111 ; and a portion of the substrate 110 is also etched.

[0111] In the embodiment of the present disclosure, after performing step S101, the method for forming the semiconductor structure 100 further includes depositing a first insulating material between the sub-regions b to form an initial first insulating structure 220a as shown in FIG7 . The first insulating material may be a low-K material. The initial first insulating structure 220a can protect the side surfaces of the stacked structure 300 along the X-axis from damage during subsequent processing of the stacked structure 300.

[0112] Next, referring to FIG. 4 and FIG. 8 to FIG. 13 , step S102 is performed to form word line structures 120 extending through the sub-region b along the Z-axis direction. Each word line structure 120 includes a plurality of gate structures 130 sequentially spaced apart along the Z-axis direction.

[0113] In some embodiments, the word line structure 120 extending along the Z-axis direction and penetrating the sub-region b may be formed by the following steps S1021 to S1023:

[0114] In step S1021 , the sub-region b is etched to form a third trench 173 extending along the Z-axis direction; the third trench 173 exposes the bottommost spacer layer 210 .

[0115] In some embodiments, step S1021 may be performed by:

[0116] In step S1021 a , the sub-region b is etched until the bottom spacer layer 210 is exposed, thereby forming an eighth trench 178 extending along the Z-axis direction.

[0117] During implementation, the sub-region b can be etched by a wet etching process (for example, etching with a strong acid such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or a dry etching process (for example, a plasma etching process, a reactive ion etching process, or an ion milling process) until the bottom-layer spacer layer 210 is exposed, thereby forming the eighth groove 178 extending along the Z-axis direction as shown in FIG8 .

[0118] In step S1021b, a portion of the first sacrificial layer 211 and a portion of the second sacrificial layer 212 are laterally etched away through the eighth groove 178 to form a third groove 173; the third groove 173 wraps around the eighth groove 178 and is zigzag-shaped; the size d1 of the third groove 173 located between the first sacrificial layers 211 is larger than the size d2 of the third groove 173 located between the second sacrificial layers 212.

[0119] During implementation, a wet etching process can be used to lateral-etch through the eighth groove 178 to laterally etch away a portion of the first sacrificial layer 211 and a portion of the second sacrificial layer 212 to form the third groove 173 as shown in FIG9 ; wherein the etching solution can be hydrofluoric acid (DHF), a mixed solution of diluted hydrofluoric acid and ammonia water (NH4OH), or a mixed solution of diluted hydrofluoric acid and tetramethylammonium hydroxide (TMAH).

[0120] It should be noted that, because the first sacrificial layer 211 has a larger selective etching ratio than the second sacrificial layer 212, the first sacrificial layer 211 is more easily etched and removed than the second sacrificial layer 212 during the etching process. Therefore, when forming the third trenches 173, the size of the third trenches 173 located between the first sacrificial layers 211 is larger than the size of the third trenches 173 located between the second sacrificial layers 212. In addition, the dimension d1 of the third trenches 173 located between the first sacrificial layers 211 and the dimension d2 of the third trenches 173 located between the second sacrificial layers 212 can both be dimensions or areas in any direction within the substrate plane.

[0121] In step S1022 , a first initial active pillar structure 140 a is formed on a portion of the inner wall of the third trench 173 .

[0122] In some embodiments, step S1022 may be performed by:

[0123] Step S1022 a , forming a second initial active pillar structure 140 b on the inner wall and bottom of the third trench 173 .

[0124] During implementation, an active material may be deposited on the inner wall and bottom of the third trench 173 to form a second initial active pillar structure 140b as shown in FIG10 . The active material may include an oxide semiconductor, such as indium gallium zinc oxide. The second initial active pillar structure 140b may be formed by any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.

[0125] Step S1022 b , removing the second initial active pillar structure 140 b at the bottom of the third trench 173 and the sidewall of the spacer layer 210 to form a first initial active pillar structure 140 a .

[0126] During implementation, the second initial active column structure 140b can be etched by a dry etching process or a wet etching process to remove the second initial active column structure 140b at the bottom of the third trench 173, the sidewall of the spacer layer 210 and the surface of the topmost spacer layer 210 to form the first initial active column structure 140a as shown in Figure 11.

[0127] In step S1023 , the first preliminary active pillar structure 140 a is partially or completely embedded in the first sacrificial layer 211 ; and a word line structure 120 is formed in the third trench 173 having the first preliminary active pillar structure 140 a .

[0128] It should be noted that if the first initial active pillar structure 140a is entirely embedded in the first sacrificial layer 211, the first trench 171 and the second trench 172 can be formed simultaneously thereafter. In other embodiments, if the first initial active pillar structure 140a is partially embedded in the first sacrificial layer 211, only the first trench 171 or the second trench 172 is subsequently formed. The embodiments of the present disclosure are described using the example of the first initial active pillar structure 140a being entirely embedded in the first sacrificial layer 211.

[0129] During implementation, after forming the first initial active pillar structure 140a, a gate insulating material and a conductive material are sequentially deposited in the third trench 173 having the first initial active pillar structure 140a to form a gate insulating layer 131 and a gate conductive layer as shown in FIG12. The gate insulating layer 131 and the gate conductive layer constitute the gate structure 130, and the gate conductive layer can serve as the word line structure 120 as shown in FIG12.

[0130] Here, the gate insulating material can be a high-k dielectric (HK) material or other suitable materials such as silicon oxide. High-k dielectric materials can include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), zirconium oxide (ZrO2), and aluminum oxide (Al2O3). The conductive material can be any one of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt), and palladium (Pd). The gate insulating layer 131 and the wordline structure 120 can be formed by any suitable process.

[0131] 13 , after forming the wordline structure 120, the method for forming the semiconductor structure 100 further includes removing a portion of the initial first insulating structure 220a to expose a portion of the first sacrificial layer 211. Specifically, the portion of the initial first insulating structure 220a can be removed by a dry etching process or a wet etching process to expose both sides of the first sacrificial layer 211 along the X-axis direction.

[0132] 13 , after exposing both sides of the first sacrificial layer 211 along the X-axis direction, a portion of the first sacrificial layer 211 is removed along the X-axis direction by side etching to expose both sides of the first initial active pillar structure 140 a along the X-axis direction.

[0133] Next, referring to Figures 4, 14 and 15, step S103 is performed to form a plurality of active pillar structures 140 that surround the gate structure 130 and are arranged at intervals; the active pillar structure 140 has a groove 170 with an opening facing the Y-axis direction at at least one end along the Y-axis direction; part of the active pillar structure 140 surrounding the gate structure 130 constitutes a channel structure 150, and part of the active pillar structure 140 located on both sides of the channel structure 150 along the Y-axis direction and adjacent to the groove 170 constitutes a source and a drain.

[0134] In some embodiments, step S103 of forming a plurality of active pillar structures 140 surrounding the gate structure 130 and spaced apart includes:

[0135] The portion of the first initial active column structure 140a extending into between the second sacrificial layer 212 and the spacer layer 210 in the X-axis direction is removed to form the active column structure 140 as shown in Figure 14; wherein, the remaining portion of the first initial active column structure 140a embedded between the second sacrificial layer 212 and the spacer layer 210 constitutes the source and drain; the remaining portion of the first initial active column structure 140a extending into between the second sacrificial layer 212 and the spacer layer 210 and the area between the first initial active column structure 140a located on the side wall of the second sacrificial layer 212 form a groove 170.

[0136] Here, please continue to refer to Figure 14. The groove 170 includes a first groove 171 and a second groove 172 respectively located at both ends of the active column structure 140 along the Y-axis direction; the source and drain include a first source and drain 181 and a second source and drain 182 located at both ends of the active column structure 140 along the Y-axis direction. The portion of the active column structure 140 adjacent to the first groove 171 constitutes the first source and drain 181, and the portion of the active column structure 140 adjacent to the second groove 172 constitutes the second source and drain 182.

[0137] During implementation, a portion of the first initial active pillar structure 140 a extending between the second sacrificial layer 212 and the spacer layer 210 in the X-axis direction may be removed by lateral etching to form the active pillar structure 140 shown in FIG. 14 .

[0138] In the embodiment of the present disclosure, please continue to refer to FIG. 14 . After the active pillar structure 140 , the method for forming the semiconductor structure 100 further includes: removing the second sacrificial layer 212 exposed in the X-axis direction; and exposing both sides of the active pillar structure 140 along the X-axis direction.

[0139] In the embodiment of the present disclosure, after the second sacrificial layer 212 exposed in the X-axis direction is removed, a first insulating material is deposited between two adjacent sub-regions b along the X-axis direction to form a first insulating structure 220 as shown in FIG. 15 .

[0140] Finally, referring to FIG. 5 and FIG. 16 to FIG. 20 , step S104 is performed to form an isolation structure 160 in the trench adjacent to the inner wall of the gate structure 130 .

[0141] In some embodiments, the isolation structure 160 includes a first isolation structure 161 located in the first trench 171 adjacent to an inner wall of the gate structure 130 , and a second isolation structure 162 located in the second trench 172 adjacent to an inner wall of the gate structure 130 . Step S104 can be formed by following the steps S1041 to S1042 :

[0142] In step S1041 , the second sacrificial layer 212 between the channel structures 150 is removed to form a first trench 171 and a second trench 172 .

[0143] In some embodiments, the method for forming the semiconductor structure 100 further includes: while forming the first trench 171 and the second trench 172 , removing the second sacrificial layer 212 in the stacked structure 300 to form a fourth trench 174 and a fifth trench 175 as shown in FIG16 ; the fourth trench 174 wraps the first trench 171 , and the fifth trench 175 wraps the second trench 172 .

[0144] During implementation, the second sacrificial layer 212 may be removed by lateral etching using a wet etching process to form the fourth trench 174 and the fifth trench 175 as shown in FIG. 16 .

[0145] In step S1042 , a first isolation structure 161 and a second isolation structure 162 are formed in the first trench 171 and the second trench 172 adjacent to the inner walls of the gate structure 130 , respectively.

[0146] In some embodiments, step S1042 may be performed by:

[0147] In step S1042a, after forming the fourth trench 174 and the fifth trench 175, any insulating material is filled into the fourth trench 174 and the fifth trench 175 to form the initial first isolation structure 161a and the initial second isolation structure 162a as shown in FIG17. Here, the insulating material filled into the fourth trench 174 and the insulating material filled into the fifth trench 175 can be the same or different.

[0148] Step S1042 b , etching the initial first isolation structure 161 a to form the first isolation structure 161 .

[0149] During implementation, the initial first isolation structure 161 a may be etched in a lateral etching manner using a wet etching process to form the first isolation structure 161 as shown in FIG. 18 .

[0150] Here, at the same time as or after forming the first isolation structure 161 as shown in Figure 18, the first sacrificial layer 211 in the first region A and the second region B on the side close to the first region A along the X-axis direction is removed to form the sixth trench 176 as shown in Figure 18; the sixth trench 176 wraps the fourth trench 174; and a bit line 200 as shown in Figure 19 is formed in the sixth trench 176 and connected to the first source and drain 181.

[0151] The bit lines 200 extend along the X-axis direction, and a row of bit lines 200 arranged along the X-axis direction are connected to each other; a plurality of bit lines 200 arranged along the Z-axis direction form a step structure.

[0152] Step S1042 c , etching the initial second isolation structure 162 a to form a second isolation structure 162 .

[0153] During implementation, the initial first isolation structure 162 a may be etched in a lateral etching manner using a wet etching process to form the second isolation structure 162 as shown in FIG. 20 .

[0154] Here, after or at the same time as forming the second isolation structure 162 as shown in Figure 20, the remaining first sacrificial layer 211 in the stacked structure 300 is removed to form the seventh trench 177 as shown in Figure 20; the seventh trench 177 wraps the fifth trench 175; and a capacitor structure 190 connected to the second source and drain 182 is formed in the seventh trench 177 (refer to Figure 2).

[0155] During implementation, the remaining first sacrificial layer 211 in the stacked structure 300 is removed to form a seventh groove 177; next, a first electrode layer 191, a dielectric layer 192 and a second electrode layer 193 are formed in sequence in the seventh groove 177, and the first electrode layer 191, the dielectric layer 192 and the second electrode layer 193 constitute the capacitor structure 190 as shown in Figure 2.

[0156] It should be noted that in the embodiment of the present disclosure, the bit line 200 is formed first, and then the capacitor structure 190 is formed; in other embodiments, the capacitor structure 190 may be formed first, and then the bit line 200 is formed, which is not limited here.

[0157] The method for forming a semiconductor structure provided by the embodiment of the present disclosure has an active pillar structure in the formed semiconductor structure having a groove opening toward the Y-axis direction at at least one end along the Y-axis direction, and a portion of the active pillar structure adjacent to the groove constitutes a source and drain. In this way, not only can the distance between the gate structure and the drain be increased, thereby reducing the generation of GIDL, but also the contact area between the capacitor structure and the source and drain, as well as the contact area between the bit line and the source and drain, can be increased, thereby reducing the contact resistance and improving the response speed of the semiconductor structure. In addition, since the inner wall adjacent to the gate structure in the trench has an isolation structure, not only can the GIDL be further reduced, but also the parasitic capacitance between the gate structure and the capacitor structure, as well as the parasitic capacitance between the gate structure and the bit line, can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0158] The semiconductor structure formed by the method provided in the embodiment of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above-mentioned embodiment for understanding, and no further details will be given here.

[0159] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in non-targeted ways. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0160] The features disclosed in several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0161] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. Industrial Applicability

[0162] An embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate; word line structures arranged at intervals along a first direction on the substrate, each word line structure including a plurality of gate structures arranged in sequence at intervals along a third direction; a plurality of active pillar structures arranged on the outer wall of each gate structure; at least one end of the active pillar structure along a second direction having a groove opening toward the second direction; a portion of the active pillar structure surrounding the gate structure constitutes a channel structure, and a portion of the active pillar structure located on both sides of the channel structure along the second direction and adjacent to the trench constitutes a source and a drain; and an isolation structure located on the inner wall of the trench adjacent to the gate structure. Since at least one end of the active pillar structure along the second direction has a trench opening toward the second direction, and a portion of the active pillar structure adjacent to the trench constitutes a source and drain, this not only increases the distance between the gate structure and the drain, thereby reducing the generation of GIDL, but also increases the contact area between the capacitor structure and the source and drain, as well as the contact area between the bit line and the source and drain, thereby reducing the contact resistance and improving the response speed of the semiconductor structure. In addition, since the inner wall adjacent to the gate structure in the trench has an isolation structure, not only can the GIDL be further reduced, but also the parasitic capacitance between the gate structure and the capacitor structure, and between the gate structure and the bit line, can be reduced, thereby reducing the power consumption of the semiconductor structure.

Claims

1. A semiconductor structure (100), comprising: A substrate (110); word line structures (120) arranged at intervals along a first direction on the substrate (110), each of the word line structures (120) comprising a plurality of gate structures (130) arranged in sequence at intervals along a third direction; A plurality of active column structures (140) are arranged on the outer wall of each gate structure (130); at least one end of the active column structure (140) along the second direction has a groove (170) opening toward the second direction; a portion of the active column structure (140) surrounding the gate structure (130) constitutes a channel structure (150), and a portion of the active column structure (140) located on both sides of the channel structure (150) along the second direction and adjacent to the groove (170) constitutes a source and a drain; An isolation structure (160) located in the trench (170) adjacent to an inner wall of the gate structure (130); The first direction intersects with the second direction and is located in the plane where the substrate (110) is located; the third direction intersects with the plane where the substrate (110) is located.

2. The semiconductor structure (100) according to claim 1, wherein: The groove (170) comprises a first groove (171) and a second groove (172) respectively located at two ends of the active pillar structure (140) along the second direction; The isolation structure (160) comprises: a first isolation structure (161) and a second isolation structure (162); The first isolation structure (161) is located in the first trench (171) adjacent to the inner wall of the gate structure (130), and the second isolation structure (162) is located in the second trench (172) adjacent to the inner wall of the gate structure (130).

3. The semiconductor structure (100) according to claim 1 or 2, wherein: The sidewall of the word line structure (120) along the third direction cross section is sawtooth-shaped, and the word line structure (120) comprises a gate structure (130) and a recessed portion that are alternately arranged in sequence along the third direction, the size of the gate structure (130) along the second direction is larger than the size of the recessed portion along the second direction, and the size of the gate structure (130) along the first direction is larger than the size of the recessed portion along the first direction.

4. The semiconductor structure (100) according to claim 2, wherein: The source and drain electrodes include a first source and drain electrode (181) and a second source and drain electrode (182) located at two ends of the active pillar structure (140) along the second direction; The portion of the active pillar structure (140) adjacent to the first trench (171) constitutes the first source and drain (181), and the portion of the active pillar structure (140) adjacent to the second trench (172) constitutes the second source and drain (182).

5. The semiconductor structure (100) according to claim 4, wherein: Also included: a bit line (200) and a capacitor structure (190); The bit line (200) is connected to the first source and drain (181), and is embedded in the first trench (171) and connected to the first isolation structure (161); The capacitor structure (190) is connected to the second source and drain (182), and is embedded in the second trench (172) and connected to the second isolation structure (162).

6. The semiconductor structure (100) according to claim 5, wherein: Also included: a spacer layer (210); The spacer layer (210) is located between the plurality of bit lines (200) arranged along the third direction, between the plurality of capacitor structures (190) arranged along the third direction, and between the plurality of active pillar structures (140) arranged along the third direction.

7. The semiconductor structure (100) according to claim 5 or 6, wherein: The bit lines (200) extend along the first direction, and a row of the bit lines (200) arranged along the first direction are connected to each other; A plurality of bit lines (200) arranged along the third direction form a step structure.

8. The semiconductor structure (100) according to claim 2, wherein: The gate structure (130) comprises a gate insulating layer (131), and the thickness of the first isolation structure (161) and the second isolation structure (162) is greater than the thickness of the gate insulating layer (131).

9. The semiconductor structure (100) according to claim 2, wherein: The first isolation structure (161) and the second isolation structure (162) include silicon oxide, silicon oxynitride or an air gap.

10. The semiconductor structure (100) according to claim 1, wherein: The semiconductor structure (100) further comprises a first insulating structure (220), wherein the first insulating structure (220) is located between active pillar structures (140) adjacent to each other along a first direction.

11. The semiconductor structure (100) according to claim 10, wherein: The material of the first insulating structure (220) is a low dielectric constant material.

12. The semiconductor structure (100) according to claim 6, wherein: The semiconductor structure (100) further comprises a second insulating structure (111), wherein the second insulating structure (111) is located between the substrate (110) and the spacer layer (210).

13. A method for forming a semiconductor structure (100), the method comprising: A substrate (110) is provided, on which a stacking structure (300) is formed; a projection of the stacking structure (300) on the substrate (110) is in a comb-tooth shape; the stacking structure (300) comprises a first region (A) and a second region (B) arranged along a second direction; the second region (B) comprises a plurality of sub-regions (b) arranged at intervals along the first direction; forming a word line structure (120) extending along a third direction and penetrating the sub-region (b), each of the word line structures (120) comprising a plurality of gate structures (130) sequentially spaced apart along the third direction; A plurality of active column structures (140) are formed that surround the gate structure (130) and are arranged at intervals; at least one end of the active column structure (140) along the second direction has a groove (170) opening toward the second direction; a portion of the active column structure (140) that surrounds the gate structure (130) constitutes a channel structure (150), and a portion of the active column structure (140) that is located on both sides of the channel structure (150) along the second direction and adjacent to the groove (170) constitutes a source and a drain; forming an isolation structure (160) in the trench (170) adjacent to an inner wall of the gate structure (130); The first direction intersects with the second direction and is parallel to the plane where the substrate (110) is located, and the third direction is perpendicular to the plane where the substrate (110) is located.

14. The method according to claim 13, wherein: The stacked structure (300) comprises a spacer layer (210), a first sacrificial layer (211), a second sacrificial layer (212), and the first sacrificial layer (211) which are cyclically and alternately arranged along the third direction; The forming of a word line structure (120) extending along a third direction and penetrating the sub-region (b) comprises: Etching the sub-region (b) to form a third groove (173) extending along the third direction; The third groove (173) exposes the bottommost spacer layer (210); A first initial active pillar structure (140a) is formed on a portion of the inner wall of the third trench (173); the first initial active pillar structure (140a) is partially or completely embedded in the first sacrificial layer (211); The word line structure (120) is formed in the third trench (173) having the first initial active pillar structure (140a).

15. The method according to claim 14, wherein: A plurality of active pillar structures (140) are formed surrounding the gate structure (130) and arranged at intervals, comprising: removing a portion of the first initial active pillar structure (140a) extending in the first direction into between the second sacrificial layer (212) and the spacer layer (210) to form the active pillar structure (140); The remaining portion of the first initial active pillar structure (140a) embedded between the second sacrificial layer (212) and the spacer layer (210) constitutes the source and drain; The remaining portion of the first initial active column structure (140a) extending into between the second sacrificial layer (212) and the spacer layer (210) and the first initial active column structure located on the side wall of the second sacrificial layer (212) The area between (140a) forms the groove (170).

16. The method according to claim 14 or 15, wherein: The groove (170) comprises a first groove (171) and a second groove (172) respectively located at two ends of the active pillar structure (140) along the second direction; the isolation structure (160) comprises a first isolation structure (161) located in the first groove (171) adjacent to the inner wall of the gate structure (130), and a second isolation structure (162) located in the second groove (172) adjacent to the inner wall of the gate structure (130); An isolation structure (160) is formed in the trench (170) adjacent to an inner wall of the gate structure (130), comprising: removing the second sacrificial layer (212) between the channel structures (150) to form the first trench (171) and the second trench (172); The first isolation structure (161) and the second isolation structure (162) are respectively formed in the first trench (171) and the second trench (172) adjacent to the inner wall of the gate structure (130).

17. The method according to claim 16, wherein: The source and drain electrodes include a first source and drain electrode (181) and a second source and drain electrode (182) located at two ends of the active pillar structure (140) along the second direction, and a portion of the active pillar structure (140) adjacent to the first trench (171) constitutes the first source and drain electrode (181); the method further includes: While forming the first groove (171) and the second groove (172), the second sacrificial layer (212) in the stacked structure (300) is removed to form a fourth groove (174) and a fifth groove (175); the fourth groove (174) wraps around the first groove (171); and the fifth groove (175) wraps around the second groove (172); After or simultaneously with forming the first isolation structure (161) and the second isolation structure (162), the first sacrificial layer (212) in the first region (A) and the second region (B) on one side close to the first region (A) along the first direction is removed to form a sixth trench (176); the sixth trench (176) wraps the fourth trench (174); A bit line (200) connected to the first source and drain (181) is formed in the sixth trench (176).

18. The method according to claim 17, wherein: The portion of the active pillar structure (140) adjacent to the second trench (172) constitutes the second source and drain (182); the method further comprises: Removing the remaining first sacrificial layer (211) in the stacked structure (300) to form a seventh groove (177); the seventh groove (177) wraps the fifth groove (175); A capacitor structure (190) connected to the second source and drain (182) is formed in the seventh trench (177).

19. The method according to any one of claims 14 to 18, wherein: A first initial active pillar structure (140a) is formed on a portion of the inner wall of the third trench (173), comprising: forming a second initial active pillar structure (140b) on the inner wall and bottom of the third trench (173); The second initial active pillar structure (140b) at the bottom of the third trench (173) and the sidewall of the spacer layer (210) is removed to form the first initial active pillar structure (140a).

20. The method according to any one of claims 14 to 19, wherein: The etching of the sub-region (b) to form a third trench (173) extending along the third direction comprises: Etching the sub-region (b) until the bottommost spacer layer (210) is exposed, thereby forming an eighth groove (178) extending along the third direction; Part of the first sacrificial layer (211) and part of the second sacrificial layer (212) are removed by side etching through the eighth groove (178) to form the third groove (173); the third groove (173) wraps the eighth groove (178) and is zigzag-shaped; the size of the third groove (173) located between the first sacrificial layers (211) is larger than the size of the third groove (173) located between the second sacrificial layers (212).

Images