Preparation method for heterojunction back-contact battery, and heterojunction back-contact battery

Abstract

A preparation method for a heterojunction back-contact battery, and a heterojunction back-contact battery. The method comprises: forming a first initial semiconductor passivation layer on one side of a semiconductor substrate layer; forming a first initial doped semiconductor layer on the surface of the side of the first initial semiconductor passivation layer away from the semiconductor substrate layer; performing first laser ablation treatment on part of the first initial doped semiconductor layer and part of the first initial semiconductor passivation layer, and performing first cleaning treatment after the first laser ablation treatment, to form a first opening, cause the first initial semiconductor passivation layer to form a first semiconductor passivation layer located on the side part of the first opening, and cause the first initial doped semiconductor layer to form a first doped semiconductor layer located on the side part of the first opening; and forming, in the first opening, a second semiconductor passivation layer, and a second doped semiconductor layer located on the surface of the side of the second semiconductor passivation layer away from the semiconductor substrate layer. The method can effectively simplify the process, reduce costs, improve patterning precision and reduce damage.

Description

Preparation method of heterojunction back contact battery and heterojunction back contact battery

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310966147.5 and invention name “Method for preparing heterojunction back contact battery and heterojunction back contact battery”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a method for preparing a heterojunction back-contact cell and a heterojunction back-contact cell. Background Art

[0004] In recent years, energy crises and environmental pressures have driven the rapid development of solar cell research and industry. Currently, the mainstream photovoltaic cell is crystalline silicon solar cells, which account for over 90% of the photovoltaic market and will continue to dominate for a considerable period of time.

[0005] Due to the limitations of its technical mechanism, the N-type TOPCon (Tunnel Oxide Passivated Contact) tunnel oxide passivated contact cell has encountered a bottleneck in improving its conversion efficiency. The back-contact cell is a special structure in which the positive and negative electrode grid lines are all located on the back side, achieving an unobstructed front side effect, thereby maximizing the use of light, thereby significantly improving the conversion efficiency. At the same time, the design of no grid lines on the front side also makes the component more aesthetically pleasing. The N-type HBC (heterojunction back-contact cell) combines the advantages of full light reception of the back-contact cell and the high-quality passivation of the heterojunction cell. Its experimental efficiency has reached 26.63%, a significant improvement in efficiency. On the one hand, it increases the power generation per watt of the cell itself, and on the other hand, it helps to reduce the power generation cost of the entire industry chain.

[0006] HBC currently uses a masked etching process to create the opposite PN junction region and remove portions of the conductive layer to separate them, thereby preventing short circuits between the positive and negative gate lines. However, the masked etching process is complex, has low precision, and is difficult to control etching quality, limiting the large-scale production of HBC.

[0007] Therefore, a preparation method for HBC heterojunction back contact cells that effectively simplifies the process, has high production efficiency and low cost is urgently needed in the market.

[0008] Summary of the Invention

[0009] The technical problem to be solved by this application is to overcome the problems in the process of preparing heterojunction back-contact batteries in the prior art, and to provide a method for preparing heterojunction back-contact batteries and a heterojunction back-contact battery that can not only effectively simplify the process, improve production efficiency, and reduce costs, but also improve the accuracy of graphics, reduce damage, and facilitate large-scale production.

[0010] In order to solve the above technical problems, the present application provides a method for preparing a heterojunction back contact battery, comprising: providing a semiconductor substrate layer; forming a first initial semiconductor passivation layer on a side surface of the semiconductor substrate layer; forming a first initial doped semiconductor layer on a side surface of the first initial semiconductor passivation layer away from the semiconductor substrate layer; performing a first laser ablation treatment on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, performing a first cleaning treatment after the first laser ablation treatment to form a first opening, and forming the first initial semiconductor passivation layer into a first semiconductor passivation layer located on a side portion of the first opening, and forming the first initial doped semiconductor layer into a first doped semiconductor layer located on a side portion of the first opening; forming a second A semiconductor passivation layer and a second doped semiconductor layer located on a surface of the second semiconductor passivation layer facing away from the semiconductor substrate layer, the second doped semiconductor layer and the second semiconductor passivation layer are both separated from the first semiconductor passivation layer and the first doped semiconductor layer, the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types and are located on the same side of the semiconductor substrate layer; a first transparent conductive film is formed on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer; a second transparent conductive film is formed on a surface of the second doped semiconductor layer facing away from the semiconductor substrate layer; a first gate line is formed on a surface of the first transparent conductive film facing away from the semiconductor substrate layer, and a second gate line is formed on a surface of the second transparent conductive film facing away from the semiconductor substrate layer.

[0011] Optionally, the parameters of the first laser ablation process include: the laser used is ultraviolet light or green laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W.

[0012] Optionally, the wavelength of the laser used is 355 nm or 532 nm.

[0013] Optionally, the parameters of the first cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is KOH solution or NaOH solution, and the cleaning time is 100 seconds to 130 seconds; or, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

[0014] Optionally, it also includes: before performing the first laser ablation treatment on part of the first initial doped semiconductor layer and part of the first initial semiconductor passivation layer, an initial isolation layer is formed on the surface of the first initial doped semiconductor layer facing away from the semiconductor substrate layer; in the process of performing the first laser ablation treatment on part of the first initial doped semiconductor layer and part of the first initial semiconductor passivation layer, the initial isolation layer is also subjected to the first laser ablation treatment to form an isolation layer; the preparation method of the heterojunction back contact battery also includes: in the process of forming the second semiconductor passivation layer and the second doped semiconductor layer, a second additional passivation layer and a second additional doped layer are formed on the surface of part of the isolation layer facing away from the semiconductor substrate layer, the material of the second additional passivation layer is the same as the material of the second semiconductor passivation layer, the material of the second additional doped layer is the same as the material of the second doped semiconductor layer, the second additional doped layer is located on the surface of the second additional passivation layer facing away from the semiconductor substrate layer, a second opening is formed in the isolation layer, and the second opening exposes the first doped semiconductor layer.

[0015] Optionally, the steps of forming the second semiconductor passivation layer and the second doped semiconductor layer, the second additional passivation layer and the second additional doped layer include: forming a second initial passivation film and a second initial doped semiconductor film in the first opening and on the side of the isolation layer facing away from the semiconductor substrate layer in sequence; performing a second laser ablation treatment and a second cleaning treatment on part of the isolation layer and part of the second initial passivation film and the second initial doped semiconductor film on the side of the isolation layer facing away from the semiconductor substrate layer, so that the second initial passivation film on the side of the isolation layer facing away from the semiconductor substrate layer forms a second additional passivation layer, and the second initial doped semiconductor film on the side of the isolation layer facing away from the semiconductor substrate layer forms a second additional doped layer, and forming a second opening in the isolation layer; performing a third laser ablation treatment and a third cleaning treatment on the area where the second initial passivation film and the second initial doped semiconductor film in the first opening intersect with the first semiconductor passivation layer and the first doped semiconductor layer in sequence, so that the second initial passivation film in the first opening forms the second semiconductor passivation layer, and the second initial doped semiconductor film in the first opening forms the second doped semiconductor layer.

[0016] Optionally, the parameters of the second laser ablation treatment include: the laser used is ultraviolet light or green laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W; optionally, the wavelength of the laser used is 355nm or 532nm.

[0017] Optionally, the parameters of the second cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

[0018] Optionally, the parameters of the third laser ablation process include: the laser used is a green laser, and the pulse width of the laser used is in the nanosecond level.

[0019] Optionally, the wavelength of the laser used is 532 nm.

[0020] Optionally, the parameters of the third cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is KOH solution or NaOH solution, and the cleaning time is 100 seconds to 130 seconds; or, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

[0021] Optionally, it also includes: performing texturing treatment on the other side surface of the semiconductor substrate layer to form an anti-reflection velvet surface; forming a third semiconductor passivation layer on the reflective velvet surface; and forming an anti-reflection layer on the side surface of the third semiconductor passivation layer away from the semiconductor substrate layer.

[0022] Optionally, the step of forming the first transparent conductive film and the second transparent conductive film includes: after performing the second cleaning treatment and before performing the third laser ablation treatment, forming a transparent conductive film on the surface of the first doped semiconductor layer facing away from the semiconductor substrate layer and the surface of the second initial doped semiconductor film facing away from the semiconductor substrate layer; in the step of performing the third laser ablation treatment, the third laser ablation treatment also removes the boundary area between the transparent conductive film in the first opening and the first semiconductor passivation layer and the first doped semiconductor layer, so that the transparent conductive film forms the first transparent conductive film and the second transparent conductive film.

[0023] The present application also provides a heterojunction back-contact battery, comprising: a semiconductor substrate layer; a first semiconductor passivation layer located on one side surface of the semiconductor substrate layer, and a first doped semiconductor layer located on the side surface of the first semiconductor passivation layer facing away from the semiconductor substrate layer; a first opening penetrating the first doped semiconductor layer and the first semiconductor passivation layer; a second semiconductor passivation layer and a second doped semiconductor layer located within the first opening, the second doped semiconductor layer located on the side surface of the second semiconductor passivation layer facing away from the semiconductor substrate layer, the second doped semiconductor layer and the second semiconductor passivation layer both being separated from the first semiconductor passivation layer and the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer having opposite conductivity types and being located on the same side of the semiconductor substrate layer; a first transparent conductive film located on the side surface of the first doped semiconductor layer facing away from the semiconductor substrate layer; a second transparent conductive film located on the side surface of the second doped semiconductor layer facing away from the semiconductor substrate layer; a first gate line located on the side surface of the first transparent conductive film facing away from the semiconductor substrate layer; and a second gate line located on the side surface of the second transparent conductive film facing away from the semiconductor substrate layer.

[0024] The technical solution of this application has the following technical effects:

[0025] The technical solution of the present application provides a method for preparing a heterojunction back-contact battery, which performs a first laser ablation treatment on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, and performs a first cleaning treatment after the first laser ablation treatment to form a first opening, and makes the first initial semiconductor passivation layer form the first semiconductor passivation layer on the side of the first opening, and makes the first initial doped semiconductor layer form the first doped semiconductor layer on the side of the first opening, and forms a second semiconductor passivation layer and a second doped semiconductor layer located on the surface of the second semiconductor passivation layer away from the semiconductor substrate layer in the first opening, and the second doped semiconductor layer and the second semiconductor passivation layer are separated from the first semiconductor passivation layer and the first doped semiconductor layer, thereby reducing the lateral electrical crosstalk between the second doped semiconductor layer and the first doped semiconductor layer, and reducing the lateral electrical crosstalk between the second semiconductor passivation layer and the first semiconductor passivation layer, and the first laser ablation treatment has a fast processing speed, high precision, low cost, and low pollution, which can effectively simplify the process, reduce costs, improve the accuracy of patterning, and reduce damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] FIG1 is a flow chart of a heterojunction back contact cell provided by one embodiment of the present application;

[0028] 2 to 11 are structural diagrams of a preparation process of a heterojunction back contact cell provided in one embodiment of the present application.

[0029] Figure symbols: semiconductor substrate layer 100; third semiconductor passivation layer 110; anti-reflection layer 120; first initial semiconductor passivation layer 130; first initial doped semiconductor layer 140; first doped semiconductor layer 140a; initial isolation layer 150; isolation layer 150a; first opening 160; second initial passivation film 170; second additional passivation layer 170a; second semiconductor passivation layer 170b; second initial doped semiconductor film 180; second additional doped layer 180a; second doped semiconductor layer 180b; second opening 190; transparent conductive film 200; first transparent conductive film 200a; second transparent conductive film 200b. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this invention.

[0031] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0034] This embodiment provides a method for preparing a heterojunction back-contact cell, referring to FIG1 , comprising:

[0035] Step S1: providing a semiconductor substrate layer;

[0036] Step S2: forming a first initial semiconductor passivation layer on one side of the semiconductor substrate layer;

[0037] Step S3: forming a first initial doped semiconductor layer on a surface of the first initial semiconductor passivation layer facing away from the semiconductor substrate layer;

[0038] Step S4: performing a first laser ablation process on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, and performing a first cleaning process after the first laser ablation process to form a first opening, and forming the first initial semiconductor passivation layer into a first semiconductor passivation layer located on a side of the first opening, and forming the first initial doped semiconductor layer into a first doped semiconductor layer located on a side of the first opening;

[0039] Step S5: forming a second semiconductor passivation layer and a second doped semiconductor layer located on a surface of the second semiconductor passivation layer facing away from the semiconductor substrate layer in the first opening, wherein the second doped semiconductor layer and the second semiconductor passivation layer are separated from the first semiconductor passivation layer and the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types and are located on the same side of the semiconductor substrate layer;

[0040] Step S6: forming a first transparent conductive film on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer; forming a second transparent conductive film on a surface of the second doped semiconductor layer facing away from the semiconductor substrate layer;

[0041] Step S7: forming a first gate line on a surface of the first transparent conductive film facing away from the semiconductor substrate layer, and forming a second gate line on a surface of the second transparent conductive film facing away from the semiconductor substrate layer.

[0042] In the preparation method of the heterojunction back contact battery of this embodiment, the first laser ablation treatment has a fast processing speed, high precision, low cost and low pollution, which can effectively simplify the process, reduce costs, improve the accuracy of graphics, reduce damage, and facilitate large-scale production.

[0043] The second doped semiconductor layer and the second semiconductor passivation layer are separated from the first semiconductor passivation layer and the first doped semiconductor layer, thereby reducing the lateral electrical crosstalk between the second doped semiconductor layer and the first doped semiconductor layer, and reducing the lateral electrical crosstalk between the second semiconductor passivation layer and the first semiconductor passivation layer.

[0044] 2 to 11 are structural diagrams of a preparation process of a heterojunction back contact cell provided in one embodiment of the present application.

[0045] 2 , a semiconductor substrate layer 100 is provided.

[0046] The semiconductor substrate layer 100 is made of N-type single crystal silicon. In one embodiment, the semiconductor substrate layer 100 has a thickness of 145 micrometers to 155 micrometers, for example, 150 micrometers.

[0047] 4 , a first initial semiconductor passivation layer 130 is formed on one side of the semiconductor substrate layer 100 ; and a first initial doped semiconductor layer 140 is formed on a side of the first initial semiconductor passivation layer 130 facing away from the semiconductor substrate layer 100 .

[0048] The material of the first initial semiconductor passivation layer 130 includes intrinsic hydrogenated amorphous silicon.

[0049] In one embodiment, the thickness of the first initial semiconductor passivation layer is 6 nm-10 nm.

[0050] The conductivity type of the first initially doped semiconductor layer 140 is different from the conductivity type of the semiconductor substrate layer 100. In other embodiments, the conductivity type of the first initially doped semiconductor layer 140 is the same as the conductivity type of the semiconductor substrate layer 100.

[0051] The material of the first initial doped semiconductor layer 140 includes amorphous silicon doped with first conductive ions.

[0052] In one embodiment, the thickness of the first initial doped semiconductor layer 140 is 28 nm to 32 nm, for example, 30 nm.

[0053] In this embodiment, referring to Figure 3, optionally, before forming the first initial semiconductor passivation layer 130 and the first initial doped semiconductor layer 140, it also includes: forming a third semiconductor passivation layer 110 on the other side surface of the semiconductor substrate layer 100; and forming an anti-reflection layer 120 on the side surface of the third semiconductor passivation layer 110 away from the semiconductor substrate layer 100.

[0054] The third semiconductor passivation layer 110 is formed before forming the first initial semiconductor passivation layer 130 and the first initial doped semiconductor layer 140 . The third semiconductor passivation layer 110 can protect the other side surface of the semiconductor substrate layer 100 from being contaminated by subsequent process steps.

[0055] The side of the semiconductor substrate layer 100 facing the third semiconductor passivation layer 110 is the front side, and the side of the semiconductor substrate layer 100 facing the first initial semiconductor passivation layer 140 is the back side. Surface defects on the side of the semiconductor substrate layer 100 facing the third semiconductor passivation layer 110 have a significant impact on the electrical performance of the heterojunction back-contact cell, requiring better protection of the front side of the semiconductor substrate layer 100. Therefore, in this embodiment, the first initial semiconductor passivation layer 130 is formed after the third semiconductor passivation layer 110 is formed. In other embodiments, the third semiconductor passivation layer 110 may be formed after the first initial semiconductor passivation layer 130 is formed.

[0056] The third semiconductor passivation layer 110 is formed by plasma-enhanced chemical vapor deposition (PECVD). The anti-reflection layer 120 is formed by plasma-enhanced chemical vapor deposition (PECVD). In one embodiment, the thickness of the third semiconductor passivation layer 110 is 6 nm to 10 nm, and the thickness of the anti-reflection layer 120 is 80 nm to 100 nm.

[0057] The material of the third semiconductor passivation layer 110 includes intrinsic hydrogenated amorphous silicon.

[0058] The anti-reflection layer 120 is made of silicon nitride.

[0059] In this embodiment, the third semiconductor passivation layer 110 and the anti-reflection layer 120 are formed before forming the first initial semiconductor passivation layer 140. In other embodiments, the third semiconductor passivation layer 110 and the anti-reflection layer 120 may be formed after forming the subsequent first transparent conductive film and the second transparent conductive film.

[0060] In this embodiment, it also includes: before forming the third semiconductor passivation layer 110, the other side surface of the semiconductor substrate layer 100 is textured, so that the other side surface of the semiconductor substrate layer 100 presents an anti-reflection velvet surface; forming the third semiconductor passivation layer 110 on the reflective velvet surface; and forming an anti-reflection layer 120 on the side surface of the third semiconductor passivation layer 110 away from the semiconductor substrate layer 100.

[0061] Before the other side surface of the semiconductor substrate layer 100 is subjected to the texturing treatment and before the first initial semiconductor passivation layer 130 is formed, in the example, before the other side surface of the semiconductor substrate layer 100 is subjected to the texturing treatment and before the first initial semiconductor passivation layer 130 is formed, it also includes: pre-cleaning the semiconductor substrate layer 100; after the pre-cleaning, polishing the surface of the semiconductor substrate layer 100; after the polishing of the surface of the semiconductor substrate layer 100, performing the main cleaning treatment on the surface of the semiconductor substrate layer 100.

[0062] In one embodiment, the texturing process is: etching the other side surface of the semiconductor substrate layer by using a reactive plasma etching process, so that the other side surface of the semiconductor substrate layer 100 presents an anti-reflective textured surface.

[0063] In one embodiment, the parameters of the reactive plasma etching process include: the gases used include SF6, O2 and SiCl4, the flow rate of SF6 is 1120sccm-1600sccm, the flow rate of O2 is 1400sccm-2000sccm, the flow rate of SiCl4 is 700sccm-1000sccm, the chamber pressure is 25 Pa-30 Pa, the temperature is 150°C-200°C, and the etching rate is 10mm / s-18mm / s.

[0064] Because the anti-reflective suede is formed using a reactive plasma etching process, the reflectivity of the anti-reflective suede is less than or equal to 7%. The reflectivity of the anti-reflective suede formed by conventional wet etching is greater than 10%. The reflectivity of the anti-reflective suede in this embodiment is significantly reduced, resulting in better light absorption and optimal short-circuit current.

[0065] 5 , an initial isolation layer 150 is formed on a surface of the first initial doped semiconductor layer 140 facing away from the semiconductor substrate layer 100 .

[0066] The material of the initial isolation layer 150 includes silicon nitride.

[0067] In one embodiment, the thickness of the initial isolation layer 150 is 60 nm-120 nm.

[0068] The process for forming the initial isolation layer includes a plasma enhanced chemical vapor deposition process, and the parameters include: the gases used include SiH4 and NH3, the temperature is 180-200°C, the chamber pressure is 220mtorr-2200mtorr, the deposition time is 1min-2min, the flow rate of SiH4 is 1800ml / min-2300ml / min, and the flow rate of NH3 is 6000ml / min-7000ml / min.

[0069] Referring to Figure 6, a first laser ablation treatment is performed on a portion of the first initial doped semiconductor layer 140 and a portion of the first initial semiconductor passivation layer 130. During the process of performing the first laser ablation treatment on a portion of the first initial doped semiconductor layer 140 and a portion of the first initial semiconductor passivation layer 130, a first laser ablation treatment is also performed on the initial isolation layer 150. After the first laser ablation treatment, a first cleaning treatment is performed to form a first opening 160, and the first initial semiconductor passivation layer 130 is formed into a first semiconductor passivation layer 130a, the first initial doped semiconductor layer 140 is formed into a first doped semiconductor layer 140a, and the initial isolation layer 150 is formed into an isolation layer 150a.

[0070] In one embodiment, the parameters of the first laser ablation process include: the laser used is ultraviolet light or green laser, the pulse width of the laser used is in the picosecond or femtosecond range, and the laser power is 30 W to 50 W. Optionally, the wavelength of the laser used in the first laser ablation process is 355 nm or 532 nm.

[0071] In one embodiment, the parameters of the first cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is a KOH solution or a NaOH solution, and the cleaning time is 100 seconds to 130 seconds; or, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

[0072] The preparation method of the heterojunction back contact battery also includes: in the process of forming the second semiconductor passivation layer and the second doped semiconductor layer, forming a second additional passivation layer and a second additional doped layer on the surface of a side of the isolation layer away from the semiconductor substrate layer, the material of the second additional passivation layer is the same as the material of the second semiconductor passivation layer, the material of the second additional doped layer is the same as the material of the second doped semiconductor layer, the second additional doped layer is located on the surface of the side of the second additional passivation layer away from the semiconductor substrate layer, and a second opening is formed in the isolation layer, and the second opening exposes the first doped semiconductor layer.

[0073] The steps of forming the second semiconductor passivation layer, the second doped semiconductor layer, the second additional passivation layer, and the second additional doped layer include: sequentially forming a second initial passivation film and a second initial doped semiconductor film in the first opening and on the side of the isolation layer facing away from the semiconductor substrate layer; performing a second laser ablation process and a second cleaning process on a portion of the isolation layer and a portion of the second initial passivation film and the second initial doped semiconductor film on the side of the isolation layer facing away from the semiconductor substrate layer, so that the second initial passivation film on the side of the isolation layer facing away from the semiconductor substrate layer forms the second additional passivation layer, and the second initial doped semiconductor film on the side of the isolation layer facing away from the semiconductor substrate layer forms the second additional doped layer, and forming a second opening in the isolation layer. Sequentially performing a third laser ablation process and a third cleaning process on the second initial passivation film and the second initial doped semiconductor film in the first opening and at the interface between the first semiconductor passivation layer and the first doped semiconductor layer, so that the second initial passivation film in the first opening forms the second semiconductor passivation layer, and the second initial doped semiconductor film in the first opening forms the second doped semiconductor layer.

[0074] The steps of forming the first transparent conductive film and the second transparent conductive film include: after performing the second cleaning treatment and before performing the third laser ablation treatment, forming a transparent conductive film on the surface of the first doped semiconductor layer on the side facing away from the semiconductor substrate layer and the surface of the second initial doped semiconductor film on the side facing away from the semiconductor substrate layer; in the step of performing the third laser ablation treatment, the third laser ablation treatment also removes part of the transparent conductive film, so that the transparent conductive film forms the first transparent conductive film and the second transparent conductive film, and the first transparent conductive film and the second transparent conductive film are separated.

[0075] 7 , a second initial passivation film 170 and a second initial doped semiconductor film 180 are sequentially formed in the first opening 160 and on a side of the isolation layer 150 a facing away from the semiconductor substrate layer 100 .

[0076] It should be noted that the second initial passivation film 170 is conformally deposited, and the second initial doped semiconductor film 180 is conformally deposited, that is, the second initial passivation film 170 in the first opening 160 and the second initial passivation film 170 on the side of the isolation layer 150a away from the semiconductor substrate layer 100 are connected together, and the second initial doped semiconductor film 180 in the first opening 160 and the second initial doped semiconductor film 180 on the side of the isolation layer 150a away from the semiconductor substrate layer 100 are connected together.

[0077] The second preliminary passivation film 170 is made of intrinsic hydrogenated silicon. In one embodiment, the second preliminary passivation film 170 has a thickness of 6 nm to 10 nm.

[0078] The material of the second initially doped semiconductor film 180 includes amorphous silicon doped with second conductive ions. The second conductive ions and the first conductive ions have different conductivity types.

[0079] In one embodiment, the second initially doped semiconductor film 180 has a thickness of 28 nm to 32 nm, for example, 30 nm.

[0080] Referring to Figure 8, a second laser ablation treatment and a second cleaning treatment are performed on a portion of the isolation layer 150a and the second initial passivation film 170 and the second initial doped semiconductor film 180 on the side of the isolation layer 150a away from the semiconductor substrate layer 100, so that the second initial passivation film 170 on the side of the isolation layer 150a away from the semiconductor substrate layer 100 forms a second additional passivation layer 170a, and the second initial doped semiconductor film 180 on the side of the isolation layer 150a away from the semiconductor substrate layer 100 forms a second additional doped layer 180a, and a second opening 190 is formed in the isolation layer 150a.

[0081] In one embodiment, the parameters of the second laser ablation treatment include: the laser used is ultraviolet light or green laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W; optionally, the wavelength of the laser used in the second laser ablation treatment is 355nm or 532nm.

[0082] In one embodiment, the parameters of the second cleaning process include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

[0083] Referring to Figure 9, after the second cleaning treatment and before the third laser ablation treatment, a transparent conductive film 200 is formed on the side surface of the first doped semiconductor layer 140a facing away from the semiconductor substrate layer 100 and on the side surface of the second initial doped semiconductor film 180 in the first opening 160 facing away from the semiconductor substrate layer 100.

[0084] The transparent conductive film 200 is made of indium tin oxide. In one embodiment, the transparent conductive film 200 has a thickness of 70 nm to 100 nm.

[0085] 10 and 11 , FIG10 is a schematic diagram based on FIG9 , and FIG11 is a top view of FIG10 . A third laser ablation treatment and a third cleaning treatment are sequentially performed on the second initial passivation film 170 and the second initial doped semiconductor film 180 in the first opening at the junction of the first semiconductor passivation layer 130 a and the first doped semiconductor layer 140 a, so that the second initial passivation film 170 in the first opening 160 forms the second semiconductor passivation layer 170 b, and the second initial doped semiconductor film 180 in the first opening 160 forms the second doped semiconductor layer 180 b. In the step of performing the third laser ablation treatment, the third laser ablation treatment also removes the junction area between the transparent conductive film 200 in the first opening 160 and the first semiconductor passivation layer 130 a and the first doped semiconductor layer 140 a, so that the transparent conductive film 200 forms the first transparent conductive film 200 a and the second transparent conductive film 200 b, and the first transparent conductive film 200 a and the second transparent conductive film 200 b are separated.

[0086] The parameters of the third laser ablation process include: the laser used is a green laser, and the pulse width of the laser used is in the nanosecond level; optionally, the wavelength of the laser used in the third laser ablation process is 532 nm.

[0087] The parameters of the third cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is a KOH solution or a NaOH solution, and the cleaning time is 100 seconds to 130 seconds; or the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

[0088] The preparation method of the heterojunction back-contact battery of this embodiment uses laser ablation to form the front connecting grid lines and the back connecting grid lines on the back side, so that the patterning accuracy of the grid lines is improved and the aspect ratio is optimized.

[0089] In this embodiment, the first gate line is formed on a surface of the first transparent conductive film 200 a facing away from the semiconductor substrate layer 100 , and the second gate line is formed on a surface of the second transparent conductive film 200 b facing away from the semiconductor substrate layer 100 .

[0090] In one embodiment, the second transparent conductive film 200 b and the first transparent conductive film 200 a are arranged in parallel and in an alternating manner.

[0091] The first doped semiconductor layer 140a and the second doped semiconductor layer 180b have opposite conductivity types. When the conductivity type of the first doped semiconductor layer 140a is opposite to that of the semiconductor substrate layer 100, the first doped semiconductor layer 140a and the semiconductor substrate layer 100 form a PN junction. When the conductivity type of the second doped semiconductor layer 180b is opposite to that of the semiconductor substrate layer 100, the second doped semiconductor layer 180b and the semiconductor substrate layer 100 form a PN junction. The side of the semiconductor substrate layer 100 facing the third semiconductor passivation layer 110 is the front side. Light is irradiated into the semiconductor substrate layer 100 through the anti-reflection layer 120 and the third semiconductor passivation layer 110. The anti-reflection layer 120 reduces the reflectivity and increases the transmittance of light. Light irradiation at the PN junction generates photogenerated carriers. The third semiconductor passivation layer 110 is located on the front side, providing a field barrier to prevent minority carriers from migrating toward the front side. The first transparent conductive film 200a and the second transparent conductive film 200b collect the photogenerated carriers.

[0092] The present application also provides a heterojunction back-contact cell formed using the above-mentioned method for preparing a heterojunction back-contact cell. Referring to Figures 10 and 11 , the cell comprises: a semiconductor substrate layer 100; a first semiconductor passivation layer 130a located on one side of the semiconductor substrate 100, and a first doped semiconductor layer 140a located on a side of the first semiconductor passivation layer 130a facing away from the semiconductor substrate 100; a first opening 160 extending through the first doped semiconductor layer 140a and the first semiconductor passivation layer 130a; a second semiconductor passivation layer 170b and a second doped semiconductor layer 180b located in the first opening 160, the second doped semiconductor layer 180b located on a side of the second semiconductor passivation layer 170b facing away from the semiconductor substrate 100, and both the second doped semiconductor layer 180b and the second semiconductor passivation layer 170b being separated from the first semiconductor passivation layer 130a and the first doped semiconductor layer 140a. The second doped semiconductor layer 180b and the first doped semiconductor layer 140a have opposite conductivity types and are located on the same side of the semiconductor substrate.

[0093] The second doped semiconductor layer 180b and the second semiconductor passivation layer 170b are separated from the first semiconductor passivation layer 130a and the first doped semiconductor layer 140a, which means that the second doped semiconductor layer 180b and the second semiconductor passivation layer 170b are separated from the first semiconductor passivation layer 130a, and the second doped semiconductor layer 180b and the second semiconductor passivation layer 170b are separated from the first doped semiconductor layer 140a.

[0094] In this embodiment, the present invention further includes: a first transparent conductive film 200a and a second transparent conductive film 200b. The first transparent conductive film 200a is located on a surface of the first doped semiconductor layer 140a facing away from the semiconductor substrate layer 100, and the second transparent conductive film 200b is located on a surface of the second doped semiconductor layer 180b facing away from the semiconductor substrate layer 100. The first transparent conductive film 200a and the second transparent conductive film 200b are separated.

[0095] This embodiment further includes: an isolation layer 150a, located on a surface of a portion of the first doped semiconductor layer 140a facing away from the semiconductor substrate layer 100; a second additional passivation layer 170a, located on a surface of the isolation layer 150a facing away from the semiconductor substrate layer 100; and a second additional doped layer 180a, located on a surface of the second additional passivation layer 170a facing away from the semiconductor substrate layer 100. The isolation layer 150a has a second opening 190 (see FIG. 8 ), and the first transparent conductive film 200a is located in the second opening 190.

[0096] In this embodiment, the first gate line is formed on the surface of the first transparent conductive film 200 a facing away from the semiconductor substrate layer 100 , and the second gate line is formed on the surface of the second transparent conductive film 200 b facing away from the semiconductor substrate layer 100 .

[0097] In this embodiment, the present invention further includes: a third semiconductor passivation layer 110 located on a surface of the semiconductor substrate layer 100 facing away from the first semiconductor passivation layer 130 a ; and an anti-reflection layer 120 located on a surface of the third semiconductor passivation layer 110 facing away from the semiconductor substrate layer 100 .

[0098] Taking the semiconductor substrate layer 100 as an N-type substrate as an example, since the first doped semiconductor layer 140a and the second doped semiconductor layer 180b have opposite conductivity types, when the first doped semiconductor layer 140a is doped with a P-type, the second doped semiconductor layer 180b is doped with an N-type. The first doped semiconductor layer 140a and the semiconductor substrate layer 100 form a PN junction, causing electrons of photogenerated carriers to migrate into the semiconductor substrate layer 100, while holes migrate into the first doped semiconductor layer 140a. The doping concentration of the second doped layer 180b is much higher than that of the semiconductor substrate layer 100, forming a built-in electric field between the second doped semiconductor layer 180b and the semiconductor substrate layer 100, causing electrons of photogenerated carriers to migrate into the second doped semiconductor layer 180b, while holes migrate into the semiconductor substrate 100. Therefore, when light is applied to generate carriers, electrons migrate to the second doped semiconductor layer 180b, which serves as the battery's negative electrode, while holes migrate to the first doped semiconductor layer 140a, which serves as the battery's positive electrode. Similarly, if the first doped semiconductor layer 140a is N-type doped and the second doped semiconductor layer 180b is P-type doped, then the first doped semiconductor layer 140a serves as the battery's negative electrode, and the second doped semiconductor layer 180b serves as the battery's positive electrode.

[0099] The side of the semiconductor substrate layer 100 facing the third semiconductor passivation layer 110 is the front side. Light passes through the anti-reflection layer 120 and the third semiconductor passivation layer 110 and enters the semiconductor substrate layer 100. The anti-reflection layer 120 reduces the reflectivity of light and increases its transmittance. The third semiconductor passivation layer 110 is located on the front side, and the field barrier prevents minority carriers from migrating toward the front side. The first transparent conductive film 200a and the second transparent conductive film 200b collect photogenerated carriers. The first transparent conductive film 200a and the second transparent conductive film 200b collect photogenerated carriers of different electrical properties.

[0100] Since there is no grid line blocking the front of the heterojunction back-contact battery, the light is strong and the area is fully utilized, and the battery conversion efficiency is high; although the first grid line and the second grid line are set on the back of the heterojunction back-contact battery, the light on the back is not as direct as the front (including reflection, etc.), so it has little effect on optical loss.

[0101] In general, heterojunction back contact cells can reduce optical losses. In addition, the second doped semiconductor layer and the second semiconductor passivation layer are separated from the first semiconductor passivation layer and the first doped semiconductor layer, thereby reducing the lateral electrical crosstalk between the second doped semiconductor layer and the first doped semiconductor layer; and, the electrode grid lines are printed on the back, and there is no need to consider the shading area factor, and there are no special requirements for the grid line width (wide grid lines can be designed), so the resistance loss is small, which can reduce the resistance loss. In summary, the heterojunction back contact cell can reduce optical loss and resistance loss to a certain extent due to the improved graphic accuracy of the grid lines and the optimized aspect ratio, which can improve Jsc and FF. Jsc can be increased by more than 6% compared with conventional HJT cells, and the efficiency is increased by more than 1.5%.

[0102] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A method for preparing a heterojunction back contact battery, characterized in that: include: providing a semiconductor substrate layer; Forming a first initial semiconductor passivation layer on a surface of one side of the semiconductor substrate layer; forming a first initial doped semiconductor layer on a surface of the first initial semiconductor passivation layer facing away from the semiconductor substrate layer; Performing a first laser ablation process on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, and performing a first cleaning process after the first laser ablation process to form a first opening, and to form the first initial semiconductor passivation layer into a first semiconductor passivation layer located at a side of the first opening, and to form the first initial doped semiconductor layer into a first doped semiconductor layer located at a side of the first opening; A second semiconductor passivation layer and a second doped semiconductor layer located on a surface of the second semiconductor passivation layer facing away from the semiconductor substrate layer are formed in the first opening, the second doped semiconductor layer and the second semiconductor passivation layer are both separated from the first semiconductor passivation layer and the first doped semiconductor layer, the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types and are located on the same side of the semiconductor substrate layer; forming a first transparent conductive film on a surface of the first doped semiconductor layer away from the semiconductor substrate layer; forming a second transparent conductive film on a surface of the second doped semiconductor layer away from the semiconductor substrate layer; A first gate line is formed on a surface of the first transparent conductive film on a side away from the semiconductor substrate layer, and a second gate line is formed on a surface of the second transparent conductive film on a side away from the semiconductor substrate layer.

2. The method for preparing a heterojunction back contact battery according to claim 1, characterized in that: The parameters of the first laser ablation process include: the laser used is ultraviolet light or green laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W; Preferably, the wavelength of the laser used is 355 nm or 532 nm.

3. The method for preparing a heterojunction back contact battery according to claim 1, characterized in that: The parameters of the first cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is a KOH solution or a NaOH solution, and the cleaning time is 100 seconds to 130 seconds; Alternatively, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

4. The method for preparing a heterojunction back contact battery according to claim 1, characterized in that: Also includes: Before performing a first laser ablation process on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, forming an initial isolation layer on a surface of the first initial doped semiconductor layer facing away from the semiconductor substrate layer; In the process of performing the first laser ablation treatment on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, the initial isolation layer is also subjected to the first laser ablation treatment, so that the initial isolation layer forms an isolation layer; The preparation method of the heterojunction back contact battery also includes: in the process of forming a second semiconductor passivation layer and a second doped semiconductor layer, forming a second additional passivation layer and a second additional doped layer on the surface of a side of the isolation layer away from the semiconductor substrate layer, the material of the second additional passivation layer is the same as the material of the second semiconductor passivation layer, the material of the second additional doped layer is the same as the material of the second doped semiconductor layer, the second additional doped layer is located on the surface of the side of the second additional passivation layer away from the semiconductor substrate layer, and a second opening is formed in the isolation layer, and the second opening exposes the first doped semiconductor layer.

5. The method for preparing a heterojunction back contact battery according to claim 4, characterized in that: The steps of forming the second semiconductor passivation layer and the second doped semiconductor layer, the second additional passivation layer and the second additional doped layer include: sequentially forming a second initial passivation film and a second initial doped semiconductor film in the first opening and on the side of the isolation layer away from the semiconductor substrate layer; performing a second laser ablation process and a second cleaning process on a part of the isolation layer and a part of the second initial passivation film and the second initial doped semiconductor film on the side of the isolation layer away from the semiconductor substrate layer, so that the second initial passivation film on the side of the isolation layer away from the semiconductor substrate layer forms a second additional passivation layer, and the second initial doped semiconductor film on the side of the isolation layer away from the semiconductor substrate layer forms a second additional doped layer, and forming a second opening in the isolation layer; The second initial passivation film and the second initial doped semiconductor film in the first opening are subjected to a third laser ablation treatment and a third cleaning treatment in sequence at the junction of the first semiconductor passivation layer and the first doped semiconductor layer, so that the second initial passivation film in the first opening forms the second semiconductor passivation layer, and the second initial doped semiconductor film in the first opening forms the second doped semiconductor layer.

6. The method for preparing a heterojunction back contact battery according to claim 5, characterized in that: The parameters of the second laser ablation process include: the laser used is ultraviolet light or green light laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W; preferably, the wavelength of the laser used is 355nm or 532nm; Preferably, the parameters of the second cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

7. The method for preparing a heterojunction back contact battery according to claim 5, characterized in that: The parameters of the third laser ablation process include: the laser used is a green laser, the pulse width of the laser used is in the nanosecond level; preferably, the wavelength of the laser used is 532nm; Preferably, the parameters of the third cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is a KOH solution or a NaOH solution, and the cleaning time is 100 seconds to 130 seconds; Alternatively, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

8. The method for preparing a heterojunction back contact cell according to any one of claims 1 to 4, characterized in that: Also includes: Performing a texturing treatment on the other side surface of the semiconductor substrate layer to form an anti-reflection texturing surface; forming a third semiconductor passivation layer on the reflective velvet surface; An anti-reflection layer is formed on a surface of the third semiconductor passivation layer facing away from the semiconductor substrate layer.

9. The method for preparing a heterojunction back contact cell according to claim 8, characterized in that: The steps of forming the first transparent conductive film and the second transparent conductive film include: after performing a second cleaning treatment and before performing a third laser ablation treatment, forming a transparent conductive film on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer and a surface of the second initial doped semiconductor film facing away from the semiconductor substrate layer; in the step of performing the third laser ablation treatment, the third laser ablation treatment also removes the boundary area between the transparent conductive film in the first opening and the first semiconductor passivation layer and the first doped semiconductor layer, so that the transparent conductive film forms the first transparent conductive film and the second transparent conductive film.

10. A heterojunction back contact battery, characterized in that: include: Semiconductor substrate layer; A first semiconductor passivation layer located on a surface of one side of the semiconductor substrate layer, and a first doped semiconductor layer located on a surface of the first semiconductor passivation layer facing away from the semiconductor substrate layer; a first opening, penetrating the first doped semiconductor layer and the first semiconductor passivation layer; a second semiconductor passivation layer and a second doped semiconductor layer located in the first opening, wherein the second doped semiconductor layer is located on a surface of the second semiconductor passivation layer facing away from the semiconductor substrate layer, and the second doped semiconductor layer and the second semiconductor passivation layer are both separated from the first semiconductor passivation layer and the first doped semiconductor layer; The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types and are located on the same side of the semiconductor substrate layer; A first transparent conductive film located on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer; A second transparent conductive film located on a surface of the second doped semiconductor layer on a side away from the semiconductor substrate layer; A first gate line located on a surface of the first transparent conductive film on a side away from the semiconductor substrate layer; A second gate line is located on a surface of the second transparent conductive film on a side away from the semiconductor substrate layer.

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