Computer, information processing device, server, and storage device

Abstract

Provided is an information processing device with reduced power consumption. This information processing device has first to third layers. The first layer has a processor, the second layer has a first memory cell, and the third layer has a second memory cell. The first memory cell is composed of a first transistor and a second transistor. The second transistor has a gate connected to the source or drain of the first transistor. The second memory cell is composed of a third transistor, a fourth transistor, and a capacitor. The fourth transistor has a gate connected to the source or drain of the third transistor and one electrode of the capacitor. The first to fourth transistors are vertical transistors, in which the source and the drain are positioned at different heights and which each have an oxide semiconductor for a channel The second layer is located between the first layer and the third layer.

Description

Computer, information processing device, server, and storage device

[0001] One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a memory device. One embodiment of the present invention relates to an arithmetic processing unit. One embodiment of the present invention relates to a semiconductor device including a memory device and an arithmetic processing unit. One embodiment of the present invention relates to a computer, an information processing device, and a server.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] Various computers, such as smartphones, tablet devices, personal computers, and servers, incorporate various processors, such as a central processing unit (CPU) and a graphics processing unit (GPU), as well as memory devices. There are various types of memory devices, such as static random access memory (SRAM), dynamic random access memory (DRAM), and NAND memory, which are suitable for high-speed operation and can easily be increased in capacity. In many cases, computers incorporate multiple types of memory devices.

[0004] Furthermore, a transistor having an oxide semiconductor or a metal oxide in a channel formation region thereof (also referred to as an oxide semiconductor transistor or an OS (oxide semiconductor) transistor) is known. An OS transistor has a characteristic that its drain current (also referred to as an off-state current) is extremely small when the transistor is in an off state. Patent Document 1 discloses a nonvolatile memory device including an OS transistor. Patent Document 2 discloses a memory device including a vertical OS transistor.

[0005] JP 2011-109079 A JP 2013-211537 A

[0006] DRAM, one of the memory devices used in many computers, stores information by storing electrical charge input via transistors in capacitors. When DRAM reads information, the charge in the capacitor is lost, so the data must be rewritten each time it is read. Furthermore, due to leakage current from transistors, the data retention period is short, requiring repeated write operations (refresh operations) at predetermined intervals, which requires a large amount of power just to retain the data. DRAM is also used in large-scale AI servers, so its power consumption worldwide may be at a level that has an impact on global warming.

[0007] An object of one embodiment of the present invention is to provide a memory device, an arithmetic processing device, a semiconductor device, or a data processing device with reduced power consumption.An object of one embodiment of the present invention is to provide a memory device that can be highly integrated, or an arithmetic processing device, a semiconductor device, or a data processing device including the memory device.An object of one embodiment of the present invention is to provide a memory device, an arithmetic processing device, a semiconductor device, or a data processing device that generates low heat.

[0008] An object of one embodiment of the present invention is to provide a highly reliable storage device, an arithmetic processing device, a semiconductor device, or a data processing device.An object of one embodiment of the present invention is to provide a storage device, an arithmetic processing device, a semiconductor device, or a data processing device having a novel structure.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One embodiment of the present invention is a data processing device having first to third layers. The first layer has a processor, the second layer has a first memory cell, and the third layer has a second memory cell. The first memory cell includes a first transistor and a second transistor. The second transistor has a gate connected to one of the source and drain of the first transistor. The second memory cell includes a third transistor, a fourth transistor, and a capacitor. The fourth transistor has a gate connected to one of the source and drain of the third transistor and one electrode of the capacitor. The first to fourth transistors each include an oxide semiconductor in a channel, and are vertical transistors whose source and drain are located at different heights. The second layer is located between the first layer and the third layer.

[0011] In the above, it is preferable that the second layer is located on the first layer, and the third layer is located on the second layer.

[0012] Alternatively, in the above, it is preferable that the first layer is located on the second layer, and the second layer is located on the third layer.

[0013] Another embodiment of the present invention is a data processing device having first to fifth layers. The first layer includes a first processor, the second layer includes a first memory cell, the third layer includes a second memory cell, the fourth layer includes a second processor, and the fifth layer includes a NAND memory. The first memory cell includes a first transistor and a second transistor. The second transistor has a gate connected to one of the source and drain of the first transistor. The second memory cell includes a third transistor, a fourth transistor, and a capacitor. The fourth transistor has a gate connected to one of the source and drain of the third transistor and one electrode of the capacitor. The first to fourth transistors each include an oxide semiconductor in a channel, and are vertical transistors whose source and drain are located at different heights. The second layer is located between the first layer and the fifth layer and between the fourth layer and the fifth layer. The third layer is located between the second layer and the fifth layer.

[0014] In the above, it is preferable that the first processor is a CPU and the second processor is a GPU.

[0015] Another embodiment of the present invention is any one of the above information processing devices, which does not include a DRAM.

[0016] Another embodiment of the present invention is a computer including a housing in which the above-described information processing device is mounted and a display unit.

[0017] Another aspect of the present invention is a server having a motherboard on which the above-described information processing device is mounted, and a rack for storing the motherboard.

[0018] Another embodiment of the present invention includes a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, the third insulating layer, and a first oxide semiconductor layer. The second transistor includes a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, the fourth insulating layer, the fifth insulating layer, and the second oxide semiconductor layer. The capacitor includes the third conductive layer, the sixth insulating layer, and the fourth conductive layer. The first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is located over the first insulating layer. The first oxide semiconductor layer is in contact with a top surface of the second conductive layer and is in contact with the first conductive layer through the first opening. The third insulating layer is located over the first opening. the sixth insulating layer is located inside the first oxide semiconductor layer in the first opening, the third conductive layer is located inside the third insulating layer in the first opening, the sixth insulating layer is located on the third conductive layer, the fourth conductive layer is located on the sixth insulating layer, the second insulating layer is located on the fourth conductive layer, the sixth insulating layer, the fourth conductive layer, and the second insulating layer have a second opening reaching the third conductive layer, the fifth conductive layer is located on the second insulating layer, and the fourth insulating layer is in contact with at least the fourth conductive layer in the second opening, the second oxide semiconductor layer is in contact with an upper surface of the fifth conductive layer and is in contact with the third conductive layer through the second opening, the fifth insulating layer is located inside the second oxide semiconductor layer in the second opening, and the sixth conductive layer is located inside the fifth insulating layer in the second opening.

[0019] In addition, in the above, it is preferable that the shortest distance between the upper surface of the third conductive layer and the lower surface of the fourth conductive layer is shorter than the shortest distance between the upper surface of the fourth conductive layer and the lower surface of the fifth conductive layer.

[0020] In the above, it is preferable that the first conductive layer has a first recess, the first opening overlaps with the first recess, and the first oxide semiconductor layer be in contact with a bottom surface and a side surface of the first recess.

[0021] In the above, it is preferable that the third conductive layer has a second recess, the second opening overlaps with the second recess, and the second oxide semiconductor layer be in contact with a bottom surface and a side surface of the second recess.

[0022] In the above, it is preferable that the first opening and the second opening are circular in plan view.

[0023] In the above, it is preferable that the first opening and the second opening have centers at different positions in a plan view.

[0024] According to one embodiment of the present invention, a memory device, an arithmetic processing device, a semiconductor device, or an information processing device with reduced power consumption can be provided. According to one embodiment of the present invention, a memory device that can be highly integrated, or an arithmetic processing device, a semiconductor device, or an information processing device including the memory device can be provided. According to one embodiment of the present invention, a memory device, an arithmetic processing device, a semiconductor device, or an information processing device that generates low heat can be provided.

[0025] According to one aspect of the present invention, a highly reliable storage device, an arithmetic processing device, a semiconductor device, or an information processing device can be provided. Alternatively, a storage device, an arithmetic processing device, a semiconductor device, or an information processing device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be at least alleviated.

[0026] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0027] FIGS. 1A and 1B are configuration examples of a semiconductor device. FIGS. 2A and 2B are configuration examples of a semiconductor device. FIGS. 3A and 3B are diagrams illustrating the hierarchy of a memory device in a semiconductor device. FIGS. 4A to 4C are diagrams illustrating the hierarchy of a memory device in a semiconductor device. FIG. 5A is a configuration example of an arithmetic processing unit, and FIG. 5B is a configuration example of a GPU. FIGS. 6A and 6B are configuration examples of a memory device. FIGS. 7A and 7B are configuration examples of a memory device. FIGS. 8A to 8E are configuration examples of a memory device. FIGS. 9A and 9B are circuit diagrams illustrating an example of a memory device. FIGS. 9C and 9D are plan views illustrating an example of a memory device. FIG. 10 is a cross-sectional view illustrating an example of a memory device. FIG. 11 is a cross-sectional view illustrating an example of a memory device. FIG. 12 is a cross-sectional view illustrating an example of a memory device. FIG. 13 is a cross-sectional view illustrating an example of a memory device. FIG. 14 is a cross-sectional view illustrating an example of a memory device. FIG. 15 is a cross-sectional view illustrating an example of a memory device. FIG. 16 is a cross-sectional view illustrating an example of a memory device. FIGS. 17A to 17C are plan views illustrating an example of a memory device. FIG. 18 is a cross-sectional view showing an example of a memory device. FIG. 19 is a cross-sectional view showing an example of a memory device. FIG. 20 is a cross-sectional view showing an example of a memory device. FIGS. 21A to 21C are cross-sectional views showing an example of a memory device. FIG. 22 is a cross-sectional view showing an example of a memory device. FIG. 23 is a cross-sectional view showing an example of a memory device. FIG. 24 is a cross-sectional view showing an example of a memory device. FIG. 25 is a cross-sectional view showing an example of a memory device. FIG. 26 is a cross-sectional view showing an example of a memory device. FIG. 27 is a cross-sectional view showing an example of a memory device. FIG. 28 is a block diagram illustrating a configuration example of a memory device. FIGS. 29A to 29D are cross-sectional views illustrating a method for forming a metal oxide film. FIGS. 30A to 30D are cross-sectional views illustrating a method for forming a metal oxide film. FIGS. 31A to 31J show configuration examples of electronic devices. FIGS. 32A to 32H show configuration examples of electronic devices.

[0028] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0030] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0031] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0032] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0033] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0034] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0035] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0036] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0037] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0038] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0039] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0040] Embodiment 1 In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention includes a processor and a memory device. The semiconductor device according to one embodiment of the present invention can hold data and process the data (arithmetic processing). Therefore, one embodiment of the present invention can also be referred to as an arithmetic processing device or a data processing device. In this specification and the like, the term "semiconductor device" can be substituted for the term "arithmetic processing device" or "data processing device" unless otherwise specified.

[0041] A memory device referred to as a NOSRAM described below is used as the semiconductor device of one embodiment of the present invention. Therefore, the semiconductor device of one embodiment of the present invention can also be called a device using a NOSRAM.

[0042] Fig. 1A is a schematic perspective view of a semiconductor device 10 according to one embodiment of the present invention. Fig. 1B is a schematic perspective view showing each layer of the semiconductor device 10 in isolation. The semiconductor device 10 has a stacked structure in which five layers are stacked. The semiconductor device 10 has a configuration in which a layer 11, a layer 12, a layer 13, a layer 14, and a layer 15 are stacked in this order.

[0043] Layer 11 and layer 12 each have a processor. Here, layer 11 is a layer having a GPU, and layer 12 is a layer having a CPU. Note that when the CPU and GPU are formed side by side on the same plane, layers 11 and 12 may be combined into one layer. Furthermore, the stacking order of layers 11 and 12 is not limited to this, and layer 11 having a GPU may be stacked on layer 12 having a CPU.

[0044] Layer 13 is a layer having a memory array. The memory array of layer 13 has a plurality of memory cells 20 arranged in a matrix. The memory cells 20 may be stacked not only in the in-plane direction of the layer but also in the thickness direction of the layer, and may be arranged in a three-dimensional matrix.

[0045] 1B, the memory cell 20 is composed of two transistors, with the gate of one transistor connected to either the source or the drain of the other transistor.

[0046] Like layer 13, layer 14 is a layer having a memory array. The memory array of layer 14 has a plurality of memory cells 30. Like memory cells 20, memory cells 30 may be stacked not only in the in-plane direction of the layer but also in the thickness direction of the layer, and may be arranged in a three-dimensional matrix.

[0047] 1B, the memory cell 30 includes two transistors and one capacitor (also referred to as a capacitor element). The memory cell 30 has a configuration in which the gate of one transistor is connected to one of the source and drain of the other transistor and one electrode of the capacitor. In addition, FIG. 1B shows an example in which the other transistor has a back gate (second gate) that is connected to the other electrode of the capacitor.

[0048] The memory cell 20 provided in the layer 13 and the memory cell 30 provided in the layer 14 have a common connection relationship between the two transistors. That is, the gate of one of the two transistors is connected to either the source or the drain of the other transistor. A memory having such a configuration, in which an oxide semiconductor is used for the channel of at least one of the transistors, can be called a nonvolatile oxide semiconductor random access memory (NOSRAM). Unlike a dynamic random access memory (DRAM), one of the features of an NOSRAM is that it is capable of nondestructive readout.

[0049] The main difference between memory cells 20 and 30 is whether they have capacity or not. Memory cells 20 without capacity can increase the drive speed (particularly the data write speed), and therefore can be suitably used as a memory region with a high access frequency. On the other hand, memory cells 30 with capacity are inferior to memory cells 20 in drive speed, but can hold data for a longer period, and therefore can be suitably used as a memory region with a lower access frequency than memory cells 20.

[0050] In this way, by arranging layer 13 having memory cells 20 with a fast driving speed close to layers 11 and 12 having processors, and arranging layer 14 having memory cells 30 with a long data retention period further away, it is possible to realize a semiconductor device capable of faster information processing.

[0051] Layer 15 includes a memory array in which multiple memory strings 40 are arranged. As shown in FIG. 1B, each memory string 40 includes multiple cell transistors connected in series. Each cell transistor can hold one or more bits of data. Examples of cell transistors include transistors with charge storage layers, transistors with ferroelectric layers, and transistors with floating gates.

[0052] The memory string 40 in the layer 15 is a so-called nonvolatile memory with an extremely long data retention period. Because the layer 15 has a structure that is easily integrated three-dimensionally, it can be used as a storage device with an extremely large data capacity. However, the write and read speeds of the layer 15 are slower than those of the memory cells 20 and 30. Therefore, the layer 15 can be suitably used as a memory region that is accessed even less frequently than the layer 14.

[0053] In this way, layers having memories with faster drive speeds are arranged closer to layers 11 and 12 having processors, and layers having memories with longer data retention periods are arranged further away from layers 11 and 12. Furthermore, by stacking all of the layers rather than arranging them side by side on a plane, it becomes possible to extremely shorten the wiring length, which not only significantly improves access speed but also makes it possible to drastically reduce power consumption, heat generation, etc. By using such a configuration, it is possible to realize a semiconductor device with extremely low power consumption and high performance.

[0054] The bonding method for each layer can be wire bonding using gold or copper wiring, flip-chip bonding using bumps, or direct bonding (hybrid bonding) using a direct bonding technique such as Cu-Cu bonding. Alternatively, a method can be used in which two or more layers are bonded together with insulating films and then through-electrodes are formed to connect the electrodes provided on each layer. In particular, using a method using direct bonding or through-electrodes allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at high density, which is preferable because it increases the amount of data transmitted between layers.

[0055] When bonding two layers, any of CoC (chip-on-chip) bonding, CoW (chip-on-wafer) bonding, and WoW (wafer-on-wafer) bonding may be used. WoW bonding is superior in productivity because wafers are bonded together, but since all chips, including both good and bad, are bonded together, the yield may be reduced. On the other hand, CoW bonding, which bonds a chip to a wafer, and CoC bonding, which bonds chips together, are inferior to WoW bonding in terms of productivity, but the yield is significantly improved because good chips can be bonded together. Furthermore, CoC bonding is inferior in productivity to the other two, but is superior in versatility because it can bond two layers even when the sizes of the two layers are significantly different.

[0056] A wiring layer such as an interposer may be provided between the two layers, which eliminates the need to align the positions of bonding electrodes between two adjacent layers, increasing the degree of freedom in designing each layer and enabling the realization of a semiconductor device with higher performance.

[0057] 2A and 2B is an example in which the stacking order of the layers in the semiconductor device 10 is reversed. In the semiconductor device 10A, layers 15, 14, 13, 12, and 11 are stacked in this order.

[0058] Here, the hierarchy of a memory device applied to a semiconductor device will be described. Figure 3A shows the hierarchy of a conventional memory device.

[0059] In Figure 3A, the closer a device is to the processor (CPU / GPU), the higher the access frequency, and the longer the base of the triangle, the larger the data capacity. The closer a storage device is to the processor, the faster the operating speed is required, while the farther away a storage device is, the larger the storage capacity and recording density are required. Figure 3A shows an example in which a register is used as a memory integrated into a processor such as a CPU or GPU, and SRAM is used as cache memory, DRAM is used as main memory, and NAND memory and HDD (Hard Disk Drive) are used as storage.

[0060] The memory embedded in processors such as CPUs and GPUs is used for temporary storage of calculation results, and is therefore frequently accessed by the arithmetic processing unit. Therefore, faster operating speed is required rather than storage capacity. Registers also have the function of storing setting information for the arithmetic processing unit.

[0061] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate faster than main memory. In addition, data rewritten in the cache is duplicated and supplied to main memory.

[0062] The main memory has a function of holding programs, data, etc. read from the storage.

[0063] Storage has the function of storing data that requires long-term storage, various programs used by processing units, etc. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. For example, NAND type memory such as 3D NAND, high-capacity non-volatile storage devices such as HDDs can be used.

[0064] In one embodiment of the present invention, among various storage devices shown in FIG. 3A , at least the DRAM used as the main memory is replaced with a storage device using an oxide semiconductor (OS memory). In particular, the DRAM requires a refresh operation and is a destructive readout storage device, and therefore consumes significantly more power than other storage devices. Therefore, power consumption can be significantly reduced by not using the DRAM. Note that in FIG. 3A , the range of various storage devices that is targeted for replacement with the OS memory is indicated by a dashed line. In other words, not only the DRAM used as the main memory, but also part of the SRAM used as the cache and the NAND memory used for storage can be replaced with the OS memory.

[0065] 3B illustrates an example of a semiconductor device according to one embodiment of the present invention, and is a schematic diagram illustrating various memory devices used in the semiconductor device 10 and the semiconductor device 10A, layer by layer.

[0066] In FIG. 3B, a plurality of caches (L1 cache, L2 cache) and a Last Level cache (LLC) are shown as caches.

[0067] Multiple caches are provided in the order of L1 cache and L2 cache from the highest to lowest. The higher the cache, the more frequently it is accessed by the processor, so high-speed operation is required. Since the operating speed can also be increased by reducing the data capacity, it is preferable to reduce the data capacity of the higher-level cache. The higher-level cache is preferably physically closer to the processor and has shorter wiring length, so it is preferable to provide it in a form integrated with the layer where the processor is provided. The lower-level cache may be provided in a layer different from the processor.

[0068] The lowest level cache can be called an LLC. While LLCs do not require faster operating speeds than higher-level caches, they desirably have large storage capacities. The OS memory of one embodiment of the present invention, described below, is suitable for use as an LLC because it has fast operating speeds and can retain data for long periods of time. Note that LLCs can also be called FLCs (Final Level Caches).

[0069] SRAM can be used for various caches. OS memory can be used for LLC and main memory. This storage device has high operating speed and can retain data for a long period of time.

[0070] 3B, layers 11 and 12 in FIG. 1A or 2A can be applied to the layer where the CPU / GPU is provided. Layer 13 can be applied to the layer where the LLC is provided, layer 14 can be applied to the layer where the main memory is provided, and layer 15 can be applied to the layer where the storage is provided.

[0071] The configuration exemplified here does not use DRAM, which has been conventionally used as a main memory, etc. Instead, the DRAM is replaced with an OS memory according to one embodiment of the present invention. This configuration allows for a dramatic reduction in power consumption (for example, to one hundredth or one thousandth or less). Therefore, it is expected that the worldwide deployment of information processing devices, including computers, servers, and the like, to which this configuration is applied, will contribute significantly to the prevention of global warming.

[0072] Here, we will explain the specifications required for the memory used in each hierarchy. Table 1 shows the access time and capacity required for each memory. Note that Table 1 is a guideline and can be changed as appropriate to suit the purpose of use, architecture, etc.

[0073]

[0074] As shown in Table 1, it can be seen that the higher the hierarchy, the faster the operation is required, and the lower the hierarchy, the larger the capacity is required.

[0075] It should be noted that the access time and capacity of storage differ depending on whether it is a storage device using flash memory such as an SSD (Solid State Drive) or an SD card, or a hard disk.

[0076] Based on Table 1 above, the specifications required for the OS memory are shown in Table 2.

[0077]

[0078] Table 3 shows a comparison between a conventional DRAM, a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) as an example of an OS memory, and an NOSRAM. Note that the DOSRAM has a configuration in which the transistors of the DRAM are replaced with OS transistors.

[0079]

[0080] As shown in Table 3, NOSRAM has advantages over DRAM, such as the ability to perform non-destructive readout, the ability to make the cell area equivalent to that of DRAM, and low power consumption.

[0081] Next, an example of a semiconductor device different from the above will be described.

[0082] 4A shows an example in which NOSRAM1 is used for the highest level cache, NOSRAM2 for the lower level cache, NOSRAM3 for the main memory, and a hard disk for storage. FIG. 4B shows an example in which 3D NAND memory is used for storage.

[0083] Furthermore, a configuration may be adopted in which a hard disk and a 3D NAND memory are not used. Fig. 4C shows an example in which NOSRAM2 is used as the main memory and NOSRAM3 is used as the storage.

[0084] The NOSRAM 1 is a memory capable of high-speed operation. For example, a storage device including the memory cells 20 exemplified above can be used.

[0085] Although NOSRAM2 and NOSRAM3 are slower in operating speed than NOSRAM1, they are memories with better data retention characteristics. For example, a storage device including the memory cell 30 exemplified above can be used. Furthermore, NOSRAM3 is a memory in which the memory cell 30 has a larger capacity than NOSRAM2, and has improved data retention characteristics.

[0086] That is, NOSRAM1 has the fastest operating speed and NOSRAM3 has the slowest. On the other hand, NOSRAM3 has the longest data retention period and NOSRAM1 has the shortest data retention period. Furthermore, even NOSRAM1, which has the shortest data retention period, has a longer refresh cycle than a DRAM (for example, about 60 ms).

[0087] For example, the data retention period of NOSRAM1 is preferably 0.1 seconds or more, more preferably 1 second or more, and even more preferably 3 seconds or more. Furthermore, the data retention period of NOSRAM2 is preferably 30 seconds or more, more preferably 1 minute or more, and even more preferably 10 minutes or more. The data retention period of NOSRAM3 is preferably more than 10 minutes, more preferably 1 hour or more, and even more preferably 1 day or more. Note that the longer the data retention period, the better, so no upper limit is specified.

[0088] For example, if the data retention period of the NOSRAM 3 is one year or more, it can be used as a substantially non-volatile memory and can also be applied to storage. When used as storage, data may be rewritten once every few days.

[0089] Next, more specific examples of each layer exemplified above will be described.

[0090] [Layer 12] Fig. 5A shows a block diagram of a processing unit as an example of layer 12. Fig. 5A shows an example of the configuration of a CPU.

[0091] 5A includes an ALU 71 (Arithmetic logic unit), an ALU controller 72, an instruction decoder 73, an interrupt controller 74, a timing controller 75, a register 76, a register controller 77, a bus interface 78, a cache 79, and a cache interface 70. The layer 12 may also include a rewritable ROM and a ROM interface. The cache 79 and the cache interface 70 may be provided in different layers.

[0092] The cache 79 is connected to a main memory provided in a different layer via a cache interface 70. The cache interface 70 has a function of supplying a portion of the data held in the main memory to the cache 79. The cache 79 has a function of holding the data.

[0093] The arithmetic processing device shown in Figure 5A is merely an example of a simplified configuration, and actual arithmetic processing devices have a wide variety of configurations depending on their applications. For example, a configuration including the arithmetic processing device or arithmetic circuit shown in Figure 5A may be used as one core, and multiple such cores may be included, with each core operating in parallel, i.e., a GPU-like configuration may be used. Furthermore, the number of bits that the arithmetic processing device can handle in its internal arithmetic circuit or data bus may be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0094] An instruction input to the arithmetic processing unit via the bus interface 78 is input to the instruction decoder 73 , decoded, and then input to the ALU controller 72 , interrupt controller 74 , register controller 77 , and timing controller 75 .

[0095] The ALU controller 72, interrupt controller 74, register controller 77, and timing controller 75 perform various controls based on the decoded instructions. Specifically, the ALU controller 72 generates signals for controlling the operation of the ALU 71. Furthermore, the interrupt controller 74 processes interrupt requests from external input / output devices or peripheral circuits while the arithmetic processing unit is executing a program, judging their priority or mask status. The register controller 77 generates addresses for registers 76 and reads or writes data from or to the registers 76 depending on the state of the arithmetic processing unit.

[0096] Furthermore, the timing controller 75 generates signals that control the timing of the operations of the ALU 71, the ALU controller 72, the instruction decoder 73, the interrupt controller 74, and the register controller 77. For example, the timing controller 75 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0097] 5A, memory devices are provided for the register 76 and the cache 79. It is preferable to use an SRAM for the cache 79. Alternatively, an NOSRAM may be used.

[0098] 5A, the register controller 77 selects the holding operation of the register 76 in accordance with an instruction from the ALU 71. That is, it selects whether the memory cells of the register 76 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 76. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 76 can be stopped.

[0099] Layer 11 FIG. 5B shows a block diagram of a GPU as an example of layer 11.

[0100] The GPU shown in FIG. 5B includes a controller 81, a plurality of processors 82, a plurality of caches 83, a cache 84, an interface 85, and the like.

[0101] The controller 81 controls the processors 82, for example, by allocating input instructions to available processors among the plurality of processors 82.

[0102] The processor 82 further includes a parallel computing unit capable of simultaneously executing multiple processes. The processor 82 includes, for example, multiple processor cores and registers.

[0103] A plurality of caches 83 are provided for each processor 82. Furthermore, a cache 84 can be shared by a plurality of processors 82.

[0104] For example, in response to an instruction input from the CPU to the GPU, the controller 81 allocates and outputs the instruction to an available processor 82. At this time, the instruction may be divided into multiple threads and output to multiple processors 82. Data processed by the processor 82 is temporarily stored in a cache 83, cache 84, etc., and is sent to the CPU, etc. via an interface 85.

[0105] At this time, since the layers 11 and 12 are stacked and joined together, the wiring length is short and data can be transferred using an extremely large number of wirings, thereby making it possible to extremely increase the data transfer efficiency.

[0106] The semiconductor device may have a configuration including a DSP (Digital Signal Processor), an FPGA (Field-Programmable Gate Array), etc. as a processor in addition to the CPU and GPU.

[0107] Layer 13 FIG. 6A shows a memory array and its peripheral circuitry that can be used in layer 13.

[0108] The layer 13 has a plurality of memory cells 20 arranged in a matrix, and circuits 21, 22, 23, and 24. The circuit 21 is connected to a plurality of wirings WBL, the circuit 22 to a plurality of wirings WWL, the circuit 23 to a plurality of wirings RBL, and the circuit 24 to a plurality of wirings RWL. The wirings WWL and RWL extend in the row direction, the wirings WBL and RBL extend in the column direction, and the wirings WWL and RWL intersect with the wirings WBL and RBL, respectively. Each memory cell 20 is connected to one wiring WWL, one wiring WBL, one wiring RWL, and one wiring RBL.

[0109] The memory cell 20 is composed of a transistor M1 and a transistor M2. The gate of the transistor M1 is connected to a wiring WWL, one of the source and the drain is connected to a wiring WBL, and the other is connected to the gate of the transistor M2. The source and the drain of the transistor M2 are connected to a wiring RWL and the other is connected to a wiring RBL. A node FN, where the other of the source and the drain of the transistor M1 and the gate of the transistor M2 are connected, functions as a storage node of the memory cell 20.

[0110] The circuit 21, the circuit 22, and the circuit 24 function as driver circuits that supply signals to the wiring WBL, the wiring WWL, and the wiring RWL, respectively. The circuit 23 functions as a read circuit and has a function of reading data held in the memory cell 20 by detecting the current flowing through the wiring RBL or the potential of the wiring RBL.

[0111] Here, the case where both the transistor M1 and the transistor M2 are N-channel transistors will be described. Note that when one or both of the transistors M1 and M2 are P-channel transistors, the potentials supplied to the various wirings may be changed appropriately.

[0112] When writing data to a memory cell 20, a potential that turns on the transistor M1 is applied to the wiring WWL connected to the target memory cell 20, and a data potential is supplied to the wiring WBL. Then, a potential that turns off the transistor M1 is applied to the wiring WWL, so that the data potential is held at the node FN of the memory cell 20. When a high-level potential is written to the memory cell 20, the transistor M2 is turned on, and when a low-level potential is written, the transistor M2 is turned off. When reading data from the memory cell 20, a potential is applied to the wiring RWL connected to the target memory cell 20, and the data can be read by detecting the current flowing through the wiring RBL or the potential of the wiring RBL. At this time, to turn off the transistor M2 of the memory cells 20 in a row (non-selected row) different from the target memory cell 20, a lower potential (e.g., a negative potential) may be applied to the wiring WWL of the non-selected row.

[0113] In the configuration shown in FIG. 6A, the memory cells 20 do not have capacitance, so that the signal delay during writing and reading is small, enabling high-speed operation.

[0114] 6B illustrates an example in which the transistor M2 of the memory cell 20 has a back gate (second gate). The back gate of the transistor M2 is connected to the wiring WWL. This allows the transistor M2 of the memory cell 20 to be reliably turned off by applying a low potential (e.g., a negative potential) to the wiring WWL of a non-selected row. Note that the back gate of the transistor M2 may be connected to another wiring instead of the above.

[0115] 6A and 6B, the transistor M1 may have a back gate. In this case, it is preferable to apply a signal or potential to the back gate for controlling the threshold voltage of the transistor M1. Alternatively, the back gate may be connected to the wiring WWL, the wiring WBL, or the gate of the transistor M2.

[0116] Layer 14 Figure 7A shows a memory array and its peripheral circuitry that can be used in layer 14.

[0117] The layer 14 includes a plurality of memory cells 30 arranged in a matrix, and a circuit 31, a circuit 32, a circuit 33, and a circuit 34. The circuit 31 is connected to a plurality of wirings WBL, the circuit 32 is connected to a plurality of wirings WWL and a plurality of wirings CWL, the circuit 33 is connected to a plurality of wirings RBL, and the circuit 34 is connected to a plurality of wirings RWL. The memory cell 30 is connected to one wiring WWL, one wiring WBL, one wiring RWL, one wiring RBL, and one wiring CWL.

[0118] The memory cell 30 is composed of a transistor M3, a transistor M4, and a capacitor C. The gate of the transistor M3 is connected to a wiring WWL, one of the source and drain is connected to a wiring WBL, and the other is connected to the gate of the transistor M4 and one electrode of the capacitor C. The transistor M2 has one of the source and drain connected to a wiring RWL and the other connected to a wiring RBL. The other electrode of the capacitor C is connected to a wiring CWL. A node FN to which the other of the source and drain of the transistor M3, the gate of the transistor M4, and one electrode of the capacitor C are connected functions as a storage node of the memory cell 30.

[0119] The circuits 31, 32, and 34 function as driver circuits that supply signals to the wiring WBL, the wiring WWL, and the wiring RWL, respectively. The circuit 32 also has a function of supplying a signal to the wiring CWL. The circuit 33 functions as a readout circuit and has a function of detecting a current flowing through the wiring RBL or a potential of the wiring RBL.

[0120] Here, the case where both the transistor M3 and the transistor M4 are N-channel transistors will be described. Note that if one or both of the transistors M3 and M4 are P-channel transistors, the potentials supplied to the various wirings may be changed appropriately.

[0121] For methods of writing and reading data to and from the memory cells 30, see the description of the layer 13. When reading data from the memory cells 30, in a non-selected row, a low potential is applied to the wiring CWL to lower the potential applied to the gate of the transistor M4, thereby turning off the transistor M4. This allows data from the row of the target memory cell 30 to be read with higher accuracy.

[0122] 7A, the memory cell 30 has a capacitance C connected to the gate of the transistor M4, which allows for a longer data retention period. The larger the capacitance C (capacitance value), the better the data retention characteristics of the memory cell 30.

[0123] 7B illustrates an example in which the transistor M3 of the memory cell 30 has a back gate. The back gate of the transistor M3 is connected to the wiring CWL. When the transistor M3 is not selected, a low potential is applied to the wiring CWL, which can shift the threshold voltage of the transistor M3 in a positive direction and reduce the leakage current between the source and drain of the transistor M3. This can further improve the data retention characteristics.

[0124] Layer 15 FIG. 8A shows a perspective schematic diagram of a memory device that can be used for layer 15.

[0125] The memory device is provided on an insulating layer 50 and has a plurality of memory strings 40. The memory strings 40 have a plurality of cell transistors stacked in a direction perpendicular to the upper surface of the insulating layer 50. The memory device further has a plurality of conductive layers 51, 52, 53, 54, and 55 that function as various wirings, as well as a plurality of plugs 56.

[0126] In Figure 8A, the orthogonal X, Y, and Z directions are indicated by arrows. The memory strings 40 are arranged at equal intervals in both the X and Y directions. Figure 8A shows, as an example, one block having 5 x 5 memory strings 40. A memory device has multiple such blocks. In practice, it is preferable that one block have a larger number of memory strings 40.

[0127] One memory string 40 is provided to connect between conductive layers 53 and 54. For example, conductive layer 53 functions as a source line, and conductive layer 54 functions as a bit line. Furthermore, a plurality of conductive layers 51 are stacked and provided between conductive layer 53 and conductive layer 54. Conductive layer 51 functions as a control gate line. Furthermore, a conductive layer 52 functioning as a select line is provided between the uppermost conductive layer 51 and conductive layer 54. Furthermore, each of the plurality of conductive layers 51 is connected to one of the plurality of conductive layers 55 via a plug 56.

[0128] The conductive layers 54 and 52 extend in directions intersecting each other to form a 5 × 5 matrix. The conductive layers 51 and 53 are connected to all of the memory strings 40 (here, 5 × 5) in the block.

[0129] 8A shows an example of a configuration having five conductive layers 51, but the number of layers is not limited to this. The greater the number of stacked layers, the greater the number of cell transistors that make up one memory string 40, allowing for a larger data capacity of the memory device. The greater the number of cell transistors that make up one memory string 40, the more preferable it is, and the number can be, for example, 64 or more, 128 or more, 160 or more, 192 or more, 224 or more, or 256 or more.

[0130] 8B shows an extracted configuration of one memory string 40 and its vicinity. A memory cell 65 functioning as a cell transistor is provided at a portion of the memory string 40 that intersects with the conductive layer 51. Of the multiple conductive layers 51, the lowest conductive layer 51 may function as a selection line.

[0131] 8C is a circuit diagram of the configuration shown in Fig. 8B . The conductive layer 53 corresponds to the wiring CL, the conductive layer 54 corresponds to the wiring BL, the lowermost conductive layer 51 corresponds to the wiring SSL, the other conductive layers 51 correspond to the wirings WL (wirings WL1 to WLm (m is an integer of 2 or more)), and the conductive layer 52 corresponds to the wiring BSL.

[0132] 8C , a transistor STr, a plurality of transistors CTr, and a transistor BTr are provided between a wiring BL and a wiring CL. The transistors STr and BTr each function as a selection transistor, and the transistor CTr functions as a cell transistor. The transistor CTr functions as one memory element.

[0133] The transistor CTr may be a memory element using a ferroelectric, such as a structure in which a ferroelectric capacitor is connected to the gate, a structure in which a ferroelectric is applied to the gate insulating layer, etc. Note that, for example, a charge trap type flash memory or a floating gate type flash memory may also be used.

[0134] 8D and 8E show an example in which a pair of memory strings constitute one memory string 40. In this case, the conductive layer 53 functions as a pipe gate line, and the conductive layer 57 functions as a source line. The transistor PTr provided at the bottom of the U-shaped memory string functions as a selection transistor (also called a pipe transistor) for connecting the pair of memory strings.

[0135] This concludes the explanation of each layer.

[0136] The semiconductor device of one embodiment of the present invention can be applied to any communication device or information processing device that requires a processor, such as a mobile phone, a smartphone, a tablet terminal, a television device, a wearable device for VR (Virtual Reality) or AR (Augmented Reality), a wristwatch terminal, a game console, a personal computer (including a laptop computer), or a data server. Furthermore, the semiconductor device can be applied to any facility, device, or apparatus that requires a processor, including moving objects such as automobiles, motorcycles, trains, airplanes, and drones, as well as household appliances such as refrigerators and washing machines. Replacing a conventional processor with the semiconductor device of one embodiment of the present invention can significantly reduce power consumption, which is expected to contribute to the suppression of global warming.

[0137] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0138] Embodiment 2 In this embodiment, a memory device of one embodiment of the present invention will be described with reference to FIGS.

[0139] A memory device according to one embodiment of the present invention includes two vertical transistors each having an oxide semiconductor layer in a channel formation region, stacked vertically. The gate of the lower vertical transistor is electrically connected to the source or drain of the upper vertical transistor. A capacitor is formed by the gate of the lower vertical transistor, the back gate of the upper vertical transistor, and an insulating layer between the gate and the back gate. Forming the capacitor using components of the two vertical transistors can prevent an increase in the number of manufacturing steps for the memory device.

[0140] A memory device according to one embodiment of the present invention can be said to have a memory cell (hereinafter referred to as a 2Tr1C memory cell) including two transistors and one capacitor. In a 2Tr1C memory cell, providing a capacitor in addition to the two transistors can reduce the degree of integration of the memory cell. By providing a capacitor so as to overlap with two vertical transistors in a plan view, an increase in the area occupied by the memory cell due to the provision of the capacitor can be suppressed. Furthermore, a memory cell including a capacitor can be manufactured with an area that is the same as or almost the same as the area occupied by two vertical transistors stacked above and below. Therefore, providing a capacitor can prevent a reduction in the degree of integration of the memory cell.

[0141] As described above, 2Tr1C memory cells can be arranged at high density by a simple manufacturing method, and the memory device of one embodiment of the present invention can have a large storage capacity.

[0142] Furthermore, since a transistor including an oxide semiconductor has a small off-state current, when used in a memory device, stored data can be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using a transistor including an oxide semiconductor in a memory device, the memory device can be highly integrated and have low power consumption. Furthermore, by using an oxide semiconductor with high crystallinity, the on-state current of the transistor can be increased and frequency characteristics can be improved. Therefore, reading and writing of the memory device can be performed at higher speed.

[0143] In a transistor included in a memory device of one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction). Therefore, the transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0144] In a vertical transistor, the source electrode, the semiconductor layer, and the drain electrode can be provided in a stacked manner, and therefore the occupied area can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a plane.

[0145] The channel length of a vertical transistor can be controlled by the thickness of the stacked layers. Therefore, it is possible to realize a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor. Therefore, it is possible to realize a transistor with a small occupancy area and a large on-state current.

[0146] <Configuration Example 1 of Memory Device> FIGS. 9A and 9B show examples of circuit diagrams of the memory cell 150. FIG.

[0147] 9A and 9B includes a transistor 201, a transistor 202, and a capacitor 203. The memory cell 150 is connected to one wiring WWL, one wiring WBL, one wiring RWL, one wiring RBL, and one wiring CWL.

[0148] The transistor 202 has a gate connected to a wiring WWL, one of a source and a drain connected to a wiring WBL, the other connected to the gate of the transistor 201 and one electrode of the capacitor 203, and a backgate connected to the other electrode of the capacitor 203 and a wiring CWL. The transistor 201 has a source and a drain connected to a wiring RWL, and the other connected to a wiring RBL.

[0149] The transistor 202 preferably has a back gate. When the transistor 202 is not selected, a low potential is applied to the wiring CWL, which can shift the threshold voltage of the transistor 202 in the positive direction and reduce leakage current between the source and drain of the transistor 202. This can further improve data retention characteristics. The transistor 201 may or may not have a back gate. FIG. 9A illustrates an example in which the transistor 201 does not have a back gate, and FIG. 9B illustrates an example in which the transistor 201 has a back gate.

[0150] The memory cell 150 includes a node FN where the gate of the transistor 201, one of the source and the drain of the transistor 202, and one electrode of the capacitor 203 are electrically connected.

[0151] FIG. 9C shows an example of a plan view of one memory cell 150. FIG. 9D shows an example of a plan view of a plurality of memory cells 150 arranged in a matrix. Note that some elements are omitted from the plan view for clarity. FIG. 9D shows an example of an arrangement of 5×5 memory cells 150 in the X and Y directions. As shown in FIGS. 9C and 9D , the memory cell 150 is provided at the intersection of a conductive layer 265 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 9D , the diameter of the opening (shown by a solid-line circle in FIG. 9D , corresponding to openings 190 and 290) can be made smaller than the width of the short side of the conductive layer 240, the width of the short side of the conductive layer 255, and the width of the short side of the conductive layer 265. Thus, the memory cell 150 can be said to have a structure that allows for high integration and miniaturization.

[0152] 10 and 11 show examples of cross-sectional views of a memory device having memory cells 150. Fig. 10 is a cross-sectional view taken along dashed line A1-A2 in Fig. 9C. Fig. 11 is a cross-sectional view taken along dashed line A3-A4 in Fig. 9C.

[0153] The memory device shown in Figures 10 and 11 has an insulating layer 140 on a substrate (not shown), a memory cell 150 on the insulating layer 140, an insulating layer 161c on the insulating layer 140, an insulating layer 161a on the insulating layer 161c, an insulating layer 161d on the insulating layer 161a, an insulating layer 185, an insulating layer 280a, an insulating layer 280f, an insulating layer 280b on the insulating layer 280f, an insulating layer 280d on the insulating layer 280b, an insulating layer 285, a conductive layer 265a on the insulating layer 285, and a conductive layer 265b on the conductive layer 265a. The insulating layer 140, the insulating layer 161a, the insulating layer 161c, the insulating layer 161d, the insulating layer 185, the insulating layer 280a, the insulating layer 280b, the insulating layer 280d, the insulating layer 280f, and the insulating layer 285 function as interlayer films. Note that at least one of these interlayer films may be considered as a component of the memory cell 150. The conductive layer 265a and the conductive layer 265b function as wirings. Note that at least one of the conductive layer 265a and the conductive layer 265b may be considered as a component of the memory cell 150. Note that the conductive layer 265a and the conductive layer 265b may be collectively referred to as the conductive layer 265 in some cases.

[0154] The memory cell 150 includes a transistor 201A, a transistor 202A, and a capacitor 203A.

[0155] The transistor 201A includes a conductive layer 120a, a conductive layer 120b on the conductive layer 120a, a conductive layer 120c on the conductive layer 120b, a conductive layer 145a on the insulating layer 161d, a conductive layer 145b on the conductive layer 145a, an oxide semiconductor layer 135, an insulating layer 151 on the oxide semiconductor layer 135, and a conductive layer 164 on the insulating layer 151.

[0156] Note that the conductive layers 120a, 120b, and 120c may be collectively referred to as conductive layers 120. The conductive layers 145a and 145b may be collectively referred to as conductive layers 145.

[0157] In the transistor 201A, the oxide semiconductor layer 135 functions as a semiconductor layer, the conductive layer 164 functions as a first gate electrode, the insulating layer 151 functions as a first gate insulating layer, the conductive layer 120 functions as one of a source electrode and a drain electrode, and the conductive layer 145 functions as the other of the source electrode and drain electrode. The transistor 201A may further include a conductive layer functioning as a second gate electrode and an insulating layer functioning as a second gate insulating layer.

[0158] The oxide semiconductor layer 135 has a region overlapping with the conductive layer 164 with the insulating layer 151 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 201A. One of the region of the oxide semiconductor layer 135 in contact with the conductive layer 120 and the region of the oxide semiconductor layer 230 in contact with the conductive layer 145 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0159] The transistor 201A has a structure in which the oxide semiconductor layer 135 surrounds the conductive layer 164 functioning as a gate electrode, and thus can be said to be a transistor with a channel-all-around (CAA) structure.

[0160] The transistor 202A includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 255 over the insulating layer 280e, a conductive layer 240a over the insulating layer 280d, a conductive layer 240b over the conductive layer 240a, an insulating layer 235a, an insulating layer 235b, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The conductive layer 260 is electrically connected to a conductive layer 265 that functions as a gate wiring.

[0161] The conductive layers 220a and 220b may be collectively referred to as the conductive layers 220. The conductive layers 240a and 240b may be collectively referred to as the conductive layers 240. The insulating layers 235a and 235b may be collectively referred to as the insulating layers 235.

[0162] In the transistor 202A, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 235 functions as a second gate insulating layer.

[0163] It is preferable that the conductive layer 260 function as a gate electrode and the conductive layer 255 function as a back gate electrode. When the conductive layer 260, which has a wider region facing the oxide semiconductor layer 230 than the conductive layer 255, is used as a gate, a gate electric field is applied to the oxide semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor. In this case, the insulating layer 250 functions as a gate insulating layer and the insulating layer 235 functions as a back gate insulating layer. Note that the conductive layer 260 may function as a back gate electrode and the conductive layer 255 may function as a gate electrode.

[0164] When the channel length of a transistor is shortened, the transistor tends to have normally-on characteristics due to the so-called short channel effect (SCE). The transistor 202A has a back gate. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized. Furthermore, fluctuations in the threshold voltage can be suppressed. That is, even when miniaturized, the transistor 202A has a high on-state current, is normally-off, and has high reliability.

[0165] The conductive layer 260 has a portion overlapping with the top surface of the conductive layer 240. Here, if parasitic capacitance between the source electrode or drain electrode and the gate wiring is large, the operation of the transistor may slow down, and the frequency characteristics of a circuit using the transistor may deteriorate. Therefore, it is preferable to provide a conductive layer 265 that functions as a gate wiring separately from the conductive layer 260 and to provide an insulating layer 285 between the conductive layer 265 and the conductive layer 240. The conductive layer 265 is connected to the conductive layer 260 through an opening 270 provided in the insulating layer 285. This increases the physical distance between the conductive layer 265 and the conductive layer 240, thereby reducing the parasitic capacitance between the gate wiring and the conductive layer 240. This can suppress deterioration in the frequency characteristics of a circuit using the transistor 202A.

[0166] The conductive layer 260 does not extend in either the X direction or the Y direction. The width of the conductive layer 260 is preferably narrow in both the X direction and the Y direction. This makes it possible to reduce the area of ​​the region of the conductive layer 260 that overlaps with the upper surface of the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 260 and the conductive layer 240.

[0167] The oxide semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween and with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 202A. One of the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 and the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0168] The conductive layer 164 of the transistor 201A and the conductive layer 220 of the transistor 202A are in contact with the conductive layer 165. That is, the conductive layer 164 and the conductive layer 220 are electrically connected to each other through the conductive layer 165. This electrically connects the gate of the transistor 201A to the source or drain of the transistor 202A. Note that the conductive layer 165 may be regarded as part of the source or drain electrode of the transistor 202A.

[0169] The conductive layer 164 does not extend in either the X direction or the Y direction, which reduces the area of ​​the region of the conductive layer 164 that overlaps with the upper surface of the conductive layer 145, thereby reducing the parasitic capacitance that occurs between the conductive layer 164 and the conductive layer 145.

[0170] It can also be said that the conductive layer 164, the conductive layer 165, the conductive layer 220a, and the conductive layer 220b function as one of the source electrode and drain electrode of the transistor 202A and as the gate electrode of the transistor 201A. That is, it can also be said that the transistor 201A and the transistor 202A share part of their structure. With this structure, the transistor 201A and the transistor 202A can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be arranged at high density and increasing the storage capacity of the storage device.

[0171] The capacitor 203A includes at least a conductive layer 220b, an insulating layer 280c over the conductive layer 220b, an insulating layer 280g over the insulating layer 280c, an insulating layer 280e over the insulating layer 280g, and a conductive layer 255 over the insulating layer 280e. At least some of the components of the capacitor 203A can also serve as components of the transistor 201A or the transistor 202A. Therefore, an increase in the number of manufacturing steps of the memory device due to the provision of the capacitor can be suppressed. By providing the capacitor 203A so as to overlap with the transistors 201A and 202A in a plan view, a decrease in the integration density of the memory cell 150 can be suppressed.

[0172] The shortest distance from the top surface of the conductive layer 220b to the bottom surface of the conductive layer 255 is preferably shorter than the shortest distance from the top surface of the conductive layer 255 to the bottom surface of the conductive layer 240. This can increase the capacitance of the capacitor 203A. Furthermore, the parasitic capacitance generated between the conductive layer 240 and the conductive layer 255 can be reduced.

[0173] 10 includes a conductive layer 165, a conductive layer 220a, and a conductive layer 220b over an insulating layer 185. The conductive layer 165 is connected to the conductive layer 164 through an opening 174 provided in the insulating layer 185. The conductive layer 165, the conductive layer 220a, and the conductive layer 220b overlap with the top surface of the conductive layer 145 with the insulating layer 185 interposed therebetween. By providing the insulating layer 185, the physical distance between the conductive layer 165 and the conductive layer 145 can be increased and the parasitic capacitance generated between the conductive layer 165 and the conductive layer 145 can be reduced compared to when the insulating layer 185 is not provided.

[0174] Here, in order to increase the capacitance value of the capacitor 203A, it is preferable to increase the area of ​​the region where the lower surface of the conductive layer 255 overlaps with the upper surface of the conductive layer 220b. Increasing the area of ​​the region where the lower surface of the conductive layer 255 overlaps with the upper surface of the conductive layer 220b also increases the area of ​​the region where the lower surface of the conductive layer 220b overlaps with the upper surface of the conductive layer 145. As described above, in the memory cell 150 shown in FIG. 10 , the physical distance between the conductive layer 165 and the conductive layer 145 is large, so that the parasitic capacitance generated between the conductive layer 165 and the conductive layer 145 can be reduced. Therefore, the area of ​​the region where the lower surface of the conductive layer 255 overlaps with the upper surface of the conductive layer 220b and the area where the lower surface of the conductive layer 220b overlaps with the upper surface of the conductive layer 145 can be increased, thereby increasing the capacitance value of the capacitor 203A.

[0175] 10 and the like shows an example in which the insulating layer 280a is provided to planarize the surface on which the insulating layer 280g is formed, but this is not limiting. For example, the capacitor 203A may have the insulating layer 280a between the insulating layer 280c and the insulating layer 280g. Alternatively, instead of providing the insulating layer 280a, the insulating layer 280g, the insulating layer 280e, the conductive layer 255, and the like may be provided along the side and top surfaces of the conductive layer 220, similar to the insulating layer 280c. This can increase the area where the conductive layer 220b and the conductive layer 255 overlap with each other via the insulating layer, thereby increasing the capacitance of the capacitor 203A.

[0176] As shown in Figures 10 and 11, openings 290 reaching the conductive layer 220 are provided in the insulating layer 280c, the insulating layer 280g, the insulating layer 280e, the conductive layer 255, the insulating layer 280f, the insulating layer 280b, the insulating layer 280d, the conductive layer 240a, and the conductive layer 240b.

[0177] The conductive layer 220 includes a conductive layer 220a and a conductive layer 220b on the conductive layer 220a, and a recess is provided in the conductive layer 220b. In other words, the conductive layer 220 has a recess, the bottom surface of which corresponds to the bottom surface of the recess in the conductive layer 220b, and the side surface of which corresponds to the side surface of the recess in the conductive layer 220b. Specifically, the conductive layer 220b has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220b, and then, when processing the insulating layer 235, the first recess is provided in the conductive layer 220b. 10 and the like, the side surface of the first recess is aligned with the surface of the insulating layer 235 facing the oxide semiconductor layer 230, and the side surface of the second recess is aligned with the side surface of the insulating layer 280c or the like facing the opening 290. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0178] The opening 290 overlaps the recess of the conductive layer 220b. Here, the sidewall of the opening 290 includes the side surfaces of the insulating layer 280c, the side surfaces of the insulating layer 280g, the side surfaces of the insulating layer 280e, the side surfaces of the conductive layer 255, the side surfaces of the insulating layer 280f, the side surfaces of the insulating layer 280b, the side surfaces of the insulating layer 280d, the side surfaces of the conductive layer 240a, and the side surfaces of the conductive layer 240b. The bottom of the opening 290 may be considered to include the bottom surface of the recess of the conductive layer 220b. The side surfaces of the recess of the conductive layer 220b may be considered to be part of the sidewall of the opening 290. In other words, the recess of the conductive layer 220b may be considered to be part of the opening 290.

[0179] The opening 290 includes an opening in the insulating layer 280c, an opening in the insulating layer 280g, an opening in the insulating layer 280e, an opening in the conductive layer 255, an opening in the insulating layer 280f, an opening in the insulating layer 280b, an opening in the insulating layer 280d, an opening in the conductive layer 240a, and an opening in the conductive layer 240b. In other words, the opening in the region where the insulating layer 280c overlaps with the conductive layer 220a is a part of the opening 290, the opening in the region where the insulating layer 280g overlaps with the conductive layer 220a is another part of the opening 290, the opening in the region where the insulating layer 280e overlaps with the conductive layer 220a is another part of the opening 290, the opening in the region where the conductive layer 255 overlaps with the conductive layer 220a is another part of the opening 290, and the opening in the region where the insulating layer 280f overlaps with the conductive layer 220a is another part of the opening 290. An opening in the region where the insulating layer 280b overlaps with the conductive layer 220a is another part of the opening 290, an opening in the region where the insulating layer 280d overlaps with the conductive layer 220a is another part of the opening 290, an opening in the region where the insulating layer 280d overlaps with the conductive layer 220a is another part of the opening 290, an opening in the region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening 290, and an opening in the region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening 290. The shape and size of the openings 290 in a plan view may differ depending on the layer. Furthermore, when the top surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric. The opening in the insulating layer 280a may also be considered part of the opening 290.

[0180] At least some of the components of the transistor 202A are disposed in the opening 290. Specifically, at least some of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed in the opening 290.

[0181] The insulating layer 235 has at least a region located between the oxide semiconductor layer 230 and the conductive layer 255. The oxide semiconductor layer 230 is in contact with the insulating layer 235 in the opening 290.

[0182] 10 and other drawings, the insulating layer 235 contacts the bottom and side surfaces of the recesses (specifically, the second recesses) of the conductive layer 220, and also contacts the side surfaces of the insulating layer 280c, the insulating layer 280g, the insulating layer 280e, the conductive layer 255, the insulating layer 280f, the insulating layer 280b, the insulating layer 280d, the conductive layer 240a, and the conductive layer 240b within the opening 290. The oxide semiconductor layer 230 contacts the bottom and side surfaces of the recesses (specifically, the first recesses) of the conductive layer 220, the insulating layer 235, and the top surface of the conductive layer 240b. The insulating layer 250 is located inside the oxide semiconductor layer 230 within the opening 290, and the conductive layer 260 is located inside the insulating layer 250 within the opening 290.

[0183] The insulating layer 235 is provided along at least a part of the sidewall of the opening 290. Furthermore, the portions of the oxide semiconductor layer 230 and the insulating layer 250 that are disposed within the opening 290 are provided to reflect the shape of the opening 290. Specifically, the oxide semiconductor layer 230 is provided so as to cover the bottom surface of the recess of the conductive layer 220b and the insulating layer 235, and the insulating layer 250 is provided so as to cover the oxide semiconductor layer 230. Then, the conductive layer 260 is provided so as to fill at least a part of the recess of the insulating layer 250 that reflects the shape of the opening 290.

[0184] The insulating layer 235 can be formed, for example, by forming an insulating film so as to cover the opening 290 and processing the insulating film by anisotropic etching to remove a region of the insulating film located on the upper surface of the conductive layer 240b and a region located on the bottom surface of the opening 290. This allows the insulating layer 235 to remain only on the side surfaces within the opening 290. The insulating film that becomes the insulating layer 235 is preferably processed by highly anisotropic etching using a dry etching method.

[0185] The insulating layer 235 may have a single-layer structure or a stacked-layer structure. In this embodiment, an example in which the insulating layer 235 includes an insulating layer 235a and an insulating layer 235b over the insulating layer 235a is mainly shown. The insulating layer 235a and the insulating layer 235b function as a second gate insulating layer (also referred to as a back-gate insulating layer) of the transistor 202A.

[0186] One of the insulating layer 235a and the insulating layer 235b preferably includes an insulating layer having a region containing oxygen that is released by heating. The other of the insulating layer 235a and the insulating layer 235b preferably includes a barrier insulating layer against hydrogen.

[0187] This allows oxygen to be supplied from the insulating layer 235a or the insulating layer 235b to the oxide semiconductor layer 230, and also prevents hydrogen from diffusing into the oxide semiconductor layer 230, thereby improving the reliability of the transistor 202A.

[0188] For example, it is preferable to use a silicon nitride film for the insulating layer 235a and a silicon oxide film for the insulating layer 235b, or to use a silicon oxide film for the insulating layer 235a and a silicon nitride film for the insulating layer 235b.

[0189] Furthermore, a low-k material, particularly an inorganic material with a low dielectric constant, may be used for the layer that constitutes the insulating layer 235. For example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide may be used. Furthermore, TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ ) can be used.

[0190] In the transistor 202A, an example is shown in which the insulating layer 235a is provided in contact with the bottom and side surfaces of the recess of the conductive layer 220b, and the insulating layer 235b is provided over the insulating layer 235a. For example, an insulating film to be the insulating layer 235a and an insulating film to be the insulating layer 235b are stacked, and then the two insulating films are processed to form the insulating layer 235a and the insulating layer 235b having the structure shown in FIG. 10. Therefore, it can be said that this structure can be manufactured relatively easily.

[0191] In the transistor 202A, at least one layer constituting the conductive layer 260 is provided in the opening 290. When the conductive layer 260 has a stacked structure, it becomes more difficult to arrange all of the layers constituting the conductive layer 260 in the opening 290 as the transistor 202A is miniaturized and the diameter of the opening 290 becomes smaller.

[0192] By providing a recess in the conductive layer 220b at a position overlapping with the opening 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be lower than the height of the top surface of the conductive layer 220b in contact with the insulating layer 280c relative to the top surface of the insulating layer 140, as compared to a case where the recess is not provided. This makes it easier to apply a gate electric field to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 202A. Furthermore, since a gate electric field is also easier to apply to the region of the oxide semiconductor layer 230 in contact with the conductive layer 220b, the on-state current of the transistor 202A can be increased. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 202A can be improved. Here, the height of each surface can be determined based on the surface where a memory cell or a transistor is to be formed. Here, the top surface of the insulating layer 140 is used as the reference. The surface used as the reference is not limited to the surface where a memory cell or a transistor is to be formed. For example, the top surface of a substrate on which a transistor, memory cell, or storage device is provided may be used as a reference.

[0193] The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recesses of the conductive layer 220b and the top surface of the conductive layer 240b. The recesses in the conductive layer 220b can increase the area over which the oxide semiconductor layer 230 is in contact with the conductive layer 220b. This can reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b. This can suppress a decrease in the on-state current of the transistor 202A due to the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230.

[0194] The conductive layer 220b is preferably formed using a conductive material containing oxygen, which can reduce contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b.

[0195] When the conductive layer 220 and the conductive layer 240 have a stacked structure, it is preferable to use a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, because this can reduce contact resistance with the oxide semiconductor layer 230. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240b, for example.

[0196] Alternatively, when the conductive layer 220 and the conductive layer 240 have a stacked structure, a conductive material containing oxygen is used for a layer of the stacked structure that is closest to a channel formation region, and the contact resistance with the oxide semiconductor layer 230 is reduced, thereby shortening the current path between the source and the drain, and thereby increasing the on-state current of the transistor. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240a, for example.

[0197] As the conductive material containing oxygen, it is preferable to use a metal oxide having conductivity (also called an oxide conductor).

[0198] 10 and other figures show an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240b and a material having higher conductivity than the conductive layer 240b for the conductive layer 240a. Specifically, for example, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) for the conductive layer 240b and tungsten for the conductive layer 240a. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like may be used for the conductive layer 240a.

[0199] Of the conductive layer 240, the layer that is mainly in contact with the oxide semiconductor layer 230 is the conductive layer 240b. Using an oxide conductor for the conductive layer 240b is preferable because contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, using a material having higher conductivity than an oxide conductor for the layer that constitutes the conductive layer 240 is preferable because the conductivity of the conductive layer 240 can be increased.

[0200] Note that a conductive material containing oxygen can be used for the conductive layer 240a, and a material having higher conductivity than that of the conductive layer 240a can be used for the conductive layer 240b. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor can be increased.

[0201] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 165, a highly conductive material for the conductive layer 220a, and a conductive material containing oxygen (more preferably, an oxide conductor) for the conductive layer 220b. Specifically, for example, it is preferable to use titanium nitride for the conductive layer 165, tungsten for the conductive layer 220a, and an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) for the conductive layer 220b. In this case, titanium nitride is in contact with the insulating layer 185, and the oxide conductor is in contact with the oxide semiconductor layer 230. Furthermore, the oxide conductor is used in the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared to tungsten, the oxide conductor has lower contact resistance with the oxide semiconductor layer 230, which shortens the current path between the source and drain, thereby increasing the on-current of the transistor 202A. With this structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide semiconductor layer 230. When an oxide insulating layer is used for the insulating layer 185, excessive oxidation of the conductive layer 220 can be suppressed by the insulating layer 185. When a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220a, the conductivity of the conductive layer 220 can be increased.

[0202] The conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Figure 10 and other figures show an example in which the conductive layer 265 has a two-layer structure including a conductive layer 265a and a conductive layer 265b over the conductive layer 265a. In this case, for example, it is preferable to use titanium nitride as the conductive layer 265a and tungsten as the conductive layer 265b. Alternatively, it is preferable to use tantalum nitride as the conductive layer 265a and copper as the conductive layer 265b. With such a structure, the conductivity of the conductive layer 265 can be increased.

[0203] The conductive layer 265 may also have a stacked structure of three or more layers, such as a three-layer structure of tantalum nitride, titanium nitride on the tantalum nitride, and tungsten on the titanium nitride.

[0204] 10 and the like illustrate a structure in which the end portions of the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230 are aligned outside the opening 290. The conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because the number of masks required for manufacturing the memory device can be reduced. Note that the present invention is not limited to this. For example, a structure may be employed in which any one of the end portions of the oxide semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b is located closer to or closer to the other in the X direction or the Y direction. Note that the same applies to the conductive layer 145 and the oxide semiconductor layer 135.

[0205] When the side surfaces of insulating layer 280c, insulating layer 280g, insulating layer 280e, conductive layer 255, insulating layer 280f, insulating layer 280b, insulating layer 280d, conductive layer 240a, and conductive layer 240b are aligned in the opening 290, it is possible to make uniform the film thickness distribution of the insulating layer 235, the oxide semiconductor layer 230, and the like provided inside the opening 290. Furthermore, it is possible to prevent the insulating layer 235, the oxide semiconductor layer 230, and the like from being divided by a step or the like generated on the side wall of the opening 290.

[0206] 10 and other figures show a configuration in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280d in the opening 290 are flush (or can be said to be aligned or approximately aligned), but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280d in the opening 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280d in the opening 290 may differ from each other. In this case, for example, it is preferable that the taper angle of the side surface of the conductive layer 240 in the opening 290 is smaller than the taper angle of the side surface of the insulating layer 280d in the opening 290. With this configuration, the coverage of the oxide semiconductor layer 230 on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. The insulating layers 280b to 280g may have different inclinations of the side surfaces of the layers in the opening 290. When the conductive layer 240 has a stacked structure, the insulating layers 280b to 280g may have different inclinations of the side surfaces of the layers in the opening 290.

[0207] 10 and 11 , the insulating layer 161c, the insulating layer 161a, the insulating layer 161d, the conductive layer 145a, and the conductive layer 145b have openings 190 that reach the conductive layer 120. Note that for details of the openings 190 and the layers in which the openings 190 are provided, the above-described descriptions of the openings 290 and the layers in which the openings 290 are provided can be referred to.

[0208] The conductive layer 120 includes a conductive layer 120a, a conductive layer 120b on the conductive layer 120a, and a conductive layer 120c on the conductive layer 120b, and the conductive layer 120c is provided with a recess.

[0209] The opening 190 overlaps with the recess of the conductive layer 120c. The shape and size of the opening 190 in a plan view may differ depending on the layer. When the top surface shape of the opening 190 is circular, the openings in each layer may or may not be concentric.

[0210] At least some of the components of the transistor 201A are disposed in the opening 190. Specifically, at least some of the oxide semiconductor layer 135, the insulating layer 151, and the conductive layer 164 are disposed in the opening 190.

[0211] 10 and other drawings, the oxide semiconductor layer 135 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220, and is also in contact with the side surfaces of the insulating layer 161c, the insulating layer 161a, the insulating layer 161d, the conductive layer 145a, and the conductive layer 145b within the opening 190. The insulating layer 151 is located inside the oxide semiconductor layer 135 within the opening 190, and the conductive layer 164 is located inside the insulating layer 151 within the opening 190.

[0212] When the side surfaces of the insulating layer 161c, the insulating layer 161a, the insulating layer 161d, the conductive layer 145a, and the conductive layer 145b are aligned in the opening 190, the oxide semiconductor layer 135 and the like provided in the opening 190 can have a uniform film thickness distribution. Furthermore, the oxide semiconductor layer 135 and the like can be prevented from being divided by a step or the like generated on the sidewall of the opening 190.

[0213] The oxide semiconductor layer 135 is provided along the sidewall of the opening 190. Furthermore, the portions of the oxide semiconductor layer 135 and the insulating layer 151 that are disposed within the opening 190 are provided to reflect the shape of the opening 190. Then, the conductive layer 164 is provided so as to fill at least a portion of the recess of the insulating layer 151 that reflects the shape of the opening 190.

[0214] In the transistor 201A, at least one layer constituting the conductive layer 164 is provided in the opening 190. When the conductive layer 164 has a stacked structure, it becomes more difficult to arrange all of the layers constituting the conductive layer 164 in the opening 190 as the transistor 201A is miniaturized and the diameter of the opening 190 becomes smaller.

[0215] As in the transistor 202A, when the conductive layer 120c has a recess at a position overlapping with the opening 190, a gate electric field can be more easily applied to a channel formation region of the oxide semiconductor layer 135 than when the conductive layer 120c does not have the recess, and the electrical characteristics of the transistor 201A can be improved. Furthermore, since a gate electric field can be more easily applied to a region of the oxide semiconductor layer 135 in contact with the conductive layer 120c, the on-state current of the transistor 201A can be increased. Furthermore, the electrical characteristics of the transistor 201A can be improved regardless of whether the conductive layer 120 or the conductive layer 145 is used for the drain electrode.

[0216] The oxide semiconductor layer 135 is in contact with the bottom surface and side surfaces of the recessed portion of the conductive layer 120c and the top surface of the conductive layer 145b. The recessed portion of the conductive layer 120c can increase the area where the oxide semiconductor layer 135 is in contact with the conductive layer 120c. This can reduce the contact resistance between the oxide semiconductor layer 135 and the conductive layer 120c. This can suppress a decrease in the on-state current of the transistor 201A due to the contact resistance between the conductive layer 120c and the oxide semiconductor layer 135.

[0217] The conductive layer 145a is preferably formed using a material suitable for the conductive layer 240a. The conductive layer 145b is preferably formed using a material suitable for the conductive layer 240b.

[0218] Furthermore, the three-layer structure of the conductive layers 120a to 120c preferably has a structure suitable for the three-layer structure of the conductive layer 165, the conductive layer 220a, and the conductive layer 220b. In this case, the current path between the source and drain of the transistor 201A can be shortened, and the on-state current can be increased. Moreover, the insulating layer 140 can prevent the conductive layer 120 from being excessively oxidized. Furthermore, the conductivity of the conductive layer 120 can be increased.

[0219] The transistor 201A and the transistor 202A each include a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in an oxide semiconductor layer (the oxide semiconductor layer 135 or the oxide semiconductor layer 230) including a channel formation region. That is, the transistor 201A and the transistor 202A can each be referred to as an OS transistor.

[0220] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate, and reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0221] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or impurities such as hydrogen, nitrogen, or a metal element.

[0222] As described above, the oxide semiconductor layer 230 is provided inside the opening 290. In addition, the transistor 202A has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, and thus, a current flows vertically. In other words, a channel is formed along the side surface of the opening 290.

[0223] In a plan view, the conductive layer 255 surrounds the entire outer periphery of the oxide semiconductor layer 230 via the insulating layer 235. Furthermore, the oxide semiconductor layer 230 surrounds the entire outer periphery of the conductive layer 260 located in the opening 290 via the insulating layer 250. Therefore, the channel formation region of the transistor 202A can be formed on the entire outer surface of the oxide semiconductor layer 230 within the opening 290 (the entire region in contact with the insulating layer 235). In this case, for example, the channel width of the transistor 202A is determined by the outer periphery of the oxide semiconductor layer 230. That is, the channel width of the transistor 202A can be determined by the width of the opening 290 (the diameter when the opening 290 is circular in a plan view). Increasing the width of the opening 290 increases the channel width per unit area, thereby increasing the on-state current.

[0224] The width of the opening 290 may vary in the depth direction. Here, the width is particularly defined as the shortest distance between the two side surfaces of the conductive layer 255 on the opening 290 side in a cross-sectional view. In other words, the minimum width of the opening 290 in the conductive layer 255 is used as the width of the opening 290. Alternatively, the width of the opening 290 at the highest position in the conductive layer 255, the width of the opening 290 at the lowest position, the width of the opening 290 at a midpoint between these, or the average of these three widths may be used as the width of the opening 290. The method for determining the width of the opening 290 is not particularly limited. For example, the shortest distance between the two side surfaces on the opening 290 side of any layer in which the opening 290 is provided may be used as the width of the opening 290. Alternatively, the width of the opening 290 at the highest position in any layer in which the opening 290 is provided, the width of the opening 290 at the lowest position, the width of the opening 290 at a midpoint between these, or the average of these three widths may be used as the width of the opening 290.

[0225] When the opening 290 is formed using photolithography, the width of the opening 290 is limited by the exposure limit of photolithography. The width of the opening 290 is set depending on the film thickness of each of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0226] The channel length L of the transistor 202A is preferably at least shorter than the channel width W of the transistor 202A. The channel length L of the transistor 202A is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 202A. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0227] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. As a result, the distance between the conductive layer 255 and the oxide semiconductor layer 230 and the distance between the conductive layer 260 and the oxide semiconductor layer 230 are each approximately uniform, and therefore, a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0228] Although the present embodiment illustrates an example in which the opening 290 is circular in plan view, the present invention is not limited thereto. In plan view, the opening 290 may be, for example, a circle, an approximately circular shape such as an oval, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 9C and other figures, the opening 290 is preferably circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. In this specification and other documents, a circle is not limited to a perfect circle.

[0229] The channel length of the transistor 202A can be considered to be the distance between the source region and the drain region, that is, the channel length of the transistor 202A can be determined by the thicknesses of the insulating layers 280c, 280g, 280e, the conductive layer 255, the insulating layer 280f, the insulating layer 280b, and the insulating layer 280d on the conductive layer 220.

[0230] The transistor 202A includes the conductive layer 255 that functions as a back gate, and therefore the threshold voltage of the transistor 202A can be controlled by the potential applied to the conductive layer 255. In this case, a portion of the oxide semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween is most susceptible to the influence of the conductive layer 255.

[0231] At least a region of the oxide semiconductor layer 230 which overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween and with the conductive layer 265a with the insulating layer 250 interposed therebetween can be referred to as a channel formation region. The channel formation region is preferably controlled to have high resistance by a potential applied to the conductive layer 255.

[0232] A region in contact with the conductive layer 240b or the conductive layer 220b and its vicinity in the oxide semiconductor layer 230 can be referred to as a source region or a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region.

[0233] In a planar transistor, the channel length is limited by the exposure limit of photolithography. However, in one embodiment of the present invention, the channel length can be set by the film thickness of a part of the layer in which the opening 290 is provided. Therefore, the channel length of the transistor 202A can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 202A, thereby improving its frequency characteristics.

[0234] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. This allows the transistor 202A to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for higher integration of the memory device. Furthermore, the memory capacity per unit area of ​​the memory device can be increased.

[0235] For details about the channel width and channel length of the transistor 201A, the description of the transistor 202A can be referred to. The channel width of the transistor 201A can be determined by the width of the opening 190. The width of the opening 190 is set by the film thicknesses of the oxide semiconductor layer 135, the insulating layer 151, and the conductive layer 164, which are provided in the opening 190. The channel length of the transistor 201A can be determined by the thicknesses of the insulating layer 161c, the insulating layer 161a, the insulating layer 161d, and the like over the conductive layer 120c.

[0236] The memory cell 150 shown in FIG. 12 differs from the memory cell 150 shown in FIG. 10 in that it does not have a transistor 201A but has a transistor 201B.

[0237] The transistor 201B differs from the transistor 201A in that the transistor 201B includes an insulating layer 131 .

[0238] As shown in FIG. 12 , the transistor 202A includes an insulating layer 235 that functions as a back-gate insulating layer. The transistor 201B shown in FIG. 12 is a transistor without a back-gate but may include a layer corresponding to the insulating layer 235. That is, the insulating layer 131 may be provided on the sidewall of the opening 190 using a material and a manufacturing method similar to those of the insulating layer 235. When the insulating layer 131 is not provided, the oxide semiconductor layer 135 is in contact with the insulating layers 161a, 161c, and 161d inside the opening 190. On the other hand, when the insulating layer 131 is provided, the oxide semiconductor layer 135 is in contact with only the insulating layer 131 inside the opening 190. The insulating layer 131 can supply oxygen to the oxide semiconductor layer 135, suppress diffusion of hydrogen into the oxide semiconductor layer 135, control the channel length, and the like.

[0239] The memory cell 150 shown in FIG. 13 differs from the memory cell 150 shown in FIG. 10 in that it does not have a transistor 201A but has a transistor 201C.

[0240] The transistor 201C differs from the transistor 201A in that the transistor 201C includes a conductive layer 155 and an insulating layer 131 .

[0241] In the transistor 201C, the conductive layer 155 functions as a second gate electrode, and the insulating layer 131 functions as a second gate insulating layer.

[0242] It is preferable that the conductive layer 164 function as a gate electrode and the conductive layer 155 function as a back gate electrode. By using the conductive layer 164, which has a wider region facing the oxide semiconductor layer 135 than the conductive layer 155, as a gate, a gate electric field is applied to the oxide semiconductor layer 135 more efficiently, which may improve the electrical characteristics of the transistor 201C. In this case, the insulating layer 151 functions as a gate insulating layer and the insulating layer 131 functions as a back gate insulating layer. Note that the conductive layer 164 may function as a back gate electrode and the conductive layer 155 may function as a gate electrode.

[0243] An insulating layer 161e is provided over the insulating layer 161a, a conductive layer 155 is provided over the insulating layer 161e, an insulating layer 161f is provided so as to cover the top surface and side surfaces of the conductive layer 155, and an insulating layer 161b is provided over the insulating layer 161f. An opening 190 is provided in the insulating layer 161e, the insulating layer 161f, and the conductive layer 155. An insulating layer 131 is provided along a sidewall of the opening 190, and an oxide semiconductor layer 135 is provided so as to be in contact with the insulating layer 131. The circuit diagram of the memory cell 150 shown in FIG. 13 corresponds to FIG. 9B .

[0244] The shortest distance from the top surface of the conductive layer 220b to the bottom surface of the conductive layer 255 is preferably shorter than the shortest distance from the top surface of the conductive layer 155 to the bottom surface of the conductive layer 145. Furthermore, the shortest distance from the top surface of the conductive layer 220b to the bottom surface of the conductive layer 255 is preferably shorter than the shortest distance from the top surface of the conductive layer 120 to the bottom surface of the conductive layer 155. This can increase the capacitance value of the capacitor 203A. Furthermore, the parasitic capacitance generated between the conductive layer 155 and the conductive layer 145 and the parasitic capacitance generated between the conductive layer 120 and the conductive layer 155 can be reduced.

[0245] The memory cell 150 shown in FIG. 14 differs from the memory cell 150 shown in FIG. 10 in that the memory cell 150 does not include a transistor 202A and a capacitor 203A, but includes a transistor 202B and a capacitor 203B.

[0246] In the transistor 202B and the capacitor 203B, the only layer located between the conductive layer 220b and the conductive layer 255 is the insulating layer 280g. Reducing the thickness of the layer located between the conductive layer 220b and the conductive layer 255 is preferable because it can increase the capacitance of the capacitor 203B. On the other hand, as memory devices become smaller and more highly integrated, thinner dielectrics used in capacitors may cause problems such as leakage current in the transistor and the capacitor. In this case, it may be preferable to provide not only the insulating layer 280g but also one or both of the insulating layer 280c and the insulating layer 280a between the conductive layer 220b and the conductive layer 255. Furthermore, providing not only the insulating layer 280g but also one or both of the insulating layer 280c and the insulating layer 280a may further prevent impurities from being mixed into the oxide semiconductor layer 230 and prevent the amount of oxygen in the oxide semiconductor layer 230 from becoming insufficient or excessive.

[0247] The memory cell 150 shown in FIG. 15 differs from the memory cell 150 shown in FIG. 14 in that it does not have the conductive layer 165 and the insulating layer 185 .

[0248] The memory cell 150 shown in FIG. 15 does not have the conductive layer 165 and the insulating layer 185, and therefore the number of manufacturing steps can be reduced compared to the memory cell 150 shown in FIG.

[0249] 15 shows an example in which the ends of the conductive layer 164, the conductive layer 220a, and the conductive layer 220b are aligned. A conductive film to be the conductive layer 164, the conductive film to be the conductive layer 220a, and the conductive film to be the conductive layer 220b are formed in this order, and these three conductive films are processed using the same mask, whereby the conductive layer 164, the conductive layer 220a, and the conductive layer 220b shown in FIG.

[0250] The conductive layer 164, the conductive layer 220a, and the conductive layer 220b function as one of the source electrode and drain electrode of the transistor 202B and as the gate electrode of the transistor 201A, so that the transistors 201A and 202B share part of their structures. With this structure, the transistors 201A and 202B can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cells 150, thereby enabling the memory cells 150 to be arranged at high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0251] The memory cell 150 shown in FIG. 16 differs from the memory cell 150 shown in FIG. 15 in that it does not have the transistor 202B but has the transistor 202C.

[0252] Transistor 202C differs from transistor 202B primarily in that conductive layer 220b has only one recess.

[0253] A recess may be formed in the conductive layer 220b in one or both of the steps of forming the opening 290 and forming the insulating layer 235. Transistor 202B illustrates an example in which a recess is formed in the conductive layer 220b in both steps, whereas transistor 202C illustrates an example in which a recess is not formed in the conductive layer 220b in the step of forming the opening 290, but is formed in the step of forming the insulating layer 235.

[0254] In the transistor 202C, the insulating layer 235 is in contact with the side surfaces of the insulating layer 280g, the conductive layer 255, the insulating layer 280f, the insulating layer 280b, the insulating layer 280d, the conductive layer 240, and the top surface of the conductive layer 220b within the opening 290. The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recess of the conductive layer 220b.

[0255] When a recess is formed in the conductive layer 220b in at least one of the steps of forming the opening 290 and forming the insulating layer 235, the height of the bottom surface of the conductive layer 260 in the opening 290 can be reduced, making it easier for a gate electric field to be applied to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 202A.

[0256] When a recess is formed in the conductive layer 220b in the process of forming the insulating layer 235, the oxide semiconductor layer 230 can be in contact with the bottom and side surfaces of the recess in the conductive layer 220b, the contact area between the oxide semiconductor layer 230 and the conductive layer 220b is increased, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced, which is preferable.

[0257] 17A to 17C show examples of plan views of the capacitor element 203. FIG.

[0258] 17A shows an example in which the center of the conductive layer 220, the center of the opening 190 and the opening 290, and the center of a region (also referred to as an intersection) where the conductive layer 255 and the conductive layer 145 intersect with each other are all aligned (i.e., at the same position) in a plan view. With such a structure, the capacitor 203 can be provided without increasing the area occupied by the memory cell including the transistor 201 and the transistor 202 in a plan view, which is preferable.

[0259] For example, the plan view of the capacitor element 203B in the memory cell 150 shown in FIGS. 10 to 16 corresponds to FIG. 17A.

[0260] The center of the conductive layer 220 may be located at a position different from either or both of the center of the opening 190 and the center of the opening 290. The center of the conductive layer 220 may also be located at a position different from the center of the intersection of the conductive layer 255 and the conductive layer 145. Therefore, it is possible to reduce the manufacturing cost of the memory cell 150 and suppress a decrease in yield, to the extent that the integration degree is not significantly reduced.

[0261] Figure 17B shows an example in which, in a planar view, the centers of openings 190 and 290 and the center of the intersection between conductive layer 255 and conductive layer 145 are at the same position, and the center of conductive layer 220 is at a different position.

[0262] For example, the plan view of the capacitive element 203C in the memory cell 150 shown in FIG. 18 corresponds to FIG. 17B.

[0263] 18 has a structure in which a conductive layer 220b, an insulating layer 280g, and a conductive layer 255 are stacked in this order. In the cross-sectional view of FIG. 18, the region of the capacitor 203C located to the right of the conductive layer 260 is larger than the region located to the left of the conductive layer 260. For example, the structure shown in FIG. 17B can be intentionally fabricated, or the structure shown in FIG. 17B may be fabricated as a result of misalignment during the process of fabricating the structure shown in FIG. 17A.

[0264] 17C shows an example in which the center of opening 190 and the center of opening 290 are at different positions in a plan view. Also, Fig. 17C shows an example in which the center of opening 190 and the center of the intersection between conductive layer 255 and conductive layer 145 are at the same position, and the center of opening 290 and the center of conductive layer 220 are at the same position.

[0265] For example, the plan view of the capacitive element 203C in the memory cell 150 shown in FIG. 19 corresponds to FIG. 17C.

[0266] 19 has a configuration in which a conductive layer 220b, an insulating layer 280g, and a conductive layer 255 are stacked in this order. In a cross-sectional view, the region of the capacitor 203C located to the left of the conductive layer 260 is larger than the region located to the right of the conductive layer 260.

[0267] 17C , when the centers of openings 190 and 290 are at different positions in a plan view, the contact portion between oxide semiconductor layer 230 and conductive layer 220b is less susceptible to the influence of recesses that are generated in conductive layer 164, conductive layer 220a, etc. due to opening 190 in a cross-sectional view as shown in FIG. 19 . Therefore, poor connection between transistor 201A and transistor 202B can be suppressed.

[0268] The memory cell 150 shown in FIGS. 18 and 19 has the same configuration as the memory cell 150 shown in FIG. 15 except for the portions described above, and therefore detailed description thereof will be omitted.

[0269] The memory cell shown in FIG. 20 differs from the memory cell 150 shown in FIG. 14 in that the memory cell does not include the transistor 201A, the transistor 202B, and the capacitor 203B, but includes the transistor 201D, the transistor 202D, and the capacitor 203D.

[0270] In the transistor 201D, the conductive layer 164 does not overlap with a top surface of the conductive layer 145. This can reduce parasitic capacitance generated between the conductive layer 164 and the conductive layer 145.

[0271] The insulating layer 151 and the conductive layer 164 are provided to fill openings provided in the insulating layer 183 and the insulating layer 185. The upper surface of the conductive layer 164 is exposed in the openings, and the conductive layer 165 is provided to be in contact with the conductive layer 164.

[0272] The conductive layer 165, the conductive layer 220a, and the conductive layer 220b are embedded in openings provided in the insulating layer 280c and the insulating layer 280a. Specifically, the conductive layer 165 is provided along the side and bottom surfaces of the openings, the conductive layer 220a is provided in contact with the bottom surface of the recess in the conductive layer 165, and the conductive layer 220b is provided on the conductive layer 220a. Since the top surfaces of the insulating layer 183, the insulating layer 185, the insulating layer 151, and the conductive layer 164 are planarized, they are less susceptible to the influence of recesses that are generated in the conductive layer 165, the conductive layer 220a, the conductive layer 220b, etc. due to the opening 190. Therefore, poor connection between the transistor 201D and the transistor 202D can be suppressed.

[0273] The capacitor 203D has a region where the insulating layer 280g is located between the conductive layer 220b and the conductive layer 255, and a region where the insulating layer 280g is located between the conductive layer 165 and the conductive layer 255.

[0274] 20 , an insulating layer 285 is provided over the conductive layer 260, a conductive layer 265a and a conductive layer 265b over the conductive layer 265a are embedded in an opening 270 provided in the insulating layer 285, and a conductive layer 266 functioning as a gate wiring is provided over the insulating layer 285. The conductive layer 265a is in contact with the conductive layer 260 through the opening provided in the insulating layer 285. The conductive layer 266 is electrically connected to the conductive layer 260 through the conductive layer 265a and the conductive layer 265b. Even with this structure, the parasitic capacitance generated between the gate wiring and the conductive layer 240 can be reduced.

[0275] <Modifications of Transistors> The sidewalls of the openings 290 in the transistors 202A to 202D may be tapered. The sidewalls of the openings 190 in the transistors 201A to 201D may be tapered.

[0276] FIG. 21A is a cross-sectional view of a transistor 202E. FIG. 21A illustrates an example in which the sidewall of the opening 290 has a tapered shape. Tapering the sidewall of the opening 290 improves coverage with the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the like, thereby reducing defects such as voids. When the sidewall of the opening 290 has a tapered shape, for example, the taper angle θ280 of the side surface of the insulating layer 280g in the opening 290 is preferably 45 degrees or greater and less than 90 degrees. Specifically, a taper angle θ280 of 80 degrees or greater and less than 90 degrees is preferable because it allows for miniaturization or high integration of the memory device. Furthermore, a taper angle θ280 of 45 degrees or greater, or 50 degrees or greater and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable because it improves coverage with a film formed in the opening 290.

[0277] Alternatively, for example, the sidewall of the opening 290 may have a reverse tapered shape. In other words, the taper angle θ280 of the side surface of the insulating layer 280g in the opening 290 may be greater than 90 degrees. Similarly, the sidewall of the opening 190 may have a reverse tapered shape.

[0278] <Constituent Materials of Memory Device> Materials that can be used in the memory device of this embodiment will be described below. Note that descriptions of components that have already been described may be omitted. In addition, each layer that constitutes the memory device of this embodiment may have a single-layer structure or a stacked structure.

[0279] [Oxide Semiconductor Layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0280] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0281] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is low, the power consumption of a memory device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the memory device can operate at high speed.

[0282] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor of one embodiment of the present invention, refer to the description in Embodiment 3. Detailed description thereof will be omitted here.

[0283] Note that the memory device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region. Examples of such another semiconductor material include semiconductors made of a single element and compound semiconductors. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the above-mentioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0284] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0285] The semiconductor layer of a transistor may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0286] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0287] [Insulating Layer] An inorganic insulating film is preferably used for each of the insulating layers (insulating layer 131, insulating layer 140, insulating layer 151, insulating layers 161a to 161f, insulating layer 183, insulating layer 185, insulating layer 250, insulating layer 235, insulating layers 280a to 280g, insulating layer 285, etc.) included in the memory device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in the memory device may be an organic insulating film.

[0288] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0289] Examples of high-dielectric-constant (high-k) materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0290] Examples of low-k materials include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of low-k inorganic insulating materials include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Other examples include silicon oxide having vacancies. These silicon oxides may contain nitrogen. TEOS may also be used.

[0291] Furthermore, a material that can have ferroelectricity may be used for the insulating layer of the storage device. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. Ferroelectric materials include hafnium ... (here, element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0292] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0293] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0294] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal nitride oxides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0295] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0296] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of memory devices can be achieved.

[0297] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0298] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to manifest ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals with an orthorhombic crystal structure is preferred because it manifests ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystals. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0299] Furthermore, adding a Group 3 element (also referred to as a IIIa element) in the periodic table to an oxide containing one or both of hafnium and zirconium increases the concentration of oxygen vacancies in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide and make it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0300] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0301] Specifically, examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride.

[0302] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that are likely to have a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0303] Since the insulating layer 140 functions as an interlayer film, it is preferable that the insulating layer 140 has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 140.

[0304] The concentration of impurities such as water and hydrogen in the insulating layer 140 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 135.

[0305] A barrier insulating layer against hydrogen is preferably used as the insulating layer 140. When the insulating layer 140 has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed.

[0306] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0307] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0308] For example, it is preferable to use a silicon nitride film as the insulating layer 140 .

[0309] At least an insulating layer 280g is provided between the conductive layer 220b and the conductive layer 255. The insulating layer 280g functions as a dielectric layer of the capacitor element.

[0310] The insulating layer 280g is preferably made of the aforementioned high-k material. For example, the insulating layer 280g preferably has a layered structure of a high-k insulating material, more preferably a layered structure of a high-k material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 280g can be made of an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating layer 280g can be made of an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order. Alternatively, the insulating film can be made of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved and electrostatic breakdown of the capacitor element can be suppressed. The insulating layer 280g is preferably made of the aforementioned ferroelectric material.

[0311] The insulating layer 161a, the insulating layer 161b, the insulating layer 280a, and the insulating layer 280b each preferably include the above-described oxide insulating film, oxynitride insulating film, or insulating layer having a region containing excess oxygen.

[0312] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method in which hydrogen-containing molecules are not used as a deposition gas, the hydrogen concentration in the insulating layer can be reduced. By forming the insulating layers 161a and 161b in this manner, oxygen can be supplied from the insulating layers 161a and 161b to the channel formation region of the oxide semiconductor layer 135, thereby reducing oxygen vacancies and VoH. Similarly, by forming the insulating layers 280a and 280b, oxygen can be supplied from the insulating layers 280a and 280b to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0313] The concentrations of impurities such as water and hydrogen in the insulating layer 161a, the insulating layer 161b, the insulating layer 280a, and the insulating layer 280b are preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation regions of the oxide semiconductor layer 135 and the oxide semiconductor layer 230.

[0314] Furthermore, it is preferable to use a material with a low dielectric constant for each of the insulating layers 161a, 161b, 280a, and 280b. This reduces parasitic capacitance between wirings. For example, silicon oxide or silicon oxynitride can be used for each of the insulating layers 161a, 161b, 280a, and 280b.

[0315] The insulating layers 161c to 161f and the insulating layers 280c to 280f each preferably include the above-described barrier insulating layer against hydrogen, and more preferably include one or both of an aluminum oxide film and a silicon nitride film. The insulating layers 161c to 161f have a barrier property against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer 135. The insulating layers 280c to 280f have a barrier property against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer 230.

[0316] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layers 161c to 161f, oxygen can be extracted from the oxide semiconductor layer 135, which can prevent excessive oxygen vacancies from being formed in the oxide semiconductor layer 135. Furthermore, by using silicon nitride for the insulating layers 161c to 161f, excessive oxygen can be prevented from being supplied to the oxide semiconductor layer 135. Therefore, excessive oxygen can be prevented from being contained in the channel formation region of the oxide semiconductor layer 135, which can improve the reliability of the transistor 201. Similarly, by using silicon nitride for the insulating layers 280c to 280f, oxygen can be extracted from the oxide semiconductor layer 230, which can prevent excessive oxygen vacancies from being formed in the oxide semiconductor layer 230. Furthermore, excessive oxygen can be prevented from being supplied to the oxide semiconductor layer 230. Therefore, excessive oxygen can be prevented from being contained in the channel formation region of the oxide semiconductor layer 230, which can improve the reliability of the transistor 202.

[0317] For example, it is preferable to use a silicon oxide film as the insulating layers 161a and 161b, and a silicon nitride film or an aluminum oxide film as the insulating layers 161c to 161f, respectively.

[0318] For example, it is preferable to use a silicon oxide film as the insulating layers 280a and 280b, and a silicon nitride film or an aluminum oxide film as the insulating layers 280c to 280f, respectively.

[0319] The insulating layer 151 and the insulating layer 250 each function as a gate insulating layer of a transistor, and therefore, similar materials can be used for them. Although the insulating layer 250 will be mainly used as an example below, the insulating layer 151 can also be used for them. In addition, the insulating layer 131 and the insulating layer 235 also function as a gate insulating layer or a back-gate insulating layer of a transistor, and therefore, the materials that can be used for the insulating layer 250 can also be used for them.

[0320] The insulating layer 250 preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor). Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0321] Examples of materials for insulating layers capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adsorb hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used. Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0322] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0323] When the gate insulating layer has a stacked-layer structure, a layer in contact with the oxide semiconductor layer 230 preferably has a function of capturing and fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. For example, hafnium silicate or the like may be used as the layer of the insulating layer 250 in contact with the oxide semiconductor layer 230. In addition, the layer preferably has an amorphous structure.

[0324] By making the layer amorphous, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the layer. This makes the film thickness distribution of the insulating layer 250 uniform, and it is possible to reduce portions with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer 250. It is also possible to make the film thickness distribution of the film provided on the insulating layer 250 uniform.

[0325] Furthermore, by suppressing the formation of grain boundaries in the layer, leakage current due to defect levels in the grain boundaries can be reduced, and the insulating layer 250 can function as an insulating film with low leakage current.

[0326] Furthermore, since hafnium oxide is a high dielectric constant (high-k) material, hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0327] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0328] The above-described barrier insulating layer against hydrogen is preferably used as the insulating layer 250. By using a barrier insulating layer against hydrogen for the insulating layer 250, diffusion of impurities contained in the conductive layer 265 into the oxide semiconductor layer 230 can be suppressed. For example, silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 250. Furthermore, the insulating layer 250 may include an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0329] With such a structure, a transistor having good electrical characteristics can be provided, a transistor having a large on-state current can be provided, a memory device with little variation in the electrical characteristics of the transistor can be provided, and a memory device with high reliability can be provided.

[0330] Additionally, insulating layer 250 may comprise an insulating layer of a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0331] Furthermore, the insulating layer 250 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0332] The insulating layer 250 preferably has a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 240, the conductive layer 265, and the like. When the insulating layer 250 has a stacked structure, a layer in contact with the conductive layer 240 is preferably a barrier insulating layer against oxygen. In particular, among the layers constituting the insulating layer 250, a layer in contact with the conductive layer 240 and a layer in contact with the conductive layer 265 are preferably barrier insulating layers against oxygen.

[0333] The use of a barrier insulating layer against hydrogen and oxygen for a layer of the insulating layer 250 that is in contact with the conductive layer 265 can suppress oxidation of the conductive layer 265. Furthermore, oxygen contained in the oxide semiconductor layer 230 can be prevented from diffusing into the conductive layer 265, which can suppress formation of oxygen vacancies in the oxide semiconductor layer 230.

[0334] Examples of the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0335] The layer of the insulating layer 250 in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280b. The layer has oxygen barrier properties, which can prevent the side surfaces of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 202A.

[0336] Each layer constituting the insulating layer 250 is preferably a thin film. For example, by setting the thickness of each insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0337] The thickness of each layer constituting the insulating layer 250 is preferably more than 0 nm and not more than 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0338] The insulating layer 250 preferably has a three-layer structure in which, from the oxide semiconductor layer 230 side, a first insulating layer containing a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and an insulating layer having a barrier property against hydrogen and oxygen are stacked in this order. Silicon oxide or silicon oxynitride is preferably used as the material with a low dielectric constant for the first insulating layer. The first insulating layer is a layer in contact with the oxide semiconductor layer 230. By using oxide for the first insulating layer, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, by providing a third insulating layer, oxygen contained in the first insulating layer can be prevented from diffusing into the conductive layer 265, thereby preventing oxidation of the conductive layer 265. Furthermore, a decrease in the amount of oxygen supplied from the first insulating layer to the oxide semiconductor layer 230 can be prevented.

[0339] 21B and 21C show examples of enlarged views of the insulating layer 250 of the transistor 202A and the surrounding area. Fig. 21B shows an example in which the insulating layer 250 has a four-layer structure, and Fig. 21C shows an example in which the insulating layer 250 has a three-layer structure.

[0340] 21B , the insulating layer 250 preferably has a four-layer structure in which, from the oxide semiconductor layer 230 side, a fourth insulating layer (insulating layer 250d) having a barrier property against oxygen, a first insulating layer (insulating layer 250a) made of a material with a low dielectric constant, a second insulating layer (insulating layer 250b) having a function of capturing or fixing hydrogen, and a third insulating layer (insulating layer 250c) having a barrier property against hydrogen and oxygen are stacked in this order. The first to third insulating layers can have a structure similar to that of the layers used in the three-layer structure. The insulating layer 250d is in contact with the oxide semiconductor layer 230. The insulating layer 250d has a barrier property against oxygen, which can prevent oxygen from being released from the oxide semiconductor layer 230. For example, aluminum oxide may be used as the insulating layer 250d. Aluminum oxide has a function of capturing or fixing hydrogen, making it suitable for the insulating layer 250d in contact with the oxide semiconductor layer 230. Specifically, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0341] Typically, the thicknesses of the insulating layer 250d, the insulating layer 250a, the insulating layer 250b, and the insulating layer 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. Such a configuration allows the transistor to have good electrical characteristics even when miniaturized or highly integrated. The thicknesses of the insulating layer 250a, the insulating layer 250b, the insulating layer 250c, and the insulating layer 250d are not limited to the above. For example, the thicknesses of the insulating layer 250a, the insulating layer 250b, the insulating layer 250c, and the insulating layer 250d are preferably greater than 0 nm and less than or equal to 10 nm. Furthermore, any one or more of the insulating layer 250a, the insulating layer 250b, the insulating layer 250c, and the insulating layer 250d may not be provided.

[0342] 21C , it is preferable to use a three-layer structure as the insulating layer 250, in which a fourth insulating layer (insulating layer 250d) having a barrier property against oxygen, a first insulating layer (insulating layer 250a) made of a material with a low dielectric constant, and a second insulating layer (insulating layer 250b) having a function of capturing or fixing hydrogen are stacked in this order from the oxide semiconductor layer 230 side. Specifically, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side.

[0343] Typically, the thicknesses of the insulating layer 250d, the insulating layer 250a, and the insulating layer 250b are 1 nm, 2 nm, and 2 nm, respectively. With such a configuration, the transistor can have good electrical characteristics even when miniaturized or highly integrated. As described above, the thicknesses of the insulating layer 250a, the insulating layer 250b, and the insulating layer 250d are not limited to the above values.

[0344] The insulating layer 235 can also be called a sidewall, a sidewall insulating layer, a sidewall protective layer, etc. The number of layers constituting the insulating layer 235 is not particularly limited. The insulating layer 235 can be a single layer, two layers, or three or more layers.

[0345] The insulating layer 235 preferably includes an insulating layer having a region containing oxygen that is released by heating, thereby enabling oxygen to be supplied from the insulating layer 235 to the oxide semiconductor layer 230. For example, the insulating layer 235 is preferably made of silicon oxide or silicon oxynitride.

[0346] The insulating layer 235 preferably includes a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 202A. For example, the insulating layer 235 is preferably made of aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide.

[0347] Furthermore, the insulating layer 235 may be made of the above-mentioned material that can have ferroelectricity.

[0348] For example, the insulating layer 235 can have a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, or a three-layer structure of a silicon nitride film, a silicon oxide film, and a silicon nitride film. In the case of a two-layer structure of a silicon oxide film and a silicon nitride film, for example, it is preferable to provide a silicon oxide film on the oxide semiconductor layer 230 side and a silicon nitride film on the conductive layer 255 side. This makes it possible to efficiently supply oxygen to the oxide semiconductor layer 230 and to suppress the diffusion of impurities such as hydrogen into the oxide semiconductor layer 230. Alternatively, a silicon nitride film may be provided on the oxide semiconductor layer 230 side and a silicon oxide film may be provided on the conductive layer 255 side.

[0349] The insulating layer 131 can be formed using a material similar to that which can be used for the insulating layer 235. The insulating layer 250 and the insulating layer 151 may be formed using a material which can be used for the insulating layer 235. This is particularly suitable when the insulating layer 250 or the insulating layer 151 functions as a back-gate insulating layer of a transistor.

[0350] A barrier insulating layer against hydrogen is preferably used for the insulating layer 183. This can suppress diffusion of hydrogen from above the insulating layer 183 to the oxide semiconductor layer 135. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 183.

[0351] It is particularly preferable to use silicon nitride formed by a sputtering method as the insulating layer 183. The sputtering method does not require the use of molecules containing hydrogen in the deposition gas, and therefore can reduce the hydrogen concentration in the insulating layer 183. Furthermore, by forming the insulating layer 183 by a sputtering method, silicon nitride with high density can be formed.

[0352] Alternatively, an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 183. With such a structure, diffusion of hydrogen from above the insulating layer 183 to the oxide semiconductor layer 135 can be suppressed, and further, hydrogen contained in the oxide semiconductor layer 135 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 135 can be reduced. For the insulating layer 183, aluminum oxide, hafnium oxide, hafnium silicate, or the like can be used.

[0353] Alternatively, the insulating layer 183 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 183 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.

[0354] The insulating layer 185 and the insulating layer 285 each function as an interlayer film, and therefore, are preferably formed using the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 185 and the insulating layer 285 each preferably include a silicon oxide film.

[0355] [Conductive Layer] The conductive layers (conductive layer 120, conductive layer 145, conductive layer 155, conductive layer 164, conductive layer 165, conductive layer 220, conductive layer 240, conductive layer 255, conductive layer 260, conductive layer 265, etc.) included in the memory device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0356] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO®), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0357] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.

[0358] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0359] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0360] The conductive layer 120, the conductive layer 145, the conductive layer 220, and the conductive layer 240 are in contact with the oxide semiconductor layer 135 or the oxide semiconductor layer 230, respectively. Therefore, for the conductive layer 120, the conductive layer 145, the conductive layer 220, and the conductive layer 240, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer even when the conductive layer is in contact with the oxide semiconductor layer.

[0361] By using a conductive material containing oxygen for the conductive layer 120, the conductive layer 145, the conductive layer 220, and the conductive layer 240, these conductive layers can maintain their conductivity even when absorbing oxygen. It is preferable that the conductive layer 120, the conductive layer 145, the conductive layer 220, and the conductive layer 240 each be made of ITO, ITSO, IZO (registered trademark), or the like.

[0362] The conductive layer 155, the conductive layer 164, the conductive layer 165, the conductive layer 255, and the conductive layer 265 are preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 155, the conductive layer 164, the conductive layer 165, the conductive layer 255, and the conductive layer 265 are preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 155, the conductive layer 164, the conductive layer 165, the conductive layer 255, and the conductive layer 265.

[0363] For the conductive layer 164 and the conductive layer 260, a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed may be used. Alternatively, the conductive material containing the above-described metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen introduced from an outer insulating layer may be captured.

[0364] [Substrate] Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0365] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the memory device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0366] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0367] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which utilizes plasma, thermal CVD (TCVD), which utilizes heat, and photo-CVD (photo-CVD), which utilizes light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0368] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that does not use plasma and can reduce plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a memory device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the memory device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of memory devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0369] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0370] The ALD method allows atoms to be deposited layer by layer, and therefore has the advantages of enabling ultrathin film formation, film formation on high-aspect-ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable because it utilizes plasma, enabling film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. The metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of a high substrate temperature during film formation and an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be lower than when the ALD method is used without these.

[0371] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0372] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0373] Furthermore, in the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the raw material gases. For example, in the CVD method, by changing the flow rate ratio of the raw material gases while forming a film, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers, since no time is required for transport or pressure adjustment. Therefore, the productivity of memory devices can be improved in some cases.

[0374] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0375] For example, each layer provided in the opening 190 or the opening 290 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method. This allows a film to be formed in the opening with good coverage. Furthermore, the oxide semiconductor layer provided in the opening (specifically, the oxide semiconductor layer 135 and the oxide semiconductor layer 230) is preferably formed by at least one of a sputtering method and an ALD method, and more preferably by both. This allows the oxide semiconductor layer to be formed in the opening with good coverage and improves the crystallinity of the oxide semiconductor layer.

[0376] Furthermore, the thin films (insulating films, semiconductor films, conductive films, etc.) that make up the memory device can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0377] Furthermore, when processing the thin film that constitutes the memory device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0378] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0379] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0380] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0381] As the planarization treatment of the film, a planarization treatment using a chemical mechanical polishing (CMP) method (also referred to as a CMP treatment), a planarization treatment using etching (also referred to as an etch-back treatment), or the like can be used.

[0382] 22 to 25 show a configuration example of a memory cell 150 A. The memory cell 150 A is a memory cell formed of two transistors (hereinafter referred to as a 2Tr0C memory cell).

[0383] The semiconductor device of one embodiment of the present invention preferably has two or more types of memory arrays. Examples of memory cells that can be used in each memory array include a 2Tr1C memory cell, a memory cell including two transistors (hereinafter referred to as a 2Tr0C memory cell), and a memory cell including one transistor and one capacitor (hereinafter referred to as a 1Tr1C memory cell). Note that the configuration of the memory cell is not limited thereto, and a combination of two or more transistors (typically two to six transistors) and one or more capacitors (typically one to five capacitors) can be used.

[0384] For example, a semiconductor device according to one embodiment of the present invention preferably includes a memory array including the memory cell 150, which is a 2Tr1C memory cell, and a memory array including the memory cell 150A, which is a 2Tr0C memory cell.

[0385] By having two or more types of memory cells (or memory arrays) in a semiconductor device, it is possible to select the memory cell (or memory array) to be used depending on the application, thereby achieving both faster read and write speeds and reduced power consumption of the memory device.

[0386] 22 includes a transistor 201A and a transistor 202F. Neither the transistor 201A nor the transistor 202F has a back gate.

[0387] For the transistor 201A, please refer to the above description.

[0388] The transistor 202F differs from the transistor 202A in that the insulating layer 280b, the insulating layer 280e, the insulating layer 280f, the insulating layer 280g, the insulating layer 235, and the conductive layer 255 are not included.

[0389] 10 shows an example in which the area of ​​the conductive layer 220 is set to be relatively large so that the area where the conductive layer 220 overlaps with the conductive layer 255 is large in order to increase the capacitance value of the capacitor 203A. Specifically, FIG. 10 shows an example in which the width of the conductive layer 220 is larger than the width of the conductive layer 145.

[0390] On the other hand, the memory cell 150A shown in FIG. 22 does not include the capacitor 203A, and therefore the areas of the conductive layer 165, the conductive layer 220a, and the conductive layer 220b may be small. Specifically, FIG. 22 shows an example in which the widths of the conductive layer 165, the conductive layer 220a, and the conductive layer 220b are narrower than the width of the conductive layer 145. This reduces parasitic capacitance generated between the conductive layer 165, the conductive layer 220a, and the conductive layer 220b and the conductive layer 145. Note that the conductive layer 165, the conductive layer 220a, and the conductive layer 220b are located over the insulating layer 185, and therefore the physical distance between the conductive layer 145 and the conductive layer 145 is large, making it difficult for parasitic capacitance to be generated between the conductive layer 165, the conductive layer 220a, and the conductive layer 220b. Therefore, in FIG. 22, the widths of the conductive layer 165, the conductive layer 220a, and the conductive layer 220b may be wider than the width of the conductive layer 145.

[0391] Furthermore, the memory cell 150A does not necessarily have to include the conductive layer 165 and the insulating layer 185. This is preferable because the number of manufacturing steps for the memory cell 150A can be reduced.

[0392] The memory cell 150A shown in FIG. 23 includes a transistor 201A and a transistor 202G.

[0393] The transistor 202G differs from the transistor 202A mainly in that it does not have the insulating layer 280e but has the insulating layer 280a between the conductive layer 220b and the conductive layer 255.

[0394] 22 does not include the capacitor 203A, the shortest distance between the top surface of the conductive layer 220b and the bottom surface of the conductive layer 255 can be increased.

[0395] It is preferable that the difference between the shortest distance from the upper surface of the conductive layer 220b to the lower surface of the conductive layer 255 and the shortest distance from the upper surface of the conductive layer 255 to the lower surface of the conductive layer 240 be small. For example, the difference is preferably 0 nm or more and 30 nm or less, and more preferably 0 nm or more and 10 nm or less. This can reduce both the parasitic capacitance generated between the conductive layer 220b and the conductive layer 255 and the parasitic capacitance generated between the conductive layer 240 and the conductive layer 255.

[0396] For example, when comparing memory cell 150A of 2Tr0C with memory cell 150 of 2Tr1C, it is preferable that the shortest distance from the upper surface of conductive layer 220b to the lower surface of conductive layer 255 in memory cell 150A is longer than the shortest distance from the upper surface of conductive layer 220b to the lower surface of conductive layer 255 in memory cell 150.

[0397] 22, the areas of the conductive layer 165, the conductive layer 220a, and the conductive layer 220b may be small in Fig. 23. Specifically, Fig. 23 shows an example in which the widths of the conductive layer 165, the conductive layer 220a, and the conductive layer 220b are narrower than the width of the conductive layer 145. This can reduce parasitic capacitance generated between the conductive layer 165, the conductive layer 220a, and the conductive layer 220b and the conductive layer 145. Furthermore, the capacitance generated between the conductive layer 165, the conductive layer 220a, and the conductive layer 220b and the conductive layer 255 can be reduced.

[0398] In other words, in Figure 23, the shortest distance from the upper surface of conductive layer 220b to the lower surface of conductive layer 255 is long and the width of conductive layer 220b is narrow, so that the capacitance generated between conductive layer 220b and conductive layer 255 can be significantly reduced.

[0399] The memory cell 150A shown in FIG. 24 includes a transistor 201C and a transistor 202G. Both the transistor 201C and the transistor 202G have back gates. The memory cell 150A shown in FIG. 25 includes a transistor 201C and a transistor 202F. The above description can be referred to for the transistors 201C, 202F, and 202G. In this way, in a 2Tr0C memory cell, both transistors with a back gate and transistors without a back gate can be freely combined and used.

[0400] <Configuration Example 3 of Memory Device> FIG. 26 shows a cross-sectional configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided.

[0401] In FIG. 26, a memory cell 150 (transistors 201 , 202 , and capacitors 203 ) is provided above a transistor 300 .

[0402] The transistor 300 is one of the transistors included in the sense amplifier.

[0403] 26 can be applied to the memory cell 150 shown in FIG. 26. Specifically, the transistor 201 is preferably any one of the transistors 201A to 201D. The transistor 202 is preferably any one of the transistors 202A to 202G. The capacitor 203 is preferably any one of the capacitors 203A to 203D. Alternatively, the capacitor 203 may not be included. That is, the memory cell 150 can be replaced with the memory cell 150A.

[0404] 26, the bit lines can be shortened by providing a sense amplifier so as to overlap the memory cells 150. This reduces the bit line capacitance, enabling the memory device to be driven at high speed.

[0405] 26 can correspond to a memory device 900 (FIG. 28) described later. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the memory device 900. The memory cell 150 corresponds to a memory cell 950.

[0406] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region and a drain region. The transistor 300 may be either a p-channel type or an n-channel type. The substrate 311 preferably includes a silicon-based semiconductor, and more specifically, preferably includes single-crystal silicon. That is, the transistor 300 is preferably a Si transistor.

[0407] Here, in the transistor 300 shown in FIG. 26 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0408] Note that the transistor 300 illustrated in FIG. 26 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0409] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0410] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0411] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0412] A wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, in Fig. 26, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0413] The insulating layer 352, the insulating layer 354, and the like, which function as interlayer films, can be formed using the above-described insulating layer that can be used in a memory device.

[0414] For conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, a conductive material applicable to the conductive layer 240 can be used. A high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, is preferably used, and tungsten is preferably used. Alternatively, a low-resistance conductive material, such as aluminum or copper, is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0415] The conductive layer 240 of the transistor 202 is electrically connected to the low-resistance region 314b functioning as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 644, the conductive layer 645, the conductive layer 647, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0416] The conductive layer 643 is embedded in the insulating layer 280b, the insulating layer 280g, the insulating layer 280a, and the insulating layer 185. The conductive layer 644 is provided over the insulating layer 161a. The conductive layer 644 can be manufactured using the same material and in the same process as the conductive layer 145. The conductive layer 645 is embedded in the insulating layer 161a. The conductive layer 647 is provided over the insulating layer 648. The conductive layer 647 can be manufactured using the same material and in the same process as the conductive layer 120. The conductive layer 646 is embedded in the insulating layer 648. The insulating layer 648 electrically insulates the transistor 300 from the conductive layer 120.

[0417] The metal oxide layer 642 is manufactured using the same material and process as the oxide semiconductor layer 135. When the conductive layer 220 and the conductive layer 120 each have a stacked structure, the top layer is preferably an oxide conductor because it is in contact with the oxide semiconductor layer. On the other hand, the layer in contact with the conductive layer 643 or the conductive layer 645, which functions as a plug, is preferably a conductive layer with lower resistance than an oxide conductor in terms of reducing contact resistance. Therefore, as shown in FIG. 26 , the metal oxide layer 642 preferably has an opening reaching the conductive layer 644. When the conductive layer 644 and the conductive layer 647 have a two-layer structure as shown in FIG. 26 , it is preferable to provide an opening in the upper layer so that the lower layer and the plug are in contact. Note that various modes are possible for the connection points between the plugs and the memory cells and are not limited to the configuration shown in FIG. 26 .

[0418] An insulating layer 287 is provided on the memory cell 150. On the insulating layer 287, a memory cell 150 can be further provided.

[0419] FIG. 27 shows an example in which the memory cells 150 shown in FIG. 26 are stacked in n layers (n is an integer of 3 or more) in the Z direction.

[0420] The memory device shown in FIG. 27 has n memory layers 160. Specifically, a memory layer 160[2] is provided on the memory layer 160[1], and (n-2) memory layers are further provided on the memory layer 160[2], with the topmost memory layer being the memory layer 160[n]. The number of memory cells included in one memory layer 160 is not particularly limited, and two or more memory cells may be included. The memory cells included in the n memory layer 160 are electrically connected to a sense amplifier provided below the n memory layer 160 by multiple conductive layers functioning as plugs. FIG. 27 also shows a layer 170 in which a driver circuit including a sense amplifier is provided. The transistor 300 included in the layer 170 can be described above.

[0421] 27, by stacking a plurality of memory cells, it is possible to integrate and arrange the cells without increasing the area occupied by the memory array, that is, it is possible to configure a 3D memory array.

[0422] <Configuration Example 4 of Memory Device> Fig. 28 shows a block diagram illustrating a configuration example of a memory device 900. The memory device 900 can function as a memory device. The memory device 900 shown in Fig. 28 includes a driver circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Fig. 28 shows an example in which the memory array 920 includes a plurality of memory cells 950 arranged in a matrix.

[0423] The memory cell 950 can be a memory device of one embodiment of the present invention (such as the memory cell 150).

[0424] The drive circuit 910 includes a power switch 931, a power switch 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0425] In the storage device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0426] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0427] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the memory device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0428] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0429] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0430] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0431] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the memory device 900. The data output from the output circuit 926 is a signal RDA.

[0432] The power switch 931 supplies V to the peripheral circuit 915 ＤＤ The power switch 932 controls the supply of V to the row driver 923. ＨＭ Here, the high power supply voltage of the memory device 900 is V ＤＤ and the low power supply voltage is GND (ground potential). ＨＭ is the high power supply voltage used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the power switch 931, and the signal PON2 controls the on / off of the power switch 932. In FIG. 28, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0433] As described above, the memory device of one embodiment of the present invention includes two OS transistors and one capacitor stacked together, so that memory cells can be arranged with high density, and large-scale integration and low power consumption of the memory device can be achieved at the same time.

[0434] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0435] Embodiment 3 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0436] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a memory device, a semiconductor device, or the like including the transistor can be improved.

[0437] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0438] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0439] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0440] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0441] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum oxide. Examples of usable materials include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0442] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0443] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0444] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0445] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0446] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0447] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0448] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed by two different deposition methods may be referred to as a hybrid OS.

[0449] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0450] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a crystalline metal oxide is deposited by the first deposition method. The deposited metal oxide preferably has a CAAC structure. For example, a metal oxide deposited by a sputtering method is likely to have crystallinity.

[0451] When a metal oxide is formed using the first film-forming method, a mixed layer may be formed at the interface between the metal oxide and a layer on which the metal oxide is to be formed. For example, when a sputtering method is used as the first film-forming method, the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy imparted to the substrate by the sputtering particles. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide.

[0452] For example, when an insulating layer having silicon, such as silicon oxide, is used as a surface to be formed, silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide using the first film formation method, and there is a concern that the mixing of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide.

[0453] Therefore, in one embodiment of the present invention, a metal oxide is formed by a second film formation method before a metal oxide is formed by a first film formation method. That is, a metal oxide is formed as a first layer by a second film formation method, and then a metal oxide is formed as a second layer on the first layer by a first film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the first film formation method as the second film formation method. By using a film formation method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the second film formation method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, since the incorporation of impurities such as silicon into the second layer can be suppressed, the crystallinity of the second layer can be potentially improved. For example, atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering.

[0454] In addition, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure may be formed as the first layer. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0455] In the oxide semiconductor layer of one embodiment of the present invention, it is preferable that a metal oxide be first formed over a surface to be formed by the second film formation method, and then a metal oxide be formed above the metal oxide by the first film formation method.

[0456] Examples of the first film formation method include a sputtering method and a pulsed laser deposition (PLD) method.

[0457] Examples of the second film formation method include an ALD method, a plasma enhanced CVD (PECVD) method, a thermal CVD method, a photo-assisted CVD method, a metal organic CVD (MOCVD) method, and a molecular beam epitaxy (MBE) method. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed. Also, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that causes little damage to the surface on which the film is formed. Examples of the wet method include a spray coating method.

[0458] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method and then forming a metal oxide as a second layer by the first deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. The metal oxide formed by the first deposition method preferably has a CAAC structure.

[0459] Furthermore, a third layer can be formed on the second layer. Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a deposition method that easily imparts crystallinity is not used as a deposition method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a deposition method that provides better coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the entire layer. Furthermore, for example, by forming the third layer using a deposition method that causes less damage than the second layer, damage to the second layer can be reduced, and the oxide semiconductor layer can have high crystallinity throughout the entire layer.

[0460] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0461] Note that the third layer is an uppermost layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating layer when the oxide semiconductor layer is used as a semiconductor layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0462] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method, forming a metal oxide as a second layer by the first deposition method, and forming a metal oxide as a third layer by the second deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. The metal oxide formed by the first deposition method preferably has a CAAC structure. The ALD method has better coverage than the sputtering method. The use of the ALD method for the first and third layers can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0463] [Method for Manufacturing Oxide Semiconductor Layer] The oxide semiconductor layer 230 can be manufactured by, for example, forming an oxide semiconductor 230a over a layer 229 that is a surface to be formed by an ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by a sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by an ALD method. After the oxide semiconductor layer 230 is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer 230. The heat treatment here is not limited to heat treatment. For example, heat applied during the manufacturing process may be used. The layer 229 is an insulating film, such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film.

[0464] The oxide semiconductor layer 230 can be used as an oxide semiconductor layer (such as the oxide semiconductor layer 230 or the oxide semiconductor layer 135) included in the transistor described in the above embodiment. The layer 229 corresponds to one or more of the layers in contact with the oxide semiconductor layer described in the above embodiment (such as the conductive layer 120, the conductive layer 220, the insulating layer 161a, the insulating layer 235, the conductive layer 145, and the conductive layer 240).

[0465] The layer 229 does not need to be crystalline. When the layer 229 is crystalline, it may have a crystal structure with low lattice matching with a metal oxide contained in the oxide semiconductor layer 230.

[0466] An example of a method for manufacturing the oxide semiconductor layer 230 will be described with reference to FIGS. 29A to 30D.

[0467] First, an oxide semiconductor 230a is formed on the layer 229 (FIG. 29A). Then, an oxide semiconductor 230b is formed on the oxide semiconductor 230a (FIG. 29B).

[0468] The oxide semiconductor 230b is preferably formed by a sputtering method and has a composition suitable for forming a CAAC structure.

[0469] The oxide semiconductor 230a is preferably formed by a deposition method that causes less damage to a surface on which the oxide semiconductor 230a is formed than the deposition method for the oxide semiconductor 230b. Here, the oxide semiconductor 230a is formed by an ALD method.

[0470] When a metal oxide film is formed by sputtering, damage to the surface on which the film is to be formed may cause alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed.

[0471] In a method for forming an oxide semiconductor layer according to one embodiment of the present invention, the oxide semiconductor 230a is formed over the layer 229, and then the oxide semiconductor 230b is formed by a sputtering method. The oxide semiconductor 230a is preferably formed by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is to be formed. By forming the oxide semiconductor 230a between the oxide semiconductor 230b and the layer 229 by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is to be formed, alloying of components contained in the oxide semiconductor layer 230 and components contained in the layer 229 can be suppressed, and the crystallinity of the oxide semiconductor layer 230 can be further improved.

[0472] By using the above structure, the thickness of the alloyed region can be reduced, or made so thin that the alloyed region is not observable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 29A and 29B show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor 230a.

[0473] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0474] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 230a being the depth direction. Next, in the profile of quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 230a contains In) that is the main component of the oxide semiconductor 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 230a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0475] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0476] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the oxide semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0477] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0478] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor layer 230 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably between more than 0 nm and 2 nm, more preferably between 1 nm and 2 nm.

[0479] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of the oxide semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0480] Alternatively, the CAAC structure near the surface to be formed can sometimes be evaluated from a map showing the crystal orientation. The map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing a fast Fourier transform (FFT) process on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the crystal axis direction of each region. The FFT pattern reflects reciprocal lattice space information similar to an electron diffraction pattern. For example, a region in which the calculated crystal axis direction of each region is 70° or more and 100° or less relative to the surface to be formed can be considered to have a CAAC structure.

[0481] 29A , the oxide semiconductor 230a may have a region with lower crystallinity than the oxide semiconductor 230b.

[0482] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor 230a by an ALD method will be described.

[0483] First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of the layer 229. Here, the substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor.

[0484] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursor and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer of indium and oxygen combined (hereinafter referred to as the first layer). Ozone, oxygen, water, etc. can be used as the oxidizing agent. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactant and reaction products are discharged from the chamber.

[0485] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the first layer. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0486] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursors, reaction products, etc. are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are combined (hereinafter referred to as the second layer). Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants, reaction products, etc. are discharged from the chamber.

[0487] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the second layer, preferably at a temperature corresponding to the decomposition temperature of the precursor.

[0488] Here, in the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate heating temperature is, for example, 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower.

[0489] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor, leaving zinc adsorbed on the substrate while desorbing components other than zinc, thereby forming a layer of zinc and oxygen combined (hereinafter referred to as the third layer). Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0490] Next, the first layer is formed again on the third layer by the above-described method. By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor 230a on the layer 229 by an ALD method.

[0491] In the ALD method, the composition of the resulting film can be controlled by the amount of source gas introduced. For example, in the ALD method, a film of any composition can be formed by adjusting the amount of source gas introduced, the number of introductions (also referred to as the number of pulses), the time required for one pulse (also referred to as the pulse time), etc. Furthermore, in the ALD method, for example, a film whose composition changes continuously can be formed by changing the source gas while forming the film. When forming a film while changing the source gas, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of memory devices, semiconductor devices, etc. can be improved in some cases.

[0492] After the oxide semiconductor 230a is formed by an ALD method, an In-M-Zn oxide is formed as the oxide semiconductor 230b over the oxide semiconductor 230a by a sputtering method.

[0493] Here, when the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, when the oxide semiconductor 230b is formed, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, causing at least a part of the oxide semiconductor 230a to crystallize.

[0494] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0495] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0496] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0497] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease by up to about 50% compared to the sputtering target.

[0498] In the formation of the oxide semiconductor 230b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, a metal oxide with high crystallinity can be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In the formation of the oxide semiconductor 230b by a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0499] As a result, as shown in FIG. 29B, an oxide semiconductor 230a and an oxide semiconductor 230b can be formed on the layer 229.

[0500] Next, the oxide semiconductor 230c is formed on the oxide semiconductor 230b (FIG. 29C). Here, the oxide semiconductor 230c is formed by an ALD method. For the formation of the oxide semiconductor 230c by the ALD method, the method for forming the oxide semiconductor 230a can be referred to.

[0501] When an oxide semiconductor 230c having lower crystallinity than the CAAC structure is formed on an oxide semiconductor 230b having the CAAC structure by using an ALD method, the oxide semiconductor 230c may grow epitaxially around the oxide semiconductor 230b as a nucleus. Thus, when the oxide semiconductor 230c is formed, the oxide semiconductor 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 230c.

[0502] Next, a heat treatment step may be carried out.

[0503] The heat treatment may be performed at a temperature of, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the temperature is 400° C.±25° C. (375° C. to 425° C.). The treatment time may be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time may be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor 230b with the oxide semiconductor 230c (in other words, crystal molecules formed by the ALD method).

[0504] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0505] The heat treatment may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c. Furthermore, if the region is formed only below the oxide semiconductor 230c after deposition by the ALD method, the heat treatment may cause the region to expand upward ( FIG. 29D ). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 230c.

[0506] Furthermore, the heat treatment process may further repair the oxide semiconductor 230b by the oxide semiconductor 230c (in other words, the crystal molecules formed by the ALD method) filling gaps in the atomic-level crystal portions of the CAAC structure of the oxide semiconductor 230b.

[0507] Furthermore, it is preferable that at least a portion of the oxide semiconductor 230a is converted into CAAC by the heat treatment ( FIG. 29D ). It is expected that the CAAC conversion is facilitated by the mixed layer 231 formed in the oxide semiconductor 230a during the deposition of the oxide semiconductor 230b, which acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor 230a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 229.

[0508] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 230a, the CAAC can be formed up to the vicinity of the layer 229 regardless of the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0509] After the heat treatment, microwave treatment is preferably performed in an atmosphere containing oxygen. By performing the microwave treatment, impurities such as hydrogen and carbon in the oxide semiconductor layer 230 can be reduced.

[0510] 29A to 29D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 29A to 29D can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide film according to one embodiment of the present invention. As shown in FIGS. 29A to 29D , the crystallinity of the oxide semiconductor 230a and the oxide semiconductor 230c increases with the oxide semiconductor 230b, which has high crystallinity, serving as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor 230a may be increased by heat treatment during the formation of the oxide semiconductor 230b or after the formation of the oxide semiconductor 230c. The crystallinity of the oxide semiconductor 230c may be increased by heat treatment during the formation of the oxide semiconductor 230c or after the formation of the oxide semiconductor 230c. Note that the heat treatment has an assisting effect of increasing the crystallinity.

[0511] As described above, in the method for forming a metal oxide film of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the oxide semiconductor 230a and the oxide semiconductor 230c here) can be increased by using the oxide semiconductor 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown by solid-phase growth using the oxide semiconductor 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, i.e., a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC). Note that although FIGS. 29A to 29D illustrate a structure including the oxide semiconductors 230a, 230b, and 230c, the present invention is not limited thereto. For example, an AG CAAC film can also be formed in a structure including the oxide semiconductors 230a and 230b.

[0512] It is preferable that a region having the CAAC structure is widely present throughout the entire oxide semiconductor layer 230 including the oxide semiconductors 230a and 230c. FIG. 30A shows the crystallization of the oxide semiconductors 230a, 230b, and 230c. The region having the CAAC structure in the oxide semiconductor 230a is crystalline and connected to the region having the CAAC structure in the oxide semiconductor 230b. The region having the CAAC structure in the oxide semiconductor 230c is crystalline and connected to the region having the CAAC structure in the oxide semiconductor 230b. As a result, the boundary between the oxide semiconductors 230a and 230b may not be observed. The boundary between the oxide semiconductors 230b and 230c may not be observed. The oxide semiconductor layer 230 may be expressed as a single layer with no clearly observable interface. The oxide semiconductor layer 230 may be expressed as a single layer.

[0513] Furthermore, there are cases where a portion of the oxide semiconductor 230a or the oxide semiconductor 230c is not crystallized. The example shown in Fig. 30B illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a is not crystallized. Fig. 30C illustrates a state in which the vicinity of the surface in the oxide semiconductor 230c is not crystallized. Fig. 30D illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a and the vicinity of the surface of the oxide semiconductor 230c are not crystallized.

[0514] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0515] According to the method for forming an oxide semiconductor layer of one embodiment of the present invention, the crystallinity of metal oxides located above and below a metal oxide having a CAAC structure can be improved, and the entire oxide semiconductor layer can be made into a layer with high crystallinity.

[0516] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor layer 230, the boundaries between the stacked oxide semiconductors 230a, 230b, and 230c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0517] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the oxide semiconductors 230a and 230c, crystals that reflect the crystal orientation of the oxide semiconductor 230b are formed, thereby suppressing polycrystallization.

[0518] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 230b and the crystals of the oxide semiconductor 230a or the oxide semiconductor 230c is small. This allows the oxide semiconductor 230a or the oxide semiconductor 230c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 230b. In this case, for example, in cross-sectional observation of the oxide semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the oxide semiconductor 230a or the oxide semiconductor 230c.

[0519] The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c is not particularly limited as long as the lattice mismatch between the crystal of the oxide semiconductor 230b and the crystal of the oxide semiconductor 230a or the oxide semiconductor 230c is small. The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0520] [Composition of Oxide Semiconductor Layer] As described above, the oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed by, for example, a sputtering method. The oxide semiconductor 230b preferably contains, for example, zinc. The inclusion of zinc results in a metal oxide with high crystallinity. The oxide semiconductor 230b preferably contains, in addition to zinc, the element M. The inclusion of the element M in the oxide semiconductor 230b can, for example, prevent oxygen vacancies from being formed in the metal oxide. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved. Specifically, the oxide semiconductor 230b may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, or an atomic ratio of In:M:Zn = 1:3:4 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0521] The oxide semiconductor 230b may not contain the element M. For example, it may be an In—Zn oxide. Specifically, it may have a composition with an atomic ratio of In:Zn=1:1 or a composition thereabout, an atomic ratio of In:Zn=2:1 or a composition thereabout, or an atomic ratio of In:Zn=4:1 or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, it may have a composition containing a trace amount of the element M. For example, it may have a composition with an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereabout, or an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereabout. Furthermore, it may have a composition with an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereabout, or an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereabout.

[0522] The oxide semiconductor 230a and the oxide semiconductor 230c can be a metal oxide having a high proportion of In. The oxide semiconductor 230a and the oxide semiconductor 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current and frequency characteristics can be increased.

[0523] Alternatively, the oxide semiconductors 230a and 230c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition of In:Zn=1:1 (atomic ratio) or a composition therearound, a composition of In:Zn=2:1 (atomic ratio) or a composition therearound, or a composition of In:Zn=4:1 (atomic ratio) or a composition therearound. Alternatively, indium oxide may be used. The oxide semiconductors 230a and 230c may contain a trace amount of the element M. Specifically, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition close thereto, In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition close thereto.

[0524] Note that increasing the zinc composition of the oxide semiconductor can improve the crystallinity of the oxide semiconductor. It is particularly preferable that the oxide semiconductor 230a contains zinc. For example, when the oxide semiconductor 230a is formed by an ALD method and the oxide semiconductor 230b is formed by a sputtering method, zinc contained in the oxide semiconductor 230a may diffuse into the oxide semiconductor 230b. Note that this diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b is expected to improve the crystallinity. Alternatively, the diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b is expected to promote the lateral growth of crystal parts having c-axis orientation, thereby accelerating the formation of CAAC.

[0525] The oxide semiconductors 230a and 230c can be metal oxides containing a higher proportion of In than the oxide semiconductor 230b.

[0526] Alternatively, for example, metal oxides having a higher Ga content than the oxide semiconductor 230b can be used for the oxide semiconductors 230a and 230c. For example, the oxide semiconductors 230a and 230c are preferably made of a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereof, a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereof, or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereof. Increasing the Ga content can sometimes make the band gaps of the oxide semiconductors 230a and 230c larger than that of the oxide semiconductor 230b. As a result, the oxide semiconductor 230b is sandwiched between the oxide semiconductors 230a and 230c, which have larger band gaps, and the oxide semiconductor 230b mainly functions as a current path (channel). The oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c, which reduces trap states at the interface of the oxide semiconductor 230b and in the vicinity thereof. This makes it possible to realize a buried-channel transistor in which the channel is located away from the insulating layer interface, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may be formed on the back channel side is reduced, which suppresses light degradation of the transistor (e.g., negative-bias light degradation) and improves the reliability of the transistor.

[0527] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 230a and 230c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the oxide semiconductor 230b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor 230a and the oxide semiconductor 230c and the oxide semiconductor 230b.

[0528] In particular, even when the oxide semiconductor 230 a and the oxide semiconductor 230 c have a high In content, the oxide semiconductor layer can have suitable crystallinity for a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0529] The oxide semiconductor 230a and the oxide semiconductor 230c may have different compositions.

[0530] The oxide semiconductors 230a and 230c may be made of a metal oxide having the same composition as the oxide semiconductor 230b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0531] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0532] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0533] The composition of the metal oxide used in the oxide semiconductor layer 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content. Furthermore, it may be difficult to quantify element M, or element M may not be detected.

[0534] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0535] When the oxide semiconductor layer 230 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer 230 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. In addition, in transistors used in smaller memory devices, semiconductor devices, and the like, the thickness of the oxide semiconductor layer 230 is preferably 1 nm to 3 nm, or 5 nm, and is preferably 20 nm to 15 nm, 12 nm to 10 nm.

[0536] The oxide semiconductor 230b preferably has a thickness of, for example, 200 nm or less. When the oxide semiconductor 230b has a layer shape, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0537] Alternatively, if the oxide semiconductor 230b can function as a crystal nucleus, the oxide semiconductor 230b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 230b exist discretely.

[0538] The oxide semiconductor 230a and the oxide semiconductor 230c each have a thickness of, for example, preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, still more preferably 1 nm to 20 nm, and still more preferably 2 nm to 20 nm.

[0539] The oxide semiconductor layer of one embodiment of the present invention contains a metal oxide.

[0540] Metal oxides may have lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids. Factors that cause lattice defects include a discrepancy in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms) and impurities.

[0541] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used for the semiconductor layer of a transistor has few lattice defects.

[0542] The type of lattice defects likely to exist in a metal oxide and the amount of lattice defects present vary depending on the structure of the metal oxide or the method for forming the metal oxide film.

[0543] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide with a single crystal structure. By using such a metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0544] Furthermore, a metal oxide that increases the on-state current of the transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0545] [Impurities in Oxide Semiconductor] Here, the influence of each impurity in an oxide semiconductor will be described.

[0546] It is preferable that the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer have fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. Ｏ ) and impurities, the electrical characteristics are likely to fluctuate, and reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ H) and generate electrons that serve as carriers. Therefore, when oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor tends to have normally-on characteristics. Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0547] Therefore, reducing the impurity concentration in an oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in an oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0548] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0549] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0550] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10１８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0551] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0552] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0553] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0554] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0555] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0556] The c-axis orientation rate can be calculated by calculating the percentage of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20 degrees or less.

[0557] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated by, for example, TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0558] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0559] The c-axis orientation rates of the region where the oxide semiconductor 230a is formed, the region where the oxide semiconductor 230b is formed, and the region where the oxide semiconductor 230c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Rc2 is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0560] After the oxide semiconductor layer 230 is formed, the boundaries between the oxide semiconductors 230a, 230b, and 230c may not be clearly observed.

[0561] The oxide semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region has a layer shape.

[0562] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rate of the third region is 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher. The c-axis orientation rate of the second region is 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0563] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor layer 230 .

[0564] Alternatively, the layer thickness in each region may be, for example, approximately the same.

[0565] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0566] Embodiment 4 In this embodiment, application examples of a memory device according to one embodiment of the present invention and a semiconductor device including the memory device will be described.

[0567] The memory device of one embodiment of the present invention and the semiconductor device including the memory device can be applied to memory devices of various electronic devices (for example, information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, and game consoles) and semiconductor devices including the memory device. The memory device can also be used in image sensors, Internet of Things (IoT), healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0568] 31A to 31J and 32A to 32H illustrate electronic devices each including an electronic component 700 having a semiconductor device including a memory device of one embodiment of the present invention.

[0569] 31A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0570] By applying a storage device of one embodiment of the present invention, the information terminal 5500 can store data used by an application or store temporary files generated when an application is executed (e.g., a cache when using a web browser).

[0571] 31B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0572] Similar to the information terminal 5500 described above, a wearable device can store data used in an application or temporary files generated when an application is executed by applying a storage device of one embodiment of the present invention.

[0573] 31C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0574] Like the information terminal 5500 described above, the desktop information terminal 5300 can store data used by an application or temporary files generated when an application is executed by applying a storage device of one embodiment of the present invention.

[0575] In Figures 31A to 31C, smartphones, wearable terminals, and desktop information terminals have been described as electronic devices, but other information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0576] 31D shows an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, and a freezer compartment door 5803. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0577] The storage device of one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to and from an information terminal via the Internet, for example. The electric refrigerator-freezer 5800 can store programs and data used by the programs, or temporary files generated when transmitting the information, in the storage device of one embodiment of the present invention.

[0578] In Figure 31D, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0579] 31E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0580] FIG. 31F also shows a stationary game console 7500, which is an example of a game console. The stationary game console 7500 is a home-use stationary game console. The stationary game console 7500 includes a main body 7520 and a controller 7522. The controller 7522 can be connected to the main body 7520 wirelessly or via a wired connection. The shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, the shape may be modeled after a gun, a musical instrument, or a musical device. Alternatively, the controller may be equipped with one or more of a camera, a depth sensor, a motion sensor, and a microphone instead of a controller, and may be operated by the game player's gestures or voice.

[0581] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0582] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500. Furthermore, the reduced power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0583] Furthermore, by applying a storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500, it is possible to store programs or data used by the programs, or temporary files and the like required for calculations that occur during game execution.

[0584] Other examples of game machines to which the storage device of one embodiment of the present invention can be applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0585] [Mobile Body] A storage device according to one embodiment of the present invention can be applied to a mobile body such as an automobile and the area around the driver's seat of the automobile.

[0586] FIG. 31G illustrates an automobile 5700 as an example of a moving object.

[0587] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows such information may also be provided around the driver's seat.

[0588] In particular, the display device can compensate for, for example, a view blocked by a pillar or a blind spot of the driver's seat, thereby improving safety, by displaying an image from an imaging device (not shown) provided on the automobile 5700. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be improved.

[0589] The storage device of one embodiment of the present invention can store a program for performing hazard prediction, data used for the program, etc. The storage device of one embodiment of the present invention can store temporary information necessary for a system for performing autonomous driving, road guidance, hazard prediction, etc. of the automobile 5700. The storage device of one embodiment of the present invention may also store video images from a driving recorder installed in the automobile 5700.

[0590] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects may include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0591] [Camera] The storage device according to one embodiment of the present invention can be applied to a camera.

[0592] 31H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0593] The storage device of one embodiment of the present invention can be applied to the digital camera 6240. In this case, captured image data can be stored. Furthermore, temporary data used in the system of the digital camera 6240 can also be stored.

[0594] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the digital camera 6240. Furthermore, the reduced power consumption can reduce heat generation from a circuit, and the influence of heat on the circuit itself, peripheral circuits, and modules can be reduced.

[0595] [Video Camera] The storage device of one embodiment of the present invention can be applied to a video camera.

[0596] 31I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, and a connection unit 6306. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0597] By using the storage device of one embodiment of the present invention, a large amount of captured video data can be stored. Furthermore, when recording video captured by the video camera 6300, encoding needs to be performed according to the data recording format. By using the storage device of one embodiment of the present invention, the video camera 6300 can store temporary files generated during encoding.

[0598] [ICD] The storage device according to one aspect of the present invention can be applied to an implantable cardioverter defibrillator (ICD).

[0599] 31J is a cross-sectional schematic diagram showing an example of an ICD. The ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0600] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0601] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0602] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store, in the electronic component 700, data on the heart rate acquired by the sensor, the number of times pacing therapy has been performed, or the duration of the therapy, for example.

[0603] Furthermore, power can be received by the antenna 5404, and the power is charged in the battery 5401. Furthermore, the ICD main body 5400 has multiple batteries, thereby improving safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.

[0604] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0605] Furthermore, by applying the storage device of one embodiment of the present invention to the ICD main body 5400, data of an acquired organized signal can be stored as digital data. The ICD main body 5400 can output the stored data in response to a request from an external monitor device. For example, various types of biological information can be managed by a portable information terminal device such as a smartphone.

[0606] [Expansion Device for PC] A storage device according to one aspect of the present invention can be applied to an expansion device for a computer such as a PC (Personal Computer) and an information terminal.

[0607] 32A shows an expansion device 6100 that can be connected to a PC via USB (Universal Serial Bus). The expansion device 6100 can be used as a so-called USB memory. The expansion device 6100 is not limited to a small size, but can also be a relatively large expansion device equipped with a cooling fan.

[0608] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with, for example, a circuit that drives the storage device of one embodiment of the present invention. For example, an electronic component 700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0609] [SD Card] A storage device according to one embodiment of the present invention can be applied to an SD card that can be attached to an electronic device such as an information terminal or a digital camera.

[0610] FIG. 32B is a schematic diagram of the external appearance of an SD card, and FIG. 32C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the circuit board 5113. For example, an electronic component 700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 700.

[0611] The capacity of the SD card 5110 can be increased by providing the electronic component 700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 700.

[0612] [SSD] A storage device according to one embodiment of the present invention can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0613] FIG. 32D is a schematic diagram of the external appearance of an SSD, and FIG. 32E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a board 5153. The connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. The board 5153 is provided with a memory device and a circuit for driving the memory device. For example, the board 5153 is equipped with an electronic component 700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 700 on the back side of the board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC (Error-Correcting Code) circuit, and the like. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0614] [Computer] The computer 5600 shown in Fig. 32F is an example of a large computer that can be used as a server. The computer 5600 can be applied to a data server, an AI server, etc. The computer 5600 has a rack 5610 storing multiple rack-mounted computers 5620.

[0615] The computer 5620 can have the configuration shown in the perspective view in Fig. 32G, for example. In Fig. 32G, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0616] A PC card 5621 shown in Figure 32H is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 32H illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0617] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0618] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621 or inputting signals. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. The connection terminals 5623, 5624, and 5625 can comply with standards such as USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When video signals are output from the connection terminals 5623, 5624, and 5625, the standard for each can be, for example, HDMI (registered trademark).

[0619] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0620] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU.

[0621] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. An example of the semiconductor device 5628 is a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0622] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0623] By using the storage device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be miniaturized and consume less power. Furthermore, the storage device of one embodiment of the present invention consumes less power, which can reduce heat generation from a circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the storage device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0624] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0625] ADDR: signal, BL: wiring, BSL: wiring, BTr: transistor, BW: signal, CE: signal, CL: wiring, CLK: signal, CTr: transistor, CWL: wiring, FN: node, GW: signal, PTr: transistor, RBL: wiring, RDA: signal, RWL: wiring, SSL: wiring, STr: transistor, WAKE: signal, WBL: wiring, WDA: signal, WL: wiring, WLm: wiring, WWL: wiring, 10A: semiconductor device, 10: semiconductor device, 11: layer, 12: layer, 13A: layer, 13: layer, 14A: layer, 14: layer, 15: layer, 20: memory cell, 21: circuit Path, 22: Circuit, 23: Circuit, 24: Circuit, 30: Memory Cell, 31: Circuit, 32: Circuit, 33: Circuit, 34: Circuit, 40: Memory String, 50: Insulating Layer, 51: Conductive Layer, 52: Conductive Layer, 53: Conductive Layer, 54: Conductive Layer, 55: Conductive Layer, 56: Plug, 57: Conductive Layer, 65: Memory Cell, 70: Cache Interface, 71: ALU, 72: ALU Controller, 73: Instruction Decoder, 74: Interrupt Controller, 75: Timing Controller, 76: Register, 77: Register Controller, 78: Bus Interface ,79: Cache,81: Controller,82: Processor,83: Cache,84: Cache,85: Interface,120a: Conductive layer,120b: Conductive layer,120c: Conductive layer,120: Conductive layer,131: Insulating layer,135: Oxide semiconductor layer,140: Insulating layer,145a: Conductive layer,145b: Conductive layer,145: Conductive layer,150A: Memory cell,150: Memory cell,151: Insulating layer,155: Conductive layer,160[2]: Memory layer,160[n]: Memory layer,160: Memory layer,161a: Insulating layer,161b: Insulating layer,161c: Insulating layer,161d: Insulating layer, 161e: insulating layer, 161f: insulating layer, 164: conductive layer, 165: conductive layer, 170: layer, 174: opening, 183: insulating layer, 185: insulating layer, 190: opening, 201A: transistor, 201B: transistor, 201C: transistor, 201D: transistor, 201: transistor, 202A: transistor, 202B: transistor, 202C: transistor, 202D: transistor, 202E: transistor, 202F: transistor, 202G: transistor, 202: transistor, 203A: capacitor, 203B: capacitor,203C: capacitor, 203D: capacitor, 203: capacitor, 220a: conductive layer, 220b: conductive layer, 220: conductive layer, 2...

Claims

The film has first to third layers, the first tier having a processor; the second layer having a first memory cell; the third layer includes a second memory cell; the first memory cell is composed of a first transistor and a second transistor; the second transistor has a gate connected to one of the source and the drain of the first transistor; the second memory cell is composed of a third transistor, a fourth transistor, and a capacitor; the fourth transistor has a gate connected to one of the source and drain of the third transistor and one electrode of the capacitor; each of the first to fourth transistors is a vertical transistor having an oxide semiconductor in a channel and a source and a drain located at different heights; the second layer is located between the first layer and the third layer; Information processing device. 　 In claim 1 the second layer is located on the first layer; the third layer is located on the second layer; Information processing device. 　 In claim 1 the first layer is disposed on the second layer; the second layer is located on the third layer; Information processing device. 　 The film has first to fifth layers, the first tier having a first processor; the second layer having a first memory cell; the third layer includes a second memory cell; the fourth tier having a second processor; the fifth layer has a NAND memory; the first memory cell is composed of a first transistor and a second transistor; the second transistor has a gate connected to one of the source and the drain of the first transistor; the second memory cell is composed of a third transistor, a fourth transistor, and a capacitor; the fourth transistor has a gate connected to one of the source and drain of the third transistor and one electrode of the capacitor; each of the first to fourth transistors is a vertical transistor having an oxide semiconductor in a channel and a source and a drain located at different heights; the second layer is located between the first layer and the fifth layer and between the fourth layer and the fifth layer; the third layer is located between the second layer and the fifth layer; Information processing device. 　 In claim 4, the first processor is a CPU; the second processor is a GPU; Information processing device. 　 In any one of claims 1 to 5, It is characterized by not having a DRAM, Information processing device. 　 A housing in which the information processing device according to claim 6 is mounted; A display unit; computer. 　 A motherboard on which the information processing device according to claim 6 is mounted; and a rack for storing the motherboard. server. 　 a first transistor, a second transistor, a capacitance element, a first insulating layer, and a second insulating layer; the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a third insulating layer, and a first oxide semiconductor layer; the second transistor includes the third conductive layer, the fourth conductive layer, the fifth conductive layer, a sixth conductive layer, a fourth insulating layer, a fifth insulating layer, and a second oxide semiconductor layer; the capacitive element includes the third conductive layer, a sixth insulating layer, and the fourth conductive layer; the first insulating layer has a first opening reaching the first conductive layer; the second conductive layer is located on the first insulating layer; the first oxide semiconductor layer is in contact with an upper surface of the second conductive layer and is in contact with the first conductive layer through the first opening; the third insulating layer is located inside the first oxide semiconductor layer in the first opening, the third conductive layer is located inside the third insulating layer within the first opening; the sixth insulating layer is located on the third conductive layer; the fourth conductive layer is located on the sixth insulating layer; the second insulating layer overlies the fourth conductive layer; the sixth insulating layer, the fourth conductive layer, and the second insulating layer have a second opening reaching the third conductive layer; the fifth conductive layer is located on the second insulating layer; the fourth insulating layer contacts at least the fourth conductive layer in the second opening; the second oxide semiconductor layer is in contact with an upper surface of the fifth conductive layer and is in contact with the third conductive layer through the second opening; the fifth insulating layer is located inside the second oxide semiconductor layer in the second opening, The sixth conductive layer is located inside the fifth insulating layer within the second opening. 　 In claim 9, A memory device, wherein the shortest distance between an upper surface of the third conductive layer and a lower surface of the fourth conductive layer is shorter than the shortest distance between an upper surface of the fourth conductive layer and a lower surface of the fifth conductive layer. 　 In claim 9, the first conductive layer has a first recess; the first opening overlaps with the first recess; the first oxide semiconductor layer is in contact with a bottom surface and a side surface of the first recess. 　 In claim 9, the third conductive layer has a second recess; the second opening overlaps with the second recess; the second oxide semiconductor layer is in contact with a bottom surface and a side surface of the second recess. 　 In claim 9, The storage device, wherein the first opening and the second opening are circular in plan view.

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