Noise trap

Abstract

A rectifier-based noise trap is presented. The rectifier-based noise trap is arranged between a first node that carries a voltage that includes a noise component and a second node that is a capacitive node. According to one aspect, the rectifier-based noise trap provides a unidirectional flow of current from the first node to the second node to charge the second node to a higher voltage. According to another aspect, the rectifier-based noise trap provides a unidirectional flow of current from the second node to the first node to discharge the second node to a lower voltage. A direction of the flow of the current through the rectifier-based noise trap is based on a difference between voltages of the first and second node. According to one aspect, the rectifier-based noise trap includes a pair of diodes arranged in antiparallel.

Description

NOISE TRAPCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Application No. 63 / 517,482 filed on August 3, 2023, for “NOISE TRAP”, the content of which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure is related to electronic circuits, and more particularly to noise trapping and removal in such circuits.BACKGROUND

[0003] Performance of an electronic circuit (e.g., electronic system) may be based on a level of noise present in the circuit. Generally, it may be desirable to eliminate such noise for higher overall performance of the electronic circuit. In practice, complete removal of the noise may not be feasible, and therefore means for reducing the noise and / or immunizing, to some degree, sensitive portions of the circuit from the noise may be implemented. Such means however may unfavorably increase cost and size of the circuit, and feasibility for their implementation may be dependent on various design goals and requirements of the electronic circuit (e.g., voltage and / or frequency ranges of operation).

[0004] Power supplies, which may include regulators and / or charge pumps to generate an output voltage, may be considered a source of noise in an electronic circuit. This is exemplified in the electronic circuit (100) of FIG. 1, wherein a power supply block (105) is shown to generate a (positive) supply voltage, Vp, that is provided to a control circuit block (110, e.g., a control circuit). The control circuit block (110) may use the supply voltage, Vp, to generate an output voltage (VOUT, e.g., a control voltage having a nominal voltage level in the absence of noise) that in turn may be provided to a circuit block (120) to control its operation. For example, as shown in FIG. 1, the output voltage, VOUT, may be used as a gate voltage, VG, provided to a gate, G, of a transistor, MK, thereby controlling, for example, a current conducted between a drain, D, and a source, S, of the transistor, MK. It should be noted that operation of the control circuit block (110) for generation of the output voltage may be based on control circuitry thatmay be internal and / or external to the control circuit block (110) and controlled / activated via internally or externally generated control lines, details of which are omitted in FIG. 1.

[0005] As the power supply block (105) of FIG. 1 may be a source of noise, a corresponding noise component, Np, present at the supply voltage, Vp, may couple through the control circuit block (110) and generate a corresponding noise component, NOUT, at the output voltage, VOUT. In other words, the output voltage, VOUT, may be considered as the combination (e.g., sum) of a nominal voltage, VNOM, generated by the control circuit block (110) in the absence of noise, and the noise component, NOUT (for clarity purposes, only the noise component, NOUT, is shown in FIG. 1 and other figures of the present disclosure). Accordingly, coupling of the output voltage, VOUT, to the circuit block (120) may cause further coupling of derivatives related to the noise components, NOUT, through the circuit block (120), via, for example, a current conduction path provided by the drain, D, and / or the source, S, of the transistor, MK (e.g., coupling via gate-to-drain and gate-to-source capacitances of MK), and / or drain-source conductance modulation.

[0006] Some prior art techniques may include reducing (the amplitude of) the noise component, Np, by designing more performant power supplies with a tradeoff of higher cost and higher physical size of such power supplies. Linear filters (e.g., R-C filter) may also be used to reduce (i.e., filter) the noise component within the power supplies or at sensitive nodes. However, due to the relatively low frequency content (e.g., 100’s KHz to few MHz) of the noise component, Np, such linear filters may require using excessively large components (e.g., resistances and / or capacitances) which may therefore result in higher physical size and degrade performance of the power supplies.

[0007] Other prior art design techniques may include reducing the effects of the noise component (e.g., NOUT of FIG. 1) in circuit blocks (e.g., 110 or 120 of FIG. 1) coupled to the power supplies. Such techniques may include provision in such circuit blocks of low impedance nodes (e.g., resistive couplings and / or nodes) at the frequencies of the noise component that may therefore suppress / attenuate the noise component. However, such techniques may not be feasible in cases that may require capacitive couplings and / or nodes, including in cases where high speed transitions (e.g., high rise times and / or fall times) and / or signals that operate at frequencies close to the frequencies of the noise component are used.

[0008] A motivation of the present teachings is to overcome the above shortcomings of the prior art by providing a low cost and compact solution to reduce the noise component in an electronic circuit without sacrificing other performance metrics of the circuit.SUMMARY

[0009] According to a first aspect of the present disclosure, a circuit is presented, comprising: a first node configured to output a first voltage, the first voltage including a noise component; a second node configured to be charged or discharged to a second voltage that is based on the first voltage, the second node being a capacitive node; and a rectifier-based noise trap coupled between the first node and the second node, wherein the rectifier-based noise trap is configured to provide a first unidirectional low impedance current conduction path to charge the second node when the first voltage is greater than the second voltage, and the rectifierbased noise trap is further configured to provide a second unidirectional low impedance current conduction path to discharge the second node when the first voltage is smaller than the second voltage.

[0010] According to a second aspect of the present disclosure, circuit is presented, comprising: a first node configured to output a first voltage, the first voltage including a first noise component; a capacitive node; and a first rectifier-based noise trap coupled between the first node and the capacitive node via a first transistor switch, wherein during an ON state of the first transistor switch, the first rectifier-based noise trap is configured to provide a first unidirectional low impedance current conduction path between the first node and the capacitive node to charge the capacitive node to a substantially fixed voltage that is based on the first voltage, thereby removing the first noise component from the capacitive node.

[0011] According to a third aspect, a method for trapping a noise component at a capacitive node is presented, the method comprising: providing a first node; providing a capacitive node; coupling a diode-based noise trap between the first node and the capacitive node; generating a first voltage comprising a noise component at the first node; based on the generating, forward biasing a first diode of the diode-based noise trap and reverse biasing a second diode of the diode-based noise trap; based on the forward biasing, charging the capacitive node with the first voltage; and based on the reverse biasing, trapping the noise component at the capacitive node, wherein the trapping of the noise component includes exclusion at the capacitive node of a discharge path for low amplitude voltages of the noise component.

[0012] Further aspects of the disclosure are provided in the description, drawings and claims of the present application.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.

[0014] FIG. 1 shows a simplified block diagram of an electronic circuit comprising noise generated by a power supply.

[0015] FIG. 2 shows a simplified block diagram of an electronic circuit including a noise trap according to an embodiment of the present disclosure.

[0016] FIG. 3 shows a simplified block diagram of an electronic circuit including a noise trap according to another embodiment of the present disclosure.

[0017] FIG. 4A shows a simplified block diagram of an electronic circuit including a noise trap according to yet another embodiment of the present disclosure.

[0018] FIG. 4B shows a simplified block diagram of an electronic circuit including a noise trap according to yet another embodiment of the present disclosure.

[0019] FIG. 5 shows two exemplary implementations of a voltage switching circuit.

[0020] FIG. 6 shows an exemplary implementation of the electronic circuit represented in FIG. 2.

[0021] FIG. 7 shows two exemplary implementations of diode pairs connected in antiparallel.

[0022] FIG. 8 shows a block diagram of an exemplary power supply circuit.

[0023] FIG. 9 is a process chart showing various steps of a method according to the present disclosure for trapping a noise component at a capacitive node.

[0024] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0025] FIG. 1 shows a simplified block diagram of an electronic circuit (100) comprising noise, Np, generated by a power supply (105) and coupled to a load transistor, MK, with a capacitive input, CG. AS used herein, a capacitive node may be referred to as a node that is coupled to a capacitive load. In particular, considering the electronic circuit (100) of FIG. 1, the input node, G, of the circuit block (120) represents a capacitive load to the output of the control circuit block (110). With reference to FIG. 1, at the (low) frequencies of the noise component, NOUT, the gate capacitor, CG, may also charge and discharge through the low impedance conduction path provided by (the output of) the control circuit block (110). In turn, the charging and discharging of the gate capacitor, CG, may generate a gate voltage, VG, at the gate, G, of the transistor, MK, that substantially represents the output voltage, VOUT, including both a nominal voltage and the noise component, NOUT.

[0026] Teachings according to the present disclosure take advantage of presence of a gate capacitor (e.g., CG and / or CGS of FIG. 1) at an input node (e.g., node G, gate of transistor MK of FIG. 1) of a circuit block (e.g., 120 of FIG. 1) to trap a noise component (e.g., NOUT of FIG. 1) from a (noisy) output voltage (e.g., VOUT of FIG. 1) to the input node by removing, for the noise component, a current discharge path from the input node. Teachings according to the present disclosure may allow the input node to be charged to a high voltage level that is based on a peak (highest) voltage level provided by the output voltage (e.g., VOUT = VNOM + NOUT), but may not allow the input node to be discharged by relatively small voltage levels of the noise component (e.g., NOUT).

[0027] Teachings according to the present disclosure may allow the input node (e.g., node G, gate of transistor MK of FIG. 1) to be discharged by a peak (lowest) voltage level provided by the output voltage (e.g., VOUT of FIG. 1). In other words, the peak (highest and lowest) voltage levels provided by the control voltage may see low impedance conduction paths that allow the input node to be charged and discharged for normal operation of the circuit block (e.g., 120 of FIG. 1). On the other hand, the relatively small voltage levels of the noise component (e.g., NOUT of FIG. 1) may see high impedance conduction paths (e.g., forsubstantially no current conduction) that may not allow a charged input node to be discharged, or a discharged input node to be charged, by such small voltage levels.

[0028] FIG. 2 shows a simplified block diagram of an electronic circuit (200) including a noise trap (250, e.g., including diodes Dp, DN) according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the noise trap (250) may be arranged between an output of the control circuit block (110) that carries the (noisy) output voltage, VOUT, and the input node of the circuit block (120) represented by the gate, G, of the transistor, MK. Such arrangement may allow the input node, G, of the circuit block (120) to be charged by a peak (highest) voltage level of the output voltage, VOUT (where the peak voltage is the sum of the nominal voltage VNOM and a peak volage of the noise component NOUT), and once charged, to remain at that level without being discharged by further disturbances in the noise component, NOUT. It should be noted that implementation of the noise trap (e.g., circuit block 250 of FIG. 2) according to the present disclosure may not be limited to use of one or more diodes (e.g., Dp and DN of FIG. 2) operating as rectifier elements as other known in the art rectifier elements, such as, for example, synchronous / active rectifiers, may be used instead of the diodes. Accordingly, in the foregoing description, use of diodes as rectifier elements of the present noise trap, also referred to as “rectifier-based noise trap”, should be considered as merely exemplary and nonlimiting.

[0029] As shown in FIG. 2, according to an embodiment of the present disclosure, the noise trap (250) may include (rectifier elements such as) a first diode, Dp, and a second diode, DN, arranged in antiparallel. In other words, the two diodes, Dp and DN, are connected in parallel but with reversed polarities such that the anode of the first diode, Dp, is connected to the cathode of the second diode, DN, and the cathode of the first diode, Dp, is connected to the anode of the second diode, DN.

[0030] During a charging phase (e.g., when Vout is greater than VG) of the input node, G, the first diode, Dp, shown in FIG. 2 may be forward biased, and therefore conducting, to provide a low impedance conduction path for charging of the input node, G, to the nominal (higher than VG) voltage level of the output voltage, VOUT. Such low impedance conduction path may allow charging of the input node, G, without substantially affecting timing information (e.g., provided by transitions) that may be provided in the output voltage, VOUT, by the control circuit block (110). Such charging phase may be triggered by an increasing voltage level of the output voltage, VOUT, under control of the control circuit block (110).

[0031] Furthermore, during the charging phase of the input node, G, the second diode, DN, shown in FIG. 2 may be reverse biased, and therefore not conducting, to prevent discharging of the input node, G, by the noise component, NOUT. Accordingly, the input node, G, may substantially hold a charged voltage level while being substantially isolated from further disturbances in the noise component, NOUT.

[0032] With continued reference to FIG. 2, the first and second diodes, Dp and DN, may remain in their respective forward and reversed biased states so long as the output voltage, VOUT, does not decrease substantially. It should be noted that in some cases, the output voltage, VOUT, may include one or more steady states, each defined by a substantially constant nominal voltage level of the output voltage, VOUT, that defines a corresponding mode of operation the circuit block (120. e.g., an ON state or OFF state of a transistor-based switch, a biasing point of a transistor of an amplifier, etc.). Although in some applications the steady states may change at rates that are slower than a frequency content (e.g., 100’s KHz to few MHz) of the noise component, NOUT, teachings according to the present disclosure may equally apply to applications where the steady states may change at rates similar to or greater than a frequency content of the noise component, NOUT.

[0033] With further reference to FIG. 2, so long as the voltage, VOUT, is within one threshold voltage, VTHN, of the second diode, DN, from the voltage, VG, then the second diode, DN, may remain in a high impedance state, and no conduction path for discharging of the input node, G, may be available. Accordingly, because the relatively small voltage levels of the noise component (NOUT, e.g., voltage levels / amplitudes in a range of millivolts to 10’s of millivolts, mV) present at the voltage, VOUT, may be smaller than the threshold voltage (VTHN, in a range of few 100’s of millivolts) of the second diode, DN, then such small volage levels may not, by themselves, discharge the input node, G. Accordingly, the noise trap (250) of the present teachings shown in FIG. 2, in conjunction with the capacitive node VG, may be said to trap the noise component, NOUT, at the input node, G, by first allowing the noise component, as part of the voltage, VOUT, to pass through the conducting first diode, Dp, to charge the input node, G, to a peak (highest) voltage level provided by the output voltage, VOUT. AS the difference in voltages between VOUT and the input node, G, decreases below VTHP, the first diode, Dp, no longer provides a low impedance conduction path. Because the first diode, Dp, no longer provides a low impedance conduction path and the second diode, DN, is reverse biased, the input node, G, no longer has a low impedance conduction path by which the charge stored inthe gate capacitance, CG, could be discharged, effectively isolating the input node, G, from any further noise contributed by the noise component, Nout.

[0034] Under control of the control circuit block (110), the output voltage, VOUT, may decrease by an amount (e.g., one threshold voltage, VTHN, of the second diode DN) that is sufficiently low to put second diode, DN, in conduction (i.e., forward biased), and therefore the input node, G, shown in FIG. 2, may discharge through a low impedance conduction path provided by the conducting second diode, DN, to (gradually) reach a peak (lowest) voltage level provided by the output voltage, VOUT. AS the magnitude of the difference in voltages between VOUT and the input node, G, decreases below VTHN, the second diode, DN, no longer provides a low impedance conduction path. Because the second diode, DN, no longer provides a low impedance conduction path and the first diode, Dp, is reverse biased, the input node, G, no longer has a low impedance conduction path by which the charge stored in the gate capacitance, CG, could be discharged, effectively isolating the input node, G, from any further noise contributed by the noise component, Nout.

[0035] Based on the above, it may be clear that during operation of the circuit (200) of FIG. 2, the noise trap (250) according to the present teachings may selectively provide a unidirectional low impedance (current) conduction path from the output of the control circuit block (110) to the input of the circuit block (120), or vice versa. In particular, the noise trap (250) according to an embodiment of the present teachings may be coupled (e.g., connected) between a control node (e.g., output of 110) and a capacitive node (e.g., input of 120) to selectively charge and discharge the capacitive node based on a control voltage (e.g., VOUT) provided at the control node. In particular, such control voltage (e.g., VOUT) in combination with a (charged) voltage at the capacitive node (e.g., VG) may establish a difference voltage (e.g., VOUT - VG) that may forward bias one of the diodes (e.g., Dp or DN) and reverse bias the other, thereby providing a unidirectional low impedance current path through the one diode that is forward biased.

[0036] With continued reference to FIG. 2, considering the threshold voltages, VTHP and VTHN, of the diodes, Dp and DN (which may be treated as ideal diodes), the diode Dp may be considered forward biased when VOUT - VG > VTHP, and the diode DN may be considered forward biased when VG - VOUT > VTHN. Accordingly, a condition for forward biasing of the diode Dp may be provided by VOUT > VG + VTHP, and a condition for forward biasing of the diode DN may be provided by VOUT < VG - VTHN. In other words, the control voltage (e.g.,VOUT) may need to change (e.g., increase or decrease) by about (VTHP + VTHN) in order to switch from a unidirectional low impedance conduction path provided by one diode to a unidirectional (and opposite direction) low impedance conduction path provided by the other diode. This means that noise components that may have voltage levels substantially smaller than either VTHP or VTHN may not affect conduction states of the diodes Dp and DN. Accordingly, the noise trap (250) according to the present teachings may provide a separation (e.g., hysteresis in volts of the control voltage, VOUT) of about (VTHP + VTHN) between charging and discharging of the capacitive node (e.g., VG). In other words, the noise trap (250) according to the present teachings may be considered as a nonlinear filter that traps, at a capacitive node, noise components having amplitudes below the threshold voltages VTHP and / or VTHN. It should be noted that while it is useful for explanation to treat these diodes as ideal, practical diodes may be understood to perform in a substantially similar manner.

[0037] In the circuit (200) of FIG. 2, the output voltage, VOUT, provided by the control circuit block (110) may be based on a level of the supply voltage, Vp, and a level of a reference ground (VGND, e.g., zero volts) provided to the control circuit block (110). Assuming that VOUT is positive and VGND is zero, then the output voltage, VOUT, may also be positive or zero. In some nonlimiting cases, the output voltage, VOUT, may be in a range from VGND to Vp. However, such unipolar configuration should not be considered as limiting the scope of the present teachings as in some embodiments according to the present disclosure, the output voltage, VOUT, may be in a range from a negative voltage to a positive voltage. Such bipolar configuration is shown in FIG. 3.

[0038] The electronic circuit (300) of FIG. 3 is based on the electronic circuit (200) with a difference that the control circuit block (110) of FIG. 3 is provided with a negative supply voltage, VN, in addition to the positive supply voltage, Vp. In this case, the (negative) power supply block (205) that generates the negative supply voltage, VN, may also include a noise component, NN, that may couple to the output voltage, VOUT. In other words, the noise component, NOUT, at the output voltage, VOUT, of the control circuit block (110) of FIG. 3 may be based on a combination of one, or both of, the noise components Np or NN. The source of the noise component, NOUT, however may be considered irrelevant to the noise trapping functionality of the noise trap (250) according to the present disclosure. In other words, the above description of functionality of the noise trap (250) with reference to FIG. 2 may equally apply to the electronic circuit (300) of FIG. 3.

[0039] FIG. 4 A shows a simplified block diagram of an electronic circuit (400 A) including a noise trap (250p, e.g., including diode Dp as rectifier element) according to another embodiment of the present disclosure. In such embodiment according to the present disclosure, the noise component, Np, of the positive supply voltage, Vp, may be trapped at the capacitive high side input node, Hs, by using a single diode, Dp. As shown in FIG. 4A, the diode, Dp, may be arranged to provide a low impedance conduction path between the output of the positive power supply block (105) and a positive supply input (e.g., high side input, node Hs) of the control circuit block (110). In other words, in the embodiment according to the present disclosure shown in FIG. 4A, the noise component, Np, may be trapped at the capacitive high side input node, Hs, and at any nodes coupled to Hs (e.g., input node G).

[0040] In the configuration (400A) of FIG. 4A, the node Hs may be a capacitive node by virtue of the presence of a capacitive load (e.g., parasitic shunt capacitance) at the node Hs, or may be coupled to a capacitive load via a low impedance conduction path. Because the diode Dp is arranged in series connection between the positive power supply block (105, coupled to anode of the diode Dp) and the (capacitive) node Hs (coupled to cathode of the diode Dp), it may provide a low impedance conduction path for charging of the node Hs to a high voltage level that is based on a peak (highest) voltage level provided by the positive supply voltage, Vp (e.g., Vp = VP NOM + Np), while preventing the node Hs from discharging (therefore charging up to a fixed or substantially fixed voltage). Accordingly, the noise component, Np, present at the positive supply voltage, Vp, may be trapped at the node Hs.

[0041] In some embodiments the node Hs shown in FIG. 4 A may be coupled to the input (capacitive) node, G, of the circuit block (120) via a low impedance conduction path provided by the control circuit block (110). For example, the node Hs of the control circuit block (110) may be coupled to a switch circuit included in the control circuit block (110) that may selectively provide such low impedance conduction path to the input node, G. Some exemplary implementations of a control circuit block (110) comprising a switch circuit are provided with reference to FIG. 5 later described.

[0042] As shown in FIG. 4A, the reference ground, VGND, may be provided to the control circuit block (110) via a node, Ls (e.g., low side input for a unipolar configuration). In this case, effectively no noise component may be (expected to be) present at the node Ls, and therefore, as shown in FIG. 4A, there may not be a need to trap / block a noise component at the node Ls. On the other hand, considering the (bipolar) configuration (400B) of FIG. 4B whereinthe node Ls may be coupled to a negative supply voltage, VN, generated by a power supply block (205), a noise trap (250N, e.g., including diode DN as rectifier element) may be used to enable trapping of the noise component, NN, of the power supply block (205).

[0043] The node Ls shown in FIG. 4B may include characteristics (i.e., capacitive load) similar to ones described above for the node Hs with reference to FIG. 4A, including, for example, a selective coupling via a low impedance conduction path to the input node, G, of the circuit block (120). Because the diode DN is arranged in series connection between the negative power supply block (205, coupled to cathode of the diode DN) and the (capacitive) node Ls (coupled to anode of the diode DN), it may provide a low impedance conduction path for discharging of the node Ls to a low voltage level that is based on a peak (lowest) voltage level provided by the negative supply voltage, VN (e.g., |VN| = |VN_NOM| + |NN|), while preventing the node Ls from charging (therefore discharging down to a fixed or substantially fixed voltage). Accordingly, the noise component, NN, present at the negative supply voltage, VN, may be trapped at the node Ls.

[0044] As previously described, the circuit block (120) may include other transistors, including for example, a transistor, MK-I, that as shown in FIG. 4B, may be in series connection with the transistor, MK. Such series connection of two or more transistors may be found in, for example, stacked transistor amplifiers (e.g., RF amplifier) and stacked transistor switches (e.g., RF switches). In a stacked transistor (RF) switch, the gates of the series connected transistors may be controlled via a same control voltage (e.g., VOUT of FIG. 4B coupled to all gates, G, G’, etc.). On the other hand, in a stacked transistor (RF) amplifier, the gates of the series connected transistors may be controlled via different control voltages, each generated by a circuit similar to the circuit shown in, for example, FIG. 4B (or any of the circuits shown in FIGs. 3-4 inclusive of a corresponding noise trap).

[0045] FIG. 5 shows two exemplary implementations of a voltage switching circuit that may be included in the control circuit block (110) described above with reference to, for example, FIGs. 1-4. In the configuration shown on left side of FIG. 5, the control circuit block (110a) may include a high side transistor (Mp, e.g., p-type) coupled to the node Hs and a low side transistor (Mn, e.g., n-type) coupled to the node Ls. Furthermore, an output stage (105OUT) coupled to the transistors Mp and Mn, may provide the output voltage, VOUT, of the control circuit block (110a.- l i

[0046] With continued reference to FIG. 5, during a first mode of operation of the control circuit block (110a), the transistor Mp may be turned ON and the transistor Mn may be turned OFF so that a voltage at the node Hs may be provided to the output stage (105OUT). Likewise, during a second mode of operation of the control circuit block (110a), the transistor Mp may be turned OFF and the transistor Mn may be turned ON so that a voltage at the node Ls may be provided to the output stage (105OUT). In turn, the output stage (105OUT) may (selectively) provide a version of the voltage at the node Hs or Ls as the output voltage, VOUT.

[0047] In the first mode of operation of the control circuit block (110a) of FIG. 5, a combination of the turned-ON transistor Mp and the output stage (105OUT) may provide a low impedance conduction path between the node Hs and the output node of the control circuit block (110a) that carries the output voltage, VOUT. Likewise, in the second mode of operation, a combination of the turned-ON transistor Mn and the output stage (105OUT) may provide a low impedance conduction path between the node Ls and the output node of the control circuit block (110a).

[0048] The transistors Mp and Mn of the control circuit block (110a) of FIG. 5 may be controlled by respective gate voltages for operation according to the first or second modes of operation. Furthermore, as shown in FIG. 5, respective sources of the transistors Mp and Mn may be coupled (e.g., connected) to the nodes Hs and Ls, and respective drains of the transistors Mp and Mn may be coupled (e.g., connected) to the output stage (105OUT). The output stage (105OUT) may include passive and / or active (e.g., transistor) elements.

[0049] The control circuit block (110b) shown in the right side of FIG. 5 may be considered a particular implementation of the control circuit block (110a) in which the output stage (105OUT) is a short circuit. Accordingly, as shown in FIG. 5, the output voltage, VOUT, may be provided at the drain of the transistor Mp or at the drain of the transistor Mn. Under control of a control voltage, Ctrl, provided to gates of the transistors Mp and Mn, one of the transistors may be turned ON while the other may be turned OFF (e.g., a same control voltage may have opposite effect on the two transistors having opposite polarities).

[0050] The voltage switching circuits shown in the control circuit blocks (110a, 110b) of FIG. 5 may be used to implement, for example, an RF switch driver circuit that may provide a switching control signal (e.g., VOUT) that switches between two voltage levels (e.g., voltages at nodes Hs and Ls) to an RF switch comprising one or more series-connected transistors (e.g.,including transistor MK of FIGS. 3-4). By including the noise trap according to the present teachings in a path between the output of the RF switch driver and a control input node (e.g., node G of FIGs. 2-4) of the RF switch (e.g., according to FIGs. 2-3), or in a path between output of supply voltages and the RF switch driver (e.g., according to FIGs. 4A / 4B), noise at the control input node (e.g., node G of FIGs. 2-4) of the RF switch can be trapped.

[0051] FIG. 6 shows an exemplary implementation of the electronic circuit represented in FIG. 2. In particular, the control circuit block (110c) of the electronic circuit (600) may comprise an operational amplifier (Op, e.g., error amplifier) configured to generate the output voltage, VOUT, based on a reference voltage, VRef. Furthermore, as shown in FIG. 6, the operational amplifier, Op, may be arranged in a feedback circuit to correct / adjust the output voltage, VOUT, based on a difference between a voltage from the circuit block (120, stacked transistor amplifier) that may be provided to a positive (or negative) input of the operational amplifier, Op, and the reference voltage, VRef, that may be provided to a negative (or positive) input of the operational amplifier, Op. In the exemplary nonlimiting implementation shown in FIG. 6, the feedback voltage provided to the positive input of the operational amplifier, Op, may be a voltage at a drain of the transistor, MK. Such feedback configuration may allow, for example, maintaining a nominal operating condition (e.g., operating points, for example a fixed drain voltage and bias current) of the transistor, MK, by controlling the gate voltage, VG, of the transistor, MK. It should be noted that depending on a position / rank of the transistor MK in the circuit block (120), the feedback voltage to the operational amplifier, Op, may be provided by either a drain (as shown in FIG. 6) or a source of the transistor, MK.

[0052] The control circuit block (110c) of FIG. 6 may be used to bias the gate, G, of the transistor, MK, while eliminating the noise component, NOUT, at the gate, G, via the noise trap (250) arranged between nodes carrying VOUT and VG. AS previously described in the present disclosure, such noise component, NOUT, may be in part generated within the operational amplifier, Op, and in part based on the noise, Np, of the power supply block (105). Because of the feedback circuit, the operational amplifier, Op, may adjust (e.g., increase / decrease) the output voltage, VOUT, and therefore the gate voltage, VG, such as to maintain a substantially zero difference between voltages provided to the positive and negative inputs of the operational amplifier, Op. In doing so, the feedback circuit may drive each of the diodes, Dp and DN, to conduct (forward biased) or not conduct (reverse biased) to accordingly charge or discharge the gate voltage, VG. Such configuration may be used, for example, for biasing transistors of astacked transistor amplifier (e.g., RF amplifier) that may include, as shown in FIG. 6, one or more series connected transistors (e.g., MK and MK-I). In such case, gates (e.g., G, G’) of the transistors may be biased via respective feedback circuits (e.g., 110c, Dp, DN) similar to one showed in FIG. 6, the respective feedback circuits operating from the same (noisy) supply voltage, Vp, of the power supply block (105) and using respective (e.g., different) reference voltages (e.g., VRef).

[0053] The noise trap (250) according to the present disclosure may include any rectifying device (e.g., diode, synchronous / active rectifier, etc.) that may be selectively controlled to conduct or not conduct a current in one direction only (i.e., provide a unidirectional flow of current) between two nodes of the device. According to some nonlimiting embodiments of the present disclosure, such rectifying device may include a semiconductor n-p junction diode as represented by each of the diodes Dp and DN on the left side of FIG. 7, or a diode-connected transistor device (e.g., gate and drain connected to one another) as represented by each of the diode-connected transistors MDP and MDN on the right side of FIG. 7. In a case of the antiparallel diode-based noise traps (250) shown in FIG. 7, threshold voltages (e.g., VTHP, VTHN) of the diodes, Dp and DN, may be equal or different according to the present teachings. Selection of such threshold voltages may be based on, for example, performance and / or design goals that may or may not relate to noise trapping performance due to the threshold voltages’ effect on the magnitude of noise, Nout, that may be filtered, the diodes’ conductance, and the realized voltages at the input of subsequent circuits, such as VG of block (120). However, it should be noted that any drop in a control voltage due to presence of (threshold voltages of) the noise trap according to the present teachings may be factored in the overall circuit design / implementation. In some cases, such drop may be negligible in view of (high) voltage levels of the control voltage, or irrelevant in view of essential information of the control voltage (e.g., timing provided by transitions and not voltage levels). In other cases, the drop may be compensated via, for example, a feedback circuit (e.g., FIG. 6).

[0054] FIG. 8 shows a (simplified) block diagram of an exemplary power supply circuit (800) that may be configured to generate a positive voltage, Vp, and a negative voltage, VN, having respective voltage levels suitable for operation of, for example, the control circuit block (110) and / or the circuit block (110) described above with reference to FIGs. 1 -6. In other words, the power supply circuit (800) may be used as the power supply blocks (105) and / or (205) described above with reference to FIGs. 1-6. In the configuration shown in FIG. 8, the voltages(e.g., Vp, VN) are generated from a single positive (main) supply voltage, VDD, that as shown in FIG. 8 is provided to various functional blocks (e.g., 810, 820, 830, 835, 840, 845). In a case of a handheld device, the single supply voltage, VDD, may be a battery or a reduced regulated voltage from a battery. Other implementations may include two separate (main) supply voltages (e.g., a negative and a positive main supply voltage), but similar functional blocks (e.g., 810, 830, 835, 840, 845) to generate each of the positive voltage, Vp, and the negative voltage, VN.

[0055] In some implementations, the functional blocks (e.g., 810, 830, 835, 840, 845) of FIG. 8 may include a block (810) that is configured to generate a stable reference (e.g., bandgap, reference) voltage, VBG, from the (e.g., slowly varying) supply voltage, VDD. A block (820) may convert the positive supply voltage, VDD, to a negative supply volage (-VDD, e.g., inverted version of VDD) that may be of a substantially equal or different magnitude. In turn, the positive and negative charge pump blocks (830) and (840) may respectively charge pump (e.g., by a factor of 3X to 5X, such as for example, 4X) the positive and negative supply voltages, VDD, and (-VDD), which are in turn fed to respective positive and negative voltage regulator blocks (835) and (845) for regulation with the help of the stable reference voltage, VBG. Accordingly, as shown in FIG. 8, output of the positive and negative voltage regulator blocks (835) and (845) respectively provide the positive and negative voltages, Vp and VN. Functional blocks of the power supply circuit (800) may be removed in case a single positive voltage (e.g., Vp) or negative voltage (e.g., VN) is desired. In some implementations, a control signal, CTLBG, may control operation of the power supply circuit according to, for example, an active mode (e.g., generate Vp and VN) and an inactive mode (e.g., do not generate Vp and VN).

[0056] The presence of a charge pump (e.g., 830 or 840), which may include an oscillator, and / or of a voltage regulator (e.g., 835 or 845) in the power supply circuit (800) of FIG. 8 may be a source of noise at the output (e.g., Vp or VN). By arranging the noise trap according to the present teachings in a path of the output (e.g., Vp or VN) that leads to a capacitive node, the noise from such charge pump (as well as any other type of supply, such as, for example, a switch mode power supply) can be trapped.

[0057] FIG. 9 is a process chart showing various steps of a method according to the present disclosure for trapping a noise component at a capacitive node. As can be seen in FIG. 9, such steps comprise: providing a first node and providing a capacitive node, per step (910); coupling a diode-based noise trap between the first node and the capacitive node, per step (920);generating a first voltage comprising a noise component at the first node, per step (930); based on the generating, forward biasing a first diode of the diode-based noise trap and reverse biasing a second diode of the diode-based noise trap, per step (940); based on the forward biasing, charging the capacitive node with the first voltage, per step (950); and based on the reverse biasing, trapping the noise component at the capacitive node, per step (960), wherein the trapping of the noise component includes exclusion at the capacitive node of a discharge path for low amplitude voltages of the noise component.

[0058] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0059] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0060] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals duringoperation due to FET stacking, good linearity, and high frequency operation (z.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0061] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities reversed, depending on a particular specification and / or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0062] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g. , filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher- level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0063] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0064] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

CLAIMS1. A circuit, comprising: a first node configured to output a first voltage, the first voltage including a noise component; a second node configured to be charged or discharged to a second voltage that is based on the first voltage, the second node being a capacitive node; and a rectifier-based noise trap coupled between the first node and the second node, wherein the rectifier-based noise trap is configured to provide a first unidirectional low impedance current conduction path to charge the second node when the first voltage is greater than the second voltage, and the rectifier-based noise trap is further configured to provide a second unidirectional low impedance current conduction path to discharge the second node when the first voltage is smaller than the second voltage.

2. The circuit of claim 1, wherein: the rectifier-based noise trap comprises a first diode and a second diode arranged in antiparallel.

3. The circuit of claim 2, wherein: an anode of the first diode is coupled to the first node and a cathode of the first diode is coupled to the second node, and a cathode of the second diode is coupled to the first node and an anode of the second diode is coupled to the second node.

4. The circuit of claim 2 or claim 3, wherein: the first unidirectional low impedance current conduction path is provided by a forward biased state of the first diode and a reverse biased state of the second diode, and the second unidirectional low impedance current conduction path is provided by a reverse biased state of the first diode and a forward biased state of the second diode.

5. The circuit of any one of claims 2-4, wherein: the first voltage comprises a high level and a low level.

6. The circuit of claim 5, wherein: an amplitude of the noise component during the high level of the first voltage is different from an amplitude of the noise component during the low level of the first voltage.

7. The circuit of claim 5, wherein: the high level of the first voltage is provided by an ON state of a first switch that is coupled to a high side supply voltage having an output voltage at the high level, and the low level of the first voltage is provided by an ON state of a second switch that is coupled to a low side supply voltage having an output voltage at the low level.

8. The circuit of claim 6 or claim 7, wherein: the high level is a positive voltage, and the low level is a reference zero voltage or a negative voltage.

9. The circuit of claim 6 or claim 7, wherein: the first switch comprises a first transistor and the second switch comprises a second transistor that is in series connection with the first transistor, and the first node is coupled to drains of the first and second transistors.

10. The circuit of claim 9, wherein: the second node is provided by a gate of a transistor.

11. The circuit of claim 10, wherein: the transistor is in series connection with one or more additional transistors.

12. The circuit of claim 11, wherein: the transistor and the one or more additional transistors are configured to operate as a stacked transistor switch.

13. The circuit of any one of claims 2-9, wherein: the first node is provided by an output of an operational amplifier, and the second node is provided by a gate of a transistor.

14. The circuit of claim 13, wherein: a first input of the operational amplifier is coupled to a drain or a source of the transistor, and a second input of the operational amplifier is coupled to a reference voltage.

15. The circuit of claim 13 or claim 14, wherein: the transistor is in series connection with one or more additional transistors.

16. The circuit of claim 15, wherein: the transistor and the one or more additional transistors are configured to operate as a stacked transistor amplifier.

17. A circuit, comprising: a first node configured to output a first voltage, the first voltage including a first noise component; a capacitive node; and a first rectifier-based noise trap coupled between the first node and the capacitive node via a first transistor switch, wherein during an ON state of the first transistor switch, the first rectifier-based noise trap is configured to provide a first unidirectional low impedance current conduction path between the first node and the capacitive node to charge the capacitive node to a substantially fixed voltage that is based on the first voltage, thereby removing the first noise component from the capacitive node.

18. The circuit of claim 17, further comprising: a second node configured to output a second voltage that is substantially smaller than the first voltage, the second voltage including a second noise component; and a second rectifier-based noise trap coupled between the second node and the capacitive node via a second transistor switch, wherein during an ON state of the second transistor switch, the second rectifier-based noise trap is configured to provide a second unidirectional low impedance current conduction path between the capacitive node and the second node to discharge the capacitive nodeto a substantially fixed voltage that is based on the second voltage, thereby removing the second noise component from the capacitive node.

19. The circuit of claim 18, wherein: the first and second rectifier-based noise traps comprise respective first diode and second diode, an anode of the first diode is coupled to the first node and a cathode of the first diode is coupled to a source of the first transistor switch, and a cathode of the second diode is coupled to the second node and a cathode of the second diode is coupled to a source of the second transistor switch.

20. The circuit of claim 18 or claim 19, wherein: respective drains of the first and second transistor switches are coupled to the capacitive node.

21. The circuit of claim 20, wherein: the capacitive node is provided by a gate of a transistor.

22. The circuit of any one of claims 18-21, wherein: the first voltage is a positive voltage generated by a power supply circuit that includes at least one of a positive charge pump or a voltage regulator.

23. The circuit of claim 22, wherein: the second voltage is a negative voltage generated by a power supply circuit that includes at least one of a negative charge pump or a voltage regulator.

24. A method for trapping a noise component at a capacitive node, the method comprising: providing a first node; providing a capacitive node; coupling a diode-based noise trap between the first node and the capacitive node; generating a first voltage comprising a noise component at the first node; based on the generating, forward biasing a first diode of the diode-based noise trap and reverse biasing a second diode of the diode-based noise trap; based on the forward biasing, charging the capacitive node with the first voltage; andbased on the reverse biasing, trapping the noise component at the capacitive node, wherein the trapping of the noise component includes exclusion at the capacitive node of a discharge path for low amplitude voltages of the noise component.

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