Display substrate, manufacturing method therefor and display apparatus

Abstract

A display substrate, a manufacturing method therefor and a display apparatus. The display substrate comprises a plurality of repetitive units (100), a repetitive unit (100) comprising a plurality of sub-pixels; a sub-pixel at least comprises a pixel driving circuit, the pixel driving circuit being connected to a first power line (51); the pixel driving circuit at least comprises a driving transistor (T2) and a power connection electrode (20), the driving transistor (T2) comprising a driving active layer (22); a first end of the power connection electrode (20) is connected to the first power line (51) by means of a power via hole (K1), and a second end of the power connection electrode (20) is connected to a first region of the driving active layer (22) by means of an active via hole (K2); adjacent sub-pixels in the adjacent repetitive units in a pixel row direction and a pixel column direction share the power via holes (K1).

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. With the continuous development of display technology, display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being connected with a first power supply line, the first power supply line being configured to provide a first power supply signal to the pixel driving circuit; the pixel driving circuit at least comprising a driving transistor and a power supply connection electrode, the driving transistor at least comprising a driving active layer; in at least one sub-pixel, a first end of the power supply connection electrode is connected with the first power supply line through a power supply via, and a second end of the power supply connection electrode is connected with a first region of the driving active layer through an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power supply via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power supply via.

[0006] In an exemplary embodiment, the first regions of the driving active layers of the two adjacent sub-pixels in the two adjacent repeating units in the pixel column direction are connected with each other.

[0007] In an exemplary embodiment, the driving active layers of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are integrally connected, the driving active layer of the integrally connected structure has a groove, the openings of the grooves in at least one repeating unit are oppositely arranged, the groove has a groove width and a groove depth, the groove width is smaller than the groove depth, the groove width is the size in the pixel column direction, and the groove depth is the size in the pixel row direction.

[0008] In an exemplary embodiment, the first ends of the power supply connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are integrally connected, and the power supply connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are shared.

[0009] In an exemplary embodiment, the power supply connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are integrally connected.

[0010] In an exemplary embodiment, the pixel driving circuit further comprises an active connection electrode, the first end of the active connection electrode is connected with the first region of the driving active layer, the power supply connection electrode is connected with the first power supply line and the second end of the active connection electrode through a transfer via, the transfer via comprises a shallow half-hole and a deep half-hole, the shallow half-hole is an active via hole exposing the second end of the active connection electrode, and the deep half-hole is a power supply via hole exposing the first power supply line.

[0011] In an exemplary embodiment, the active connection electrode and the driving active layer are integrally connected.

[0012] In an exemplary embodiment, two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the transfer via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the transfer via.

[0013] In an exemplary embodiment, two adjacent sub-pixels in adjacent repeating units in the pixel row direction and the pixel column direction share the transfer via.

[0014] In an exemplary embodiment, the second ends of the active connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are integrally connected, and the active connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are shared.

[0015] In an exemplary embodiment, the active connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are integrally connected.

[0016] In an exemplary embodiment, the first regions of the second active layers of the adjacent sub-pixels in the adjacent repeating units in the pixel row direction and the pixel column direction are connected to each other through the active connection electrodes.

[0017] In an exemplary embodiment, the adjacent sub-pixels in the adjacent repeating units in the pixel row direction and the pixel column direction share the power supply connection electrodes.

[0018] In an exemplary embodiment, the power supply connection electrodes of the adjacent two sub-pixels in the adjacent two repeating units in the pixel row direction are an integral structure connected to each other, and the power supply connection electrodes of the adjacent two sub-pixels in the adjacent two repeating units in the pixel column direction are an integral structure connected to each other.

[0019] In an exemplary embodiment, at least one repeating unit includes two first power supply lines, four data signal lines, and one compensation signal line, the compensation signal line is located between adjacent pixel columns, two first power supply lines are located on both sides of the repeating unit in the pixel row direction, and in the pixel row direction, the first first power supply line, the first data signal line, the second data signal line, the compensation signal line, the third data signal line, the fourth data signal line, and the second first power supply line are sequentially arranged, and the driving transistor is arranged between the second data signal line and the compensation signal line or between the compensation signal line and the third data signal line.

[0020] In an exemplary embodiment, in at least one sub-pixel, the pixel driving circuit further includes a first connection electrode, a second connection electrode, and a storage capacitor, the storage capacitor includes at least a first plate, the first connection electrode and the second connection electrode are arranged on both sides of the first plate in the pixel column direction and are connected to the first plate respectively; in at least one sub-pixel, the width of the first connection electrode is smaller than the width of the second connection electrode, and the width is the size in the pixel row direction.

[0021] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a second conductive layer, a semiconductor layer, and a third conductive layer arranged in sequence on a substrate, the first power supply line is arranged in the second conductive layer, the driving active layer is arranged in the semiconductor layer, and the power supply connection electrode is arranged in the third conductive layer.

[0022] In an exemplary embodiment, the width of the driving active layer in the adjacent sub-pixels in the pixel row direction is different, and the width of the driving active layer in the adjacent sub-pixels in the pixel column direction is different, and the width is the minimum size of the driving active layer in the pixel column direction.

[0023] In an exemplary embodiment, in the pixel row direction, the first sub-pixel and the second sub-pixel are arranged alternately, the width of the driving active layer in the first sub-pixel is greater than the width of the driving active layer in the second sub-pixel; or, in the pixel row direction, the third sub-pixel and the fourth sub-pixel are arranged alternately, the width of the driving active layer in the third sub-pixel is less than the width of the driving active layer in the fourth sub-pixel.

[0024] In an exemplary embodiment, in the pixel column direction, the first sub-pixel and the third sub-pixel are arranged alternately, the width of the driving active layer in the first sub-pixel is greater than the width of the driving active layer in the third sub-pixel; or, in the pixel column direction, the second sub-pixel and the fourth sub-pixel are arranged alternately, the width of the driving active layer in the second sub-pixel is less than the width of the driving active layer in the fourth sub-pixel.

[0025] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0026] In yet another aspect, the present disclosure also provides a preparation method of a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; the preparation method comprising:

[0027] forming a pixel driving circuit in at least one sub-pixel, the pixel driving circuit being connected with a first power supply line configured to provide a first power supply signal to the pixel driving circuit; the pixel driving circuit comprising at least a driving transistor and a power supply connection electrode, the driving transistor comprising at least a driving active layer; in at least one sub-pixel, a first end of the power supply connection electrode is connected with the first power supply line through a power supply via, and a second end of the power supply connection electrode is connected with a first region of the driving active layer through an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power supply via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power supply via.

[0028] Other aspects can become apparent after reading the following detailed description and understanding the attached drawings. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the technical scheme of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical scheme of the present disclosure, and do not constitute a limitation on the technical scheme of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, the purpose is only to schematically illustrate the present disclosure.

[0030] FIG. 1 is a structural schematic diagram of a display device;

[0031] FIG. 2 is a schematic diagram of a planar structure of a display substrate according to an example embodiment of the present disclosure;

[0032] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit in a repeat unit according to an example embodiment of the present disclosure;

[0033] FIG. 4 is a schematic diagram of a structure of a display substrate according to an example embodiment of the present disclosure;

[0034] FIG. 5 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to an example embodiment of the present disclosure;

[0035] FIGS. 6A and 6B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to an example embodiment of the present disclosure;

[0036] FIGS. 7A and 7B are schematic diagrams of a display substrate after forming a semiconductor layer pattern according to an example embodiment of the present disclosure;

[0037] FIG. 8 is a schematic diagram of a display substrate after forming a second insulating layer pattern according to an example embodiment of the present disclosure;

[0038] FIGS. 9A and 9B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to an example embodiment of the present disclosure;

[0039] FIG. 9C is a cross-sectional view along the A-A direction of FIG. 9A;

[0040] FIGS. 9D to 9F are cross-sectional views along the B-B direction of FIG. 9A;

[0041] FIG. 10 is a schematic diagram of a display substrate after forming a third insulating layer and a planarization layer pattern according to an example embodiment of the present disclosure;

[0042] FIGS. 11A and 11B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0043] FIG. 12 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0044] FIG. 13 is a schematic diagram of another structure of a display substrate according to an example embodiment of the present disclosure;

[0045] FIGS. 14A and 14B are schematic diagrams of a display substrate after forming a semiconductor layer pattern according to another example embodiment of the present disclosure;

[0046] FIG. 15 is a schematic diagram of a display substrate after forming a second insulating layer pattern according to another example embodiment of the present disclosure;

[0047] FIGS. 16A and 16B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to another example embodiment of the present disclosure;

[0048] FIG. 17 is a schematic diagram of another structure of a display substrate according to an example embodiment of the present disclosure;

[0049] FIGS. 18A and 18B are schematic views of another display substrate of the present disclosure after forming a pattern of a semiconductor layer;

[0050] FIG. 19 is a schematic view of another display substrate of the present disclosure after forming a pattern of a second insulating layer;

[0051] FIGS. 20A and 20B are schematic views of another display substrate of the present disclosure after forming a pattern of a third conductive layer.

[0052] Explanation of Reference Numerals:

[0053] 10 - Substrate; 11 - First connection electrode; 12 - Second connection electrode;

[0054] 13 - Third connection electrode; 14 - Fourth connection electrode; 15 - Fifth connection electrode;

[0055] 16 - Sixth connection electrode; 17 - Seventh connection electrode; 18 - Eighth connection electrode;

[0056] 20 - Power supply connection electrode; 21 - First active layer; 22 - Second active layer;

[0057] 23 - Third active layer; 24 - Active connection electrode; 30 - Scan signal line;

[0058] 31 - First gate electrode; 32 - Second gate electrode; 33 - Third gate electrode;

[0059] 51 - First power supply line; 52 - Data signal line; 53 - Compensation signal line;

[0060] 60 - Storage capacitor; 61 - First plate; 62 - Second plate;

[0061] 63 - First electrode; 64 - Anode connection electrode; 71 - First insulating layer;

[0062] 72 - Second insulating layer; 81 - First connection block; 82 - Second connection block;

[0063] 91 - Concave; 92 - Groove; 100 - Repetition unit. DETAILED DESCRIPTION

[0064] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically explain the embodiments of the present disclosure with reference to the drawings. The embodiments can be implemented in a variety of different forms. It should be understood by those skilled in the art that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the embodiments described below. The embodiments in the present disclosure and the features in the embodiments can be combined with each other as long as there is no conflict.

[0065] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0066] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of constituent elements, and are not intended to be limited in terms of numbers.

[0067] In the present specification, for the convenience of explanation, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the constituent elements with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0068] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0069] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0070] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. In the case of using a transistor having opposite polarity or in the case where the direction of current changes in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0071] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0072] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0073] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0074] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or the like.

[0075] In this specification, "about" means not strictly limited to a limit, and a value within a range of a process and measurement error is allowed.

[0076] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the OLED display device can include a timing controller, a data driver, a scan driver, and a pixel array, the timing controller is connected to the data driver and the scan driver respectively, the data driver is connected to a plurality of data signal lines (D1 to Dn) respectively, and the scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively. The pixel array can include a plurality of sub-pixels Pxij, each sub-pixel Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, i and j can be natural numbers. At least one sub-pixel Pxij can include at least a circuit unit and a display unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected to the scan signal line and the data signal line respectively, the display unit can include at least a light emitting device, the light emitting device is connected to the pixel driving circuit of the circuit unit, and the sub-pixel Pxij can refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and connected to the j-th data signal line. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, and can provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of pixels, n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals having on-pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner of sequentially transmitting the scan start signal provided in the form of an on-pulse to the next stage circuit under the control of the clock signal, m can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0077] The exemplary embodiments of the present disclosure provide a display substrate, comprising a plurality of repetitive units, at least one repetitive unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being connected with a first power line configured to provide a first power signal to the pixel driving circuit; the pixel driving circuit comprising at least a driving transistor and a power connection electrode, the driving transistor comprising at least a driving active layer; in at least one sub-pixel, a first end of the power connection electrode is connected with the first power line through a power via, and a second end of the power connection electrode is connected with a first region of the driving active layer through an active via; two adjacent sub-pixels in two adjacent repetitive units in a pixel row direction share the power via, and two adjacent sub-pixels in two adjacent repetitive units in a pixel column direction share the power via.

[0078] In an exemplary embodiment, the first regions of the driving active layers of the two adjacent sub-pixels in the two adjacent repetitive units in the pixel column direction are connected with each other.

[0079] In an exemplary embodiment, the two adjacent sub-pixels in the two adjacent repetitive units in the pixel column direction share the active via.

[0080] In an exemplary embodiment, the pixel driving circuit further comprises an active connection electrode, a first end of the active connection electrode being connected with the first region of the driving active layer, and the power connection electrode being connected with a second end of the active connection electrode and the first power line through a transfer via, the transfer via comprising a shallow half-hole and a deep half-hole, the shallow half-hole being an active via exposing the second end of the active connection electrode, and the deep half-hole being a power via exposing the first power line.

[0081] In an exemplary embodiment, the two adjacent sub-pixels in the two adjacent repetitive units in the pixel row direction share the transfer via, and the two adjacent sub-pixels in the two adjacent repetitive units in the pixel column direction share the transfer via.

[0082] In an exemplary embodiment, the first ends of the power connection electrodes of the two adjacent sub-pixels in the two adjacent repetitive units in the pixel row direction are connected with each other, and the first ends of the power connection electrodes of the two adjacent sub-pixels in the two adjacent repetitive units in the pixel column direction are connected with each other.

[0083] In an exemplary embodiment, the power connection electrodes of the two adjacent sub-pixels in the two adjacent repetitive units in the pixel row direction are an integral structure connected with each other, and the power connection electrodes of the two adjacent sub-pixels in the two adjacent repetitive units in the pixel column direction are an integral structure connected with each other.

[0084] In an example embodiment, the two adjacent sub-pixels in the two adjacent repeating units in the pixel row direction refer to that in the two adjacent repeating units in the pixel row direction, one repeating unit includes A sub-pixel, and the other repeating unit includes B sub-pixel, and the A sub-pixel and the B sub-pixel are adjacent in the pixel row direction. The two adjacent sub-pixels in the two adjacent repeating units in the pixel column direction refer to that in the two adjacent repeating units in the pixel column direction, one repeating unit includes C sub-pixel, and the other repeating unit includes D sub-pixel, and the C sub-pixel and the D sub-pixel are adjacent in the pixel column direction.

[0085] The display substrate of the present disclosure is illustrated below through some example embodiments.

[0086] FIG. 2 is a schematic diagram of a planar structure of a display substrate according to an example embodiment of the present disclosure. As shown in FIG. 2, in an example embodiment, in a direction parallel to the display substrate, the display substrate can include a plurality of repeating units 100, and at least one repeating unit 100 can include a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns. In an example embodiment, the repeating unit is a basic unit constituting the display substrate, and the display substrate is formed by repeating and continuously arranging the repeating units in at least one direction, i.e., the display substrate is formed by splicing a plurality of repeating units.

[0087] In an example embodiment, one repeating unit 100 can include four sub-pixels, and the four sub-pixels can include a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, a third sub-pixel P3 emitting third color light, and a fourth sub-pixel P4 emitting fourth color light. The four sub-pixels can be arranged in a square manner, which can effectively increase the aperture ratio and the light transmission area.

[0088] In an example embodiment, in at least one repeating unit 100, the second sub-pixel P2 can be arranged on one side of the first sub-pixel P1 in a first direction X, the third sub-pixel P3 can be arranged on one side of the first sub-pixel P1 in a second direction Y, the fourth sub-pixel P4 can be arranged on one side of the third sub-pixel P3 in the first direction X, a plurality of sub-pixels arranged in sequence along the first direction X can be referred to as a pixel row, a plurality of sub-pixels arranged in sequence along the second direction Y can be referred to as a pixel column, and the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array. The first direction X and the second direction Y intersect.

[0089] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, the third sub-pixel P3 can be a white sub-pixel (W) emitting white light, and the fourth sub-pixel P4 can be a green sub-pixel (G) emitting green light. In some possible embodiments, the arrangement of RBWG can be adjusted according to actual needs, which is not specifically limited in the present disclosure.

[0090] In an example embodiment, in a direction perpendicular to the display substrate, the display substrate can at least include a driving circuit layer disposed on a base, a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. In at least one repeating unit, the driving circuit layer can include a plurality of circuit units, and the circuit units can at least include pixel driving circuits. The pixel driving circuits are respectively connected with a scan signal line and a data signal line, and are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line, and output a corresponding current to a light-emitting device. The light-emitting structure layer can include a plurality of light-emitting units, and the light-emitting units can at least include light-emitting devices. The light-emitting devices are connected with the pixel driving circuits of the circuit units of the sub-pixels where the light-emitting devices are located, and are configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuits of the sub-pixels where the light-emitting devices are located.

[0091] In another example embodiment, in a direction perpendicular to the display substrate, the display substrate can at least include a driving circuit layer disposed on a base, a color film structure layer disposed on a side of the driving circuit layer away from the base, and a light-emitting structure layer disposed on a side of the color film structure layer away from the base. In at least one repeating unit, the color film structure layer can include a plurality of color film units, and the color film units can at least include color filter layers. The color filter layers are configured to make the corresponding sub-pixels emit light with a required color.

[0092] In an example embodiment, the circuit unit in the present disclosure refers to an area divided according to the pixel driving circuit. The color film unit in the present disclosure refers to an area divided according to the color filter layer. The light-emitting unit in the present disclosure refers to an area divided according to the light-emitting device. The positions of the orthographic projection of the circuit unit on the base, the orthographic projection of the color filter layer on the base, and the orthographic projection of the light-emitting unit on the base can be corresponding or can not be corresponding.

[0093] In an example embodiment of the present disclosure, the positions of the orthographic projection of the circuit unit on the base, the orthographic projection of the color filter layer on the base, and the orthographic projection of the light-emitting unit on the base are substantially corresponding. The circuit unit, the color film unit, and the light-emitting unit constitute a sub-pixel, and thus in the following content, the sub-pixel is used to refer to the circuit unit, the color film unit, and the light-emitting unit.

[0094] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit in one repeat unit according to an exemplary embodiment of the present disclosure. As shown in FIG. 3, at least one repeat unit can include four pixel driving circuits, and the four pixel driving circuits can be arranged in a square manner. The pixel driving circuit can be a 3T1C structure.

[0095] In an exemplary embodiment, at least one pixel driving circuit can include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and one storage capacitor C, and the pixel driving circuit is connected to a scan signal line 30, a first power supply line 51, a data signal line 52, and a compensation signal line 53, respectively.

[0096] In an exemplary embodiment, each pixel driving circuit can include a first node N1 and a second node N2. The first node N1 is connected to a second electrode of the first transistor T1, a gate electrode of the second transistor T2, and a first terminal of the storage capacitor C, respectively. The second node N2 is connected to a second electrode of the second transistor T2, a second electrode of the third transistor T3, and a second terminal of the storage capacitor C, respectively.

[0097] In an exemplary embodiment, the first terminal of the storage capacitor C is connected to the first node N1, and the second terminal of the storage capacitor C is connected to the second node N2. The storage capacitor C is used to store a potential of the gate electrode of the second transistor T2.

[0098] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0099] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 30, a first electrode of the first transistor T1 is connected to the data signal line 52, and a second electrode of the first transistor T1 is connected to the first node N1. When an on signal is applied to the scan signal line 30, the first transistor T1 inputs a data signal of the data signal line 52 to the gate electrode of the second transistor T2.

[0100] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power supply line 51, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0101] In an example embodiment, the gate electrode of the third transistor T3 is connected with the scan signal line 30, the first electrode of the third transistor T3 is connected with the compensation signal line 53, and the second electrode of the third transistor T3 is connected with the second node N2. When a driving signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing, so as to compensate the threshold voltage Vth.

[0102] In an example embodiment, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in the pixel driving circuit of the at least one sub-pixel are connected with the same scan signal line 30.

[0103] In an example embodiment, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 in the plurality of pixel driving circuits of the at least one pixel row are connected with the same scan signal line 30.

[0104] In an example embodiment, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 in the plurality of pixel driving circuits of the at least one repeating unit are connected with the same scan signal line 30.

[0105] In an example embodiment, the light emitting device EL can be an OLED including a first electrode, an organic light emitting layer and a second electrode stacked, or can be a QLED including a first electrode, a quantum dot light emitting layer and a second electrode stacked. The first electrode of the light emitting device EL is connected with the second node N2, the second electrode of the light emitting device EL is connected with the second power supply line VSS, and the light emitting device EL emits light of a corresponding brightness in response to the current of the second electrode of the second transistor T2. In an example embodiment, the first electrode can be an anode, and the second electrode can be a cathode; or, the first electrode can be a cathode, and the second electrode can be an anode.

[0106] In an example embodiment, the signal of the first power supply line 51 is a high-level signal continuously provided, and the signal of the second power supply line VSS is a low-level signal continuously provided.

[0107] In an example embodiment, the first transistor T1 to the third transistor T3 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the third transistor T3 can include P-type transistors and N-type transistors.

[0108] In an example embodiment, the first transistor T1 to the third transistor T3 can adopt a low temperature poly-silicon thin film transistor, or can adopt an oxide thin film transistor, or can adopt a low temperature poly-silicon thin film transistor and an oxide thin film transistor. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate, i.e., an LTPS+Oxide (LTPO for short) display substrate, can take advantage of both, can realize low frequency driving, can reduce power consumption, and can improve display quality.

[0109] FIG. 4 is a structural schematic diagram of a display substrate according to an example embodiment of the present disclosure, which illustrates the structure of four repeating units (sixteen sub-pixels) in a bottom emission display substrate. In an example embodiment, the four repeating units can include a first repeating unit Q1, a second repeating unit Q2, a third repeating unit Q3, and a fourth repeating unit Q4. The second repeating unit Q2 can be disposed on one side of the first repeating unit Q1 in a first direction X extension direction, the third repeating unit Q3 can be disposed on one side of the first repeating unit Q1 in a second direction Y extension direction, and the fourth repeating unit Q4 can be disposed on one side of the third repeating unit Q3 in the first direction X extension direction. At least one repeating unit can include four sub-pixels forming two pixel rows and two pixel columns. The four sub-pixels can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The second sub-pixel P2 can be disposed on one side of the first sub-pixel P1 in the first direction X extension direction, the third sub-pixel P3 can be disposed on one side of the first sub-pixel P1 in the second direction Y extension direction, and the fourth sub-pixel P4 can be disposed on one side of the third sub-pixel P3 in the first direction X extension direction. The first direction X and the second direction Y intersect, a plurality of sub-pixels arranged in sequence along the first direction X can be referred to as a pixel row, a plurality of sub-pixels arranged in sequence along the second direction Y can be referred to as a pixel column, and a plurality of pixel rows and a plurality of pixel columns constitute an array of pixels arranged in an array.

[0110] In an example embodiment, the at least one repeating unit can include one scan signal line 30, two first power supply lines 51, four data signal lines 52, and one compensation signal line 53, which are respectively connected to the pixel driving circuit in the corresponding sub-pixel, the scan signal line 30 is configured to provide a scan signal to the pixel driving circuit, the first power supply line 51 is configured to provide a first power supply signal to the pixel driving circuit, the data signal line 52 is configured to provide a data signal to the pixel driving circuit, and the compensation signal line 53 is configured to provide a compensation signal to the pixel driving circuit.

[0111] In an example embodiment, the shape of the scan signal line 30 can be a linear shape with a main body extending along the first direction X (pixel row direction), and the shapes of the first power supply line 51, the data signal line 52, and the compensation signal line 53 can be linear shapes with main bodies extending along the second direction Y (pixel column direction). In an example embodiment, the scan signal line 30 can be disposed between adjacent pixel rows, for example, can be disposed in the middle of the second direction Y of the repeating unit; one compensation signal line 53 can be located between adjacent pixel columns, for example, can be disposed in the middle of the first direction X of the repeating unit; two first power supply lines 51 can be located on both sides of the first direction X of the repeating unit; four data signal lines 52 and a compensation signal line 53 can be located between the two adjacent first power supply lines 51, two of the four data signal lines 52 can be located on the side of one first power supply line 51 close to the compensation signal line 53, and the other two of the four data signal lines 52 can be located on the side of the other first power supply line 51 close to the compensation signal line 53, and the storage capacitor 60 can be located between the data signal line 52 and the compensation signal line 53. In this way, one scan signal line 30 extending along the first direction X defines two pixel rows, and one compensation signal line 53 extending along the second direction Y can define two pixel columns, forming a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 of one repeating unit.

[0112] In an example embodiment, each sub-pixel includes a pixel driving circuit, which can include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor 60, each transistor can include a gate electrode, an active layer, a first electrode, and a second electrode, and the storage capacitor 60 can include a first electrode plate and a second electrode plate.

[0113] In the exemplary embodiment, the first electrode of the first transistor T1 is connected to the data signal line 52, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2 and the second plate of the storage capacitor 60, the first electrode of the second transistor T2 is connected to the first power supply line 51, the first electrode of the third transistor T3 is connected to the compensation signal line 53, and the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2 and the first plate of the storage capacitor 60.

[0114] In the exemplary embodiment, the pixel driving circuit further includes a power supply connection electrode 20, and the second transistor T2 serving as a driving transistor includes at least a second active layer 22 serving as a driving active layer, and in at least one of the sub-pixels, the first power supply line 51 is connected to the first region of the second active layer 22 through the power supply connection electrode 20.

[0115] In the exemplary embodiment, the power supply connection electrode 20 can have a strip shape extending along the first direction X, and in at least one of the sub-pixels, the first end of the power supply connection electrode 20 is connected to the first power supply line 51 through a power supply via K1, and the second end of the power supply connection electrode 20 is connected to the first region of the second active layer 22 through an active via K2.

[0116] In the exemplary embodiment, the two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the same power supply via K1, and the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the same power supply via K1.

[0117] In the exemplary embodiment, the two adjacent sub-pixels in the two adjacent repeating units in the first direction X refer to the fourth sub-pixel in the first repeating unit Q1 and the third sub-pixel in the second repeating unit Q2 in the first direction X adjacent to each other, and the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y refer to the fourth sub-pixel in the first repeating unit Q1 and the second sub-pixel in the third repeating unit Q3 in the second direction Y adjacent to each other.

[0118] In the exemplary embodiment, the adjacent sub-pixels in the adjacent repeating units in the first direction X and the second direction Y share the same power supply via K1.

[0119] In the example embodiment, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are two adjacent sub-pixels, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q3 are two adjacent sub-pixels, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 of the second repeating unit Q2 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels. Therefore, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 are adjacent sub-pixels in the repeating units adjacent in the first direction X and the second direction Y, and the above sub-pixels share the same power via hole K1.

[0120] In the example embodiment, the first regions of the second active layers 22 of the two adjacent sub-pixels in the two repeating units adjacent in the second direction Y are connected to each other, for example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the first regions of the two second active layers 22 in the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 are connected to each other, and the first regions of the two second active layers 22 in the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q3 are connected to each other. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the first regions of the two second active layers 22 in the third sub-pixel P3 of the second repeating unit Q2 and the first sub-pixel P1 of the fourth repeating unit Q4 are connected to each other, and the first regions of the two second active layers 22 in the fourth sub-pixel P4 of the second repeating unit Q2 and the second sub-pixel P2 of the fourth repeating unit Q4 are connected to each other.

[0121] In the example embodiment, the second active layers 22 of the two adjacent sub-pixels in the two repeating units adjacent in the second direction Y are an integral structure connected to each other.

[0122] In an example embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same active via K2. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same active via K2. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same active via K2.

[0123] In an example embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 are connected to each other. For another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are connected to each other.

[0124] In an example embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integral structure connected to each other.

[0125] In an example embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y share the same power connection electrode 20. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same power connection electrode 20. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same power connection electrode 20.

[0126] In an example embodiment, the width of the second active layer 22 in the adjacent sub-pixels in the first direction X is different, and the width of the second active layer 22 in the adjacent sub-pixels in the second direction Y is different, which can be the minimum size of the second active layer 22 in the second direction Y.

[0127] In an example embodiment, in the first direction X, the first sub-pixels P1 and the second sub-pixels P2 are arranged alternately, and the width of the second active layer 22 in the first sub-pixels P1 is greater than the width of the second active layer 22 in the second sub-pixels P2; or, in the first direction X, the third sub-pixels P3 and the fourth sub-pixels P4 are arranged alternately, and the width of the second active layer 22 in the third sub-pixels P3 is less than the width of the second active layer 22 in the fourth sub-pixels P4.

[0128] In an exemplary embodiment, in the second direction Y, the first sub-pixel P1 and the third sub-pixel P3 are arranged alternately, and the width of the second active layer 22 in the first sub-pixel P1 is greater than the width of the second active layer 22 in the third sub-pixel P3; or, in the second direction Y, the second sub-pixel P2 and the fourth sub-pixel P4 are arranged alternately, and the width of the second active layer 22 in the second sub-pixel P2 is less than the width of the second active layer 22 in the fourth sub-pixel P4.

[0129] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate can include a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer arranged in sequence on the base, the first plate of the storage capacitor 60 can be arranged in the first conductive layer, the first power supply line 51, the data signal line 52, and the compensation signal line 53 can be arranged in the second conductive layer, the second plate of the storage capacitor 60 and the second active layer 22 can be arranged in the semiconductor layer, and the power supply connection electrode 20 and the scan signal line 30 can be arranged in the third conductive layer.

[0130] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development, etc. for organic materials. The deposition can adopt any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating, and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material made on a base by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0131] In an exemplary embodiment, taking four repeating units (the first repeating unit Q1, the second repeating unit Q2, the third repeating unit Q3, and the fourth repeating unit Q4) as an example, the preparation process of the display substrate can include the following operations.

[0132] (11) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern comprises: depositing a first conductive thin film on the substrate, patterning the first conductive thin film by a patterning process, forming the first conductive layer pattern on the substrate, as shown in FIG. 5.

[0133] In an exemplary embodiment, the first conductive layer of each sub-pixel in each repeating unit can at least include the first connection electrode 11, the second connection electrode 12, and the first plate 61 of the storage capacitor.

[0134] In an exemplary embodiment, the shape of the first plate 61 can be a rectangular shape, the corner of the rectangular shape can be provided with a chamfer, the first plate 61 can serve as one transparent plate of the transparent storage capacitor, and the first plate 61 is configured to form the transparent storage capacitor with the second plate formed subsequently.

[0135] In an exemplary embodiment, the first connection electrode 11 and the second connection electrode 12 can be located on the two sides of the second direction Y of the first plate 61, respectively.

[0136] In an exemplary embodiment, in the first sub-pixel P1 and the second sub-pixel P2, the first connection electrode 11 can be disposed on the side opposite to the extension direction of the second direction Y of the first plate 61, and the second connection electrode 12 can be disposed on the side of the extension direction of the second direction Y of the first plate 61. In the third sub-pixel P3 and the fourth sub-pixel P4, the first connection electrode 11 can be disposed on the side of the extension direction of the second direction Y of the first plate 61, and the second connection electrode 12 can be disposed on the side opposite to the extension direction of the second direction Y of the first plate 61.

[0137] In an exemplary embodiment, the shape of the first connection electrode 11 can be a strip shape with the main part extending along the second direction Y, the first end of the first connection electrode 11 is connected with the first plate 61, the second end of the first connection electrode 11 extends in a direction away from the second connection electrode 12, and the first connection electrode 11 is configured to be connected with the third connection electrode formed subsequently.

[0138] In an exemplary embodiment, the shape of the second connection electrode 12 can be a strip shape with the main part extending along the second direction Y, the first end of the second connection electrode 12 is connected with the first plate 61, the second end of the second connection electrode 12 extends in a direction away from the first connection electrode 11, and the second connection electrode 12 is configured to be connected with the fourth connection electrode formed subsequently.

[0139] In an exemplary embodiment, in the first pixel column, the first connecting electrode 11 near the edge of the side of the second pixel column can be substantially flush with the first plate 61 near the edge of the side of the second pixel column. In the second pixel column, the first connecting electrode 11 near the edge of the side of the first pixel column can be substantially flush with the first plate 61 near the edge of the side of the first pixel column.

[0140] In an exemplary embodiment, the first connecting electrode 11, the second connecting electrode 12, and the first plate 61 of each sub-pixel can be an integrated structure connected to each other.

[0141] In an exemplary embodiment, in at least one sub-pixel, the width of the first connecting electrode 11 can be smaller than the width of the second connecting electrode 12, and the width can be the size of the first direction X.

[0142] In an exemplary embodiment, in at least one sub-pixel, the first conductive layer pattern can further include a first connecting block 81, the shape of the first connecting block 81 can be a block shape (such as a rectangular shape), and the first connecting block 81 can be arranged at the corner where the first connecting electrode 11 and the first plate 61 are connected, and the two adjacent sides of the first connecting block 81 are connected to the first connecting electrode 11 and the first plate 61 respectively, forming a first corner structure. For example, the first sub-pixel can include the first connecting block 81. For another example, the second sub-pixel can include the first connecting block 81. For still another example, the third sub-pixel can include the first connecting block 81.

[0143] In an exemplary embodiment, in at least one sub-pixel, the first corner structure can have a first convex angle β1, and the first convex angle β1 can be a right angle.

[0144] In an exemplary embodiment, in at least one sub-pixel, the first conductive layer pattern can further include a second connecting block 82, the shape of the second connecting block 82 can be a block shape, and the second connecting block 82 can be arranged at the corner where the second connecting electrode 12 and the first plate 61 are connected, and the two adjacent sides of the second connecting block 82 are connected to the second connecting electrode 12 and the first plate 61 respectively, forming a second corner structure. For example, the first sub-pixel can include the second connecting block 82.

[0145] In an exemplary embodiment, the second corner structure can have a second convex angle β2, and the second convex angle β2 can be an obtuse angle.

[0146] In an exemplary embodiment, in at least one sub-pixel, the first plate 61 can be provided with a recess 91, the shape of the recess 91 can be a block shape (such as a rectangular shape), and the recess 91 can be arranged on the side of the first plate 61 away from the second connecting electrode 12, the recess 91 can have a recess width and a recess depth, the recess width can be greater than the recess depth, the recess width can be the size of the first direction X, and the recess depth can be the size of the second direction Y.

[0147] In an example embodiment, in at least one repeating unit, the positions of each pattern in the first conductive layer in the first sub-pixel P1 and the positions of each pattern in the first conductive layer in the third sub-pixel P3 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of each pattern in the first conductive layer in the second sub-pixel P2 and the positions of each pattern in the first conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to the horizontal reference line, the positions of each pattern in the first conductive layer in the first sub-pixel P1 and the positions of each pattern in the first conductive layer in the second sub-pixel P2 can be substantially mirror-symmetric with respect to a vertical reference line, and the positions of each pattern in the first conductive layer in the third sub-pixel P3 and the positions of each pattern in the first conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to the vertical reference line. The horizontal reference line can be a straight line extending along the first direction X and bisecting the repeating unit in the second direction Y, and the vertical reference line can be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0148] In an example embodiment, the material of the first conductive layer can be a transparent conductive material, such as indium tin oxide ITO or indium zinc oxide IZO, etc.

[0149] (12) Forming a second conductive layer pattern. In an example embodiment, forming the second conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a second conductive thin film, patterning the second conductive thin film by a patterning process, and forming a second conductive layer, as shown in FIGS. 6A and 6B, FIG. 6B is a schematic diagram of the second conductive layer in FIG. 6A. In an example embodiment, the second conductive layer can be referred to as a SHIELD layer.

[0150] In an example embodiment, the second conductive layer of each sub-pixel in each repeating unit can include at least a third connection electrode 13 and a fourth connection electrode 14.

[0151] In an example embodiment, the third connection electrode 13 can have a block shape (such as a rectangular shape), can be located on the side of the first plate 61 away from the second connection electrode 12, the orthographic projection of the third connection electrode 13 on the substrate at least partially overlaps the orthographic projection of the first connection electrode 11 on the substrate, and the third connection electrode 13 directly overlaps the first connection electrode 11. In an example embodiment, the third connection electrode 13 is configured to be connected to the fifth connection electrode formed subsequently, and is configured to shield light from the second transistor, reduce the light intensity incident on the second transistor, reduce the leakage current of the second transistor, and thus reduce the influence of light on the characteristics of the second transistor.

[0152] In an exemplary embodiment, the fourth connection electrode 14 can have a block shape (e.g., a rectangular shape), can be located on a side of the first electrode plate 61 away from the first connection electrode 11, the orthographic projection of the fourth connection electrode 14 on the substrate at least partially overlaps the orthographic projection of the second connection electrode 12 on the substrate, and the fourth connection electrode 14 directly overlaps the second connection electrode 12, and the fourth connection electrode 14 is configured to be connected to the sixth connection electrode to be formed later.

[0153] In an exemplary embodiment, in at least one of the sub-pixels, the area of the orthographic projection of the third connection electrode 13 on the substrate can be greater than the area of the orthographic projection of the fourth connection electrode 14 on the substrate.

[0154] In an exemplary embodiment, in at least one of the repeating units, the area of the orthographic projection of the third connection electrode 13 on the substrate in the first sub-pixel can be greater than the area of the orthographic projection of the third connection electrode 13 on the substrate in the other sub-pixels.

[0155] In an exemplary embodiment, in at least one of the repeating units, the area of the orthographic projection of the fourth connection electrode 14 on the substrate in each of the sub-pixels can be substantially equal.

[0156] In an exemplary embodiment, the second conductive layer of each repeating unit in the display substrate can include at least two first power lines 51, four data signal lines 52, and one compensation signal line 53.

[0157] In an exemplary embodiment, the first power line 51, the data signal line 52, and the compensation signal line 53 can have a shape of a straight line or a broken line with a main part extending along the second direction Y, the compensation signal line 53 can be located between the adjacent sub-pixel columns of the repeating unit, for example, at the middle of the first direction X of the repeating unit, the first first power line 51 can be located on a side of the repeating unit in the opposite direction of the first direction X of the repeating unit, the second first power line 51 can be located on a side of the repeating unit in the first direction X of the repeating unit, two of the four data signal lines 52 can be located between the first first power line 51 and the compensation signal line 53, and the other two of the four data signal lines 52 can be located between the second first power line 51 and the compensation signal line 53.

[0158] In an exemplary embodiment, the first first power line 51 and the compensation signal line 53 can define a first pixel column, and two of the data signal lines 52 are arranged in the first pixel column. The second first power line 51 and the compensation signal line 53 can define a second pixel column, and two of the data signal lines 52 are arranged in the second pixel column.

[0159] In the example embodiment, the four data signal lines 52 can include a first data signal line and a second data signal line arranged in the first pixel column, and a third data signal line and a fourth data signal line arranged in the second pixel column. The extension direction along the first direction X is in order a first first power line, a first data signal line, a second data signal line, a compensation signal line, a third data signal line, a fourth data signal line, and a second first power line, and the first electrode plate 61 can be located between the second data signal line and the compensation signal line 53 or between the compensation signal line 53 and the third data signal line.

[0160] In the example embodiment, in at least one repeating unit, the positions of the two first power lines 51 can be substantially mirror-symmetrical with respect to the vertical reference line, and the positions of the two data signal lines 52 located on the side opposite to the first direction X of the compensation signal line 53 and the positions of the two data signal lines 52 located on the side of the first direction X of the compensation signal line 53 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0161] In the example embodiment, in at least one repeating unit, the positions of the third connection electrode 13 and the fourth connection electrode 14 in the first sub-pixel P1 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the second sub-pixel P2 can be substantially mirror-symmetrical with respect to the vertical reference line, and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the third sub-pixel P3 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the vertical reference line. The positions of the third connection electrode 13 and the fourth connection electrode 14 in the first sub-pixel P1 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the third sub-pixel P3 can be substantially mirror-symmetrical with respect to the horizontal reference line, and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the second sub-pixel P2 and the positions of the third connection electrode 13 and the fourth connection electrode 14 in the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the horizontal reference line.

[0162] In the example embodiment, two adjacent repeating units in the first direction X can share the same first power line 51. For example, the first repeating unit Q1 and the second repeating unit Q2 can share the same first power line 51. For another example, the third repeating unit Q3 and the fourth repeating unit Q4 can share the same first power line 51. By arranging adjacent repeating units to share the same first power line, the present disclosure can effectively reduce the number of signal lines and the number of vias, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, and improve the display resolution.

[0163] In the example embodiment, the first power line 51, the data signal line 52 and the compensation signal line 53 can be non-equal-width zigzag lines, and the zigzag lines with variable width not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance.

[0164] (13) Forming a semiconductor layer pattern. In the example embodiment, forming the semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a semiconductor thin film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor thin film by a patterning process, forming a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIGS. 7A and 7B, FIG. 7B is a schematic view of the semiconductor layer in FIG. 7A.

[0165] In the example embodiment, the semiconductor layer of each sub-pixel in each repeating unit can at least include a first active layer 21, a second active layer 22, a third active layer 23, and a second plate 62 of a storage capacitor, the first active layer 21 can serve as an active layer of the first transistor T1, the second active layer 22 can serve as an active layer of the second transistor T2, the third active layer 23 can serve as an active layer of the third transistor T3, and the second plate 62 can serve as another transparent plate of the transparent storage capacitor, and the second plate 62 is configured to form a transparent storage capacitor with the first plate 61.

[0166] In the example embodiment, for the first sub-pixel P1 and the second sub-pixel P2, the first active layer 21 and the third active layer 23 can be disposed on one side of the first plate 61 in the second direction Y of the sub-pixel, and the second active layer 22 can be disposed on the other side of the first plate 61 in the second direction Y of the sub-pixel.

[0167] In the example embodiment, for the first sub-pixel P1, the first active layer 21 can be disposed on the side of the sub-pixel away from the second sub-pixel P2, and the third active layer 23 can be disposed on the side of the sub-pixel close to the second sub-pixel P2. For the second sub-pixel P2, the first active layer 21 can be disposed on the side of the sub-pixel away from the first sub-pixel P1, and the third active layer 23 can be disposed on the side of the sub-pixel close to the first sub-pixel P1.

[0168] In the example embodiment, for the third sub-pixel P3 and the fourth sub-pixel P4, the first active layer 21 and the third active layer 23 can be disposed on the side of the sub-pixel away from the second direction Y of the first plate 61, and the second active layer 22 can be disposed on the side of the sub-pixel close to the second direction Y of the first plate 61.

[0169] In the exemplary embodiments, for the third sub-pixel P3, the first active layer 21 can be disposed on the side of the sub-pixel away from the fourth sub-pixel P4, and the third active layer 23 can be disposed on the side of the sub-pixel close to the fourth sub-pixel P4. For the fourth sub-pixel P4, the first active layer 21 can be disposed on the side of the sub-pixel away from the third sub-pixel P3, and the third active layer 23 can be disposed on the side of the sub-pixel close to the third sub-pixel P3.

[0170] In the exemplary embodiments, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region.

[0171] In the exemplary embodiments, the first region of the first active layer 21 of each sub-pixel has an orthographic projection on the substrate that at least partially overlaps with an orthographic projection of the corresponding data signal line 52 on the substrate, and the second region of the first active layer 21 is connected with the second plate 62.

[0172] In the exemplary embodiments, the first region of the second active layer 22 of each sub-pixel has an orthographic projection on the substrate that does not overlap with an orthographic projection of the third connection electrode 13 of the sub-pixel on the substrate, and the second region and the channel region of the second active layer 22 have an orthographic projection on the substrate that at least partially overlaps with an orthographic projection of the third connection electrode 13 on the substrate, so that the third connection electrode 13 as a shielding layer can shield the channel region of the second transistor T2, avoid the influence of light on the channel, and ensure the electrical performance of the second transistor T2.

[0173] In the exemplary embodiments, in each sub-pixel, the distance between the first region of the second active layer 22 and the first power supply line 51 can be less than the distance between the second region of the second active layer 22 and the first power supply line 51, i.e., the first region of the second active layer 22 is closer to the first power supply line 51 than the channel region of the second active layer 22.

[0174] In the example embodiment, the first regions of the second active layers 22 of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y can be connected to each other, and thus the second transistors of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the first regions of the second active layers. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the first region of the second active layer 22 of the third sub-pixel P3 in the first repeating unit Q1 can be connected to the first region of the second active layer 22 of the first sub-pixel P1 in the third repeating unit Q3, and the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 can be connected to the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 can be connected to the first region of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4, and the first region of the second active layer 22 of the fourth sub-pixel P4 in the second repeating unit Q2 can be connected to the first region of the second active layer 22 of the second sub-pixel P2 in the fourth repeating unit Q4.

[0175] In the example embodiment, the second active layers 22 of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y can be an integrated structure connected to each other, and the integrated structure of the second active layers 22 has a groove 92, and the openings of the adjacent grooves 92 in at least one repeating unit are oppositely arranged. The groove 92 can have a groove width and a groove depth, the groove width can be smaller than the groove depth, the groove width can be the size in the second direction Y, and the groove depth can be the size in the first direction X. By arranging the second transistors of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y to share the first regions of the second active layers, the number of vias can be effectively reduced, the occupied area of the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, the reduction of vias can simplify the manufacturing process, reduce production cost, and improve product yield.

[0176] In the example embodiment, the widths of the second active layers in the adjacent sub-pixels in the first direction X can be different, the widths of the second active layers in the adjacent sub-pixels in the second direction Y can be different, and the width is the minimum size of the second active layer in the second direction Y.

[0177] In an example embodiment, in the first direction X, a plurality of sub-pixels with a second active layer of a larger width and a plurality of sub-pixels with a second active layer of a smaller width can be arranged alternately. For example, the first sub-pixel P1 and the second sub-pixel P2 are arranged alternately in the first direction X, and the first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the second width L2 of the second active layer 22 in the second sub-pixel P2. For another example, the third sub-pixel P3 and the fourth sub-pixel P4 are arranged alternately in the first direction X, and the third width L3 of the second active layer 22 in the third sub-pixel P3 can be smaller than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4.

[0178] In an example embodiment, in the second direction Y, a plurality of sub-pixels with a second active layer of a larger width and a plurality of sub-pixels with a second active layer of a smaller width can be arranged alternately. For example, the first sub-pixel P1 and the third sub-pixel P3 are arranged alternately in the second direction Y, and the first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3. For another example, the second sub-pixel P2 and the fourth sub-pixel P4 are arranged alternately in the second direction Y, and the second width L2 of the second active layer 22 in the second sub-pixel P2 can be smaller than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4.

[0179] In an example embodiment, in at least one repeating unit, the widths of the second active layers 22 of the four sub-pixels can be different. For example, the first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4. For another example, the second width L2 of the second active layer 22 in the second sub-pixel P2 can be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3.

[0180] In an example embodiment, by arranging the second active layer of a larger width and the second active layer of a smaller width alternately in the first direction X and the second direction Y, the present disclosure can not only effectively match the requirements of the single scanning signal line structure, but also effectively increase the uniformity of the layout of the four pixel driving circuits in the repeating unit and effectively increase the uniformity of the pixel openings of the four sub-pixels in the repeating unit.

[0181] In an example embodiment, the first region of the third active layer 23 of each sub-pixel has a projection on the substrate that at least partially overlaps a projection of the compensation signal line 53 on the substrate, and the second region of the third active layer 23 has a projection on the substrate that at least partially overlaps a projection of the fourth connection electrode 14 of the sub-pixel on the substrate.

[0182] In the exemplary embodiments, in at least one repeating unit, the first region of the third active layer 23 in the first sub-pixel P1 and the first region of the third active layer 23 in the second sub-pixel P2 can be connected to each other, and the first region of the third active layer 23 in the third sub-pixel P3 and the first region of the third active layer 23 in the fourth sub-pixel P4 can be connected to each other.

[0183] In the exemplary embodiments, the third active layer 23 in the first sub-pixel P1 and the third active layer 23 in the second sub-pixel P2 can be an integrated structure connected to each other, and the third active layer 23 in the third sub-pixel P3 and the third active layer 23 in the fourth sub-pixel P4 can be an integrated structure connected to each other, so that the third transistors of the adjacent two sub-pixels in one pixel row share the first region of the third active layer. By arranging the third transistors of the adjacent two sub-pixels in one pixel row to share the first region of the third active layer, the number of vias can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, and the reduction of vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0184] In the exemplary embodiments, the second plate 62 can be in a rectangular shape, and the corners of the rectangular shape can be chamfered and arranged between the second active layer 22 and the third active layer 23 of the sub-pixel. The orthographic projection of the second plate 62 on the substrate at least partially overlaps the orthographic projection of the first plate 61 on the substrate, and the second plate 62 can serve as another transparent plate of the transparent storage capacitor, and the first plate 61 and the second plate 62 form the transparent storage capacitor.

[0185] In the exemplary embodiments, the second plate 62 and the first active layer 21 of each sub-pixel can be an integrated structure connected to each other.

[0186] In the exemplary embodiments, in each sub-pixel, the area of the overlapping region in the orthographic projection of the first plate 61 on the substrate and the orthographic projection of the second plate 62 on the substrate can be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0187] In the exemplary embodiments, the semiconductor layer can be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0188] In the example embodiment, in at least one repeating unit, the positions of each pattern in the semiconductor layer in the first sub-pixel P1 and the positions of each pattern in the semiconductor layer in the third sub-pixel P3 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of each pattern in the semiconductor layer in the second sub-pixel P2 and the positions of each pattern in the semiconductor layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to the horizontal reference line, the positions of each pattern in the semiconductor layer in the first sub-pixel P1 and the positions of each pattern in the semiconductor layer in the second sub-pixel P2 can be substantially mirror-symmetric with respect to a vertical reference line, and the positions of each pattern in the semiconductor layer in the third sub-pixel P3 and the positions of each pattern in the semiconductor layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to the vertical reference line.

[0189] (14) Forming a second insulating layer pattern. In the example embodiment, forming the second insulating layer pattern can include: depositing a second insulating thin film on the substrate on which the aforementioned pattern is formed, and patterning the second insulating thin film by a patterning process to form the second insulating layer pattern covering the semiconductor layer, the second insulating layer being provided with a plurality of vias, as shown in FIG. 8.

[0190] In the example embodiment, the plurality of vias of each sub-pixel in each repeating unit at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, and a seventh via V7.

[0191] In the example embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer 21 and the data signal line 52 on the substrate. The first via V1 is a via of the transfer structure, including a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched away to expose the surface of the first region of the first active layer 21, and the first insulating layer and the second insulating layer in the deep half-hole are etched away to expose the surface of the data signal line 52, so that the via of the transfer structure composed of the two half-holes simultaneously exposes the first region of the first active layer 21 and the data signal line 52, and the first via V1 is configured to enable the seventh connection electrode formed subsequently to connect with the first region of the first active layer 21 and the data signal line 52 through the via.

[0192] In the example embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the first region of the second active layer 22 on the substrate, the second insulating layer in the second via V2 is etched away to expose the surface of the first region of the second active layer 22, and the second via V2 is configured to enable the power connection electrode formed subsequently to connect with the first region of the second active layer 22 through the via. In the example embodiment, the second via V2 is an active via of the present embodiment.

[0193] In the example embodiment, the first region of the second active layer 22 of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y are connected to each other, so that the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y can share the same second via V2. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same second via V2. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same second via V2. By arranging the two adjacent sub-pixels in the two adjacent repeating units to share the same second via V2, the number of vias can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, and the reduction of vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0194] In the example embodiment, the third via V3 is located within the range of the second region of the second active layer 22 and the normal projection of the third connection electrode 13 on the substrate. The third via V3 is a via of a switching structure, including a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched away to expose the surface of the second region of the second active layer 22, and the first insulating layer and the second insulating layer in the deep half-hole are etched away to expose the surface of the third connection electrode 13, so that the via of the switching structure composed of the two half-holes simultaneously exposes the second region of the second active layer 22 and the third connection electrode 13, and the third via V3 is configured to allow the fifth connection electrode formed subsequently to connect with the second region of the second active layer 22 and the third connection electrode 13 through the via.

[0195] In the example embodiment, the fourth via V4 is located within the range of the first region of the third active layer 23 and the normal projection of the compensation signal line 53 on the substrate. The fourth via V4 is a via of a switching structure, including a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched away to expose the surface of the first region of the third active layer 23, and the first insulating layer and the second insulating layer in the deep half-hole are etched away to expose the surface of the compensation signal line 53, so that the via of the switching structure composed of the two half-holes simultaneously exposes the first region of the third active layer 23 and the compensation signal line 53, and the fourth via V4 is configured to allow the eighth connection electrode formed subsequently to connect with the first region of the third active layer 23 and the compensation signal line 53 through the via.

[0196] In the example embodiment, since the first regions of the third active layers in the first sub-pixel P1 and the second sub-pixel P2 in the repeating unit are connected to each other, the first regions of the third active layers in the third sub-pixel P3 and the fourth sub-pixel P4 are connected to each other, the first sub-pixel P1 and the second sub-pixel P2 in the repeating unit can share the same fourth via V4, and the third sub-pixel P3 and the fourth sub-pixel P4 share the same fourth via V4. By arranging the adjacent sub-pixels to share the same fourth via V4, the number of vias can be effectively reduced, the occupied area of the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, and the manufacturing process can be simplified, the production cost can be reduced, and the product yield can be improved.

[0197] In the example embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second region of the third active layer 23 and the fourth connection electrode 14 on the substrate. The fifth via V5 is a via of the switching structure, including a shallow half-hole and a deep half-hole, the second insulating layer in the shallow half-hole is etched away to expose the surface of the second region of the third active layer 23, and the first insulating layer and the second insulating layer in the deep half-hole are etched away to expose the surface of the fourth connection electrode 14, so that the via of the switching structure composed of the two half-holes simultaneously exposes the second region of the third active layer 23 and the fourth connection electrode 14, and the fifth via V5 is configured to enable the sixth connection electrode formed subsequently to be connected to the second region of the third active layer 23 and the fourth connection electrode 14 through the via.

[0198] In the example embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second plate 62 on the substrate, the second insulating layer in the sixth via V6 is etched away to expose the surface of the second plate 62, and the sixth via V6 is configured to enable the second gate electrode formed subsequently to be connected to the second plate 62 through the via.

[0199] In the example embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first power line 51 on the substrate, the first insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first power line 51, and the seventh via V7 is configured to enable the power connection electrode formed subsequently to be connected to the first power line 51 through the via. In the example embodiment, the seventh via V7 serves as the power via of the present embodiment.

[0200] In the example embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share one seventh via V7. For example, the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 share one seventh via V7. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 share one seventh via V7. The present disclosure can effectively reduce the number of vias, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process, reduce production costs, and improve product yield by setting two adjacent sub-pixels in two adjacent repeating units in the first direction X to share one seventh via V7.

[0201] In the example embodiment, two adjacent sub-pixels in two adjacent repeating units in the second direction Y share one seventh via V7. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share one seventh via V7. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share one seventh via V7. The present disclosure can effectively reduce the number of vias, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process, reduce production costs, and improve product yield by setting two adjacent sub-pixels in two adjacent repeating units in the second direction Y to share one seventh via V7.

[0202] In the example embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share the same seventh via V7, i.e., four adjacent sub-pixels in adjacent repeating units share the same seventh via V7. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are two adjacent sub-pixels, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q3 are two adjacent sub-pixels, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 of the second repeating unit Q2 and the first sub-pixel P1 of the fourth repeating unit Q4 are two adjacent sub-pixels, and the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 share the same seventh via V7. By arranging four adjacent sub-pixels in adjacent repeating units to share the same seventh via V7, the number of vias can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, and the manufacturing process can be simplified, the production cost can be reduced, and the product yield can be improved.

[0203] In the example embodiment, in the process of forming the second insulating layer pattern, a dry etching process is used to form a plurality of vias, and at the same time, a first conductorization treatment is performed on the semiconductor layer exposed in the via, so that the semiconductor layer exposed in the via forms a first conductorization region. In the first conductorization treatment, the edge portion of the semiconductor layer covered by the second insulating layer near the via is also conductorized, i.e., the first conductorized semiconductor layer extends away from the via.

[0204] (15) Forming a third conductive layer pattern. In the example embodiment, forming the third conductive layer pattern can include: depositing a third conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer pattern on the second insulating layer, as shown in FIGS. 9A and 9B, FIG. 9B is a schematic view of the third conductive layer in FIG. 9A. In the example embodiment, the third conductive layer can be referred to as a gate metal (GT) layer.

[0205] In the exemplary embodiment, the third conductive layer of each sub-pixel in each repeating unit can at least include the fifth connection electrode 15, the sixth connection electrode 16, the seventh connection electrode 17, the eighth connection electrode 18, the power supply connection electrode 20, the scan signal line 30, the first gate electrode 31, the second gate electrode 32, and the third gate electrode 33.

[0206] In the exemplary embodiment, the shape of the scan signal line 30 can be a linear shape with a main body portion extending along the first direction X, and the scan signal line 30 can be arranged at the middle of the repeating unit in the second direction Y, i.e., between the first sub-pixel P1 and the second sub-pixel P2 and between the third sub-pixel P3 and the fourth sub-pixel P4, and the scan signal line 30 is configured to simultaneously control the turn-on or turn-off of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0207] In the exemplary embodiment, the orthogonal projection of the scan signal line 30 on the substrate does not overlap with the orthogonal projection of the first active layer 21 and the third active layer 23 on the substrate.

[0208] In the exemplary embodiment, the shape of the first gate electrode 31 can be a strip shape extending along the second direction Y, and the first gate electrode 31 can be arranged on the side of the scan signal line 30 close to the first active layer 21, the first end of the first gate electrode 31 is connected to the scan signal line 30, the second end of the first gate electrode 31 extends toward the first active layer 21, and the orthogonal projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthogonal projection of the first active layer 21 on the substrate. In the exemplary embodiment, the first gate electrode 31 can serve as the gate electrode of the first transistor T1, so that the scan signal line 30 can control the turn-on or turn-off of the first transistor T1.

[0209] In the exemplary embodiment, the shape of the second gate electrode 32 can be a strip shape extending along the second direction Y, the first end of the second gate electrode 32 is connected to the second plate 62 through the sixth via hole V6, and the second end of the second gate electrode 32 extends toward the second active layer 22, and the orthogonal projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthogonal projection of the second active layer 22 on the substrate. In the exemplary embodiment, the second gate electrode 32 can serve as the gate electrode of the second transistor T2, and can control the turn-on or turn-off of the second transistor T2.

[0210] In the exemplary embodiment, since the second gate electrode 32 is connected to the second plate 62, and the second plate 62 is connected to the second region of the first active layer 21, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second plate 62 (the first end of the storage capacitor) have the same potential, forming a first node in the pixel driving circuit, and the second plate 62 has the potential of the first node in the pixel driving circuit.

[0211] In an example embodiment, the third gate electrode 33 can have a strip shape extending along the second direction Y, can be disposed on a side of the scan signal line 30 close to the third active layer 23, a first end of the third gate electrode 33 can be connected to the scan signal line 30, a second end of the third gate electrode 33 can extend toward the third active layer 23, and a projection of the third gate electrode 33 on the substrate can at least partially overlap a projection of the third active layer 23 on the substrate. In an example embodiment, the third gate electrode 33 can serve as a gate electrode of the third transistor T3, so that the scan signal line 30 can control the third transistor T3 to be turned on or turned off.

[0212] In an example embodiment, in one sub-pixel, one scan signal line 30 can be connected to the first gate electrode 31 and the third gate electrode 33 at the same time, so that the scan signal line 30 can control the first transistor T1 and the third transistor T3 in one sub-pixel to be turned on or turned off.

[0213] In an example embodiment, in one pixel row, one scan signal line 30 can be connected to all the first gate electrodes 31 and all the third gate electrodes 33 in multiple sub-pixels at the same time, so that the scan signal line 30 can control all the first transistors T1 and all the third transistors T3 in one pixel row to be turned on or turned off.

[0214] In an example embodiment, in one repeating unit, one scan signal line 30 can be connected to all the first gate electrodes 31 and all the third gate electrodes 33 in multiple sub-pixels at the same time, so that the scan signal line 30 can control all the first transistors T1 and all the third transistors T3 in the repeating unit to be turned on or turned off at the same time.

[0215] In an example embodiment, the fifth connection electrode 15 can have a block shape (e.g., a rectangular shape), can be disposed on a side of the second plate 62 away from the scan signal line 30, and can be connected to the second region of the second active layer 22 and the third connection electrode 13 at the same time through the third via hole V3.

[0216] In an example embodiment, since the fifth connection electrode 15 is connected to the second region of the second active layer 22 and the third connection electrode 13 at the same time, the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first plate 61, the fifth connection electrode 15 makes the second plate 61 and the second electrode of the second transistor have the same potential. In an example embodiment, the fifth connection electrode 15 is configured to be connected to an anode connection electrode formed subsequently.

[0217] In the example embodiment, the sixth connection electrode 16 can be in a block shape (e.g., a rectangular shape) and can be disposed on the side of the second plate 62 close to the scan signal line 30. The sixth connection electrode 16 is connected to the second region of the third active layer 23 and the fourth connection electrode 14 through the fifth via V5.

[0218] In the example embodiment, since the sixth connection electrode 16 is connected to the second region of the third active layer 23 and the fourth connection electrode 14, the fourth connection electrode 14 is connected to the second connection electrode 12, and the second connection electrode 12 is connected to the first plate 61, the sixth connection electrode 16 makes the second electrode of the third transistor and the first plate 61 have the same potential.

[0219] In the example embodiment, the fifth connection electrode 15 and the sixth connection electrode 16 realize the connection between the second electrode of the second transistor, the second electrode of the third transistor, and the first plate 61 (the second terminal of the storage capacitor), form the second node in the pixel driving circuit, and thus the first plate 61 has the potential of the second node in the pixel driving circuit.

[0220] In the example embodiment, since the first plate 61 has the potential of the second node in the pixel driving circuit and the second plate 62 has the potential of the first node in the pixel driving circuit, the first plate 61 having the potential of the second node and the second plate 62 having the potential of the first node form the storage capacitor.

[0221] In the example embodiment, since the first plate 61 is made of a transparent conductive material and the second plate 62 is made of a transparent metal oxide, the storage capacitor is a transparent capacitor.

[0222] In the example embodiment, the seventh connection electrode 17 can be in a block shape (e.g., a rectangular shape) and can be disposed between the first gate electrode 31 and the first power supply line 51. The seventh connection electrode 17 is connected to the first region of the first active layer 21 and the data signal line 52 through the first via V1, and thus realizes that the data signal line 52 writes the data signal to the first electrode of the first transistor T1. In the example embodiment, each data signal line 52 can be connected to the first region of the first active layer in one sub-pixel through the first via V1, and thus realizes that the four data signal lines 52 write the data signal to the first electrodes of the first transistors T1 in the multiple repeating units arranged along the second direction Y, respectively.

[0223] In the example embodiment, the four data signal lines 52 can include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. In each repeating unit, the first data signal line can be connected to the first region of the first active layer of the first sub-pixel P1 through the seventh connection electrode 17, the second data signal line can be connected to the first region of the first active layer in the third sub-pixel P3 through the seventh connection electrode 17, the third data signal line can be connected to the first region of the first active layer in the second sub-pixel P2 through the seventh connection electrode 17, and the fourth data signal line can be connected to the first region of the first active layer in the fourth sub-pixel P4 through the seventh connection electrode 17.

[0224] In the example embodiment, the eighth connection electrode 18 can have a block shape (e.g., a rectangular shape) and can be disposed between the third gate electrodes 33 of two adjacent sub-pixels in the first direction X. The eighth connection electrode 18 is connected to the first region of the third active layer 23 and the compensation signal line 53 through the fourth via V4, so that the compensation signal line 53 writes the compensation signal to the first electrode of the third transistor T3.

[0225] In the example embodiment, since the first regions of the third active layers in the first sub-pixel P1 and the second sub-pixel P2 in the repeating unit are connected to each other, the first sub-pixel P1 and the second sub-pixel P2 share the same fourth via V4, and thus the first sub-pixel P1 and the second sub-pixel P2 share the same eighth connection electrode 18. Since the first regions of the third active layers in the third sub-pixel P3 and the fourth sub-pixel P4 are connected to each other, the third sub-pixel P3 and the fourth sub-pixel P4 share the same fourth via V4, and thus the third sub-pixel P3 and the fourth sub-pixel P4 share the same eighth connection electrode 18. The present disclosure can effectively reduce the number of connection electrodes, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, simplify the manufacturing process, reduce the production cost, and improve the product yield by arranging the sub-pixels adjacent in the first direction X in the repeating unit to share the same eighth connection electrode.

[0226] In the example embodiment, in one repeating unit, the compensation signal line 53 can provide compensation signals to the pixel driving circuits in the four sub-pixels at the same time, and thus the four pixel driving circuits in one repeating unit can share one compensation signal line 53, i.e., the compensation signal line 53 in one repeating unit has a one-to-four structure. The display substrate of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, and a reasonable layout, fully utilizes the layout space, improves the space utilization rate, increases the pixel aperture ratio, and improves the display resolution by designing the compensation signal line as a one-to-four structure.

[0227] In the example embodiment, the compensation signal line 53 is arranged between the first pixel column and the second pixel column, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically arranged relative to the compensation signal line 53. The symmetric structure of the present disclosure can ensure that the RC delay of the compensation signal written to the third transistor T3 is substantially the same, thereby ensuring display uniformity.

[0228] In the example embodiment, the power supply connection electrode 20 can have a strip shape extending along the first direction X, and can be arranged on the side of the second polar plate 62 away from the scan signal line 30. The first end of the power supply connection electrode 20 is connected to the first power supply line 51 through the seventh via V7, and the second end of the power supply connection electrode 20 is connected to the first region of the second active layer 22 through the second via V2, thereby realizing that the first power supply line 51 writes the first power supply signal to the first electrode of the second transistor T2.

[0229] In the example embodiment, in each repeating unit, the first power supply line 51 of the first pixel column can simultaneously provide the first power supply signal to the pixel driving circuit in the first sub-pixel P1 and the third sub-pixel P3, and the first power supply line 51 of the second pixel column can simultaneously provide the first power supply signal to the pixel driving circuit in the second sub-pixel P2 and the fourth sub-pixel P4, thereby realizing a one-to-two structure of the first power supply line 51 in one repeating unit. The display substrate of the present disclosure saves the number of signal lines by designing the first power supply line as a one-to-two structure, reduces the occupied space, has a simple structure, and has a reasonable layout. The display substrate of the present disclosure fully utilizes the layout space, improves the space utilization rate, increases the pixel aperture ratio, and improves the display resolution.

[0230] In the example embodiment, the two first power supply lines 51 in one repeating unit are symmetrically arranged relative to the compensation signal line 53, and the second transistor T2 of the first pixel column and the second transistor T2 of the second pixel column are symmetrically arranged relative to the compensation signal line 53. The symmetric structure of the present disclosure can ensure that the voltage drop of the first power supply line written to the second transistor T2 is substantially the same, thereby ensuring display uniformity.

[0231] In the example embodiment, the first ends of the power supply connection electrodes 20 of the adjacent two sub-pixels in the adjacent two repeating units in the first direction X can be connected to each other. For example, the first ends of the two power supply connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 can be connected to each other. For another example, the first ends of the two power supply connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 can be connected to each other.

[0232] In the example embodiment, the power supply connection electrodes 20 of the adjacent two sub-pixels in the adjacent two repeating units in the first direction X can be an integrated structure connected to each other.

[0233] In the example embodiment, since the second transistor of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y shares the first region of the second active layer, the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the same second via V2, and thus the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the same power connection electrode 20. For example, the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 share the same power connection electrode 20. For another example, the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 share the same power connection electrode 20. The present disclosure can effectively reduce the number of connection electrodes, reduce the area occupied by the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process and reduce production costs by reducing the connection electrodes, thereby improving product yield.

[0234] In the example embodiment, in at least one repeating unit, the positions of the patterns in the third conductive layer in the first sub-pixel P1 and the positions of the patterns in the third conductive layer in the third sub-pixel P3 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the patterns in the third conductive layer in the second sub-pixel P2 and the positions of the patterns in the third conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the patterns in the third conductive layer in the first sub-pixel P1 and the positions of the patterns in the third conductive layer in the second sub-pixel P2 can be substantially mirror-symmetric with respect to a vertical reference line, and the positions of the patterns in the third conductive layer in the third sub-pixel P3 and the positions of the patterns in the third conductive layer in the fourth sub-pixel P4 can be substantially mirror-symmetric with respect to a vertical reference line.

[0235] In the example embodiment, in the process of forming the third conductive layer pattern, a wet etching process is first used to form the third conductive layer pattern, so that the at least one connection electrode is connected to the second conductive layer and the semiconductor layer through the via of the transfer structure. The via of the transfer structure can include at least two half-holes: a shallow half-hole and a deep half-hole. In the shallow half-hole, the second insulating layer is removed to expose the surface of the semiconductor layer, and in the deep half-hole, the second insulating layer and the first insulating layer are removed to expose the surface of the second conductive layer, thereby achieving the connection of the connection electrode to the semiconductor layer and the second conductive layer through the shallow half-hole and the deep half-hole. In the example embodiment, a distance is provided between the end of the connection electrode in the shallow half-hole region and the edge of the shallow half-hole, i.e., the connection electrode does not completely cover the shallow half-hole.

[0236] In the example embodiment, after the third conductive layer pattern is formed by the wet etching process, the second insulating layer in the area other than the third conductive layer is etched by a dry etching process using the third conductive layer as a mask, and the semiconductor layer exposed at the same time is secondly conductive, forming a second conductive area.

[0237] In the example embodiment, in the second conductive process, the edge part of the semiconductor layer covered by the third conductive layer is also conductive, that is, the second conductive semiconductor layer extends to the first conductive area, forming a twice conductive area in the overlapping area of the first conductive area and the second conductive area, which can ensure the reliable connection between the third conductive layer and the semiconductor layer.

[0238] In the example embodiment, for the power connection electrode 20 connected to the first area of the second active layer 22 through the second via V2, and the second gate electrode 32 connected to the second plate 62 through the sixth via V6, the power connection electrode 20 and the second gate electrode 32 do not cover all the vias, and a distance is set between the edge of the connection electrode and the edge of the via.

[0239] FIG. 9C is a sectional view of A-A in FIG. 9A, and FIGS. 9D-9F are sectional views of B-B in FIG. 9A. In the direction perpendicular to the display substrate, the display substrate can at least include a second conductive layer, a first insulating layer 71, a semiconductor layer, a second insulating layer 72, and a third conductive layer arranged in sequence on the base 10. The second conductive layer can at least include a first power line 51 and a data signal line 52, the semiconductor layer can at least include a second active layer 22, and the third conductive layer can at least include a power connection electrode 20.

[0240] In the example embodiment, the first end of the power connection electrode 20 is connected to the first power line 51 through the seventh via V7, and the second end of the power connection electrode 20 is connected to the second active layer 22 through the second via V2, as shown in FIG. 9C.

[0241] In the example embodiment, in the process of forming the second insulating layer pattern, the second insulating layer in the second via V2 is etched to expose the surface of the second active layer 22, and at the same time, the semiconductor layer exposed in the second via V2 is firstly conductive, so that the semiconductor layer exposed in the second via V2 forms a first conductive area, as shown in FIG. 9D.

[0242] In the exemplary embodiment, in the process of forming the third conductive layer pattern, the third conductive layer including the power supply connecting electrode 20 is first formed by a wet etching process, and the power supply connecting electrode 20 is connected to the second active layer 22 through the second via V2, as shown in FIG. 9E. Subsequently, the second insulating layer 72 outside the third conductive layer is etched by a dry etching process using a self-alignment process with the third conductive layer as a mask, and the exposed semiconductor layer is secondly conductive at the same time the second insulating layer 72 is etched, forming a second conductive region, as shown in FIG. 9F.

[0243] (16) Forming the third insulating layer and planar layer pattern. In the exemplary embodiment, forming the third insulating layer and planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a third insulating film, then coating a planar film, and patterning the planar film and the third insulating film by a patterning process to form the third insulating layer covering the third conductive layer and the planar layer pattern disposed on the third insulating layer, and the planar layer is provided with a plurality of vias, as shown in FIG. 10.

[0244] In the exemplary embodiment, the via of each sub-pixel in each repeating unit at least includes an eleventh via V11.

[0245] In the exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is within the orthographic projection of the fifth connecting electrode 15 on the substrate, the third insulating layer and the planar layer in the eleventh via V11 are etched away, exposing the surface of the fifth connecting electrode 15, and the eleventh via V11 is configured to allow the anode connecting electrode formed subsequently to be connected to the fifth connecting electrode 15 through the via.

[0246] In the exemplary embodiment, the process uses a one-time patterning process to form the via on the third insulating layer and the planar layer at the same time, i.e., the third insulating layer and the planar layer share a one-time half-tone or gray-tone mask (MASK) process, effectively reducing the number of times of the patterning process.

[0247] (17) Forming the fourth conductive layer pattern. In the exemplary embodiment, forming the fourth conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth conductive film, and patterning the fourth conductive film by a patterning process to form the fourth conductive layer pattern on the color film layer, as shown in FIGS. 11A and 11B, and FIG. 11B is a schematic diagram of the fourth conductive layer in FIG. 11A.

[0248] In the exemplary embodiment, the fourth conductive layer of each sub-pixel in each repeating unit can at least include a first electrode 63 and an anode connecting electrode 64.

[0249] In an example embodiment, the first electrode 63 can have a rectangular shape, and the corner of the rectangular shape can be provided with a chamfer, a groove or a protrusion. The orthographic projection of the first electrode 63 on the substrate at least partially overlaps the orthographic projection of the second electrode 62 on the substrate.

[0250] In an example embodiment, the anode connecting electrode 64 can have a block shape (e.g., a rectangular shape) and can be located on the side of the first electrode 63 away from the scan signal line 30. The first end of the anode connecting electrode 64 is connected to the first electrode 63, and the second end of the anode connecting electrode 64 extends away from the scan signal line 30 and is connected to the fifth connecting electrode 15 through the eleventh via V11.

[0251] In an example embodiment, in at least one sub-pixel, the anode connecting electrode 64 and the first electrode 63 can be an integrated structure connected to each other.

[0252] In an example embodiment, in at least one repeating unit, the four first electrodes 63 can be arranged in a square shape. The upper left first electrode is connected to the pixel driving circuit in the first sub-pixel P1, the upper right first electrode is connected to the pixel driving circuit in the second sub-pixel P2, the lower left first electrode is connected to the pixel driving circuit in the third sub-pixel P3, and the lower right first electrode is connected to the pixel driving circuit in the fourth sub-pixel P4. In some possible implementations, the first electrode can serve as an anode of the light-emitting device, and the arrangement of the first electrode can be adjusted according to actual needs, which is not limited in the present disclosure.

[0253] In an example embodiment, the material of the first conductive layer can be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0254] In an example embodiment, the first electrode 63 can also serve as an auxiliary capacitor of the storage capacitor. Since the first electrode 63 is connected to the anode connecting electrode 64, and the anode connecting electrode 64 is connected to the first electrode 61 through the fifth connecting electrode 15, the third connecting electrode 13 and the first connecting electrode 11, the first electrode 63 has the potential of the second node in the pixel driving circuit. The first electrode 63 with the potential of the second node and the second electrode 62 with the potential of the first node form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. The present disclosure uses the first electrode to form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. On the one hand, the capacitance of the storage capacitor can be effectively increased, and on the other hand, the area of the electrode plate can be reduced while ensuring the capacitance of the storage capacitor, thereby effectively reducing the occupied area.

[0255] (18) Forming a pixel definition layer. In an example embodiment, forming the pixel definition layer pattern can include: on the substrate on which the aforementioned pattern is formed, applying a pixel definition film, patterning the pixel definition film by a patterning process, and forming the pixel definition layer covering the fourth conductive layer, as shown in FIG. 12.

[0256] In an example embodiment, a pixel opening PK is formed on the pixel definition layer of each sub-pixel in each repeating unit, the pixel definition film in the pixel opening PK is removed, and part of the surface of the first electrode 63 is exposed, and the orthographic projection of the pixel opening PK on the substrate is within the orthographic projection of the first electrode 63 on the substrate.

[0257] In an example embodiment, in a plane parallel to the substrate, the shape of the pixel opening PK can be similar to the shape of the first electrode 63, and in a plane perpendicular to the substrate, the cross-sectional shape of the pixel opening PK can be rectangular or trapezoidal, etc.

[0258] In an example embodiment, the shape of the pixel opening can include any one or more of the following: triangular, rectangular, trapezoidal, parallelogram, pentagon, hexagon, circular, and elliptical.

[0259] In an example embodiment, the shapes of the pixel openings of the four sub-pixels in the repeating unit can be the same or different. The areas of the pixel openings of the four sub-pixels can be the same or different.

[0260] In an example embodiment, the shapes and areas of the pixel openings of the four sub-pixels in the repeating unit can be different to adapt to the transmittance of different sub-pixel filters, so that the light emitting devices of the four sub-pixels can emit the same brightness at different currents, maximize the life of the light emitting devices of the four sub-pixels, and ensure the product life.

[0261] In an example embodiment, at least one partition groove M can also be provided on the pixel definition layer of each repeating unit. The shape of the partition groove M can be a strip shape extending along the second direction Y, and the partition groove M can be arranged between the pixel openings PK adjacent in the first direction X. For example, the partition groove M can be arranged between the pixel opening PK of the first sub-pixel P1 and the pixel opening PK of the second sub-pixel P2. For another example, the partition groove M can be arranged between the pixel opening PK of the third sub-pixel P3 and the pixel opening PK of the fourth sub-pixel P4. In an example embodiment, the partition groove M is configured to cut off the organic light emitting layer formed subsequently, block the lateral propagation path of the hole type carriers, eliminate lateral leakage, and eliminate lateral cross talk of the sub-pixels.

[0262] In an example embodiment, the pixel definition layer can be made of polyimide, acrylic, polyethylene terephthalate, etc.

[0263] (19) Forming an organic light-emitting layer and a cathode pattern. In an example embodiment, forming the organic light-emitting layer and the cathode pattern can include: first forming an organic light-emitting layer pattern, the organic light-emitting layer being connected to the first electrode 63 through the pixel opening PK. Then, a second electrode is formed, the second electrode being connected to the organic light-emitting layer. In an example embodiment, the second electrode can serve as the cathode of the light-emitting device.

[0264] In an example embodiment, the organic light-emitting layer can include a light-emitting layer (EML), and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an example embodiment, the organic light-emitting layer can be formed by fine metal mask (FMM) or Open Mask evaporation, or by an inkjet process.

[0265] (20) Forming an encapsulation structure layer pattern. In an example embodiment, forming the encapsulation structure layer pattern can include: first depositing a first inorganic thin film using an Open Mask to form a first encapsulation layer. Then, an organic material is inkjet printed on the first encapsulation layer using an inkjet printing process, and after curing into a film, a second encapsulation layer is formed. Then, a second inorganic thin film is deposited using an Open Mask to form a third encapsulation layer, the first, second, and third encapsulation layers forming the encapsulation structure layer. The first and third encapsulation layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbon nitride (SiCN), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. The second encapsulation layer can be a resin material, forming a stack structure of inorganic material / organic material / inorganic material, with the organic material layer being disposed between the two inorganic material layers, so as to prevent external moisture from entering the light-emitting structure layer.

[0266] So far, the preparation of the display substrate of the example embodiment of the present disclosure has been completed. The display substrate can include a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate. In a direction perpendicular to the display substrate, the driving circuit layer can include, in order on the substrate, a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a planarization layer. The light-emitting structure layer can include a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode. The encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together.

[0267] In the example embodiment, for the display substrate including the color film structure layer, after the third conductive layer is formed, the third insulating layer is formed first, then the red color film layer, the green color film layer and the blue color film layer are sequentially formed, and then the planarization layer is formed, which will not be described herein.

[0268] In the example embodiment, the substrate can be a flexible substrate or can be a rigid substrate. The rigid substrate can be one or more of, but is not limited to, glass, quartz, and the flexible substrate can be one or more of, but is not limited to, polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In the example embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer stacked, the materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET) or a surface-treated polymer soft film, etc., the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0269] In the example embodiment, the second conductive layer and the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer and the second insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), which can be a single layer, a multi-layer or a composite layer. The planarization layer can be made of an organic material, such as resin, etc.

[0270] The display substrate with bottom emission structure provided by the example embodiment of the present disclosure reduces the number of vias by arranging the first electrode of the second transistor in the sub-pixel to be close to the first power supply line, and arranging the two adjacent sub-pixels in the two adjacent repeating units in the first direction to share the power supply via connected between the gate metal layer and the second conductive layer, and arranging the two adjacent sub-pixels in the two adjacent repeating units in the second direction to share the power supply via connected between the gate metal layer and the second conductive layer, which can effectively reduce the area occupied by the pixel driving circuit, increase the pixel aperture ratio and improve the display resolution. In addition, reducing the vias can simplify the preparation process, reduce the production cost and improve the product yield.

[0271] The display substrate provided by the embodiment of the present disclosure sets the second active layers of the two adjacent sub-pixels in the two adjacent repeating units in the second direction into an integrated structure connected with each other, so that the two adjacent sub-pixels in the two adjacent repeating units in the second direction share the active via connected between the gate metal layer and the semiconductor layer, the number of the switching vias is further reduced, the area occupied by the pixel driving circuit can be effectively reduced, the pixel aperture ratio is increased, and the display resolution is improved.

[0272] The display substrate provided by the embodiment of the present disclosure sets the power connection electrodes of the two adjacent sub-pixels in the two adjacent repeating units in the first direction into an integrated structure connected with each other, so that the two adjacent sub-pixels in the two adjacent repeating units in the second direction share the power connection electrodes, the number of the connection electrodes is reduced, the area occupied by the pixel driving circuit can be effectively reduced, the pixel aperture ratio is increased, and the display resolution is improved. In addition, the reduction of the connection electrodes can simplify the preparation process, reduce the production cost, and improve the product yield.

[0273] The display substrate provided by the embodiment of the present disclosure sets the second active layers with a larger width and the second active layers with a smaller width in the first direction X and the second direction Y alternately, which not only effectively matches the requirements of the single scanning signal line structure, but also effectively increases the uniformity of the four pixel driving circuit layouts in the repeating unit and effectively increases the uniformity of the four sub-pixel apertures in the repeating unit.

[0274] The display substrate provided by the embodiment of the present disclosure sets the first power line, the data signal line, and the compensation signal line in the SHIELD layer, which is located on the side of the semiconductor layer close to the base, and sets the scanning signal line and the gate electrodes of the plurality of transistors in the GT layer, which is located on the side of the semiconductor layer away from the base, which not only reduces one conductive layer, but also reduces the patterning process of the switching via and the patterning process of the switching conductive layer, so that the preparation process of the driving structure layer only needs six times of patterning (MASK) process. Compared with the existing preparation process which needs nine times of patterning process, the display substrate provided by the present disclosure reduces the number of times of the patterning process, effectively improves the production efficiency, effectively reduces the production cost, and maximizes the product yield.

[0275] The display substrate provided by the embodiment of the present disclosure adopts a 3T1C pixel driving circuit of one scanning signal line, and the scanning signal line is connected with the first transistor and the third transistor in the pixel driving circuit. By reducing the number of the scanning signal lines, the structure of the pixel driving circuit can be simplified, the area occupied by the pixel driving circuit can be reduced, and high-resolution display can be realized. In addition, since only one scanning signal line is needed to drive one repeating unit, the number of the corresponding gate driving circuit (GOA) and clock signal line (CLK) can be reduced by several times, the area occupied by the gate driving circuit and the clock signal line is effectively reduced, and narrow frame can be realized, which improves the product advantage.

[0276] The display substrate of the embodiment of the present disclosure can make light pass through the transparent storage capacitor composed of the transparent conductive layer and the transparent semiconductor layer, so that the storage capacitor can be arranged in the pixel opening, which can effectively increase the capacitance of the storage capacitor and the pixel opening rate.

[0277] The display substrate of the embodiment of the present disclosure can effectively increase the pixel opening rate and improve the display effect by arranging the sub-pixels in a square manner and using the first power line structure in a non-network structure, which is more suitable for display of the display type.

[0278] The preparation process of the present disclosure is compatible with the existing preparation process, simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.

[0279] FIG. 13 is a structural schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, which illustrates the structure of four repeating units (sixteen sub-pixels) in a bottom emission display substrate. In the exemplary embodiment, the main structure of the display substrate of the present embodiment is basically the same as that of the foregoing embodiments, except that the pixel driving circuit further includes an active connection electrode 24, and the power connection electrode 20 is connected to the first power line 51 and the active connection electrode 24 through a switching via.

[0280] In the exemplary embodiment, the structures of the scan signal line 30, the first power line 51, the data signal line 52, the compensation signal line 53, the storage capacitor 60, the first transistor T1, the second transistor T2, and the third transistor T3 are basically the same as those of the foregoing embodiments, and will not be described here.

[0281] In the exemplary embodiment, the pixel driving circuit further includes an active connection electrode 24. The active connection electrode 24 can have a strip shape extending along the first direction X, the first end of the active connection electrode 24 is connected to the first region of the second active layer 22 in the one-piece structure, and the second end of the active connection electrode 24 extends to the region where the first power line 51 is located in a direction away from the second active layer 22.

[0282] In the exemplary embodiment, the second active layer 22 and the active connection electrode 24 can be a one-piece structure.

[0283] In the exemplary embodiment, the second end of the active connection electrode 24 has an orthographic projection on the substrate that at least partially overlaps the orthographic projection of the first power line 51 on the substrate.

[0284] In an example embodiment, the orthographic projection of the active connection electrode 24 on the substrate at least partially overlaps the orthographic projection of the data signal line 52 on the substrate, forming a structure in which the second active layer 22 crosses the data signal line 52.

[0285] In an example embodiment, the power connection electrode 20 can have a block shape (e.g., a rectangular shape), and the power connection electrode 20 is connected to the first power line 51 and the second end of the active connection electrode 24 through the relay via hole K3.

[0286] In an example embodiment, the relay via hole K3 can include a shallow half-hole and a deep half-hole, the shallow half-hole exposes the surface of the second end of the active connection electrode 24, and the deep half-hole exposes the surface of the first power line 51. The shallow half-hole can serve as an active via hole of the present disclosure, and the deep half-hole can serve as a power via hole of the present disclosure.

[0287] In an example embodiment, two adjacent subpixels in two adjacent repeat units in the first direction X share the same relay via hole K3. For example, for the first repeat unit Q1 and the second repeat unit Q2 adjacent in the first direction X, the fourth subpixel P4 in the first repeat unit Q1 and the third subpixel P3 in the second repeat unit Q2 share the same relay via hole K3. For another example, for the third repeat unit Q3 and the fourth repeat unit Q4 adjacent in the first direction X, the fourth subpixel P4 in the third repeat unit Q3 and the third subpixel P3 in the fourth repeat unit Q4 share the same relay via hole K3.

[0288] In an example embodiment, two adjacent subpixels in two adjacent repeat units in the second direction Y share the same relay via hole K3. For example, for the first repeat unit Q1 and the third repeat unit Q3 adjacent in the second direction Y, the third subpixel P3 in the first repeat unit Q1 and the first subpixel P1 in the third repeat unit Q3 can share the same relay via hole K3, and the fourth subpixel P4 in the first repeat unit Q1 and the second subpixel P2 in the third repeat unit Q3 can share the same relay via hole K3. For another example, for the second repeat unit Q2 and the fourth repeat unit Q4 adjacent in the second direction Y, the third subpixel P3 in the second repeat unit Q2 and the first subpixel P1 in the fourth repeat unit Q4 can share the same relay via hole K3, and the fourth subpixel P4 in the second repeat unit Q2 and the second subpixel P2 in the fourth repeat unit Q4 can share the same relay via hole K3.

[0289] In an example embodiment, adjacent sub-pixels in adjacent repeating units in the first direction X share the same transfer via hole K3. For example, the fourth sub-pixel P4 in the first repeating unit Q1, the third sub-pixel P3 in the second repeating unit Q2, the second sub-pixel P2 in the third repeating unit Q3, and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same transfer via hole K3.

[0290] In an example embodiment, the second ends of the active connection electrodes 24 of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X can be connected to each other. Since the active connection electrode 24 of each sub-pixel is connected to the first region of the second active layer 22, the first regions of the second active layers 22 of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X are connected to each other through the active connection electrodes 24. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 are connected to each other through the active connection electrode 24. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the third repeating unit Q3 and the first region of the second active layer 22 of the third sub-pixel P3 in the fourth repeating unit Q4 are connected to each other through the active connection electrode 24.

[0291] In an example embodiment, the active connection electrodes 24 of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X are an integral structure connected to each other.

[0292] In an example embodiment, the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y can share the same active connection electrode 24. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same active connection electrode 24, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same active connection electrode 24. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same active connection electrode 24, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same active connection electrode 24.

[0293] In the exemplary embodiment, the first regions of the second active layers 22 of the adjacent sub-pixels in the adjacent repeating units in the first direction X and the second direction Y can be connected to each other by the active connection electrodes 24.

[0294] In the exemplary embodiment, the two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the same power connection electrode 20. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same power connection electrode 20. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same power connection electrode 20.

[0295] In the exemplary embodiment, the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the same power connection electrode 20. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same power connection electrode 20. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same power connection electrode 20.

[0296] In the exemplary embodiment, the two adjacent sub-pixels in the adjacent repeating units in the first direction X and the second direction Y share the same power connection electrode 20, i.e., the four adjacent sub-pixels in the adjacent repeating units share the same power connection electrode 20. For example, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 share the same power connection electrode 20.

[0297] In the exemplary embodiment, the preparation process of the substrate can include the following operations.

[0298] (21) Forming a first conductive layer pattern, the process and the structure of the formed first conductive layer are basically the same as those of the aforementioned embodiment step (11).

[0299] (22) Forming a second conductive layer pattern, the process and the structure of the formed second conductive layer are substantially the same as those of the aforementioned embodiment step (12).

[0300] (23) Forming a semiconductor layer pattern, the process and the structure of the formed semiconductor layer are substantially the same as those of the aforementioned embodiment step (13), except that the semiconductor layer further comprises an active connection electrode 24, as shown in FIGS. 14A and 14B, which is a schematic view of the semiconductor layer in FIG. 14A.

[0301] In an exemplary embodiment, the semiconductor layer of each sub-pixel in each repeating unit can at least comprise the first active layer 21, the second active layer 22, the third active layer 23, and the second plate 62 of the storage capacitor, and the above structure is substantially the same as that of the aforementioned embodiment.

[0302] In an exemplary embodiment, the semiconductor layer of each sub-pixel can further comprise an active connection electrode 24, the shape of the active connection electrode 24 can be a strip shape extending along the first direction X, the first end of the active connection electrode 24 is connected to the first region of the second active layer 22 of the integral structure, and the second end of the active connection electrode 24 extends to the region where the first power supply line 51 is located in a direction away from the second active layer 22, and the second end of the active connection electrode 24 is configured to be connected to the first power supply line 51 through the subsequently formed power supply connection electrode.

[0303] In an exemplary embodiment, the second active layer 22 and the active connection electrode 24 can be an integral structure connected to each other.

[0304] In an exemplary embodiment, the second end of the active connection electrode 24 has an orthographic projection on the substrate that at least partially overlaps with an orthographic projection of the first power supply line 51 on the substrate.

[0305] In an exemplary embodiment, the active connection electrode 24 has an orthographic projection on the substrate that at least partially overlaps with an orthographic projection of the data signal line 52 on the substrate, forming a structure in which the second active layer 22 crosses the data signal line 52.

[0306] In the exemplary embodiments, the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y can be an integrated structure connected to each other, and thus the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y can share the same active connection electrode 24. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same active connection electrode 24, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same active connection electrode 24. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same active connection electrode 24, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same active connection electrode 24.

[0307] In the exemplary embodiments, the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X can be connected to each other. Since the active connection electrode 24 of each sub-pixel is connected to the first region of the second active layer 22, the first regions of the second active layers 22 of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X are connected to each other through the active connection electrodes 24. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1 and the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2 are connected to each other through the active connection electrode 24. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the first region of the second active layer 22 of the fourth sub-pixel P4 in the third repeating unit Q3 and the first region of the second active layer 22 of the third sub-pixel P3 in the fourth repeating unit Q4 are connected to each other through the active connection electrode 24.

[0308] In the exemplary embodiments, the active connection electrodes 24 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integrated structure connected to each other.

[0309] In the example embodiment, the first regions of the second active layers 22 of the adjacent sub-pixels in the adjacent repeating units in the first direction X and the second direction Y can be connected to each other through the active connection electrodes 24. For example, the first region of the second active layer 22 of the fourth sub-pixel P4 in the first repeating unit Q1, the first region of the second active layer 22 of the third sub-pixel P3 in the second repeating unit Q2, the first region of the second active layer 22 of the second sub-pixel P2 in the third repeating unit Q3, and the first region of the second active layer 22 of the first sub-pixel P1 in the fourth repeating unit Q4 can be connected to each other through the active connection electrodes 24. By arranging the first regions of the second active layers of the four adjacent sub-pixels in the adjacent repeating units to share the second active layer, the number of vias can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, and the production process can be simplified, the production cost can be reduced, and the product yield can be improved.

[0310] In the example embodiment, the width of the second active layer in the adjacent sub-pixels in the first direction X is different, and the width of the second active layer in the adjacent sub-pixels in the second direction Y is different.

[0311] (24) Forming a second insulating layer pattern, the process and the structure of the formed second insulating layer are basically the same as those in the step (14) of the foregoing embodiment, except that the eighth via V8 is a via of a switching structure, as shown in FIG. 15.

[0312] In the example embodiment, a plurality of vias are provided on the second insulating layer, and the plurality of vias of each sub-pixel in each repeating unit at least include the first via V1, the third via V3, and the sixth via V6. The structure of the above-mentioned via is basically the same as that in the foregoing embodiment.

[0313] In the example embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the second end of the active connection electrode 24 and the orthographic projection of the first power supply line 51 on the substrate. The eighth via V8 as a switching via of the present disclosure includes a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away to expose the surface of the second end of the active connection electrode 24, and the first insulating layer and the second insulating layer in the deep half-hole are etched away to expose the surface of the first power supply line 51, so that the switching structure via composed of the two half-holes simultaneously exposes the second end of the active connection electrode 24 and the first power supply line 51. The eighth via V8 is configured to enable the subsequently formed power supply connection electrode to be connected to the second end of the active connection electrode 24 and the first power supply line 51 through the via. In the example embodiment, the eighth via V8 as a switching via of the present disclosure, the shallow half-hole can be used as an active via of the present disclosure, and the deep half-hole can be used as a power supply via of the present disclosure.

[0314] In the example embodiment, since the active connection electrodes 24 of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X are integrally connected to each other, the two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the same eighth via V8. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same eighth via V8. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same eighth via V8. The present disclosure can effectively reduce the number of vias, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process, reduce production costs, and improve product yield by arranging the two adjacent sub-pixels in the two adjacent repeating units in the first direction X to share the same eighth via V8.

[0315] In the example embodiment, since the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y can share the same active connection electrode 24, the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the same eighth via V8. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same eighth via V8, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same eighth via V8. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same eighth via V8, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same eighth via V8. The present disclosure can effectively reduce the number of vias, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process, reduce production costs, and improve product yield by arranging the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y to share the same eighth via V8.

[0316] In the exemplary embodiment, the first direction X and the second direction Y adjacent sub-pixels in adjacent repeating units share the same switching via K3, i.e., the fourth sub-pixel P4 in the first repeating unit Q1, the third sub-pixel P3 in the second repeating unit Q2, the second sub-pixel P2 in the third repeating unit Q3 and the first sub-pixel P1 in the fourth repeating unit Q4 share the same eighth via V8.

[0317] (25) Forming a third conductive layer pattern, the process and the structure of the third conductive layer formed are basically the same as those of the aforementioned embodiment step (15), except that the power supply connecting electrode 20 is connected to the second end of the active connecting electrode 24 and the first power supply line 51 through the eighth via V8 of the switching structure, as shown in FIGS. 16A and 16B, wherein FIG. 16B is a schematic view of the third conductive layer in FIG. 16A.

[0318] In the exemplary embodiment, the third conductive layer of each sub-pixel in each repeating unit can include at least the fifth connecting electrode 15, the sixth connecting electrode 16, the seventh connecting electrode 17, the eighth connecting electrode 18, the power supply connecting electrode 20, the scanning signal line 30, the first gate electrode 31, the second gate electrode 32 and the third gate electrode 33, except that the power supply connecting electrode 20 is basically the same as the aforementioned embodiment.

[0319] In the exemplary embodiment, the power supply connecting electrode 20 can be in the shape of a block (e.g., a rectangle), and the power supply connecting electrode 20 is connected to the second end of the active connecting electrode 24 and the first power supply line 51 through the eighth via V8 of the switching structure. Since the active connecting electrode 24 is connected to the first region of the second active layer, the first power supply line 51 writes the first power supply signal to the first electrode of the second transistor T2.

[0320] In the example embodiment, since the two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the same eighth via V8, the two adjacent sub-pixels in the two adjacent repeating units in the first direction X share the same power connection electrode 20. For example, for the first repeating unit Q1 and the second repeating unit Q2 adjacent in the first direction X, the fourth sub-pixel P4 in the first repeating unit Q1 and the third sub-pixel P3 in the second repeating unit Q2 share the same power connection electrode 20. For another example, for the third repeating unit Q3 and the fourth repeating unit Q4 adjacent in the first direction X, the fourth sub-pixel P4 in the third repeating unit Q3 and the third sub-pixel P3 in the fourth repeating unit Q4 share the same power connection electrode 20. The present disclosure can effectively reduce the number of connection electrodes, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process, reduce production costs, and improve product yield by arranging the two adjacent sub-pixels in the two adjacent repeating units in the first direction X to share the same power connection electrode 20.

[0321] In the example embodiment, since the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the same eighth via V8, the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y share the same power connection electrode 20. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent in the second direction Y, the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can share the same power connection electrode 20. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent in the second direction Y, the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can share the same power connection electrode 20, and the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can share the same power connection electrode 20. The present disclosure can effectively reduce the number of connection electrodes, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process, reduce production costs, and improve product yield by arranging the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y to share the same power connection electrode 20.

[0322] In the exemplary embodiments, the four adjacent sub-pixels in the adjacent repeating units share one power connection electrode 20, i.e., the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 share one power connection electrode 20. The present disclosure can effectively reduce the number of connection electrodes, reduce the occupied area of the pixel driving circuit, increase the pixel aperture ratio, improve the display resolution, and simplify the manufacturing process, reduce production costs, and improve product yield by arranging four adjacent sub-pixels in adjacent repeating units to share one power connection electrode 20.

[0323] In the exemplary embodiments, the processes of forming the third insulating layer, the planarization layer, the fourth conductive layer, the pixel definition layer, the organic light-emitting layer, the cathode, and the encapsulation structure layer, and the formed structures are basically the same as those in the foregoing embodiments, and will not be described here.

[0324] The display substrate with a bottom emission structure provided in the embodiments of the present disclosure effectively reduces the number of transfer vias and connection electrodes by arranging the source connection electrodes so that the adjacent sub-pixels in the adjacent repeating units in the first direction and the second direction share the transfer vias and connection electrodes connecting the gate metal layer, the semiconductor layer, and the SHIELD layer, effectively reduces the occupied area of the pixel driving circuit, increases the pixel aperture ratio, improves the display resolution, and simplifies the manufacturing process, reduces production costs, and improves product yield by reducing the number of transfer vias and connection electrodes.

[0325] The display substrate in the embodiments of the present disclosure also has the technical effects of reducing the number of patterning processes, reducing the number of scanning signal lines, and increasing the pixel aperture ratio.

[0326] FIG. 17 is a structural schematic diagram of another display substrate in the exemplary embodiments of the present disclosure, which illustrates the structure of four repeating units (sixteen sub-pixels) in a bottom emission display substrate. In the exemplary embodiments, the main structure of the display substrate in the present embodiment is basically the same as that in the foregoing embodiments, except that the first area of the second active layer 22 of the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y is not connected, and the first ends of the power connection electrodes 20 of the two adjacent sub-pixels in the two adjacent repeating units in the first direction X and the second direction Y are connected to each other.

[0327] In the example embodiment, the structures of the scan signal line 30, the first power supply line 51, the data signal line 52, the compensation signal line 53, the storage capacitor 60, the first transistor T1, the second transistor T2, and the third transistor T3 are substantially the same as those of the foregoing embodiment, and thus the description thereof will not be repeated here.

[0328] In the example embodiment, in at least one of the repeating units, the first regions of the second active layers 22 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are not connected, and the first power supply line 51 is connected to the first regions of the second active layers 22 in each of the sub-pixels through the power supply connection electrode 20.

[0329] In the example embodiment, the power supply connection electrode 20 can have a strip shape extending along the first direction X, the first end of the power supply connection electrode 20 is connected to the first power supply line 51 through the power supply via K1, and the second end of the power supply connection electrode 20 is connected to the first region of the second active layer 22 through the active via K2.

[0330] In the example embodiment, two adjacent sub-pixels in two adjacent repeating units in the first direction X share one power supply via K1, and two adjacent sub-pixels in two adjacent repeating units in the second direction Y share one power supply via K1.

[0331] In the example embodiment, four adjacent sub-pixels in adjacent repeating units in the first direction X and the second direction Y share one power supply via K1. For example, the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3, and the first sub-pixel P1 of the fourth repeating unit Q4 share one power supply via K1.

[0332] In the example embodiment, the first ends of the power supply connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are connected to each other. For example, the first ends of the two power supply connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 are connected to each other. For another example, the first ends of the two power supply connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are connected to each other.

[0333] In the example embodiment, the power supply connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X are an integral structure connected to each other.

[0334] In an exemplary embodiment, the first ends of the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are connected to each other. For example, the first ends of the power connection electrodes 20 of the third sub-pixel P3 of the first repeating unit Q1 and the first sub-pixel P1 of the third repeating unit Q3 are connected to each other. For another example, the first ends of the power connection electrodes 20 of the fourth sub-pixel P4 of the first repeating unit Q1 and the second sub-pixel P2 of the third repeating unit Q2 are connected to each other.

[0335] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the second direction Y are an integral structure connected to each other.

[0336] In an exemplary embodiment, the power connection electrodes 20 of two adjacent sub-pixels in two adjacent repeating units in the first direction X and the second direction Y are an integral structure connected to each other, i.e. the power connection electrodes 20 of four adjacent sub-pixels in two adjacent repeating units are an integral structure connected to each other. For example, the four power connection electrodes 20 of the fourth sub-pixel P4 of the first repeating unit Q1, the third sub-pixel P3 of the second repeating unit Q2, the second sub-pixel P2 of the third repeating unit Q3 and the first sub-pixel P1 of the fourth repeating unit Q4 are an integral structure connected to each other.

[0337] In an exemplary embodiment, the preparation process of the substrate of the present embodiment can include the following operations.

[0338] (31) Forming a first conductive layer pattern, the process and the structure of the formed first conductive layer are basically the same as those of the step (11) of the foregoing embodiment.

[0339] (32) Forming a second conductive layer pattern, the process and the structure of the formed second conductive layer are basically the same as those of the step (12) of the foregoing embodiment.

[0340] (33) Forming a semiconductor layer pattern, the process and the structure of the formed semiconductor layer are basically the same as those of the step (13) of the foregoing embodiment, except that the second active layer 22 of each sub-pixel is separately provided, i.e. the first area of the second active layer 22 of adjacent sub-pixels is not connected, as shown in FIGS. 18A and 18B, wherein FIG. 18B is a schematic view of the semiconductor layer in FIG. 18A.

[0341] In an exemplary embodiment, the second area and the channel region of the second active layer 22 of each sub-pixel are at least partially overlapped with the orthographic projection of the third connection electrode 13 on the substrate, so that the third connection electrode 13 as a shielding layer can shield the channel region of the second transistor T2, avoid the influence of light on the channel, and ensure the electrical performance of the second transistor T2.

[0342] In the exemplary embodiments, the first region of the second active layer 22 in each sub-pixel is separately arranged, i.e. the first region of the second active layer 22 in adjacent sub-pixels is not connected. In at least one sub-pixel, the distance between the first region of the second active layer 22 and the first power line 51 can be smaller than the distance between the second region of the second active layer 22 and the first power line 51, i.e. the first region of the second active layer 22 is closer to the first power line 51 than the second region of the second active layer 22.

[0343] In the exemplary embodiments, the width of the second active layer in adjacent sub-pixels is different in the first direction X, and the width of the second active layer in adjacent sub-pixels is different in the second direction Y. In the first direction X, a plurality of second active layers of a larger width and a plurality of second active layers of a smaller width are arranged alternately, and in the second direction Y, a plurality of second active layers of a larger width and a plurality of second active layers of a smaller width are arranged alternately.

[0344] In the exemplary embodiments, the first sub-pixel P1 and the second sub-pixel P2 are arranged alternately in the first direction X, and the first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the second width L2 of the second active layer 22 in the second sub-pixel P2. The third sub-pixel P3 and the fourth sub-pixel P4 are arranged alternately in the first direction X, and the third width L3 of the second active layer 22 in the third sub-pixel P3 can be smaller than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4.

[0345] In the exemplary embodiments, the first sub-pixel P1 and the third sub-pixel P3 are arranged alternately in the second direction Y, and the first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3. The second sub-pixel P2 and the fourth sub-pixel P4 are arranged alternately in the second direction Y, and the second width L2 of the second active layer 22 in the second sub-pixel P2 can be smaller than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4.

[0346] In the exemplary embodiments, in at least one repeating unit, the widths of the second active layers 22 of the four sub-pixels can be different. For example, the first width L1 of the second active layer 22 in the first sub-pixel P1 can be greater than the fourth width L4 of the second active layer 22 in the fourth sub-pixel P4. For another example, the second width L2 of the second active layer 22 in the second sub-pixel P2 can be greater than the third width L3 of the second active layer 22 in the third sub-pixel P3.

[0347] In the exemplary embodiments, the present disclosure can effectively match the requirements of the single scanning signal line structure, effectively increase the uniformity of the four pixel driving circuit layouts in the repeating unit, and effectively increase the uniformity of the four sub-pixel pixel openings in the repeating unit by alternately arranging the second active layer with a larger width and the second active layer with a smaller width in the first direction X and the second direction Y.

[0348] (34) Form a second insulating layer pattern, the process and the structure of the formed second insulating layer are basically the same as those in the step (14) of the foregoing embodiment, except that the second via V2 of each sub-pixel is arranged individually, i.e., adjacent sub-pixels do not share the second via V2, as shown in FIG. 19.

[0349] In the exemplary embodiments, the second insulating layer is provided with a plurality of vias, and the plurality of vias of each sub-pixel in each repeating unit at least includes the first via V1 to the seventh via V7, and the structure of the above vias is basically the same as that in the foregoing embodiment.

[0350] In the exemplary embodiments, the seventh via V7 is shared by the two adjacent sub-pixels in the two adjacent repeating units in the first direction X, and the seventh via V7 is shared by the two adjacent sub-pixels in the two adjacent repeating units in the second direction Y.

[0351] In the exemplary embodiments, the seventh via V7 is shared by the adjacent sub-pixels in the adjacent repeating units in the first direction X and the second direction Y, i.e., the seventh via V7 is shared by the four adjacent sub-pixels in the adjacent repeating units.

[0352] (35) Form a third conductive layer pattern, the process and the structure of the formed third conductive layer are basically the same as those in the step (15) of the foregoing embodiment, except that the power supply connection electrode 20 is connected to the first area of the second active layer 22 of the two sub-pixels through the second via V2 of the two sub-pixels, as shown in FIGS. 20A and 20B, wherein FIG. 20B is a schematic view of the third conductive layer in FIG. 20A.

[0353] In the exemplary embodiments, the third conductive layer of each sub-pixel in each repeating unit can at least include the fifth connection electrode 15, the sixth connection electrode 16, the seventh connection electrode 17, the eighth connection electrode 18, the power supply connection electrode 20, the scanning signal line 30, the first gate electrode 31, the second gate electrode 32, and the third gate electrode 33, and the structures of the other components are basically the same as those in the foregoing embodiment, except for the power supply connection electrode 20.

[0354] In an example embodiment, the power connection electrode 20 can have a strip shape extending along the first direction X, the first end of the power connection electrode 20 is connected to the first power line 51 through the seventh via V7, and the second end of the power connection electrode 20 is connected to the first region of the second active layer 22 through the second via V2, so that the first power line 51 writes the first power signal to the first electrode of the second transistor T2.

[0355] In an example embodiment, the first ends of the power connection electrodes 20 of the adjacent two sub-pixels in the adjacent two repeating units along the first direction X can be connected to each other. For example, the first ends of the two power connection electrodes 20 in the second sub-pixel P2 of the first repeating unit Q1 and the first sub-pixel P1 of the second repeating unit Q2 are connected to each other. For another example, the first ends of the two power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1 and the third sub-pixel P3 of the second repeating unit Q2 are connected to each other.

[0356] In an example embodiment, the power connection electrodes 20 of the adjacent two sub-pixels in the adjacent two repeating units along the first direction X are an integrated structure connected to each other.

[0357] In an example embodiment, the first ends of the power connection electrodes 20 of the adjacent two sub-pixels in the adjacent two repeating units along the second direction Y can be connected to each other. For example, for the first repeating unit Q1 and the third repeating unit Q3 adjacent along the second direction Y, the first ends of the power connection electrodes 20 of the third sub-pixel P3 in the first repeating unit Q1 and the first sub-pixel P1 in the third repeating unit Q3 can be connected to each other, and the first ends of the power connection electrodes 20 of the fourth sub-pixel P4 in the first repeating unit Q1 and the second sub-pixel P2 in the third repeating unit Q3 can be connected to each other. For another example, for the second repeating unit Q2 and the fourth repeating unit Q4 adjacent along the second direction Y, the first ends of the power connection electrodes 20 of the third sub-pixel P3 in the second repeating unit Q2 and the first sub-pixel P1 in the fourth repeating unit Q4 can be connected to each other, and the first ends of the power connection electrodes 20 of the fourth sub-pixel P4 in the second repeating unit Q2 and the second sub-pixel P2 in the fourth repeating unit Q4 can be connected to each other.

[0358] In an example embodiment, the power connection electrodes 20 of the adjacent two sub-pixels in the adjacent two repeating units along the second direction Y are an integrated structure connected to each other.

[0359] In the example embodiment, the power connection electrodes 20 of the adjacent sub-pixels in the adjacent repeating units in the first direction X and the second direction Y are in an integrated structure connected to each other, i.e., the power connection electrodes 20 of the four adjacent sub-pixels in the adjacent repeating units are in an integrated structure connected to each other. For example, the power connection electrodes 20 in the fourth sub-pixel P4 of the first repeating unit Q1, the power connection electrodes 20 in the third sub-pixel P3 of the second repeating unit Q2, the power connection electrodes 20 in the second sub-pixel P2 of the third repeating unit Q3, and the power connection electrodes 20 in the first sub-pixel P1 of the fourth repeating unit Q4 are in an integrated structure connected to each other. By arranging the power connection electrodes 20 of the four adjacent sub-pixels in the adjacent repeating units in an integrated structure connected to each other, the number of vias can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, the pixel aperture ratio can be increased, the display resolution can be improved, and the number of vias can be reduced to simplify the manufacturing process, reduce production costs, and improve product yield.

[0360] In the example embodiment, the processes of forming the third insulating layer, the planarization layer, the fourth conductive layer, the pixel definition layer, the organic light-emitting layer, the cathode, and the encapsulation structure layer, and the formed structure are substantially the same as those in the foregoing embodiments, and will not be described herein.

[0361] The display substrate with a bottom emission structure provided by the example embodiment of the present disclosure has the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the first direction in an integrated structure connected to each other, and the power connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the second direction in an integrated structure connected to each other, which effectively reduces the number of switching vias, effectively reduces the area occupied by the pixel driving circuit, increases the pixel aperture ratio, and improves the display resolution. In addition, reducing the number of switching vias can simplify the manufacturing process, reduce production costs, and improve product yield.

[0362] The display substrate of the example embodiment of the present disclosure also has the technical effects of reducing the number of patterning processes, reducing the number of scanning signal lines, and increasing the pixel aperture ratio.

[0363] The structure shown in the present disclosure and the preparation process thereof are only an example of illustration. In the example embodiment, the corresponding structure can be changed, and the number of patterning processes can be increased or reduced, which is not limited in the present disclosure.

[0364] In the example embodiment, the display substrate of the present disclosure can be applied to a display device with a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light-emitting diode display (Micro LED or Mini LED), or a quantum dot light-emitting diode display (QDLED), which is not limited in the present disclosure.

[0365] The exemplary embodiments of the present disclosure also provide a preparation method of a display substrate for preparing the aforementioned display substrate. In the exemplary embodiments, the display substrate comprises a plurality of repeating units, at least one repeating unit comprises a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; and the preparation method comprises:

[0366] forming a pixel driving circuit in at least one sub-pixel, the pixel driving circuit being connected with a first power supply line configured to provide a first power supply signal to the pixel driving circuit; the pixel driving circuit at least comprising a driving transistor and a power supply connection electrode, the driving transistor at least comprising a driving active layer; in at least one sub-pixel, a first end of the power supply connection electrode is connected with the first power supply line through a power supply via, and a second end of the power supply connection electrode is connected with a first region of the driving active layer through an active via; two adjacent sub-pixels in two adjacent repeating units in the pixel row direction share the power supply via, and two adjacent sub-pixels in two adjacent repeating units in the pixel column direction share the power supply via.

[0367] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiments. The display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0368] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above-mentioned embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions and omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two rows of pixels and at least two columns of pixels, at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit being connected with a first power line, the first power line being configured to provide a first power signal to the pixel driving circuit; The pixel driving circuit comprises at least a driving transistor and a power supply connection electrode, and the driving transistor comprises at least a driving active layer. In at least one of the sub-pixels, a first end of the power supply connection electrode is connected to the first power supply line through a power supply via, and a second end of the power supply connection electrode is connected to the first region of the driving active layer through an active via; adjacent two sub-pixels in adjacent two repeating units in the pixel row direction share the power supply via, or / and adjacent two sub-pixels in adjacent two repeating units in the pixel column direction share the power supply via. 2.The display substrate of claim 1, wherein, The first regions of the driving active layers of adjacent two sub-pixels in adjacent two repeating units in the pixel column direction are connected to each other. 3.The display substrate of claim 2, wherein, The driving active layers of adjacent two sub-pixels in adjacent two repeating units in the pixel column direction are an integrated structure connected to each other, the driving active layer of the integrated structure has a groove, and the openings of adjacent grooves in at least one repeating unit are oppositely arranged; the groove has a groove width and a groove depth, the groove width is smaller than the groove depth, the groove width is the size in the pixel column direction, and the groove depth is the size in the pixel row direction. 4.The display substrate of claim 1, wherein, The first ends of the power supply connection electrodes of adjacent two sub-pixels in adjacent two repeating units in the pixel row direction are connected to each other, and adjacent two sub-pixels in adjacent two repeating units in the pixel column direction share the power supply connection electrode. 5.The display substrate of claim 4, wherein, The power supply connection electrodes of adjacent two sub-pixels in adjacent two repeating units in the pixel row direction are an integrated structure connected to each other. 6.The display substrate of claim 2, wherein, The pixel driving circuit further comprises an active connection electrode, a first end of the active connection electrode is connected to the first region of the driving active layer, and the power supply connection electrode is connected to the second end of the active connection electrode and the first power supply line through a switching via; the switching via comprises a shallow via and a deep via, the shallow via is an active via exposing the second end of the active connection electrode, and the deep via is a power supply via exposing the first power supply line. 7.The display substrate of claim 6, wherein, The active connection electrode and the driving active layer are an integrated structure connected to each other. 8.The display substrate of claim 6, wherein, Adjacent two sub-pixels in adjacent two repeating units in the pixel row direction share the switching via, and adjacent two sub-pixels in adjacent two repeating units in the pixel column direction share the switching via. 9.The display substrate of claim 6, wherein, Adjacent sub-pixels in adjacent repeating units in the pixel row direction and the pixel column direction share the switching via. 10.The display substrate of claim 6, wherein, The second ends of the active connection electrodes of adjacent two sub-pixels in adjacent two repeating units in the pixel row direction are connected to each other, and adjacent two sub-pixels in adjacent two repeating units in the pixel column direction share the active connection electrode. 11.The display substrate of claim 10, wherein, The active connection electrodes of adjacent two sub-pixels in adjacent two repeating units in the pixel row direction are an integrated structure connected to each other. 12.The display substrate of claim 6, wherein, The first regions of the second active layers of adjacent sub-pixels in adjacent repeating units in the pixel row direction and the pixel column direction are connected to each other through the active connection electrode. 13.The display substrate of claim 6, wherein, Adjacent sub-pixels in adjacent repeating units in the pixel row direction and the pixel column direction share the power supply connection electrode. 14.The display substrate of claim 1, wherein, The power supply connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel row direction are in an integrated structure connected to each other, and the power supply connection electrodes of two adjacent sub-pixels in two adjacent repeating units in the pixel column direction are in an integrated structure connected to each other. 15.The display substrate according to any one of claims 1 to 14, wherein The at least one repeating unit includes two first power supply lines, four data signal lines and one compensation signal line, the compensation signal line is located between adjacent pixel columns, and two first power supply lines are located on both sides of the repeating unit in the pixel row direction. Along the pixel row direction, the first first power supply line, the first data signal line, the second data signal line, the compensation signal line, the third data signal line, the fourth data signal line and the second first power supply line are sequentially arranged, and the driving transistor is arranged between the second data signal line and the compensation signal line or between the compensation signal line and the third data signal line. 16.The display substrate according to any one of claims 1 to 14, wherein In at least one sub-pixel, the pixel driving circuit further includes a first connection electrode, a second connection electrode and a storage capacitor, the storage capacitor at least includes a first plate, the first connection electrode and the second connection electrode are arranged on both sides of the first plate in the pixel column direction and are connected with the first plate respectively; in at least one sub-pixel, the width of the first connection electrode is smaller than the width of the second connection electrode, and the width is the size in the pixel row direction.

17. The display substrate according to any one of claims 1 to 14, wherein, In the direction perpendicular to the display substrate, the display substrate includes a second conductive layer, a semiconductor layer and a third conductive layer arranged on the substrate in sequence, the first power supply line is arranged in the second conductive layer, the driving active layer is arranged in the semiconductor layer, and the power supply connection electrode is arranged in the third conductive layer.

18. The display substrate according to any one of claims 1 to 14, wherein, The width of the driving active layer in the adjacent sub-pixels in the pixel row direction is different, and the width of the driving active layer in the adjacent sub-pixels in the pixel column direction is different, and the width is the minimum size of the driving active layer in the pixel column direction.

19. The display substrate of claim 18, wherein, In the pixel row direction, the first sub-pixel and the second sub-pixel are arranged alternately, and the width of the driving active layer in the first sub-pixel is greater than the width of the driving active layer in the second sub-pixel; or, in the pixel row direction, the third sub-pixel and the fourth sub-pixel are arranged alternately, and the width of the driving active layer in the third sub-pixel is smaller than the width of the driving active layer in the fourth sub-pixel.

20. The display substrate of claim 18, wherein, In the pixel column direction, the first sub-pixel and the third sub-pixel are arranged alternately, and the width of the driving active layer in the first sub-pixel is greater than the width of the driving active layer in the third sub-pixel; or, in the pixel column direction, the second sub-pixel and the fourth sub-pixel are arranged alternately, and the width of the driving active layer in the second sub-pixel is smaller than the width of the driving active layer in the fourth sub-pixel.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

22. A method for manufacturing a display substrate, the display substrate comprising a plurality of repeating units, at least one repeating unit comprising a plurality of sub-pixels forming at least two pixel rows and at least two pixel columns; the method comprising: A pixel driving circuit is formed in at least one sub-pixel, the pixel driving circuit is connected with a first power supply line, and the first power supply line is configured to provide a first power supply signal to the pixel driving circuit; The pixel driving circuit at least includes a driving transistor and a power supply connection electrode, and the driving transistor at least includes a driving active layer; In at least one sub-pixel, a first end of the power supply connection electrode is connected with the first power supply line through a power supply via, and a second end of the power supply connection electrode is connected with a first region of the driving active layer through an active via; adjacent two sub-pixels in adjacent two repeating units in the pixel row direction share the power supply via, and adjacent two sub-pixels in adjacent two repeating units in the pixel column direction share the power supply via.

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