Silicon wafer texturing method, textured silicon wafer, crystalline silicon cell and manufacturing method therefor

Abstract

A silicon wafer texturing method and a textured silicon wafer. The texturing method comprises: forming on a silicon wafer a pyramid textured surface; then carrying out rounding treatment to form a rounded textured surface; and then forming on the rounded textured surface pits to finish the texturing, wherein the rounding treatment comprises: successively performing first treatment and second treatment in a first mixed solution and a second mixed solution, the first mixed solution comprising HNO3 and HF, the mass fraction of HNO3 being greater than the mass fraction of HF, the second mixed solution comprising HNO3 and HF, and the mass fraction of HNO3 being less than the mass fraction of HF. With regard to the obtained pits, the number is 10 / cm2-100 / cm2, the width is 0.01 μm-0.08 μm, and the depth is 5 nm-50 nm.

Description

Silicon wafer texturing method, silicon wafer after texturing, crystalline silicon cell and preparation method thereof

[0001] Related applications

[0002] This application claims priority to the Chinese patent application filed on August 4, 2023, with application number 202310980080.0, and invention name “Method for texturing silicon wafers and silicon wafers after texturing, crystalline silicon cells and preparation methods thereof”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of solar cells, and in particular to a texturing method for silicon wafers, the texturized silicon wafers, crystalline silicon cells, and methods for preparing the same. Background Art

[0004] Texturing involves forming pyramidal structures on the surface of silicon wafers to reduce their reflectivity. Conventional texturing often produces a textured surface with sharp pyramidal tips. However, in this current textured surface, the passivation film deposition quality at the pyramidal tips and base differs from that at other locations, resulting in poorer deposition. This leads to higher recombination rates and defect state density in these areas, impacting solar cell quality. Therefore, optimization of the textured surface is necessary to improve the quality of the passivation film deposition and, consequently, the passivation effect.

[0005] Traditional velvet optimization techniques primarily involve treating the pyramidal velvet with a highly oxidizing acidic solution to achieve a rounded effect. The greater the degree of rounding, the better the deposition of the passivation film, and thus the better the passivation effect, which in turn increases the open-circuit voltage of the resulting battery. However, velvet rounding also increases the reflectivity of the silicon wafer, thereby reducing the battery's short-circuit current. Therefore, how to improve the passivation effect while maintaining a low reflectivity of the silicon wafer has become a key factor limiting the high performance of solar cells.

[0006] Summary of the Invention

[0007] According to various embodiments of the present application, a method for texturing a silicon wafer, a silicon wafer after texturing, a crystalline silicon cell, and a method for preparing the same are provided.

[0008] A method for texturing a silicon wafer comprises the following steps:

[0009] Forming a pyramid velvet surface on a silicon wafer;

[0010] The pyramid velvet surface is subjected to a rounding treatment to form a rounded velvet surface, comprising: placing a silicon wafer with the pyramid velvet surface in a first mixed solution for a first treatment, and then placing the silicon wafer in a second mixed solution for a second treatment, wherein the first treatment and the second treatment constitute a cycle, and the cycle is performed at least twice, wherein the first mixed solution and the second mixed solution both comprise HNO3 and HF, the mass fraction of HNO3 in the first mixed solution is greater than the mass fraction of HF, the mass fraction of HNO3 in the second mixed solution is less than the mass fraction of HF, and the time of the first treatment is greater than the time of the second treatment;

[0011] Form pits on the rounded pile surface to complete the pile making, wherein the number of the pits is 10 / cm 2 -100 pieces / cm 2 The width of the pit is 0.01 μm-0.08 μm, and the depth is 5 nm-50 nm.

[0012] In one embodiment, the number of cycles is 5 to 20 times.

[0013] In one embodiment, the first treatment step lasts for 15s-20s;

[0014] And / or, in the step of the second treatment, the time is 5s-10s.

[0015] In one embodiment, the concentration of HNO3 in the first mixed solution is 40wt%-80wt%, and the concentration of HF is 10wt%-20wt%;

[0016] And / or, the concentration of HNO 3 in the second mixed solution is 10 wt %-20 wt %, and the concentration of HF is 40 wt %-80 wt %.

[0017] In one embodiment, pits are formed on the rounded suede surface by metal etching.

[0018] In one embodiment, the rounded suede surface is treated for a third time and a fourth time with a third mixed solution and a fourth mixed solution, respectively, wherein the third mixed solution includes copper ions and HF, and the concentration of the copper ions is 1wt%-5wt%, the concentration of the HF is 40wt%-60wt%, and the time of the third treatment is 100s-200s; the fourth mixed solution includes HCl and H2O2, and the concentration of the HCl is 2wt%-10wt%, the concentration of the H2O2 is 5wt%-20wt%, and the time of the fourth treatment is 50s-200s.

[0019] In one embodiment, the size of the base of a single pyramid velvet surface is 1 μm-2.5 μm.

[0020] A texturized silicon wafer obtained by adopting the texturizing method for a silicon wafer.

[0021] A method for preparing a crystalline silicon cell comprises adopting the aforementioned silicon wafer texturing method.

[0022] A crystalline silicon cell obtained by adopting the preparation method of the crystalline silicon cell.

[0023] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0025] FIG1 is a schematic diagram of a pyramid velvet surface after velveting according to one or more embodiments of the present application;

[0026] FIG2 is a schematic diagram of a rounded suede surface;

[0027] FIG3 is a schematic diagram showing the principle of forming pits by metal etching on a rounded velvet surface;

[0028] FIG4 is a schematic diagram of a rounded suede surface with pits. DETAILED DESCRIPTION

[0029] To facilitate understanding of the present application, the present application will be described in more detail below. However, it should be understood that the present application can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments or embodiments and are not intended to limit the present application. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0031] The present application provides a method for texturing a silicon wafer, comprising the following steps:

[0032] S1, forming a pyramid velvet surface on a silicon wafer;

[0033] S2, rounding the pyramid velvet surface to form a rounded velvet surface, comprising: placing a silicon wafer with the pyramid velvet surface in a first mixed solution for a first treatment, and then placing the silicon wafer in a second mixed solution for a second treatment, wherein the first treatment and the second treatment constitute one cycle, and the cycle is performed at least twice, wherein the first mixed solution and the second mixed solution both comprise HNO3 and HF, the mass fraction of HNO3 in the first mixed solution is greater than the mass fraction of HF, the mass fraction of HNO3 in the second mixed solution is less than the mass fraction of HF, and the time of the first treatment is greater than the time of the second treatment;

[0034] S3, forming pits on the rounded pile surface to complete the pile making, wherein the number of the pits is 10 / cm 2 -100 pieces / cm 2 The width of the pit is 0.01 μm-0.08 μm, and the depth is 5 nm-50 nm.

[0035] In step S1 , the steps of forming the pyramid velvet surface on the silicon wafer are not limited. Preferably, the steps include: first performing a pre-cleaning process, and then performing a velvet process to obtain the pyramid velvet surface.

[0036] Optionally, during the pre-cleaning step, a pre-cleaning solution is prepared using NaOH and H2O2 to remove oil stains and cutting marks from the silicon wafer surface. The concentration of NaOH in the pre-cleaning solution is preferably 0.05wt%-0.2wt%, and the concentration of H2O2 is preferably 1wt%-5wt%. The pre-cleaning time is preferably 50s-150s, and the temperature is preferably 60°C-65°C. After the pre-cleaning step, deionized water can be used for rinsing, preferably for 50s-100s.

[0037] In the texturing treatment step, an alkaline texturing solution is prepared using NaOH and a texturing additive, and the silicon wafer is etched in the alkaline texturing solution to form a pyramid texturing surface. Among them, in the formed pyramid texturing surface, the size of the bottom edge of a single pyramid texturing surface is 1μm-2.5μm, specifically, the size of the diagonal line of the bottom edge of a single pyramid texturing surface. Such a setting is conducive to forming the pits described in this application on the rounded texturing surface after rounding treatment.

[0038] Optionally, the concentration of NaOH in the alkaline texturing solution is preferably 0.5wt%-5wt%, the concentration of the texturing additive is preferably 0.3wt%-1wt%, the texturing time is preferably 200s-300s, and the temperature is preferably 65°C-75°C, so as to form a pyramid velvet surface of the above-mentioned size; after texturing, it is preferably washed with deionized water for preferably 50s-100s. A schematic diagram of the pyramid velvet surface after texturing is shown in Figure 1.

[0039] During the rounding process, HNO3 oxidizes the sharp areas of the velvet surface, forming silicon oxide, while HF removes the oxidized silicon oxide. These two processes have distinct roles: one oxidizes, the other removes, thereby flattening the sharp areas. If the silicon oxide formed by HNO3 oxidation isn't promptly and effectively removed, it will block the subsequent HNO3 reaction with the inner silicon layer, significantly affecting the degree of rounding. Therefore, striking a balance between silicon oxide formation and removal is key to achieving optimal rounding results.

[0040] To this end, in step S2 of the present application, a first mixed solution consisting of a high concentration of HNO3 and a low concentration of HF is first treated, and then a second mixed solution of a low concentration of HNO3 and a high concentration of HF is used for a second treatment. This is used as a cycle, and multiple cycles are performed to round the velvet surface. At the same time, the time distribution relationship between the first treatment and the second treatment in each cycle is controlled, so that the formation and removal of silicon oxide can be balanced, thereby achieving the purpose of uniform and rapid rounding of the entire area of ​​the pyramid velvet surface. The schematic diagram of the rounded velvet surface is shown in Figure 2.

[0041] Optionally, HNO in the first mixed solution Concentration is preferably 40wt%-80wt%, and the concentration of HF is preferably 10wt%-20wt%, and / or, HNO in the second mixed solution Concentration is preferably 10wt%-20wt%, and the concentration of HF is preferably 40wt%-80wt%; The time of processing for the first time is preferably 15s-20s, and / or, the time of processing for the second time is preferably 5s-10s, and the cycle number is preferably 5-20 time, thereby can further realize the effect of full-area uniform rounding and rapid rounding in the rounding process. In other words, with the first mixed solution and the second mixed solution of specific ratio, the pyramid suede face is carried out cyclic treatment, and the time allocation relationship when adopting two kinds of mixed solutions to process in each cyclic process is controlled, can reach the purpose of pyramid suede face full-area uniform rounding and rapid rounding.

[0042] Optionally, during each cycle, the first treatment time may be the same or different, and the second treatment time may be the same or different. For example, during each cycle, the first treatment time and the second treatment time are kept the same; or, during each cycle, the first treatment time and the second treatment time are gradually reduced as the number of cycles increases, thereby avoiding excessive rounding and increasing reflectivity; or, during each cycle, the first treatment time and the second treatment time are gradually increased as the number of cycles increases.

[0043] Then, in step S3, 10 pieces / cm 2 -100 pieces / cm 2 The pits, with a width of 0.01 μm to 0.08 μm and a depth of 5 nm to 50 nm, do not affect the deposition of the passivation film, but can also increase the specific surface area of ​​the textured surface, keeping the reflectivity below 5%. Therefore, in the preparation method of crystalline silicon cells, the use of the texturing method of the present invention can effectively improve the conversion efficiency of crystalline silicon cells.

[0044] Preferably, the number of pits is 40 / cm 2 -80 pieces / cm 2 , which is conducive to obtaining a suede surface with better reflectivity and passivation effect, effectively improving the conversion efficiency of crystalline silicon cells.

[0045] In step S3, the method of forming the pits on the rounded velvet surface is not particularly limited. Preferably, the pits are formed on the rounded velvet surface by metal etching. The steps include:

[0046] The rounded velvet surface is treated for a third time and a fourth time using a third mixed solution and a fourth mixed solution, respectively, wherein the third mixed solution includes copper ions and HF, and the concentration of the copper ions is 1wt%-5wt%, the concentration of the HF is 40wt%-60wt%, and the third treatment time is 100s-200s; the fourth mixed solution includes HCl and H2O2, and the concentration of the HCl is 2wt%-10wt%, the concentration of the H2O2 is 5wt%-20wt%, and the fourth treatment time is 50s-200s. In the third mixed solution, the copper ions are derived from at least one of copper chloride or copper nitrate.

[0047] The main principle is shown in Figure 3. Specifically, during the third treatment, the Cu 2+ Reacts with Si to form copper particles to form copper cores, and the electrode potential of Cu is greater than that of silicon. 2+ It will continuously react with Si on the rounded velvet surface to generate copper particles, and silicon will undergo oxidation reaction to generate silicon oxide, so that the copper particles will aggregate and grow, and form a thicker layer of silicon oxide aggregates underneath; then the HF in the solution will react with the silicon oxide aggregates to generate SiF6 2- After the silicon oxide aggregates are removed, pits are formed below. Finally, a fourth mixed solution of HCl and H2O2 is used for the fourth treatment to remove the copper particles aggregated above, thereby forming pits on the rounded suede surface. The rounded suede surface with pits is shown in Figure 4.

[0048] The present application also provides a texturized silicon wafer, which is obtained by using the texturizing method for the silicon wafer.

[0049] The present application also provides a method for preparing a crystalline silicon cell. In the preparation method, the texturing process adopts the texturing method of the silicon wafer described in the present application, and then the texturized silicon wafer is diffused, cleaned, coated, printed and sintered to prepare the crystalline silicon cell.

[0050] The present application also provides a crystalline silicon cell, which is obtained using the crystalline silicon cell preparation method. The crystalline silicon cell can be a TOPCon cell, a PERC cell, etc.

[0051] In the preparation method of crystalline silicon cells, the texturing method of the present application is used to improve the passivation effect while maintaining the low reflectivity of the silicon wafer, thereby improving the open circuit voltage and short circuit current of the cell, thereby effectively improving the conversion efficiency of the crystalline silicon cell.

[0052] Hereinafter, the silicon wafer texturing method, silicon wafer, crystalline silicon cell and their preparation methods will be further described through the following specific examples.

[0053] Example 1

[0054] A pre-cleaning solution was prepared using NaOH and H2O2, with the concentration of NaOH being 0.1wt% and the concentration of H2O2 being 3wt%. The silicon wafer was placed in the pre-cleaning solution at 65°C for 100s, and then cleaned with deionized water for 80s.

[0055] An alkaline texturing solution is prepared using NaOH and texturing additives. The concentration of NaOH in the alkaline texturing solution is 2wt%, and the concentration of the texturing additive is 0.5wt%. At 70°C, the pre-cleaned silicon wafer is placed in the alkaline texturing solution for 250s to form a pyramid texturing surface, and then the silicon wafer is cleaned with deionized water for 80s.

[0056] A first mixed solution and a second mixed solution were prepared using HNO3 and HF, respectively, wherein the concentration of HNO3 in the first mixed solution was 60wt%, and the concentration of HF was 15wt%, and the concentration of HNO3 in the second mixed solution was 15wt%, and the concentration of HF was 60wt%. The silicon wafer with a pyramid velvet surface was immersed in the first mixed solution for 15s and then immersed in the second mixed solution for 5s, and 10 cycles were performed in sequence to form a rounded velvet surface.

[0057] The third mixed solution is prepared by using CuCl2 and HF. 2+ The concentration of HF is 3wt%, the concentration of HF is 50wt%, and the rounded texture surface is etched and immersed in the third mixed solution for 150s, and pits with copper particles gathered on the rounded texture surface are formed by point-induced etching.

[0058] A fourth mixed solution is prepared using HCl and H2O2, wherein the concentration of HCl in the fourth mixed solution is 2wt%, and the concentration of H2O2 is 5wt%. The copper particles are aggregated and removed by soaking in the fourth mixed solution for 50s, leaving pits, thereby completing the texturing process.

[0059] After testing, the number of pits formed in this embodiment is 50 / cm 2 , the width of the pit is 0.05μm and the depth is 25nm.

[0060] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a solar cell structure.

[0061] The electrical performance results of the battery cell formed in this embodiment are shown in Table 1.

[0062] Example 2

[0063] The difference between Example 2 and Example 1 is that: HNO3 and HF are used to prepare a first mixed solution and a second mixed solution respectively, wherein the concentration of HNO3 in the first mixed solution is 80wt%, and the concentration of HF is 10wt%, and the concentration of HNO3 in the second mixed solution is 10wt%, and the concentration of HF is 80wt%; the silicon wafer with a pyramid velvet surface is immersed in the first mixed solution for 20s, and then immersed in the second mixed solution for 10s, and 15 cycles are performed in sequence to form a rounded velvet surface.

[0064] After testing, the number of pits on the rounded pile surface formed in this embodiment is 60 / cm 2 , the width of the pit is 0.06μm and the depth is 30nm.

[0065] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a solar cell structure.

[0066] The electrical performance results of the battery cell formed in this embodiment are shown in Table 1.

[0067] Example 3

[0068] The difference between Example 3 and Example 1 is that: CuCl2 and HF are used to prepare the third mixed solution, and the Cu 2+ The concentration of HF is 5wt%, the concentration of HF is 60wt%, and the rounded texture surface is etched and immersed in the third mixed solution for 200s, and pits with copper particles gathered on the rounded texture surface are formed by point-induced etching.

[0069] After testing, the number of pits on the rounded pile surface formed in this embodiment is 80 / cm 2 , the width of the pit is 0.07μm and the depth is 40nm.

[0070] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a solar cell structure.

[0071] The electrical performance results of the battery cell formed in this embodiment are shown in Table 1.

[0072] Comparative Example 1

[0073] A pre-cleaning solution was prepared using NaOH and H2O2, with the concentration of NaOH being 0.1wt% and the concentration of H2O2 being 3wt%. The silicon wafer was placed in the pre-cleaning solution at 65°C for 100s, and then cleaned with deionized water for 80s.

[0074] An alkaline texturing solution is prepared using NaOH and texturing additives. The concentration of NaOH in the alkaline texturing solution is 2wt%, and the concentration of the texturing additive is 0.5wt%. At 70°C, the pre-cleaned silicon wafer is placed in the alkaline texturing solution for 250s to form a pyramid texturing surface, and then the silicon wafer is cleaned with deionized water for 80s.

[0075] A first mixed solution and a second mixed solution were prepared using HNO3 and HF, respectively, wherein the concentration of HNO3 in the first mixed solution was 60wt%, and the concentration of HF was 15wt%, and the concentration of HNO3 in the second mixed solution was 15wt%, and the concentration of HF was 60wt%. The silicon wafer with a pyramid velvet surface was immersed in the first mixed solution for 15s and then immersed in the second mixed solution for 5s, and 10 cycles were performed in sequence to form a rounded velvet surface.

[0076] The silicon wafer with a rounded textured surface is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a cell structure.

[0077] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0078] Comparative Example 2

[0079] A pre-cleaning solution was prepared using NaOH and H2O2, with the concentration of NaOH being 0.1wt% and the concentration of H2O2 being 3wt%. The silicon wafer was placed in the pre-cleaning solution at 65°C for 100s, and then cleaned with deionized water for 80s.

[0080] An alkaline texturing solution is prepared using NaOH and texturing additives. The concentration of NaOH in the alkaline texturing solution is 2wt%, and the concentration of the texturing additive is 0.5wt%. At 70°C, the pre-cleaned silicon wafer is placed in the alkaline texturing solution for 250s to form a pyramid texturing surface, and then the silicon wafer is cleaned with deionized water for 80s.

[0081] The silicon wafer with pyramid velvet surface is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a cell structure.

[0082] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0083] Comparative Example 3

[0084] The difference between Comparative Example 3 and Example 1 is that: a mixed solution is prepared using HNO3 and HF, wherein the concentration of HNO3 in the mixed solution is 40wt%, and the concentration of HF is 40wt%; the silicon wafer with a pyramid velvet surface is immersed in the mixed solution for 200s to form a rounded velvet surface.

[0085] After testing, the number of pits on the rounded suede surface formed in this comparative example is 5 / cm 2 , the width of the pit is 0.01 μm and the depth is 2 nm.

[0086] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a solar cell structure.

[0087] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0088] Comparative Example 4

[0089] The difference between Comparative Example 4 and Example 1 is that the first mixed solution and the second mixed solution are respectively prepared using HNO3 and HF, wherein the concentration of HNO3 in the first mixed solution is 15wt%, and the concentration of HF is 60wt%, and the concentration of HNO3 in the second mixed solution is 60wt%, and the concentration of HF is 15wt%.

[0090] After testing, the number of pits on the rounded suede surface formed in this comparative example is 20 / cm 2 , the width of the pit is 0.02μm and the depth is 4nm.

[0091] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a solar cell structure.

[0092] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0093] Comparative Example 5

[0094] The difference between Comparative Example 5 and Example 1 is that the silicon wafer with the pyramid velvet surface is immersed in the first mixed solution for 5 seconds and then immersed in the second mixed solution for 15 seconds, and 10 cycles are performed in sequence to form a rounded velvet surface.

[0095] After testing, the number of pits on the rounded suede surface formed in this comparative example is 20 / cm 2 , the width of the pit is 0.1 μm and the depth is 10 nm.

[0096] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a solar cell structure.

[0097] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0098] Table 1

[0099] In Table 1: Uoc represents open circuit voltage; Isc represents short circuit current; FF represents fill factor; Eta represents battery conversion efficiency.

[0100] From Comparative Example 1 and Comparative Example 2 in Table 1, it can be seen that since Comparative Example 1 only rounded the pyramid velvet surface, the passivation effect is enhanced and the open circuit voltage is increased, but the rounding loses part of the reflectivity, resulting in a decrease in the short-circuit current, which shows that only rounding the pyramid velvet surface can only improve the passivation effect but cannot achieve low reflectivity, and the battery conversion efficiency of the battery cell is low.

[0101] It can be seen from Example 1 and Comparative Example 1 in Table 1 that, since Example 1 performs metal etching on the rounded velvet surface to form nano-scale pits, the specific surface area of ​​the rounded pyramid velvet surface is increased, thereby reducing the reflectivity of the rounded velvet surface from 11.2% to 3.29%, so that the prepared battery cell can take into account both high passivation effect and low reflection performance. Therefore, both the open circuit voltage and the short circuit current are improved, and the battery conversion efficiency of the battery cell is increased from 24.98% to 25.24%.

[0102] It can be seen from Example 1 and Comparative Example 3 in Table 1 that the suede surface is rounded once with a mixed solution of hydrofluoric acid and nitric acid, and the relationship between the concentrations of hydrofluoric acid and nitric acid is not restricted. As a result, silicon oxide cannot be well formed and removed during the rounding process, resulting in poor rounding effect and affecting the subsequent formation of pits on the rounded suede surface, thereby increasing the reflectivity of the battery and decreasing both the short-circuit current and the open-circuit voltage.

[0103] It can be seen from Example 1 and Comparative Example 4 in Table 1 that the nitric acid concentration in the first treatment is lower than the hydrofluoric acid concentration, and the nitric acid concentration in the second treatment is higher than the hydrofluoric acid concentration, resulting in incomplete removal of sharp areas, poor rounding effect, and decreased short-circuit current and open-circuit voltage.

[0104] It can be seen from Example 1 and Comparative Example 5 in Table 1 that the time of the first treatment is shorter than that of the second treatment, resulting in poor oxidation effect and thus poor rounding effect. The pits formed on the rounded velvet surface are also poor, and both the open circuit voltage and the short circuit current decrease.

[0105] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above-described embodiments merely illustrate several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that variations and improvements are possible within the scope of the present invention, as would be apparent to one skilled in the art. These variations and improvements fall within the scope of the present invention. Therefore, the scope of the present invention is governed by the appended claims.

Claims

1. A method for texturing a silicon wafer, characterized in that: The following steps are involved: Forming a pyramid velvet surface on a silicon wafer; The pyramid velvet surface is subjected to rounding treatment to form a rounded velvet surface, comprising: placing a silicon wafer with the pyramid velvet surface in a first mixed solution for a first treatment, and then placing the silicon wafer in a second mixed solution for a second treatment, wherein the first treatment and the second treatment constitute a cycle, and the cycle is performed at least twice, wherein the first mixed solution and the second mixed solution both comprise HNO3 and HF, the mass fraction of HNO3 in the first mixed solution is greater than the mass fraction of HF, the mass fraction of HNO3 in the second mixed solution is less than the mass fraction of HF, and the time of the first treatment is greater than the time of the second treatment; Form pits on the rounded pile surface to complete the pile making, wherein the number of the pits is 10 / cm 2 -100pcs / cm 2 The width of the pit is 0.01 μm-0.08 μm, and the depth is 5 nm-50 nm.

2. The method for texturing a silicon wafer according to claim 1, wherein: The number of cycles is 5 to 20 times.

3. The method for texturing a silicon wafer according to claim 1, wherein: In the step of the first treatment, the time is 15s-20s; And / or, in the step of the second treatment, the time is 5s-10s.

4. The method for texturing a silicon wafer according to claim 1, wherein: The concentration of HNO3 in the first mixed solution is 40wt%-80wt%, and the concentration of HF is 10wt%-20wt%; And / or, the concentration of HNO3 in the second mixed solution is 10wt%-20wt%, and the concentration of HF is 40wt%-80wt%.

5. The method for texturing a silicon wafer according to any one of claims 1 to 4, wherein: Pits are formed on the rounded suede surface by metal etching.

6. The method for texturing a silicon wafer according to claim 5, wherein: The step of forming pits on the rounded velvet surface by metal etching includes: sequentially treating the rounded velvet surface for a third time and a fourth time by a third mixed solution and a fourth mixed solution, wherein the third mixed solution includes copper ions and HF, and the concentration of the copper ions is 1wt%-5wt%, the concentration of the HF is 40wt%-60wt%, the time of the third treatment is 100s-200s, the fourth mixed solution includes HCl and H2O2, and the concentration of the HCl is 2wt%-10wt%, the concentration of the H2O2 is 5wt%-20wt%, and the time of the fourth treatment is 50s-200s.

7. The method for texturing a silicon wafer according to any one of claims 1 to 4, wherein: The size of the base of a single pyramid velvet surface is 1μm-2.5μm.

8. A texturized silicon wafer obtained by the texturizing method for a silicon wafer as described in any one of claims 1 to 7.

9. A method for preparing a crystalline silicon battery, characterized in that: The invention comprises a method for texturing a silicon wafer using the method as described in any one of claims 1 to 7.

10. A crystalline silicon cell obtained by the method for preparing a crystalline silicon cell according to claim 9.

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