Filter and preparation method therefor, and electronic device

Abstract

Provided in the present disclosure are a filter and a preparation method therefor, and an electronic device. The filter comprises a base substrate, which is provided with a conductive column, wherein a first structure layer is provided on a first surface of the base substrate, and a second structure layer, a first insulating layer, a lead layer, a second insulating layer and a pad layer are provided on a second surface of the base substrate. The first structure layer and the second structure layer each comprise a connecting electrode connected to the conductive column, and the second structure layer further comprises a capacitor structure; the lead layer comprises at least one lead, wherein the lead is connected to the capacitor structure; the pad layer comprises at least one pad, wherein the pad is connected to the lead; and the materials of the first insulating layer and the second insulating layer comprise an organic material. By means of providing a first insulating layer and a second insulating layer, which are made of an organic material, the present disclosure can improve the performance stability and reliability of a filter, thereby also improving the performance of the filter.

Description

Filter and preparation method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 9, 2023, with application number 202311001494.0 and invention name “Filter, preparation method thereof, and electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of semiconductor technology, and in particular to a filter, a manufacturing method thereof, and an electronic device. Background Art

[0003] As a crucial component in communication terminals, filters can resolve mutual interference during signal transmission and improve spectrum efficiency. With the advancement of mobile communication technology, mobile communication systems require filters that are compact, high-performance, and highly consistent. Integrated Passive Devices (IPDs), due to their superior performance as standalone passive components, are widely used in radio frequency (RF) front-end chips in wireless communication equipment.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] On the one hand, the present disclosure provides a filter, including a substrate, in which a conductive column is provided that passes through the substrate in the thickness direction, a first structural layer is provided on the first surface of the substrate, a second structural layer is provided on the second surface of the substrate, a first insulating layer is provided on the side of the second structural layer away from the substrate, a lead layer is provided on the side of the first insulating layer away from the substrate, a second insulating layer is provided on the side of the lead layer away from the substrate, and a pad layer is provided on the side of the second insulating layer away from the substrate, the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive column, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, and the pad layer includes at least one pad connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

[0007] In an exemplary embodiment, the capacitor structure includes a first electrode plate arranged on the second surface of the base substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the base substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the base substrate; the orthographic projection of the second electrode plate on the base substrate is within the range of the orthographic projection of the capacitor dielectric layer on the base substrate.

[0008] In an exemplary embodiment, the orthographic projection of the capacitor dielectric layer on the base substrate is located within the range of the orthographic projection of the first electrode plate on the base substrate.

[0009] In an exemplary embodiment, areas of the first electrode plate, the capacitor dielectric layer, and the second electrode plate decrease in sequence in a direction away from the base substrate.

[0010] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, a first distance exists between an edge of the first electrode plate and an edge of the capacitor dielectric layer, and the first distance is greater than or equal to 50 nm.

[0011] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, a second distance exists between an edge of the capacitor dielectric layer and an edge of the second electrode plate, and the second distance is greater than or equal to 50 nm.

[0012] In an exemplary embodiment, the first electrode includes a seed layer arranged on the second surface of the substrate and a conductive layer arranged on a side of the seed layer away from the substrate; the connecting electrode in the second structural layer includes a seed layer arranged on the second surface of the substrate and a conductive layer arranged on a side of the seed layer away from the substrate.

[0013] In an exemplary embodiment, the seed layer includes a double-layer structure of a titanium layer and a copper layer, and the thickness of the titanium layer is 10 nm to 200 nm.

[0014] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are provided in the same layer and are formed simultaneously through the same patterning process.

[0015] In an exemplary embodiment, the orthographic projection of the connection electrode in the second structure layer on the base substrate is located within the range of the orthographic projection of the capacitor dielectric layer on the base substrate.

[0016] In an exemplary embodiment, the first electrode includes a seed layer arranged on the second surface of the substrate, a conductive layer arranged on a side of the seed layer away from the substrate, and a conductive protective layer arranged on a side of the conductive layer away from the substrate; the connecting electrode in the second structural layer includes a seed layer arranged on the second surface of the substrate, a conductive layer arranged on a side of the seed layer away from the substrate, and a conductive protective layer arranged on a side of the conductive layer away from the substrate.

[0017] In an exemplary embodiment, the seed layer includes a double-layer structure of a titanium layer and a copper layer, the conductive protection layer includes titanium, and the thickness of the titanium layer is 10 nm to 200 nm.

[0018] In an exemplary embodiment, the first electrode plate and the connecting electrode are disposed in the same layer and are simultaneously formed by a same damascene process.

[0019] In an exemplary embodiment, the first electrode plate and the connecting electrode are formed separately through different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connecting electrode.

[0020] In an exemplary embodiment, the second electrode plate adopts a stacked structure of titanium layer / copper layer / titanium layer, or a stacked structure of titanium layer / aluminum layer / titanium layer, wherein the thickness of the titanium layer is 30nm to 50nm, and the thickness of the copper layer or the aluminum layer is 200nm to 400nm.

[0021] In an exemplary embodiment, the connection electrode in the first structural layer includes a seed layer and a conductive layer arranged on a side of the seed layer away from the substrate, the seed layer includes a double-layer structure of a titanium layer and a copper layer, and the thickness of the titanium layer is 10nm to 200nm.

[0022] In an exemplary embodiment, the first structure layer further includes a protection layer disposed on a side of the connection electrode away from the base substrate. The material of the protection layer includes an organic material, and the thickness of the protection layer is 1 μm to 10 μm.

[0023] In an exemplary embodiment, a cross-sectional shape of the conductive pillar in a direction perpendicular to the base substrate includes a pillar shape, a cone shape, or an hourglass shape.

[0024] On the other hand, the present disclosure also provides an electronic device including the aforementioned filter.

[0025] In another aspect, the present disclosure further provides a method for preparing a filter, comprising:

[0026] forming a metallized through-hole substrate, wherein the substrate is provided with a conductive column penetrating the substrate in a thickness direction;

[0027] A first structural layer is formed on one side of the first surface of the base substrate, a second structural layer is formed on one side of the second surface of the base substrate, a first insulating layer is arranged on a side of the second structural layer away from the base substrate, a lead layer is arranged on a side of the first insulating layer away from the base substrate, a second insulating layer is arranged on a side of the lead layer away from the base substrate, and a pad layer is arranged on a side of the second insulating layer away from the base substrate, the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead, the lead is connected to the capacitor structure, the pad layer includes at least one pad, the pad is connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

[0028] In an exemplary embodiment, the capacitor structure includes a first electrode plate arranged on the second surface of the base substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the base substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the base substrate; the orthographic projection of the second electrode plate on the base substrate is within the range of the orthographic projection of the capacitor dielectric layer on the base substrate, and the orthographic projection of the capacitor dielectric layer on the base substrate is within the range of the orthographic projection of the first electrode plate on the base substrate.

[0029] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are provided in the same layer and are formed simultaneously through the same patterning process.

[0030] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structural layer are provided in the same layer and are formed simultaneously through the same damascene process.

[0031] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are formed by different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connecting electrode in the second structure layer.

[0032] In an exemplary embodiment, the capacitor dielectric layer and the second electrode plate are respectively formed by a patterning process including a dry etching process.

[0033] In another aspect, the present disclosure further provides a method for preparing a filter, comprising:

[0034] forming a metallized blind hole substrate, wherein the substrate substrate is provided with a conductive column that does not penetrate the substrate substrate in a thickness direction;

[0035] forming a second structure layer on one side of the second surface of the base substrate, a first insulating layer arranged on a side of the second structure layer away from the base substrate, a lead layer arranged on a side of the first insulating layer away from the base substrate, a second insulating layer arranged on a side of the lead layer away from the base substrate, and a pad layer arranged on a side of the second insulating layer away from the base substrate;

[0036] Turning over the base substrate, and performing a thinning process on the first surface of the base substrate until the conductive pillars are exposed, wherein the first surface and the second surface are surfaces facing away from each other;

[0037] forming a first structural layer on one side of the first surface of the base substrate;

[0038] The first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead, the lead is connected to the capacitor structure, the pad layer includes at least one pad, and the pad is connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

[0039] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0041] FIG1 is a schematic structural diagram of a filter according to an exemplary embodiment of the present disclosure;

[0042] 2A and 2B are schematic diagrams of a metallized TGV substrate for forming a filter according to the present disclosure;

[0043] 3A and 3B are schematic diagrams of forming a first structural layer of a filter according to the present disclosure;

[0044] FIG4 is a schematic diagram of a filter according to the present disclosure after forming a second conductive layer;

[0045] FIG5 is a schematic diagram of a filter according to the present invention after a surface insulating layer is formed;

[0046] FIG6 is a schematic diagram of a filter after forming a second plate according to the present disclosure;

[0047] FIG7 is a schematic diagram of a filter according to the present disclosure after forming a first insulating layer;

[0048] FIG8 is a schematic diagram of a filter according to the present disclosure after forming a lead layer;

[0049] FIG9 is a schematic diagram of a filter according to the present disclosure after forming a second insulating layer;

[0050] FIG10 is a schematic structural diagram of another filter according to an exemplary embodiment of the present disclosure;

[0051] FIG11 is a schematic cross-sectional view of a capacitor structure according to an exemplary embodiment of the present disclosure;

[0052] 12A to 12E are schematic diagrams showing another filter according to the present disclosure, wherein a first structural layer and a second conductive layer are formed;

[0053] FIG13 is a schematic diagram of another filter according to the present disclosure after forming a capacitor dielectric layer;

[0054] FIG14 is a schematic diagram of another filter after forming a second plate according to the present disclosure;

[0055] FIG15 is a schematic diagram of a planar structure of a capacitor structure according to an exemplary embodiment of the present disclosure;

[0056] FIG16 is a schematic structural diagram of another filter according to an exemplary embodiment of the present disclosure;

[0057] 17A and 17B are schematic diagrams of a metallized BGV substrate for forming another filter according to the present disclosure;

[0058] 18A to 18D are schematic diagrams showing a second conductive layer formed in another filter according to the present disclosure;

[0059] FIG19 is a schematic diagram of another filter according to the present disclosure after forming a capacitor dielectric layer;

[0060] FIG20 is a schematic diagram of another filter after forming a second plate according to the present disclosure;

[0061] FIG21 is a schematic diagram of another filter after forming a pad layer according to the present disclosure;

[0062] 22A and 22B are schematic diagrams of another filter after forming the first conductive layer according to the present disclosure;

[0063] FIG23 is a schematic structural diagram of yet another filter according to an exemplary embodiment of the present disclosure.

[0064] Explanation of the accompanying drawings: 10—base substrate; 11—protective layer; 12—surface insulating layer; 31—first conductive column; 32—second conductive column; 41—first connecting electrode; 42—second connecting electrode; 43—third connecting electrode; 44—fourth connecting electrode; 45—fifth connecting electrode; 51—first electrode plate; 52—second electrode plate; 53—capacitor dielectric layer; 61—first insulating layer; 62—second insulating layer; 71—first lead; 72—second lead; 73—third lead; 81—first soldering pad; 82—second soldering pad; 83—third soldering pad; 91—first through hole; 92—second through hole; 93—first blind hole; 94—second blind hole; 100—first structural layer; 200—second structural layer. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0066] The scales of the figures in this disclosure are intended to serve as a reference for actual processes, but are not intended to be limiting. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted based on actual needs. The figures described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0067] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0068] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0069] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0070] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0071] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0072] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0073] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0074] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0075] With the development of 5G technology, the number of 5G frequency bands continues to increase, and the RF front-end is facing growing demand. In the 5G RF front-end, filtering devices are one of the core components, and each 5G mobile phone contains at least 50 filters. In order to meet the requirements of miniaturization, high integration, high frequency bandwidth and low cost, through glass via (TGV) technology has gradually become a feasible technology for the design of passive filters (LC filters). Through glass via TGV technology refers to making a through hole on a glass substrate and filling the through hole with metal material to electrically connect the functional structure on the upper surface of the glass substrate and the functional structure on the lower surface of the glass substrate. Because glass materials have advantages such as good high-frequency characteristics, good insulation, low loss, and excellent Q value of glass-core 3D inductors, compared with silicon (Si)-based IPDs, TGV-based IPDs can avoid the problem of high microwave loss of devices caused by poor silicon-based insulation. Compared with low-temperature co-fired ceramic (LTCC) and high-resistance silicon (HRSi)-based IPD filters, TGV-based IPDs have the characteristics of compact size, low insertion loss, good high-frequency performance and easy packaging. They can achieve better electrical performance and can play an important role in 5G NR and WiFi 6.

[0076] The present disclosure provides a passive filter, comprising a substrate, wherein the substrate is provided with a conductive column that passes through the substrate in a thickness direction, a first structural layer is provided on a first surface of the substrate, a second structural layer is provided on a second surface of the substrate, a first insulating layer is provided on a side of the second structural layer away from the substrate, a lead layer is provided on a side of the first insulating layer away from the substrate, a second insulating layer is provided on a side of the lead layer away from the substrate, and a pad layer is provided on a side of the second insulating layer away from the substrate, wherein the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive column, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, and the pad layer includes at least one pad connected to the lead; the material of the first insulating layer and the second insulating layer includes an organic material.

[0077] In an exemplary embodiment, the thickness of the first insulating layer and the second insulating layer may be approximately 1 μm to 10 μm.

[0078] In an exemplary embodiment, the capacitor structure includes a first electrode plate arranged on the second surface of the base substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the base substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the base substrate; the orthographic projection of the second electrode plate on the base substrate is within the range of the orthographic projection of the capacitor dielectric layer on the base substrate, and the orthographic projection of the capacitor dielectric layer on the base substrate is within the range of the orthographic projection of the first electrode plate on the base substrate.

[0079] In an exemplary embodiment, areas of the first electrode plate, the capacitor dielectric layer, and the second electrode plate decrease in sequence in a direction away from the base substrate.

[0080] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, there is a first distance between an edge of the first electrode plate and an edge of the capacitor dielectric layer, and the first distance is greater than or equal to 50 nm.

[0081] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, a second distance exists between an edge of the capacitor dielectric layer and an edge of the second electrode plate, and the second distance is greater than or equal to 50 nm.

[0082] Figure 1 is a schematic diagram of the structure of a filter according to an exemplary embodiment of the present disclosure. As shown in Figure 1, the main structure of the filter according to the exemplary embodiment of the present disclosure may include a base substrate 10, a first structure layer 100, and a second structure layer 200. The first structure layer 100 may be disposed on one side of the first surface of the base substrate 10, and the second structure layer 200 may be disposed on one side of the second surface of the base substrate 10. The first surface and the second surface are two surfaces of the base substrate 10 that are opposite to each other.

[0083] In an exemplary embodiment, a plurality of conductive pillars are embedded in the base substrate 10 , and the plurality of conductive pillars penetrate the base substrate 10 in the thickness direction, so that corresponding electrodes in the first structure layer 100 and the second structure layer 200 can be connected to each other through the plurality of conductive pillars.

[0084] In an exemplary embodiment, the plurality of conductive pillars may include at least a first conductive pillar 31 and a second conductive pillar 32. The structures of the two conductive pillars may be substantially the same. In a plane parallel to the substrate, the conductive pillar may be circular or elliptical in shape, and in a plane perpendicular to the substrate, the cross-sectional shape of the conductive pillar may be an hourglass shape.

[0085] In an exemplary embodiment, the first structural layer 100 may include at least a first connecting electrode 41 and a second connecting electrode 42 arranged on the first surface of the base substrate 10, and a protective layer 11 arranged on the side of the first connecting electrode 41 and the second connecting electrode 42 away from the base substrate, the first connecting electrode 41 is connected to the first conductive column 31, the second connecting electrode 42 is connected to the second conductive column 32, and the material of the protective layer 11 includes an organic material.

[0086] In an exemplary embodiment, the second structure layer 200 may include at least a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, and a capacitor structure disposed on the second surface of the base substrate 10. The fourth connection electrode 44 is connected to the first conductive pillar 31, and the fifth connection electrode 45 is connected to the second conductive pillar 32. The capacitor structure may include a first electrode plate 51 disposed on the second surface of the base substrate 10, a surface insulating layer 12 disposed on a side of the first electrode plate 51 away from the base substrate, and a second electrode plate 52 disposed on a side of the surface insulating layer 12 away from the base substrate.

[0087] In an exemplary embodiment, the first connecting electrode 41, the second connecting electrode 42, the third connecting electrode 43, the fourth connecting electrode 44, and the fifth connecting electrode 45 are configured as a filter inductor coil routing to form a filter inductor with a three-dimensional spiral inductor structure. The first electrode plate 51 can serve as the lower electrode plate of the capacitor structure, and the second electrode plate 52 can serve as the upper electrode plate of the capacitor structure. The first electrode plate 51, the surface insulating layer 12, and the second electrode plate 52 form a filter capacitor with an MIM structure.

[0088] In an exemplary embodiment, the third connection electrode 43 , the fourth connection electrode 44 , the fifth connection electrode 45 and the first electrode plate 51 may be disposed in the same layer and simultaneously formed through the same patterning process.

[0089] In an exemplary embodiment, the filter may further include a first insulating layer 61 arranged on the side of the second structural layer 200 away from the base substrate, a lead layer arranged on the side of the first insulating layer 61 away from the base substrate, a second insulating layer 62 arranged on the side of the lead layer away from the base substrate, and a pad layer arranged on the side of the second insulating layer 62 away from the base substrate.

[0090] In an exemplary embodiment, the first insulating layer 61 may be provided with a first via, a second via, and a third via. The lead layer may include at least a first lead 71, a second lead 72, and a third lead 73. The first lead 71 is connected to the third connection electrode 43 via the first via, the second lead 72 is connected to the first electrode plate 51 via the second via, and the third lead 73 is connected to the second electrode plate 52 via the third via. The second insulating layer 62 may be provided with a fourth via, a fifth via, and a sixth via. The pad layer may include at least a first pad 81, a second pad 82, and a third pad 83. The first pad 81 is connected to the first lead 71 via the fourth via, the second pad 82 is connected to the second lead 72 via the fifth via, and the third pad 83 is connected to the third lead 73 via the sixth via.

[0091] In an exemplary embodiment, the material of the first insulating layer 61 and the second insulating layer 62 includes an organic material, and the thickness of the first insulating layer 61 and the second insulating layer 62 may be approximately 1 μm to 10 μm.

[0092] In an exemplary embodiment, the first connection electrode 41 and the second connection electrode 42 may include a stacked seed layer and a conductive layer, wherein the seed layer is disposed on the first surface of the base substrate, and the conductive layer is disposed on a side of the seed layer away from the base substrate. The third connection electrode 43, the fourth connection electrode 44, the fifth connection electrode 45, and the first electrode plate 51 may each include a stacked seed layer and a conductive layer, wherein the seed layer is disposed on the second surface of the base substrate, and the conductive layer is disposed on a side of the seed layer away from the base substrate.

[0093] In an exemplary embodiment, the seed layer includes a double-layer structure of a titanium layer and a copper layer, and the thickness of the titanium layer is 10 nm to 200 nm.

[0094] In an exemplary embodiment, the second electrode plate 52 may have a sandwich structure of Ti / Cu / Ti or a sandwich structure of Ti / Al / Ti.

[0095] The following is an illustrative explanation of the preparation process of the filter. The "patterning process" mentioned in the present disclosure includes depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, stripping the photoresist, and other processes for metal materials, inorganic materials or transparent conductive materials. For organic materials, it includes coating an organic material, mask exposure and development, and other processes. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be achieved by any one or more of spraying, spin coating and inkjet printing. Etching can be achieved by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the filter. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0096] In an exemplary embodiment, the preparation process of the filter of this embodiment may include the following steps.

[0097] (11) Forming a Metallized TGV Substrate. In an exemplary embodiment, forming a metallized TGV substrate may include:

[0098] (a1) A base substrate 10 is provided, and a plurality of through holes are formed on the base substrate by laser induced etching, sandblasting, laser ablation, or other processes. The plurality of through holes may include at least a first through hole 91 and a second through hole 92, as shown in FIG. 2A .

[0099] In an exemplary embodiment, the structures of the two through-holes may be substantially the same, both being through-hole structures penetrating the base substrate 10. The through-holes may be circular or elliptical in a plane parallel to the base substrate, and may have an hourglass cross-sectional shape in a plane perpendicular to the base substrate. The through-holes are configured to accommodate subsequently formed conductive pillars.

[0100] In an exemplary embodiment, the base substrate 10 may include a first surface and a second surface facing away from each other. In the following description, the lower surface of the base substrate 10 is the first surface, and the upper surface of the base substrate 10 is the second surface.

[0101] In an exemplary embodiment, the base substrate may be made of alkali-free glass, quartz glass, etc., and may have a thickness of about 0.2 mm to 0.3 mm, for example, about 0.25 mm.

[0102] In an exemplary embodiment, a diameter of each through-hole may be approximately 1 μm to 50 μm.

[0103] (a2) First, a deep-hole physical vapor deposition (PVD) process is used to form a continuous through-hole adhesion layer and a through-hole seed layer on the inner sidewalls of the plurality of through-holes. Then, a double-sided electroplating process is used to form a plurality of conductive pillars in the plurality of through-holes. The plurality of conductive pillars may include at least a first conductive pillar 31 filling the first through-hole 91 and a second conductive pillar 32 filling the second through-hole 92. Finally, a chemical mechanical polishing (CMP) process is used to remove the conductive material on the second surface and the first surface of the substrate 10, as shown in FIG2B .

[0104] In an exemplary embodiment, the structures of the two conductive pillars may be substantially the same, both being filling structures that penetrate the base substrate 10. In a plane parallel to the base substrate, the conductive pillars may be circular or elliptical in shape, and in a plane perpendicular to the base substrate, the cross-sectional shape of the conductive pillars may be hourglass-shaped. The through-holes are configured to accommodate subsequently formed conductive pillars.

[0105] In an exemplary embodiment, the material of the through-hole adhesion layer can be titanium (Ti), tantalum (Ta), titanium nitride (TiN) or tantalum nitride (TaN), or other metals or metal nitrides with high adhesion to glass, and the thickness of the through-hole adhesion layer can be approximately 30nm to 100nm.

[0106] In an exemplary embodiment, the via seed layer may be made of copper (Cu), the conductive pillars may be made of copper (Cu), and the thickness of the via seed layer may be approximately 30 nm to 100 nm.

[0107] (12) Forming a first structural layer. In an exemplary embodiment, forming the first structural layer may include:

[0108] (b1) A seed film is first deposited on one side of the first surface of the base substrate 10 using a PVD process, and then a conductive layer is formed on the seed film using a full-surface electroplating process. Subsequently, a first conductive layer is formed on the first surface of the base substrate 10 through a patterning process including photoresist coating, exposure, development, etching, and stripping. The first conductive layer may include at least a first connecting electrode 41 and a second connecting electrode 42, which serve as the routing for the filter inductor coil. The first connecting electrode 41 is connected to the first conductive pillar 31, and the second connecting electrode 42 is connected to the second conductive pillar 32, as shown in FIG3A .

[0109] In an exemplary embodiment, the seed layer can adopt a double-layer structure of Ti / Cu, the conductive layer can be made of Cu, the Ti layer contacts the substrate, and the Cu layer contacts the conductive layer. The Ti layer can effectively enhance the adhesion between Cu and the substrate.

[0110] In an exemplary embodiment, the thickness of the titanium layer may be approximately 10 nm to 200 nm. That is, the distance between the Cu layer in the first connection electrode 41 and the second connection electrode 42 and the Cu layer in the base substrate may be approximately 10 nm to 200 nm. For example, the thickness of the titanium layer may be approximately 100 nm to 150 nm. For another example, the thickness of the titanium layer may be approximately 133 nm.

[0111] In example embodiments, the seed layer may have a thickness of approximately 30 nm to 200 nm, and the conductive layer may have a thickness greater than 1 μm.

[0112] (b2) Forming a protective layer: A first protective film is spin-coated on one side of the first surface of the base substrate 10 by a spin coating process to form a protective layer 11 covering the first conductive layer, as shown in FIG3B .

[0113] In an exemplary embodiment, the protective layer 11 may be made of an insulating material such as polyimide (PI) or photoresist, and the thickness of the protective layer 11 may be approximately 1 μm to 10 μm.

[0114] In an exemplary embodiment, the dielectric constant of the material of the protection layer 11 may be approximately 3, and the dielectric loss may be approximately 0.001, which can effectively protect the first connection electrode 41 and prevent the connection electrode from being oxidized.

[0115] In an exemplary embodiment, the first conductive layer disposed on the first surface of the base substrate and the protective layer 11 disposed on a side of the first conductive layer away from the base substrate constitute a first structural layer.

[0116] (13) Forming a second conductive layer. In an exemplary embodiment, forming the second structural layer may include: first depositing a seed film on one side of the second surface of the base substrate 10 by a PVD process, and then forming a conductive layer on the seed film by a subtractive full-surface electroplating process. Subsequently, a second conductive layer is formed on the second surface of the base substrate 10 by a patterning process of coating a photoresist, exposing, developing, wet etching, and stripping. The second conductive layer may include at least a first electrode 51 and a third connecting electrode 43, a fourth connecting electrode 44, and a fifth connecting electrode 45 serving as a filter inductor coil wiring, wherein the fourth connecting electrode 44 is connected to the first conductive column 31, and the fifth connecting electrode 45 is connected to the second conductive column 32, as shown in FIG4 .

[0117] In an exemplary embodiment, the seed layer can adopt a double-layer structure of Ti / Cu, the conductive layer can be made of Cu, the Ti layer contacts the substrate, and the Cu layer contacts the conductive layer. The Ti layer can effectively enhance the adhesion between Cu and the substrate.

[0118] In an exemplary embodiment, the thickness of the titanium layer may be approximately 10 nm to 200 nm, ie, the distance between the Cu layer in the third, fourth, and fifth connection electrodes 43 , 44 , and 45 and the Cu layer in the base substrate may be approximately 10 nm to 200 nm.

[0119] In example embodiments, the seed layer may have a thickness of approximately 30 nm to 200 nm, and the conductive layer may have a thickness greater than 1 μm.

[0120] In an exemplary embodiment, the third connection electrode 43 , the fourth connection electrode 44 , the first conductive pillar 31 , the first connection electrode 41 , the second connection electrode 42 , the second conductive pillar 32 and the fifth connection electrode 45 may be sequentially connected to form a filter inductor of a three-dimensional spiral inductor structure.

[0121] In an exemplary embodiment, the first electrode plate 51 may serve as a lower electrode plate of the capacitor structure. The first electrode plate 51 may include a stacked seed layer (Ti / Cu) and a conductive layer (Cu).

[0122] (14) Forming a surface insulating layer. In an exemplary embodiment, forming the surface insulating layer may include: depositing a surface insulating layer 12 on one side of the second surface of the substrate 10 by a process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD), wherein the surface insulating layer 12 covers the third connecting electrode 43, the fourth connecting electrode 44, the fifth connecting electrode 45, and the first electrode 51. The surface insulating layer 12 covering the third connecting electrode 43, the fourth connecting electrode 44, and the fifth connecting electrode 45 serves as an insulating protection layer, and the surface insulating layer 12 covering the first electrode 51 serves as a capacitor dielectric layer of the capacitor structure, as shown in FIG5 .

[0123] In an exemplary embodiment, the material of the surface insulating layer 12 can be silicon nitride (SiNx), silicon oxide (SiO2) or aluminum oxide (Al2O3) and the thickness of the surface insulating layer 12 (as a capacitor dielectric layer) covering the first electrode 51 area can be 100nm to 200nm.

[0124] (15) Forming the Second Electrode. In an exemplary embodiment, forming the second electrode may include: depositing a second electrode conductive film, patterning the second electrode conductive film through a patterning process, and forming the second electrode 52 on the capacitor dielectric layer 53, as shown in FIG6 .

[0125] In an exemplary embodiment, the second electrode plate 52 may serve as an upper electrode plate of the capacitor structure, and the first electrode plate 51 , the capacitor dielectric layer 53 , and the second electrode plate 52 constitute a filter capacitor of an MIM structure.

[0126] In an exemplary embodiment, the second electrode plate 52 may have a sandwich structure of titanium layer / copper layer / titanium layer (Ti / Cu / Ti), or a sandwich structure of titanium layer / aluminum layer / titanium layer (Ti / Al / Ti). The thickness of the Ti layer may be approximately 30 nm to 50 nm, and the thickness of the Cu layer or the Al layer may be approximately 200 nm to 400 nm.

[0127] In an exemplary embodiment, the second conductive layer disposed on the second surface of the base substrate, the surface insulating layer disposed on the side of the second conductive layer away from the base substrate, and the second electrode disposed on the side of the surface insulating layer away from the base substrate constitute the second structural layer.

[0128] (16) Forming a first insulating layer. In an exemplary embodiment, forming the first insulating layer may include: spin-coating a first insulating film on one side of the second surface of the base substrate 10 by a spin coating process, patterning the first insulating film by a patterning process to form a first insulating layer 61 covering the third connecting electrode 43, the fourth connecting electrode 44, the fifth connecting electrode 45 and the capacitor structure, wherein a plurality of via holes are formed in the first insulating layer 61, as shown in FIG. 7 .

[0129] In an exemplary embodiment, the plurality of vias may include at least a first via K1, a second via K2, and a third via K3. The orthographic projection of the first via K1 on the substrate may be located within the orthographic projection of the third connection electrode 43 on the substrate. The first insulating film and the surface insulating layer 12 within the first via K1 are removed, exposing the surface of the third connection electrode 43. The orthographic projection of the second via K2 on the substrate may be located within the orthographic projection of the first electrode plate 51 on the substrate. The first insulating film and the surface insulating layer 12 within the second via K2 are removed, exposing the surface of the first electrode plate 51. The orthographic projection of the third via K3 on the substrate may be located within the orthographic projection of the second electrode plate 52 on the substrate. The first insulating film within the third via K3 is removed, exposing the surface of the second electrode plate 52.

[0130] In an exemplary embodiment, the first insulating layer 61 may be made of an insulating material such as polyimide, and the thickness of the first insulating layer 61 may be approximately 1 μm to 10 μm.

[0131] (17) Forming a lead layer. In an exemplary embodiment, forming a lead layer may include: first depositing a lead adhesive film and a lead seed film in sequence on the first insulating layer 61 through a PVD process, and patterning the lead adhesive film and the lead seed film through a patterning process. Subsequently, electroplating a lead material on the lead seed film through an additive plating process, and forming a lead layer on the first insulating layer 61 through a wet etching process. The lead layer may include at least a first lead 71, a second lead 72, and a third lead 73, wherein the first lead 71 is connected to the third connection electrode 43 through a first via K1, the second lead 72 is connected to the first electrode 51 through a second via K2, and the third lead 73 is connected to the second electrode 52 through a third via K3, as shown in FIG8 .

[0132] In an exemplary embodiment, the material of the wire adhesive layer may adopt Ti, the material of the wire seed layer may adopt Cu, and the material of the wire material may adopt Cu.

[0133] In an exemplary embodiment, the thickness of the first lead 71 , the second lead 72 , and the third lead 73 may be approximately 1 μm to 10 μm.

[0134] (18) Forming a second insulating layer. In an exemplary embodiment, forming the second insulating layer may include: spin-coating a second insulating film on one side of the second surface of the base substrate 10 by a spin coating process, patterning the second insulating film by a patterning process to form a second insulating layer 62 covering the first lead 71, the second lead 72, and the third lead 73, wherein a plurality of vias are formed in the second insulating layer 62, as shown in FIG9.

[0135] In an exemplary embodiment, the plurality of vias may include at least a fourth via K4, a fifth via K5, and a sixth via K6. The orthographic projection of the fourth via K4 on the substrate may be located within the orthographic projection of the first lead 71 on the substrate. The second insulating film within the fourth via K4 is removed, exposing the surface of the first lead 71. The orthographic projection of the fifth via K5 on the substrate may be located within the orthographic projection of the second lead 72 on the substrate. The second insulating film within the fifth via K5 is removed, exposing the surface of the second lead 72. The orthographic projection of the sixth via K6 on the substrate may be located within the orthographic projection of the third lead 73 on the substrate. The second insulating film within the sixth via K6 is removed, exposing the surface of the third lead 73.

[0136] In an exemplary embodiment, the second insulating layer 62 may be made of an insulating material such as polyimide, and the thickness of the second insulating layer 62 may be approximately 1 μm to 10 μm.

[0137] (19) Forming a pad layer. In an exemplary embodiment, forming the pad layer may include: first depositing a pad adhesion film and a pad seed film in sequence on the second insulating layer 62 by a PVD process, and patterning the pad adhesion film and the pad seed film by a patterning process. Subsequently, electroplating a pad material on the pad seed film by an electroplating process, and forming a pad layer on the second insulating layer 62 by an etching and thermal annealing (Reflow) process. The pad layer may include at least a first pad 81, a second pad 82, and a third pad 83, wherein the first pad 81 is connected to the first lead 71 through the fourth via K4, the second pad 82 is connected to the second lead 72 through the fifth via K5, and the third pad 83 is connected to the third lead 73 through the sixth via K6, as shown in FIG1 .

[0138] In an exemplary embodiment, on a plane parallel to the substrate, the cross-sectional shape of the first pad 81, the second pad 82, and the third pad 83 may be circular, elliptical, rectangular, polygonal, etc., and on a plane perpendicular to the substrate, the cross-sectional shape of the first pad 81, the second pad 82, and the third pad 83 may be semicircular, semi-elliptical, trapezoidal, etc. The first pad 81, the second pad 82, and the third pad 83 may be referred to as bumps.

[0139] In an exemplary embodiment, the pad adhesion film can be made of Ti, the pad seed film can be made of Cu, and the pad layer can have a Cu / Ni / SnAg stacked structure or a Cu / Ni / Sn stacked structure. The Ni layer can have a thickness of approximately 30 nm to 100 nm, the Cu layer can have a thickness of approximately 200 nm to 600 nm, and the tin-silver alloy (SnAg) layer or the tin (Sn) layer can have a thickness of approximately 200 nm to 500 nm. These layers not only have good scalability but also corrosion resistance. By providing the Ni layer as a barrier layer, the present disclosure can effectively prevent Sn from penetrating into the Cu layer.

[0140] At this point, the filter of this embodiment is completed. In an exemplary embodiment, the filter of this embodiment may include: a substrate substrate, a first structural layer arranged on one side of the first surface of the substrate substrate, and a second structural layer arranged on one side of the second surface of the substrate substrate. The first structural layer may include: a first connecting electrode and a second connecting electrode arranged on one side of the first surface of the substrate substrate, and a protective layer covering the first connecting electrode and the second connecting electrode. The second structural layer may include: a third connecting electrode, a fourth connecting electrode, a fifth connecting electrode and a capacitor structure arranged on one side of the second surface of the substrate substrate. The filter also includes a first insulating layer covering the third connecting electrode, the fourth connecting electrode, the fifth connecting electrode and the capacitor structure, a first lead, a second lead and a third lead arranged on the first insulating layer, a second insulating layer covering the first lead, the second lead and the third lead, and a first solder pad, a second solder pad and a third solder pad arranged on the second insulating layer.

[0141] In a filter, the first insulating layer and the second insulating layer are made of inorganic materials. Since the thickness of the first insulating layer and the second insulating layer is relatively thin, less than 300nm, on the one hand, it will cause large parasitic capacitance to form between the various conductive layers, seriously affecting the performance of the filter, and on the other hand, it will cause poor drilling and cause unstable device performance. Due to the thin thickness of the first insulating layer and the second insulating layer, the coverage of the edge position of the connecting electrode is not ideal, and even cracks may appear. In the subsequent wet etching process, the etching liquid will etch the connecting electrode at the crack, resulting in poor drilling. The first insulating layer and the second insulating layer of the filter disclosed in the present invention are made of thicker organic materials, which can not only effectively reduce the parasitic capacitance between the various conductive layers, but also effectively avoid poor drilling, thereby ensuring the performance stability and reliability of the filter and improving the performance of the filter.

[0142] The disclosed filter utilizes a glass substrate, which not only reduces filter losses but also production costs. The disclosed filter utilizes TGV technology to create a glass core TGV 3D spiral inductor, effectively increasing the inductance and Q value per unit area. This makes the filter structure more compact, reduces the filter size, and facilitates filter integration.

[0143] The filter disclosed herein uses a seed layer including a titanium layer and a copper layer. The titanium layer is in contact with the base substrate. The thickness of the titanium layer is 10nm to 200nm, which can not only effectively enhance the adhesion between the connecting electrode and the base substrate, but also ensure seamless overlap between the connecting electrode and the conductive column.

[0144] The preparation process disclosed herein can be realized using existing mature preparation equipment, with minor improvements to existing processes, and can be well compatible with existing preparation processes. The process is simple to realize, easy to implement, with high production efficiency, low production cost, and high yield rate.

[0145] Figure 10 is a schematic diagram of the structure of another filter according to an exemplary embodiment of the present disclosure. As shown in Figure 10, the main structure of the filter according to the exemplary embodiment of the present disclosure may include a base substrate 10, a first structure layer 100 disposed on one side of the first surface of the base substrate 10, and a second structure layer 200 disposed on one side of the second surface of the base substrate 10. The main structure of the base substrate 10 and the first structure layer 100 in this embodiment is substantially the same as that in the previous embodiment.

[0146] In an exemplary embodiment, the second structure layer 200 may include at least a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, and a capacitor structure disposed on the second surface of the base substrate 10. The fourth connection electrode 44 is connected to the first conductive pillar 31, and the fifth connection electrode 45 is connected to the second conductive pillar 32. The capacitor structure may include a first electrode plate 51 disposed on the second surface of the base substrate 10, a capacitor dielectric layer 53 disposed on a side of the first electrode plate 51 away from the base substrate, and a second electrode plate 52 disposed on a side of the capacitor dielectric layer 53 away from the base substrate.

[0147] In an exemplary embodiment, the first connecting electrode 41, the second connecting electrode 42, the third connecting electrode 43, the fourth connecting electrode 44, and the fifth connecting electrode 45 are configured as a filter inductor coil routing to form a filter inductor with a three-dimensional spiral inductor structure. The first electrode plate 51 can serve as the lower electrode plate of the capacitor structure, and the second electrode plate 52 can serve as the upper electrode plate of the capacitor structure. The first electrode plate 51, the capacitor dielectric layer 53, and the second electrode plate 52 form a filter capacitor with an MIM structure.

[0148] In an exemplary embodiment, the third connection electrode 43 , the fourth connection electrode 44 , the fifth connection electrode 45 and the first electrode plate 51 may be disposed in the same layer and simultaneously formed through the same damascene process.

[0149] In an exemplary embodiment, the filter may also include a first insulating layer 61 arranged on the side of the second structural layer 200 away from the substrate, a lead layer arranged on the side of the first insulating layer 61 away from the substrate, a second insulating layer 62 arranged on the side of the lead layer away from the substrate, and a pad layer arranged on the side of the second insulating layer 62 away from the substrate. The main structure of the first insulating layer 61, the lead layer, the second insulating layer 62 and the pad layer are basically the same as those in the aforementioned embodiments.

[0150] In an exemplary embodiment, the first and second connection electrodes 41 and 42 may include a stacked seed layer and a conductive layer, wherein the seed layer is disposed on the first surface of the base substrate and the conductive layer is disposed on a side of the seed layer away from the base substrate. The thickness of the conductive layer may be greater than 1 μm.

[0151] In an exemplary embodiment, the third connecting electrode 43, the fourth connecting electrode 44, the fifth connecting electrode 45 and the first electrode 51 may each include a stacked seed layer, a conductive layer and a conductive protective layer, the seed layer being arranged on the second surface of the base substrate, the conductive layer being arranged on a side of the seed layer away from the base substrate, and the conductive protective layer being arranged on a side of the conductive layer away from the base substrate, and the conductive protective layer being configured to prevent the conductive layer from diffusing into the capacitor dielectric layer and to increase the adhesion between the conductive layer and the capacitor dielectric layer.

[0152] In an exemplary embodiment, the seed layer includes a double-layer structure of a titanium layer and a copper layer, the thickness of the titanium layer is 10 nm to 200 nm, and the material of the conductive protection layer includes titanium.

[0153] In an exemplary embodiment, the second electrode plate 52 may have a sandwich structure of Ti / Cu / Ti or a sandwich structure of Ti / Al / Ti.

[0154] Figure 11 is a schematic cross-sectional view of a capacitor structure according to an exemplary embodiment of the present disclosure. As shown in Figure 11, both the capacitor dielectric layer 53 and the second electrode plate 52 are patterned using a dry etching process. The orthographic projection of the second electrode plate 52 on the substrate can be located within the orthographic projection of the capacitor dielectric layer 53 on the substrate, and the orthographic projection of the capacitor dielectric layer 53 on the substrate can be located within the orthographic projection of the first electrode plate 51 on the substrate.

[0155] In an exemplary embodiment, the areas of the first electrode plate 51 , the capacitor dielectric layer 53 , and the second electrode plate 52 decrease in sequence as they move away from the substrate.

[0156] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, a first distance d1 is present between an edge of the first electrode 51 and an edge of the capacitor dielectric layer 53 . The first distance d1 may be greater than or equal to 50 nm.

[0157] In an exemplary embodiment, on a plane parallel to the substrate, in at least one direction, a second distance d2 is present between an edge of the capacitor dielectric layer 53 and an edge of the second electrode 52 . The second distance d2 may be greater than or equal to 50 nm.

[0158] In an exemplary embodiment, the preparation process of the filter of this embodiment may include the following steps.

[0159] (21) A metallized TGV substrate is formed. The manufacturing process and the structure formed are basically the same as step (11) of the aforementioned embodiment.

[0160] (22) Forming a first structural layer and a second conductive layer. In an exemplary embodiment, forming the first structural layer and the second conductive layer may include:

[0161] (b1) A first photoresist layer is spin-coated on the first surface of the substrate 10, and a second photoresist layer is spin-coated on the second surface of the substrate 10. A first trace pattern is formed on the first photoresist layer, and a second trace pattern is formed on the second photoresist layer, through a patterning process including exposure and development. The first photoresist layer is removed from the location of the first trace pattern, exposing the first surface of the substrate 10. The second photoresist layer is removed from the location of the second trace pattern, exposing the second surface of the substrate 10, as shown in FIG12A.

[0162] In an exemplary embodiment, the material of the first photoresist layer and the second photoresist layer may be polyimide, and the thickness of the first photoresist layer and the second photoresist layer may be about 1 μm to 10 μm.

[0163] (b2) A seed film is first deposited on the first and second surfaces of the substrate 10 using a PVD process. The seed film at the location of the first wiring pattern is disposed on the first surface of the substrate 10, while the seed film in areas outside the first wiring pattern is disposed on the first photoresist layer. The seed film at the location of the second wiring pattern is disposed on the second surface of the substrate 10, while the seed film in areas outside the second wiring pattern is disposed on the second photoresist layer. Subsequently, a conductive layer is formed on the seed film on the first and second surfaces of the substrate 10 using an additive electroplating process. The conductive layer is higher than the photoresist layer. On the first surface of the substrate 10, the distance between the surface of the conductive layer away from the substrate and the first surface is greater than the distance between the surface of the first photoresist layer away from the substrate and the first surface. On the second surface of the substrate 10, the distance between the surface of the conductive layer away from the substrate and the second surface is greater than the distance between the surface of the second photoresist layer away from the substrate and the second surface, as shown in FIG12B.

[0164] In an exemplary embodiment, the seed layer can adopt a double-layer structure of Ti / Cu, the material of the conductive layer can be Cu, the Ti layer is in contact with the base substrate, the thickness of the titanium layer is 10nm to 200nm, the Cu layer is in contact with the conductive layer, and the Ti layer can effectively enhance the adhesion between Cu and the base substrate.

[0165] In exemplary embodiments, the seed layer may have a thickness of about 30 nm to 200 nm.

[0166] (b3) Using a CMP process, the first photoresist layer and the second photoresist layer are used as cutoff layers to completely remove the conductive layer and the seed film on the first photoresist layer and the second photoresist layer, respectively, thereby forming a first conductive layer on the first surface of the base substrate 10 and a transition conductive layer on the second surface of the base substrate 10. The first conductive layer may include at least a first connecting electrode 41 and a second connecting electrode 42, wherein the first connecting electrode 41 is connected to the first conductive pillar 31, and the second connecting electrode 42 is connected to the second conductive pillar 32, as shown in FIG12C .

[0167] In an exemplary embodiment, the first and second connection electrodes 41 and 42 may include a stacked seed layer (Ti / Cu) and a conductive layer (Cu), and the thickness of the conductive layer may be greater than 1 μm.

[0168] (b4) Forming a protective layer: A first protective film is spin-coated on one side of the first surface of the base substrate 10 by a spin coating process to form a protective layer 11 covering the first conductive layer, as shown in FIG12D .

[0169] In an exemplary embodiment, the protective layer 11 may be made of an insulating material such as polyimide (PI) or photoresist, and the thickness of the protective layer 11 may be approximately 1 μm to 10 μm.

[0170] In an exemplary embodiment, the dielectric constant of the material of the protection layer 11 may be approximately 3, and the dielectric loss may be approximately 0.001, which can effectively protect the first connection electrode 41 and prevent the connection electrode from being oxidized.

[0171] In an exemplary embodiment, the first conductive layer disposed on the first surface of the base substrate and the protective layer 11 disposed on a side of the first conductive layer away from the base substrate constitute a first structural layer.

[0172] (b5) Forming a second conductive layer. A protective conductive film is deposited on one side of the second surface of the base substrate 10 using a PVD process. The protective conductive film is patterned using a patterning process to form a conductive protective layer on the transition conductive layer. The conductive protective layer and the transition conductive layer together constitute a second conductive layer. The second conductive layer may include at least a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, and a first electrode plate 51. The fourth connecting electrode 44 is connected to the first conductive pillar 31, and the fifth connecting electrode 45 is connected to the second conductive pillar 32, as shown in FIG12E.

[0173] In an exemplary embodiment, the conductive protective layer may be made of Ti and may have a thickness of approximately 30 nm to 100 nm. In an exemplary embodiment, the conductive protective layer may prevent the conductive layer (Cu) from diffusing into a subsequently formed capacitor dielectric layer and may also enhance adhesion between the conductive layer (Cu) and the subsequently formed capacitor dielectric layer.

[0174] In an exemplary embodiment, the third connecting electrode 43, the fourth connecting electrode 44 and the fifth connecting electrode 45 are configured as filter inductor coil lines, and can each include a stacked seed layer (Ti / Cu), a conductive layer (Cu) and a conductive protective layer (Ti), and the thickness of the conductive layer can be greater than 1 μm.

[0175] In an exemplary embodiment, the first electrode 51 can serve as the lower electrode of the capacitor structure. The first electrode 51 can include a stacked seed layer (Ti / Cu), a conductive layer (Cu) and a conductive protection layer (Ti). The thickness of the conductive layer can be greater than 1 μm.

[0176] In exemplary embodiments, the first electrode plate 51 may be directly connected to the fifth connection electrode 45 or connected through a connection electrode.

[0177] In an exemplary embodiment, since the transition conductive layer in the second conductive layer is formed by a CMP process, the first electrode 51 formed in the present disclosure has good thickness uniformity, surface flatness and surface smoothness, which is beneficial to improving the uniformity of the subsequently formed capacitor dielectric layer and the uniformity of the capacitor structure.

[0178] (23) Forming a capacitor dielectric layer. In an exemplary embodiment, forming the capacitor dielectric layer may include: depositing a capacitor dielectric film on one side of the second surface of the substrate 10 by a process such as CVD, PECVD, LPCVD, or ALD, and patterning the capacitor dielectric film by a patterning process to form a capacitor dielectric layer 53 on the first electrode 51, as shown in FIG13 .

[0179] In an exemplary embodiment, the capacitor dielectric layer 53 may be patterned by a dry etching process, and the orthographic projection of the capacitor dielectric layer 53 on the base substrate may be within the range of the orthographic projection of the first electrode 51 on the base substrate.

[0180] In an exemplary embodiment, the capacitor dielectric layer 53 may be made of materials such as silicon nitride (SiNx), silicon oxide (SiO2), or aluminum oxide (Al2O3), and may have a thickness of 100 nm to 200 nm. Because the first electrode 51 has good thickness uniformity and surface smoothness, the capacitor dielectric layer of the present disclosure has good thickness uniformity, effectively improving the capacitance uniformity of the capacitor structure.

[0181] (24) Forming the second electrode plate. In an exemplary embodiment, forming the second electrode plate may include: depositing a second electrode plate conductive film on one side of the second surface of the base substrate 10 by a PVD process, patterning the second electrode plate conductive film by a patterning process, and forming the second electrode plate 52 on the capacitor dielectric layer 53, as shown in FIG14 .

[0182] In an exemplary embodiment, the second electrode plate 52 may be patterned using a dry etching process, and the orthographic projection of the second electrode plate 52 on the base substrate may be located within the range of the orthographic projection of the capacitor dielectric layer 53 on the base substrate.

[0183] In an exemplary embodiment, the second electrode plate 52 may serve as an upper electrode plate of the capacitor structure, and the first electrode plate 51 , the capacitor dielectric layer 53 , and the second electrode plate 52 constitute a filter capacitor of the MIM structure.

[0184] In an exemplary embodiment, the second electrode 52 may have a sandwich structure of Ti / Cu / Ti or a sandwich structure of Ti / Al / Ti, wherein the thickness of the Ti layer may be approximately 30 nm to 50 nm, and the thickness of the Cu layer or the Al layer may be approximately 200 nm to 400 nm.

[0185] In an exemplary embodiment, the second conductive layer disposed on the second surface of the base substrate, the capacitor dielectric layer disposed on the side of the second conductive layer away from the base substrate, and the second electrode disposed on the side of the capacitor dielectric layer away from the base substrate constitute the second structural layer.

[0186] Figure 15 is a schematic diagram of a planar structure of a capacitor structure according to an exemplary embodiment of the present disclosure. As shown in Figure 15 , the capacitor structure of the MIM structure may include a first plate 51, a capacitor dielectric layer 53, and a second plate 52. The capacitor dielectric layer 53 is disposed on a side of the first plate 51 away from the substrate, and the capacitor dielectric layer 53 is disposed on a side of the capacitor dielectric layer 53 away from the substrate. The first plate 51, the capacitor dielectric layer 53, and the second plate 52 are rectangular in shape.

[0187] In an exemplary embodiment, the areas of the first electrode plate 51 , the capacitor dielectric layer 53 , and the second electrode plate 52 decrease in sequence as they move away from the base substrate 10 .

[0188] In an exemplary embodiment, the capacitor dielectric layer 53 and the second electrode plate 52 are both patterned by a dry etching process with high etching accuracy, which not only effectively improves the dimensional accuracy and capacitance uniformity of the capacitor structure, but also ensures the dimensional accuracy of the capacitor dielectric layer 53 and the second electrode plate 52. Moreover, by arranging the areas of the first electrode plate 51, the capacitor dielectric layer 53 and the second electrode plate 52 to decrease successively, the orthographic projection of the second electrode plate 52 on the substrate can be located within the range of the orthographic projection of the capacitor dielectric layer 53 on the substrate, and the orthographic projection of the capacitor dielectric layer 53 on the substrate can be located within the range of the orthographic projection of the first electrode plate 51 on the substrate, further ensuring the dimensional accuracy, effectively ensuring the effective area of ​​the electrode plate, and improving the performance consistency of the device.

[0189] In an exemplary embodiment, on a plane parallel to the base substrate 10, in at least one direction, a first distance d1 is provided between an edge of the first electrode 51 and an edge of the capacitor dielectric layer 53, and a second distance d2 is provided between an edge of the capacitor dielectric layer 53 and an edge of the second electrode 52. The first distance d1 may be greater than or equal to 50 nm, and the second distance d2 may be greater than or equal to 50 nm.

[0190] The present disclosure effectively ensures the processing accuracy of the capacitor structure and the effective area of ​​the capacitor structure by setting the stacking relationship of the first electrode plate, the capacitor dielectric layer and the second electrode plate, thereby improving the consistency of the filter performance.

[0191] (25)-(28) form the first insulating layer, the lead layer, the second insulating layer and the pad layer in sequence. The manufacturing process and the formed structure are basically the same as steps (15)-(18) of the aforementioned embodiment, as shown in FIG10.

[0192] In a capacitor structure of a filter, the lower plate is made by subtractive electroplating, and the upper plate is formed by a wet etching process. Due to the uneven and rough surface of the lower plate, the thickness of the capacitor dielectric layer is uneven, resulting in problems such as uneven capacitance in the capacitor structure. Due to the low precision of wet etching, the dimensional deviation of the capacitor structure is large, resulting in problems such as low performance consistency in the filter. In the filter provided by the embodiment of the present disclosure, the first plate of the capacitor structure is prepared by a Damascus process including additive electroplating and CMP. The first plate has good thickness uniformity, surface flatness and surface smoothness, so that the capacitor dielectric layer has good thickness uniformity, effectively improving the capacitance uniformity of the capacitor structure. The capacitor dielectric layer and the second plate of the capacitor structure of the present disclosure are prepared by a dry etching process with high etching precision, which not only effectively improves the dimensional accuracy and dimensional uniformity of the capacitor structure, but also effectively ensures the effective area of ​​the plate by arranging the areas of the first plate, capacitor dielectric layer and second plate to be reduced in sequence, further improving the processing accuracy of the capacitor structure, ensuring dimensional accuracy and dimensional uniformity, improving the consistency of filter performance, and improving product yield and product quality.

[0193] The present disclosure uses optimized additive electroplating and CMP processes to ensure seamless connection between the connecting electrodes and the conductive pillars, reduce process steps, and effectively improve the working reliability and performance stability of the filter.

[0194] In a capacitor structure of a filter, the lower plate adopts a Ti / Cu laminated structure. Since Cu is in direct contact with the capacitor dielectric layer (SiNx), not only will Cu ions diffuse into SiNx, but the adhesion between the two is also small, which is prone to peeling, resulting in abnormal filter characteristics or even failure. The first plate of the capacitor structure disclosed in the present invention adopts a Ti / Cu / Ti laminated structure. The Ti layer contacts SiNx, which not only blocks the diffusion of Cu ions into SiNx, but also avoids peeling, effectively improving the reliability and stability of the filter.

[0195] The first and second insulating layers of the capacitor structure in the disclosed embodiment are made of organic materials and have a thickness of approximately 1μm to 10μm. This not only effectively reduces the parasitic capacitance between the conductive layers but also effectively prevents undercutting, ensuring the stability and reliability of the filter's performance and improving its performance. The disclosed filter utilizes TGV technology to implement a glass-core TGV 3D spiral inductor, effectively increasing the inductance and Q value per unit area, making the filter structure more compact, reducing the filter size, and making the filter easier to integrate.

[0196] Figure 16 is a schematic diagram of the structure of another filter of an exemplary embodiment of the present disclosure. The main structure of the filter of this embodiment is substantially the same as that of the embodiment shown in Figure 10, except that the cross-sectional shape of the conductive column embedded in the substrate of this embodiment is a column shape or a cone shape. As shown in Figure 16, the main structure of the filter of the exemplary embodiment of the present disclosure may include a substrate 10, a first structure layer 100 and a second structure layer 200. The first structure layer 100 may be arranged on one side of the first surface of the substrate 10, and the second structure layer 200 may be arranged on one side of the second surface of the substrate 10. In an exemplary embodiment, the structure of the first structure layer 100 and the second structure layer 200 are substantially the same as those of the embodiment shown in Figure 10, and will not be repeated here.

[0197] In an exemplary embodiment, a plurality of conductive pillars are embedded in the base substrate 10. The plurality of conductive pillars may include at least a first conductive pillar 31 and a second conductive pillar 32. The structures of the two conductive pillars may be substantially identical. In a plane parallel to the base substrate, the conductive pillars may be circular or elliptical in shape. In a plane perpendicular to the base substrate, the cross-sectional shape of the conductive pillars may be cylindrical or conical.

[0198] In an exemplary embodiment, the base substrate 10 is obtained by first forming a metallized blind hole base substrate and then performing a thinning process.

[0199] In an exemplary embodiment, the preparation process of the filter of this embodiment may include the following steps.

[0200] (31) Forming a metalized blind via glass (BGV) substrate. In an exemplary embodiment, forming a metalized BGV substrate may include:

[0201] (a1) A base substrate 10 is provided, and a plurality of blind holes are formed on the base substrate by laser induced etching, sandblasting, laser ablation, or other processes. The plurality of blind holes may include at least a first blind hole 93 and a second blind hole 94, as shown in FIG. 17A .

[0202] In an exemplary embodiment, the structures of the two blind vias may be substantially the same, both being blind via structures that do not penetrate the base substrate 10. On a plane parallel to the base substrate, the blind vias may be circular or elliptical, and on a plane perpendicular to the base substrate, the cross-sectional shape of the blind vias may be columnar or conical, etc. The blind vias are configured to accommodate subsequently formed conductive pillars.

[0203] In an exemplary embodiment, the cross-sectional shape of the blind hole may be a cone shape, with a taper less than or equal to 5°.

[0204] In an exemplary embodiment, two blind holes may be provided on the second surface of the base substrate 10 , and no blind holes are provided on the first surface of the base substrate 10 .

[0205] In an exemplary embodiment, the base substrate may be made of alkali-free glass, quartz glass, or the like, and may have a thickness of approximately 0.7 mm to 1.0 mm.

[0206] In an exemplary embodiment, the diameter of each blind hole may be approximately 1 μm to 50 μm.

[0207] (a2) First, a continuous blind hole adhesion layer and a blind hole seed layer are formed on the inner sidewalls of the plurality of blind holes through a PVD process. Then, a plurality of conductive pillars are formed in the plurality of blind holes through an electroplating process. The plurality of conductive pillars may include at least a first conductive pillar 31 filling the first blind hole 93 and a second conductive pillar 32 filling the second blind hole 94. Finally, a CMP process is performed to remove the conductive material on the second surface of the base substrate 10, as shown in FIG17B .

[0208] In an exemplary embodiment, materials of the blind via adhesion layer, the blind via seed layer, and the conductive pillars are substantially the same as those of the previous embodiment.

[0209] (32) Forming a second conductive layer. In an exemplary embodiment, forming the second conductive layer may include:

[0210] (b1) A photoresist layer is spin-coated on one side of the second surface of the base substrate 10. A trace pattern is formed on the photoresist layer through a patterning process including exposure and development. The photoresist layer at the location of the trace pattern is then removed, exposing the second surface of the base substrate 10, as shown in FIG18A .

[0211] (b2) A seed film is first deposited on the second surface of substrate 10 using a PVD process. The seed film is disposed on the second surface of substrate 10 where the trace pattern is located, and the seed film is disposed on the photoresist layer in areas outside the trace pattern. Subsequently, a conductive layer is formed on the seed film on the second surface of substrate 10 using an additive electroplating process. The conductive layer is higher than the photoresist layer, i.e., the distance between the surface of the conductive layer away from the substrate and the second surface is greater than the distance between the surface of the photoresist layer away from the substrate and the second surface, as shown in FIG18B .

[0212] In an exemplary embodiment, the seed layer can adopt a double-layer structure of Ti / Cu, the conductive layer can be made of Cu, the Ti layer contacts the substrate, and the Cu layer contacts the conductive layer. The Ti layer can effectively enhance the adhesion between Cu and the substrate.

[0213] (b3) Using the CMP process, the photoresist layer is used as a cut-off layer to completely remove the conductive layer and the seed film on the photoresist layer, thereby forming a transition conductive layer on the second surface of the base substrate 10, as shown in FIG18C.

[0214] (b4) Forming a second conductive layer. A protective conductive film is deposited on one side of the second surface of the base substrate 10 using a PVD process. The protective conductive film is patterned using a patterning process to form a conductive protective layer on the transition conductive layer. The conductive protective layer and the transition conductive layer together constitute a second conductive layer. The second conductive layer may include at least a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, and a first electrode plate 51. The second connecting electrode 42 is connected to both the second conductive pillar 32 and the third conductive pillar 33, and the third connecting electrode 43 is connected to the first conductive pillar 31, as shown in FIG18D.

[0215] In an exemplary embodiment, the conductive protective layer may be made of Ti and may have a thickness of approximately 30 nm to 100 nm. In an exemplary embodiment, the conductive protective layer may prevent the conductive layer (Cu) from diffusing into a subsequently formed capacitor dielectric layer and may also enhance adhesion between the conductive layer (Cu) and the subsequently formed capacitor dielectric layer.

[0216] In an exemplary embodiment, the third, fourth, and fifth connection electrodes 43, 44, and 45 may each include a stacked seed layer (Ti / Cu), a conductive layer (Cu), and a conductive protection layer (Ti), and the thickness of the conductive layer may be greater than 1 μm.

[0217] In an exemplary embodiment, the first electrode plate 51 may serve as a lower electrode plate of the capacitor structure. The first electrode plate 51 may include a stacked seed layer (Ti / Cu), a conductive layer (Cu), and a conductive protection layer (Ti).

[0218] In an exemplary embodiment, since the transition conductive layer in the second conductive layer is formed by a CMP process, the first electrode 51 formed in the present disclosure has good thickness uniformity, surface flatness and surface smoothness, which is beneficial to improving the uniformity of the subsequently formed capacitor dielectric layer and the uniformity of the capacitor structure.

[0219] (33) Forming a capacitor dielectric layer. In an exemplary embodiment, the structure and process of forming the capacitor dielectric layer 53 may be substantially the same as those of the embodiment shown in FIG. 10 , as shown in FIG. 19 .

[0220] In the exemplary embodiment, since the first electrode 51 has good thickness uniformity and surface smoothness, the capacitor dielectric layer of the present disclosure has good thickness uniformity, which effectively improves the capacitance uniformity of the capacitor structure.

[0221] (34) Forming the Second Electrode Plate In an exemplary embodiment, the structure and process of forming the second electrode plate 52 may be substantially the same as those of the embodiment shown in FIG. 10 , as shown in FIG. 20 .

[0222] In an exemplary embodiment, both the capacitor dielectric layer 53 and the second plate 52 are patterned using a dry etching process. The orthographic projection of the second plate 52 on the substrate can be located within the orthographic projection of the capacitor dielectric layer 53 on the substrate, and the orthographic projection of the capacitor dielectric layer 53 on the substrate can be located within the orthographic projection of the first plate 51 on the substrate. The second plate 52 can serve as the upper plate of the capacitor structure, and the first plate 51, the capacitor dielectric layer 53, and the second plate 52 form a filter capacitor of the MIM structure.

[0223] In an exemplary embodiment, the areas of the first electrode 51, the capacitor dielectric layer 53, and the second electrode 52 decrease sequentially. In at least one direction, there is a first distance between the edge of the first electrode 51 and the edge of the capacitor dielectric layer 53, and there is a second distance between the edge of the capacitor dielectric layer 53 and the edge of the second electrode 52. The first distance can be greater than or equal to 50 nm, and the second distance can be greater than or equal to 50 nm.

[0224] (35)-(38) form the first insulating layer, the lead layer, the second insulating layer and the pad layer in sequence. The manufacturing process and the formed structure are basically the same as steps (15)-(18) of the aforementioned embodiment, as shown in FIG21.

[0225] (39) Forming a first structural layer. In an exemplary embodiment, forming the first structural layer may include:

[0226] (c1) The base substrate 10 is turned over, and the first surface of the base substrate 10 is thinned until two conductive pillars are exposed on the first surface, as shown in FIG. 22A .

[0227] (c2) A photoresist layer is spin-coated on one side of the first surface of the substrate 10 through a spin-coating process. A wiring pattern is formed on the photoresist layer through a patterning process of exposure and development. The photoresist layer at the location of the wiring pattern is removed, exposing the first surface of the substrate 10. A seed film is first deposited on one side of the first surface of the substrate 10 through a PVD process. The seed film at the location of the wiring pattern is disposed on the first surface of the substrate 10, and the seed film in the area outside the wiring pattern is disposed on the photoresist layer. Subsequently, a conductive layer is formed on the seed film on the first surface of the substrate 10 through an additive electroplating process. The conductive layer is higher than the photoresist layer. A CMP process is performed, using the photoresist layer as a cutoff layer, to completely remove the conductive layer and seed film on the photoresist layer, forming a first conductive layer on the first surface of the substrate 10. The first conductive layer may include at least a first connecting electrode 41, which is connected to both the first conductive pillar 31 and the second conductive pillar 32, as shown in FIG22B.

[0228] (c3) Forming a protective layer: A first protective film is spin-coated on one side of the first surface of the base substrate 10 by a spin coating process to form a protective layer 11 covering the first conductive layer, as shown in FIG16 .

[0229] At this point, the filter of this embodiment is completed. The main structure of the filter of this embodiment is basically the same as that of the previous embodiment. The difference is that the cross-sectional shape of the conductive column in the substrate of this embodiment is columnar or conical.

[0230] The filter of this embodiment not only has the advantages of the aforementioned embodiments, but also, compared with the hourglass-shaped holes in the substrate of the aforementioned embodiments, the columnar holes or conical holes of this embodiment can effectively reduce the stress accumulation in the holes, effectively control the warping and fragmentation caused by stress, reduce the process difficulty, improve the yield, and maximize the consistency of the overall performance of the filter.

[0231] Figure 23 is a schematic diagram of the structure of another filter of an exemplary embodiment of the present disclosure. The main structure of the filter of this embodiment is substantially the same as that of the embodiment shown in Figure 10, except that the first electrode of the capacitor structure of this embodiment is prepared by a patterning process. As shown in Figure 23, the main structure of the filter of the exemplary embodiment of the present disclosure may include a base substrate 10, a first structure layer 100 and a second structure layer 200. The first structure layer 100 may be arranged on one side of the first surface of the base substrate 10, and the second structure layer 200 may be arranged on one side of the second surface of the base substrate 10. In an exemplary embodiment, the structure of the connecting electrodes in the base substrate 10, the first structure layer 100 and the second structure layer 200 is substantially the same as that of the embodiment shown in Figure 10, and will not be repeated here.

[0232] In an exemplary embodiment, the capacitor structure in the second structure layer 200 may include a first electrode 51 arranged on the second surface of the base substrate 10, a capacitor dielectric layer 53 arranged on the side of the first electrode 51 away from the base substrate, and a second electrode 52 arranged on the side of the capacitor dielectric layer 53 away from the base substrate. The first electrode 51 can be prepared by a patterning process.

[0233] In an exemplary embodiment, the first electrode plate 51 has a thickness of h1, and the third, fourth, and fifth connection electrodes 43, 44, and 45 have a thickness of h2, where h1 is smaller than h2.

[0234] In an exemplary embodiment, the first electrode 51 may include a stacked seed layer, a conductive layer, and a conductive protective layer. The seed layer may include a titanium layer with a thickness of 10 nm to 200 nm. The material of the conductive layer may include aluminum, and the material of the conductive protective layer may include titanium, forming a Ti / Al / Ti sandwich laminate structure.

[0235] In an exemplary embodiment, the thickness of the aluminum layer may be less than 1 μm. For example, the thickness of the aluminum layer may be approximately 0.5 μm to 0.9 μm.

[0236] In an exemplary embodiment, the material of the capacitor dielectric layer 53 may be silicon nitride (SiNx), and the thickness of the capacitor dielectric layer 53 may be 100 nm to 200 nm.

[0237] In an exemplary embodiment, the material of the second electrode plate 52 includes Al, and the thickness of the second electrode plate 52 may be greater than or equal to 400 nm. Alternatively, the second electrode plate 52 may have a sandwich structure of Ti / Al / Ti.

[0238] In an exemplary embodiment, the connecting electrode and the first electrode 51 in the second structural layer are formed separately using different patterning processes. The preparation of the first electrode 51 using a patterning process may include: after forming the third connecting electrode 43, the fourth connecting electrode 44 and the fifth connecting electrode 45 of the second structural layer 200, sequentially depositing a Ti layer, an Al layer and a Ti layer on one side of the second surface of the substrate 10 by a PVD process, applying a photoresist, exposing and developing the photoresist, forming the first electrode 51 by a dry etching process, and finally stripping off the remaining photoresist. Since the thickness of the Al layer in the first electrode 51 is relatively thin and patterned by a dry etching process, the first electrode 51 has good thickness uniformity and surface smoothness, which can effectively improve the capacitance uniformity of the capacitor structure. In addition, due to the use of a patterning process, the overall process difficulty can be reduced while ensuring the flatness of the first electrode, thereby reducing production time and reducing production costs.

[0239] In an exemplary embodiment, a plurality of first vias and a plurality of third vias may be provided in the first insulating layer 61. The first lead 71 may be connected to the third connection electrode 43 through the plurality of first vias, and the third lead 73 may be connected to the second electrode plate 52 through the plurality of third vias. By providing multiple vias and adopting a multi-contact via overlap method, the present disclosure can effectively reduce contact resistance, effectively improve connection reliability, enhance capacitor performance, reduce capacitor loss, reduce the probability of process defects, and improve yield.

[0240] The structure and preparation process of the filter in the exemplary embodiment of the present disclosure are merely exemplary. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0241] The exemplary embodiments of the present disclosure further provide a method for preparing a filter to prepare the filter of the aforementioned embodiment. In an exemplary embodiment, the method for preparing the filter may include:

[0242] forming a metallized through-hole substrate, wherein the substrate is provided with a conductive column penetrating the substrate in a thickness direction;

[0243] A first structural layer is formed on one side of the first surface of the base substrate, a second structural layer is formed on one side of the second surface of the base substrate, a first insulating layer is arranged on a side of the second structural layer away from the base substrate, a lead layer is arranged on a side of the first insulating layer away from the base substrate, a second insulating layer is arranged on a side of the lead layer away from the base substrate, and a pad layer is arranged on a side of the second insulating layer away from the base substrate, the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead, the lead is connected to the capacitor structure, the pad layer includes at least one pad, the pad is connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

[0244] In an exemplary embodiment, the capacitor structure includes a first electrode plate arranged on the second surface of the base substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the base substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the base substrate; the orthographic projection of the second electrode plate on the base substrate is within the range of the orthographic projection of the capacitor dielectric layer on the base substrate, and the orthographic projection of the capacitor dielectric layer on the base substrate is within the range of the orthographic projection of the first electrode plate on the base substrate.

[0245] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are provided in the same layer and are formed simultaneously through the same patterning process.

[0246] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structural layer are provided in the same layer and are formed simultaneously through the same damascene process.

[0247] In an exemplary embodiment, the first electrode plate and the connecting electrode in the second structure layer are formed using different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connecting electrode in the second structure layer.

[0248] In an exemplary embodiment, the capacitor dielectric layer and the second electrode plate are formed by a patterning process including a dry etching process.

[0249] The exemplary embodiments of the present disclosure further provide another method for preparing a filter to prepare the filter of the aforementioned embodiment. In an exemplary embodiment, the method for preparing a filter may include:

[0250] forming a metallized blind hole substrate, wherein the substrate substrate is provided with a conductive column that does not penetrate the substrate substrate in a thickness direction;

[0251] forming a second structure layer on one side of the second surface of the base substrate, a first insulating layer arranged on a side of the second structure layer away from the base substrate, a lead layer arranged on a side of the first insulating layer away from the base substrate, a second insulating layer arranged on a side of the lead layer away from the base substrate, and a pad layer arranged on a side of the second insulating layer away from the base substrate;

[0252] Turning over the base substrate, and performing a thinning process on the first surface of the base substrate until the conductive pillars are exposed, wherein the first surface and the second surface are surfaces facing away from each other;

[0253] forming a first structural layer on one side of the first surface of the base substrate;

[0254] The first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead, the lead is connected to the capacitor structure, the pad layer includes at least one pad, and the pad is connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

[0255] The present disclosure further provides an electronic device including the filter of the aforementioned embodiment. The electronic device can be used in a radio frequency front-end device in a wireless communication device, such as a radio frequency filter.

[0256] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the appended claims.

Claims

1. A filter, comprising a substrate, wherein the substrate is provided with a conductive column that penetrates the substrate in a thickness direction, a first structural layer is provided on a first surface of the substrate, a second structural layer is provided on a second surface of the substrate, a first insulating layer is provided on a side of the second structural layer away from the substrate, a lead layer is provided on a side of the first insulating layer away from the substrate, a second insulating layer is provided on a side of the lead layer away from the substrate, and a pad layer is provided on a side of the second insulating layer away from the substrate, wherein the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive column, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, and the pad layer includes at least one pad connected to the lead; the material of the first insulating layer and the second insulating layer includes an organic material.

2. The filter according to claim 1, wherein The capacitor structure includes a first electrode plate arranged on the second surface of the base substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the base substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the base substrate; the orthographic projection of the second electrode plate on the base substrate is within the range of the orthographic projection of the capacitor dielectric layer on the base substrate.

3. The filter according to claim 2, wherein: The orthographic projection of the capacitor dielectric layer on the base substrate is located within the range of the orthographic projection of the first electrode plate on the base substrate.

4. The filter according to claim 3, wherein: Along the direction away from the base substrate, the areas of the first electrode plate, the capacitor dielectric layer and the second electrode plate decrease in sequence.

5. The filter according to claim 3, wherein: On a plane parallel to the substrate, in at least one direction, there is a first distance between an edge of the first electrode plate and an edge of the capacitor dielectric layer, and the first distance is greater than or equal to 50 nm.

6. The filter according to claim 3, wherein: On a plane parallel to the substrate, in at least one direction, there is a second distance between the edge of the capacitor dielectric layer and the edge of the second electrode plate, and the second distance is greater than or equal to 50 nm.

7. The filter according to claim 2, wherein: The first electrode includes a seed layer arranged on the second surface of the substrate and a conductive layer arranged on the side of the seed layer away from the substrate; the connecting electrode in the second structural layer includes a seed layer arranged on the second surface of the substrate and a conductive layer arranged on the side of the seed layer away from the substrate.

8. The filter according to claim 7, wherein: The seed layer includes a double-layer structure of a titanium layer and a copper layer, and the thickness of the titanium layer is 10 nm to 200 nm.

9. The filter according to claim 7, wherein: The first electrode plate and the connecting electrode in the second structural layer are arranged in the same layer and are formed synchronously through the same patterning process.

10. The filter according to claim 7, wherein: The orthographic projection of the connection electrode in the second structural layer on the base substrate is located within the range of the orthographic projection of the capacitor dielectric layer on the base substrate.

11. The filter according to claim 2, wherein: The first electrode plate includes a seed layer arranged on the second surface of the substrate, a conductive layer arranged on the side of the seed layer away from the substrate, and a conductive protective layer arranged on the side of the conductive layer away from the substrate; the connecting electrode in the second structural layer includes a seed layer arranged on the second surface of the substrate, a conductive layer arranged on the side of the seed layer away from the substrate, and a conductive protective layer arranged on the side of the conductive layer away from the substrate.

12. The filter according to claim 11, wherein The seed layer includes a double-layer structure of a titanium layer and a copper layer. The material of the conductive protection layer includes titanium. The thickness of the titanium layer is 10 nm to 200 nm.

13. The filter according to claim 11, wherein The first electrode plate and the connecting electrode are arranged in the same layer and are formed synchronously through the same Damascene process.

14. The filter according to claim 11, wherein The first electrode plate and the connecting electrode are formed by different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connecting electrode.

15. The filter according to claim 2, wherein: The second electrode plate adopts a laminated structure of titanium layer / copper layer / titanium layer, or a laminated structure of titanium layer / aluminum layer / titanium layer.

16. The filter according to claim 15, wherein The thickness of the titanium layer is 30nm to 50nm, and the thickness of the copper layer or the aluminum layer is 200nm to 400nm.

17. The filter according to any one of claims 1 to 16, wherein: The connection electrode in the first structural layer includes a seed layer and a conductive layer arranged on a side of the seed layer away from the substrate. The seed layer includes a double-layer structure of a titanium layer and a copper layer. The thickness of the titanium layer is 10nm to 200nm.

18. The filter according to claim 17, wherein The first structural layer further includes a protective layer disposed on a side of the connecting electrode away from the base substrate. The material of the protective layer includes an organic material, and the thickness of the protective layer is 1 μm to 10 μm.

19. The filter according to any one of claims 1 to 16, wherein: In a direction perpendicular to the base substrate, a cross-sectional shape of the conductive pillar includes a pillar shape, a cone shape, or an hourglass shape.

20. An electronic device comprising the filter according to any one of claims 1 to 19.

21. A method for preparing a filter, comprising: forming a metallized through-hole substrate, wherein the substrate substrate is provided with a conductive column penetrating the substrate substrate in a thickness direction; A first structural layer is formed on one side of the first surface of the base substrate, a second structural layer is formed on one side of the second surface of the base substrate, a first insulating layer is arranged on the side of the second structural layer away from the base substrate, a lead layer is arranged on the side of the first insulating layer away from the base substrate, a second insulating layer is arranged on the side of the lead layer away from the base substrate, and a pad layer is arranged on the side of the second insulating layer away from the base substrate, the first surface and the second surface are surfaces facing away from each other; the first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, the pad layer includes at least one pad connected to the lead; the material of the first insulating layer and the second insulating layer includes organic material.

22. The preparation method according to claim 21, wherein The capacitor structure includes a first electrode plate arranged on the second surface of the base substrate, a capacitor dielectric layer arranged on the side of the first electrode plate away from the base substrate, and a second electrode plate arranged on the side of the capacitor dielectric layer away from the base substrate; the orthographic projection of the second electrode plate on the base substrate is located within the range of the orthographic projection of the capacitor dielectric layer on the base substrate, and the orthographic projection of the capacitor dielectric layer on the base substrate is located within the range of the orthographic projection of the first electrode plate on the base substrate.

23. The preparation method according to claim 22, wherein: The first electrode plate and the connecting electrode in the second structural layer are arranged in the same layer and are formed synchronously through the same patterning process.

24. The preparation method according to claim 22, wherein: The first electrode plate and the connecting electrode in the second structural layer are arranged in the same layer and are formed synchronously through the same Damascene process.

25. The preparation method according to claim 22, wherein: The first electrode plate and the connecting electrode in the second structure layer are formed by different patterning processes, and the thickness of the first electrode plate is smaller than the thickness of the connecting electrode in the second structure layer.

26. The preparation method according to claim 22, wherein: The capacitor dielectric layer and the second electrode plate are respectively formed by a patterning process including a dry etching process.

27. A method for preparing a filter, comprising: Forming a metallized blind hole substrate, wherein the substrate substrate is provided with a conductive column that does not penetrate the substrate substrate in a thickness direction; A second structural layer is formed on the second surface side of the base substrate, and a second structural layer is arranged on the second structural layer away from the base substrate. A first insulating layer on one side of the bottom substrate, a lead layer arranged on a side of the first insulating layer away from the base substrate, a second insulating layer arranged on a side of the lead layer away from the base substrate, and a pad layer arranged on a side of the second insulating layer away from the base substrate; Turning over the substrate, and performing a thinning process on the first surface of the substrate until the conductive pillars are exposed, wherein the first surface and the second surface are surfaces facing away from each other; forming a first structural layer on one side of the first surface of the substrate; The first structural layer and the second structural layer both include connecting electrodes connected to the conductive pillars, the second structural layer also includes a capacitor structure, the lead layer includes at least one lead connected to the capacitor structure, the pad layer includes at least one pad connected to the lead; the materials of the first insulating layer and the second insulating layer include organic materials.

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