Semiconductor structure and preparation method therefor, semiconductor device, and electronic device

Abstract

The present disclosure provides a semiconductor structure and a preparation method therefor, a semiconductor device, and an electronic device. The preparation method comprises: providing a substrate; sequentially forming a first material layer and a second material layer made of materials having different lattice constants on the substrate; etching the first material layer and the second material layer, to form a fin structure comprising a first part formed of the first material layer undergone etching and a second part formed of the second material layer undergone etching; forming an underlying transistor on the basis of the second part; and on the basis of the first part after flipping, forming a top layer transistor.

Description

Semiconductor structure and preparation method thereof, semiconductor device, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202310987931.4 and application date August 7, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a preparation method thereof, a semiconductor device, and an electronic device. Background Art

[0004] As Moore's Law continues to deepen, furthering transistor scaling is a hot topic in the industry. Stacked transistors, by integrating two or more layers of transistors vertically, further increase transistor integration density and become a key technology for further scaling integrated circuits.

[0005] The manufacturing process for stacked transistors, whether monolithic or sequential, is both difficult and complex. Therefore, to simplify the process and reduce the difficulty, the stacked transistor manufacturing process needs to be continuously improved.

[0006] Summary of the Invention

[0007] The present disclosure provides a semiconductor structure and a preparation method thereof, a semiconductor device, and an electronic device.

[0008] According to a first aspect of the present disclosure, a method for fabricating a semiconductor structure is provided. The method comprises: providing a substrate; sequentially forming a first material layer and a second material layer on the substrate, wherein the first material layer and the second material layer are made of materials with different lattice constants; etching the first material layer and the second material layer to form a fin structure, wherein the fin structure includes a first portion formed by the etched first material layer and a second portion formed by the etched second material layer; forming a bottom-layer transistor based on the second portion; flipping the wafer and removing the substrate to expose the first portion; and forming a top-layer transistor based on the first portion.

[0009] A second aspect of the present disclosure provides a semiconductor structure. This semiconductor structure can be fabricated using the fabrication method described in any embodiment of the first aspect. The structure comprises: a bottom transistor; and a top transistor, wherein the top transistor and the bottom transistor are stacked; wherein a first active structure in the bottom transistor and a second active structure in the top transistor form a fin structure, and the first active structure and the second active structure are made of materials with different lattice constants.

[0010] A third aspect of the present disclosure provides a semiconductor device, comprising: a semiconductor structure as described in any one of the embodiments of the first aspect.

[0011] A fourth aspect of the present disclosure provides an electronic device, comprising: a circuit board and a semiconductor device as described in any one of the embodiments of the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0012] Compared with the prior art, the present disclosure has the following beneficial effects:

[0013] In the present disclosure, a bottom transistor is formed in the second part of the fin structure, and a top transistor is formed in the first part of the fin structure after flipping the wafer, so that the bottom transistor and the top transistor are self-aligned through the first part and the second part of the fin structure during the preparation process. On the one hand, this can reduce the processing steps and lower the process difficulty. On the other hand, it can also separate the bottom transistor and the top transistor, avoid the bottom transistor and the top transistor from affecting each other during the processing, and reduce the temperature control requirements during the transistor formation process.

[0014] Furthermore, because the first and second portions of the fin structure are formed from semiconductor materials with different lattice constants and are used to form the bottom transistor and top transistor, respectively, corresponding channel stress is generated in the fin structure shared by the bottom and top transistors. Based on the channel stress generated in the fin structure, the performance of the bottom and top transistors is matched, ensuring the normal operation of the top and bottom transistors.

[0015] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0017] FIG1 is an equivalent top view of a semiconductor structure provided according to an embodiment of the present disclosure.

[0018] FIG2 is a first structural schematic diagram of a semiconductor structure along the AA′ cross section provided according to an embodiment of the present disclosure.

[0019] FIG3 is a schematic structural diagram of a semiconductor structure along the BB′ cross section provided according to an embodiment of the present disclosure.

[0020] FIG4 is a schematic structural diagram of a semiconductor structure along the CC′ cross section provided according to an embodiment of the present disclosure.

[0021] FIG. 5 is a first structural schematic diagram of the semiconductor structure shown in FIG. 1 to FIG. 4 along the AA′ cross section during the preparation process according to an embodiment of the present disclosure.

[0022] FIG6 is a schematic structural diagram of the active region of the semiconductor structure shown in FIG1 to FIG4 along the AA′ cross section during the preparation process according to an embodiment of the present disclosure.

[0023] 7 to 19 are second structural schematic diagrams of the semiconductor structure shown in FIG. 1 to FIG. 4 along the AA′ cross section during the preparation process according to an embodiment of the present disclosure.

[0024] FIG20 is a second structural schematic diagram of a semiconductor structure along the AA′ cross section provided according to an embodiment of the present disclosure.

[0025] FIG21 is a schematic diagram of a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0026] Description of Reference Numerals

[0027] Semiconductor structure 1; bottom transistor 2; top transistor 3; metal pattern 4 in the bottom transistor; metal pattern 5 in the top transistor; fin structure 11; active structure 111 in the bottom transistor; active structure 112 in the top transistor; gate structure 12 in the semiconductor structure; source-drain metal structure 13; substrate 14; first shallow trench isolation layer 15; second shallow trench isolation layer 16; isolation layer 17; dummy gate structure 18 in the bottom transistor; gate structure 19 in the bottom transistor; gate dielectric layer 191 in the bottom transistor; gate electrode layer 192 in the bottom transistor; Interlayer dielectric layer 20; first metal pattern 21; second metal pattern 22; insulating layer 23; carrier 24; fourth shallow trench isolation layer 25; gate structure 26 in the top transistor; gate dielectric layer 261 in the top transistor; gate electrode layer 262 in the top transistor; source / drain 27 in the bottom transistor; source / drain metal 28 in the bottom transistor; source / drain 29 in the top transistor; source / drain metal 30 in the top transistor; dielectric layer 31; barrier layer 32; first trench 33; active area 34; second trench 35; first material layer 36; second material layer 37. DETAILED DESCRIPTION

[0028] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure.

[0029] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present disclosure. The singular forms "a," "the," and "the" used in the present disclosure are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0030] As Moore's Law continues to deepen, furthering transistor scaling is a hot topic in the industry. Stacked transistors, through three-dimensional transistor stacking, enable the integration of two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. This is considered a key technology for continuing the scaling of integrated circuits.

[0031] In one embodiment, there are two schemes for the manufacturing process of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0032] The first solution is to prepare N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate. The preparation process includes repeated exposure, etching, diffusion and other steps. After the preparation is completed, the two transistors can be stacked vertically. However, the first solution has the problem of complex vertical stacking process, requiring fine processing with a high aspect ratio, and cannot use high-mobility materials such as compound semiconductors as channel materials.

[0033] The second solution is to form stacked transistors based on wafer bonding layer by layer. The preparation process involves pasting a wafer on top of the already prepared lower (bottom) transistor to prepare the upper (top) transistor. After the preparation is completed, two transistors can be stacked vertically. However, the second solution requires controlling the preparation temperature during the formation of the upper transistor to prevent the lower transistor from becoming unstable due to high temperature, or to avoid defects in the bonding of the upper and lower transistors.

[0034] In order to solve the above technical problems, the embodiments of the present disclosure provide a method for preparing a semiconductor structure, so as to simplify the process flow of stacking transistors and reduce the difficulty of preparation.

[0035] Figure 1 is an equivalent top view of a semiconductor structure provided according to an embodiment of the present disclosure. As shown in Figure 1 , semiconductor structure 1 includes a fin structure 11, a gate structure 12, and a source / drain metal structure 13. The semiconductor structure 1 is cut along line AA' to form a fin cross-section, along line BB' to form a source / drain cross-section, and along line CC' to form a gate cross-section.

[0036] Figure 2 is a schematic diagram of a semiconductor structure along the AA' cross section according to an embodiment of the present disclosure. Figure 3 is a schematic diagram of a semiconductor structure along the BB' cross section according to an embodiment of the present disclosure. Figure 4 is a schematic diagram of a semiconductor structure along the CC' cross section according to an embodiment of the present disclosure.

[0037] As shown in Figures 2 to 4, the semiconductor structure 1 includes a bottom transistor 2 and a top transistor 3, which are stacked and share an active structure.

[0038] In one embodiment, the bottom transistor 2 and the top transistor 3 have the same channel structure type. Taking the semiconductor structure 1 shown in Figures 2 to 4 as an example, the bottom transistor 2 and the top transistor 3 in the semiconductor structure 1 are FinFETs, and the channel structures of the bottom transistor 2 and the top transistor 3 are fin structures 11.

[0039] In one embodiment, the active structure of the bottom transistor 2 and the active structure of the top transistor 3 can share the fin structure 11. The active structure of the bottom transistor 2 (hereinafter referred to as active structure 111, i.e., the first active structure) is formed by the lower half (i.e., the second portion) of the fin structure 11, and the active structure of the top transistor 3 (hereinafter referred to as active structure 112, i.e., the second active structure) is formed by the upper half (i.e., the first portion) of the fin structure 11.

[0040] In one embodiment, the gate structure of the bottom transistor 2 and the gate structure of the top transistor 3 are disposed opposite each other. Taking the semiconductor structure 1 shown in FIG. 2 to FIG. 4 as an example, the gate structure of the bottom transistor 2 and the gate structure of the top transistor 3 are disposed at opposite ends of the fin structure 11.

[0041] In one embodiment, the gate structure in the bottom transistor 2 (hereinafter referred to as gate structure 19, i.e., the first gate structure) can be set at the lower end of the fin structure 11, covering the bottom surface and side surface of the fin structure 11; the gate structure in the top transistor 3 (hereinafter referred to as gate structure 26, i.e., the second gate structure) can be set at the upper end of the fin structure 11, covering the top surface and side surface of the fin structure 11.

[0042] In one embodiment, an electrical isolation structure is provided between the gate structure 19 and the gate structure 26. The electrical isolation structure may be an insulating dielectric layer, an insulating film, or other structure. Taking the semiconductor structure 1 shown in Figures 2 to 4 as an example, the semiconductor structure 1 includes a shallow trench isolation layer (hereinafter referred to as shallow trench isolation layer 25, i.e., a fourth shallow trench isolation layer) located between the gate structure 19 and the gate structure 26.

[0043] In one embodiment, a shallow trench isolation layer 25 has one side attached to the gate structure 19 and the other side attached to the gate structure 26, thereby electrically isolating the gate structures of the bottom transistor 2 and the top transistor 3. The shallow trench isolation layer 25 can be formed by depositing a dielectric that fills the shallow trench. The process steps for forming the shallow trench isolation layer 25 can be referred to the description of the embodiments corresponding to the subsequent Figures 5 to 19.

[0044] In one embodiment, the bottom transistor 2 and the top transistor 3 can be controlled separately to achieve independent operation, or the bottom transistor 2 and the top transistor 3 can be controlled simultaneously to achieve coordinated operation.

[0045] In one example, as shown in Figures 2 to 4 , a metal pattern (hereinafter referred to as metal pattern 4) formed in a later process in bottom-layer transistor 2 and a metal pattern (hereinafter referred to as metal pattern 5) formed in a later process in top-layer transistor 3 are located at the two ends (upper and lower ends) of semiconductor structure 1, respectively. There is no interconnection between metal pattern 4 and metal pattern 5, thereby enabling the bottom-layer transistor 2 and top-layer transistor 3 to be controlled separately.

[0046] In one example, as shown in the BB' cross section of FIG3 , both active structures 111 and 112 are encapsulated by a dielectric layer 31. The source / drain of the bottom transistor 2 (hereinafter referred to as source / drain 27) and the source / drain of the top transistor 3 (hereinafter referred to as source / drain 29) are formed on the dielectric layer 31. The source / drain metal of the bottom transistor 2 (hereinafter referred to as source / drain metal 28) and the source / drain metal of the top transistor 3 (hereinafter referred to as source / drain metal 30) cover the source / drain 27 and the source / drain 29, respectively, connecting the source / drain 27 to the metal pattern 4 and the source / drain 29 to the metal pattern 5.

[0047] In one embodiment, a carrier 24 is further connected to the bottom of the bottom transistor 2. The carrier 24 is used to electrically isolate the semiconductor structure 1 from other external structural components. In one embodiment, the carrier 24 is used to electrically isolate the semiconductor structure 1 from the circuit board.

[0048] In one embodiment, an isolation layer 17 is provided at the connection between the active structure 111 and the active structure 112 . The isolation layer 17 is used to electrically isolate the active structures of the top-layer transistor 3 and the bottom-layer transistor 2 .

[0049] In one embodiment, the active structure 111 and the active structure 112 may be formed of materials having different lattice constants.

[0050] In one example, as shown in FIG. 2 to FIG. 4 , the material with the first lattice constant forms the active structure 111 , and the material with the second lattice constant forms the active structure 112 .

[0051] In one embodiment, the first lattice constant is different from the second lattice constant.

[0052] In one example, the material of the first lattice constant is silicon germanium (SiGe), and the material of the second lattice constant is silicon (Si). Alternatively, the material of the first lattice constant is silicon, and the material of the second lattice constant is silicon germanium.

[0053] In one embodiment, when the material of the first lattice constant is silicon germanium and the material of the second lattice constant is silicon, the material of the first lattice constant forms active structure 111, which serves as a stress source. Active structure 111 can form a P-type field-effect transistor, and active structure 112 can form an N-type field-effect transistor.

[0054] In one embodiment, when the material of the first lattice constant is silicon and the material of the second lattice constant is silicon germanium, the material of the second lattice constant forms active structure 112, which serves as a stress source. Active structure 111 can form an N-type field effect transistor, and active structure 112 can form a P-type field effect transistor.

[0055] In one embodiment, to change the stress provided by the active structure formed of silicon germanium (active structure 111 or active structure 112), the atomic percentage of germanium in the silicon germanium can be adjusted. In one embodiment, the atomic percentage of germanium in the silicon germanium can be 10% to 90%. The thickness of the active structure formed of silicon germanium can be 20 to 70 nm.

[0056] In one embodiment, the thickness of the active structure is within the range of 20-70 nm, and the stress provided by the active structure does not vary with thickness. The strain of the active structure is related to the atomic percentage of germanium, with the higher the atomic percentage of germanium, the greater the strain.

[0057] In one example, the thickness of the active structure is in the range of 20-70 nm, and the stress of the active structure formed by SiGe does not change with the thickness. 1-x Ge x The value of the parameter x in the equation approximately satisfies the strain relationship (Dismuske relation). The Dismuske relation is: strain (unit: %) = -4*x. The "-" represents compressive strain, and the parameter x represents the atomic percentage of germanium in the silicon germanium. In one example, when the parameter x is 0.2, the atomic percentage of germanium is 0.2, and the strain of the silicon germanium is approximately -0.8%.

[0058] In one embodiment, the shallow trench isolation layer 25 is positioned between the gate structure 19 and the gate structure 26 based on the positions of the active structure 111 and the active structure 112 .

[0059] In one embodiment, the active structure 111 is made of a material with a first lattice constant, and the active structure 112 is made of a material with a second lattice constant. The gate structure 19 and the gate structure 26 only contact the corresponding active structures, thereby preventing damage to the bottom transistor 2 and the top transistor 3 caused by the gate structure 19 and the gate structure 26 simultaneously contacting the active structure 111 made of the first lattice constant or the active structure 112 made of the second lattice constant.

[0060] In one embodiment, the shallow trench isolation layer 25 may cover the connection between the active structure 111 and the active structure 112 , so that the gate structure 19 only contacts the active structure 111 , and the gate structure 26 only contacts the active structure 112 .

[0061] The preparation process of the semiconductor structure is described below.

[0062] In one embodiment, FIG5 is a first schematic structural diagram of the semiconductor structure shown in FIG1 to FIG4 along the AA' cross section during the fabrication process according to an embodiment of the present disclosure. FIG7 to FIG19 is a second schematic structural diagram of the semiconductor structure shown in FIG1 to FIG4 along the AA' cross section during the fabrication process according to an embodiment of the present disclosure. The active structure 111 of the semiconductor structure in FIG5 and FIG7 to FIG19 is made of silicon, and the active structure 112 is made of silicon germanium.

[0063] In one embodiment, semiconductor structure 1 includes a substrate 14, which may be formed of a semiconductor material doped or undoped with impurities. In one embodiment, the semiconductor material doped or undoped with impurities may be a semiconductor material such as silicon or silicon germanium. A first material layer 36 made of silicon germanium and a second material layer 37 made of silicon may be sequentially formed on substrate 14. In one embodiment, first material layer 36 and second material layer 37 are formed by sequentially depositing silicon germanium and silicon on substrate 14.

[0064] In one embodiment, the first material layer 36 is a material having the second lattice constant, and the second material layer 37 is a material having the first lattice constant.

[0065] The fin structure 11 of the semiconductor structure 1 is formed on the substrate 14 shown in Figure 5 to obtain Figure 7. In one embodiment, the first material layer 36 and the second material layer 37 are patterned using photolithography technology to form the fin structure 11 at one time. The first material layer 36 and the second material layer 37 after etching form the active structure 112 (formed by etching the first material layer 36) and the active structure 111 (formed by etching the second material layer 37), respectively. At this time, the active structure 112 is located at the lower part of the active structure 111. In the embodiment of the present disclosure, the steps of the photolithography technology include: depositing a photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove the material layer corresponding to the portion of the photoresist material, etc.

[0066] In one embodiment, the fin structure 11 may be a parallel, spaced-apart strip-like structure in the AA' cross-section. Generally, the height of the fin structure 11 must meet the requirements of the semiconductor structure 1. In one embodiment, the active structure 111 is used in subsequent processes to form the active structure of the bottom-layer transistor 2 in the semiconductor structure 1; the active structure 112 is used in subsequent processes to form the active structure of the top-layer transistor 3 in the semiconductor structure 1. In one embodiment, the height of the fin structure 11 may be greater than 100 nm.

[0067] An oxide is deposited on the substrate 14 of the semiconductor structure 1 shown in FIG7 to form a shallow trench isolation layer (hereinafter referred to as shallow trench isolation layer 15, i.e., a first shallow trench isolation layer). As shown in FIG8 , the shallow trench isolation layer 15 surrounds or wraps the fin structure 11 when viewed from above the semiconductor structure 1. In one embodiment, the shallow trench isolation layer 15 may also be made of amorphous silicon, amorphous carbon, or diamond-like carbon, but is not limited thereto.

[0068] The shallow trench isolation layer 15 shown in FIG8 is etched to form a shallow trench isolation layer (hereinafter referred to as shallow trench isolation layer 16, i.e., a second shallow trench isolation layer). In one embodiment, the etching process can be dry etching, wet etching, reactive ion etching, or other processes. As shown in FIG9, the shallow trench isolation layer 16 surrounds or wraps around the fin structure 11 when viewed from above the semiconductor structure 1. When viewed along the AA' cross section, the top surface of the shallow trench isolation layer 16 is higher than the top surface of the active structure 112.

[0069] In some embodiments, the first material layer 36 and the second material layer 37 of the semiconductor structure 1 can be formed of a semiconductor material that is not doped with impurities. In one embodiment, the semiconductor material that is not doped with impurities can be a silicon substrate. In one embodiment, ion implantation can be performed on the fin structure 11 shown in FIG. 9 to form an isolation layer 17. As shown in FIG. 10 , the isolation layer 17 is located at the junction of the active structure 111 and the active structure 112, and the top surface of the isolation layer 17 is lower than the top surface of the shallow trench isolation layer 16.

[0070] In one embodiment, the ions implanted include P-type ions, N-type ions, or oxygen ions. In one embodiment, the P-type ions include one or more of boron ions, gallium ions, and indium ions; and the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

[0071] In one embodiment, after P-type and N-type ions are implanted in the center of the fin structure 11, an isolation layer 17 is formed. Isolation layer 17 forms a PN junction with active structure 111, and a PN junction with active structure 112, electrically isolating active structure 111 from active structure 112. Alternatively, isolation layer 17 is formed after oxygen ions are implanted in the fin structure 11. In this process, the isolation layer is formed by implanting high-dose oxygen ions into single-crystal silicon, similarly isolating active structure 111 from active structure 112.

[0072] In some embodiments, the first material layer 36 and the second material layer 37 of the semiconductor structure 1 are formed of a semiconductor material doped with impurities. During the process of forming the fin structure 11 shown in FIG. 7 , a doped layer is formed at the junction of the first material layer 36 and the second material layer 37, so that the formed fin structure 11 is doped with P-type ions, N-type ions, or oxides. The region corresponding to the P-type ions, N-type ions, or oxides corresponds to the isolation layer 17. The isolation layer 17 electrically isolates the active structure 111 from the active structure 112, eliminating the need for the additional ion implantation process shown in FIG. 11 .

[0073] A dummy gate structure (hereinafter referred to as dummy gate structure 18) of the underlying transistor 2 is formed on the active structure 111 shown in FIG10 , obtaining FIG11 . The dummy gate structure 18 is formed by stacking a gate dielectric and a polysilicon gate. In one embodiment, the polysilicon gate may be made of a variety of silicon-based materials such as polycrystalline silicon, microcrystalline silicon, and amorphous silicon. In one embodiment, the formation process of the dummy gate structure 18 may include depositing polysilicon, etc., which is not limited in this embodiment of the present application.

[0074] On the structure shown in FIG11 , the source / drain 27 and gate structure 19 of the bottom transistor 2 are formed, resulting in FIG12 . In one embodiment, the steps of forming the source / drain 27 and gate structure 19 of the bottom transistor 2 include: depositing a dielectric layer 31 on both sides of the dummy gate structure 18, epitaxially forming the source / drain 27, and depositing a source / drain metal 28 connected to the source / drain 27 on top of the source / drain 27. The steps of forming the source / drain 27 and gate structure 19 of the bottom transistor 2 also include: removing the dummy gate structure 18 and forming the gate structure 19 in the area where the dummy gate structure 18 was removed.

[0075] In some embodiments, the gate structure 19 may be a high-K metal gate (HKMG).

[0076] In some embodiments, gate structure 19 includes a gate dielectric layer (hereinafter referred to as gate dielectric layer 191) of the underlying transistor 2 and a gate electrode layer (hereinafter referred to as gate electrode layer 192) of the underlying transistor 2. Gate dielectric layer 191 is formed on fin structure 11, and gate electrode layer 192 is formed on gate dielectric layer 191. In one embodiment, gate dielectric layer 191 may be composed of a silicon oxide layer plus a high dielectric constant (high-K) hafnium oxide layer. The thickness of the silicon oxide layer and hafnium oxide layer may be determined based on the polarity and performance of the underlying transistor.

[0077] In one example, the gate dielectric layer 191 may include a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer. In one example, the gate electrode layer 192 may be composed of multiple layers of electrode materials, each layer of which may include, but is not limited to, hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), alloys of these metals, and carbides of these metals. In one embodiment, the metal carbides forming the electrode materials include hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), tantalum carbide (TaC), and aluminum carbide (AlC).

[0078] In one embodiment, the semiconductor material forming the source / drain 27 can be germanium, silicon, gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), or other suitable materials. In one embodiment, the material forming the source / drain metal 28 can be a metal, a metal compound, or other suitable material.

[0079] The back-end process of the bottom transistor 2 is completed based on the semiconductor structure 1 shown in Figure 12 to obtain Figure 13. In one embodiment, the back-end process includes forming a metal pattern 4 to complete the routing of the control circuit of the bottom transistor 2.

[0080] In one embodiment, to control the operation of the source / drain 27 and the gate structure 19, a metal pattern 4 may be formed on the source / drain 27 and the gate structure 19, respectively. In one embodiment, the metal pattern 4 may include a first metal pattern 21 and a second metal pattern 22. The first metal pattern 21 and the second metal pattern 22 are electrically connected to the source / drain metal 28 and an external power source, respectively, to provide power to the underlying transistor 2 and control the operation of the underlying transistor 2.

[0081] In one embodiment, the second metal pattern 22 may be electrically connected to the plurality of first metal patterns 21 , and the plurality of first metal patterns 21 may contact the source / drain 27 and the gate structure 19 , respectively.

[0082] In one embodiment, the back-end process may further include forming an interlayer dielectric layer 20 between the first metal pattern 21 and the gate electrode layer 192. The interlayer dielectric layer 20 is used to isolate the metal pattern 4 from the gate structure 19. In one embodiment, the interlayer dielectric layer 20 surrounds the periphery of the first metal pattern 21, allowing the first metal pattern 21 to pass through and contact the source / drain 27 and the gate structure 19, respectively.

[0083] In one embodiment, a new substrate is formed on the bottom transistor 2 to obtain FIG14. An insulating material can be deposited on the second metal pattern 22 to form an insulating layer 23. The insulating layer 23 is wafer-bonded to a carrier wafer 24 of a semiconductor structure to form a new substrate.

[0084] In one embodiment, a new substrate is formed on the bottom transistor 2. On the one hand, the bottom transistor 2 can be packaged to avoid the impact of subsequent processes on the bottom transistor 2; on the other hand, the new substrate can support the flipping of the semiconductor structure 1, facilitating subsequent processing of the semiconductor structure 1.

[0085] In one embodiment, after completing the processes related to the bottom transistor 2, the semiconductor structure 1 shown in FIG14 can be flipped to obtain FIG15. After flipping, the semiconductor structure 1 is turned upside down to facilitate processing and fabrication of the top transistor 3.

[0086] In one embodiment, the source / drain 27 and gate structure 19 formed around the active structure 111, after the semiconductor structure 1 is flipped, together with the active structure 111, form the bottom transistor 2 of the semiconductor structure. In one embodiment, the flipped active structure 112 located on the upper portion is used to form the top transistor 3.

[0087] In one embodiment, after flipping, chemical mechanical planarization (CMP) may be used to remove the substrate 14 to obtain FIG16. After removing the substrate 14, the top surface of the active structure 112 and the shallow trench isolation layer 16 are exposed.

[0088] In one embodiment, the shallow trench isolation layer 16 shown in FIG16 is etched to a preset height to form a shallow trench isolation layer 25 having a certain thickness (i.e., a third shallow trench isolation layer, and the third shallow trench isolation layer obtains a fourth shallow trench isolation layer as shown in FIG2 to FIG4 after the semiconductor structure is formed), thereby obtaining FIG17. In one embodiment, etching can be performed using processes such as dry etching, wet etching, and reactive ion etching. The shallow trench isolation layer 25 surrounds or wraps the fin structure 11 when viewed from above the semiconductor structure 1. When viewed in the AA' cross section, the shallow trench isolation layer 25 is located in the middle of the fin structure 11, completely covering the active structure 111 and exposing the side surface of the active structure 112.

[0089] In one embodiment, the thickness of the shallow trench isolation layer 25 can be selected according to actual needs, and the present disclosure does not limit this. In one embodiment, during actual processing, the shallow trench isolation layer 16 can be etched to a preset height by controlling the etching time to obtain the shallow trench isolation layer 25 of the desired thickness.

[0090] In one embodiment, a bottom transistor 2 is formed below the shallow trench isolation layer 25, and a top transistor 3 is formed above the shallow trench isolation layer 25 based on the active structure 112. The shallow trench isolation layer 25 can electrically isolate the bottom transistor 2 from the top transistor 3.

[0091] In one embodiment, the bottom transistor 2 and the top transistor 3 correspond to the active structure 111 and the active structure 112, respectively. The active structure 111 and the active structure 112 are formed using the same process. Therefore, in the manufacturing process shown in FIG17 , the bottom transistor 2 and the top transistor 3 can achieve self-alignment of the upper and lower transistors, thereby solving the problems of complex processes for forming stacked transistors and difficulty in aligning the stacked transistors.

[0092] In one embodiment, based on FIG17 , a gate structure 26 is formed to obtain FIG18 . The steps of forming the gate structure 26 are the same as the steps of forming the gate structure 19 in FIG12 to FIG13 .

[0093] In one embodiment, the gate structure 26 includes: a gate dielectric layer (hereinafter referred to as gate dielectric layer 261) in the top transistor 3 and a gate electrode layer (hereinafter referred to as gate electrode layer 262) in the top transistor 3. The gate dielectric layer 261 is formed on the active structure 112, and the gate electrode layer 262 is formed on the gate dielectric layer 261. In one embodiment, the gate dielectric layer 261 can be composed of a silicon oxide layer plus a high-K hafnium oxide layer. The thickness of the silicon oxide layer and the hafnium oxide layer can be determined based on the polarity and performance of the top transistor. In one example, the gate dielectric layer 261 can include: a 0.5 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0094] In one embodiment, the gate dielectric layer 191 and the gate dielectric layer 261 may also be made of different materials.

[0095] In one embodiment, the gate electrode layer 262 may be composed of multiple layers of electrode materials, each layer of which may include, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals. In one embodiment, the metal carbides include hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.

[0096] In one embodiment, due to the different polarities of the bottom transistor 2 and the top transistor 3, the gate electrode layer 192 and the gate electrode layer 262 may not be made of the same material. In one embodiment, the gate structure 19 may have the same shape as the gate structure 26. In one embodiment, the gate structure 19 may also have a different shape from the gate structure 26.

[0097] In one embodiment, based on Figure 18 , the back-end process of the top transistor 3 is completed to obtain Figure 19 . In one embodiment, the back-end process of the top transistor 3 is the same as the back-end process of the bottom transistor 2 corresponding to Figure 14 .

[0098] In one embodiment, after the back-end process of the top-layer transistor 3 is completed, an insulating layer 23 may be deposited on the top-layer transistor 3 to achieve packaging of the top-layer transistor 3 .

[0099] At this point, the preparation of the semiconductor structure in the embodiment of the present disclosure is completed.

[0100] In the embodiment of the present disclosure, a bottom transistor is formed in the second part of the fin structure, and a top transistor is formed in the first part of the fin structure after flipping the wafer, so that the bottom transistor and the top transistor are self-aligned through the first part and the second part of the fin structure during the preparation process. On the one hand, this can reduce the processing steps and lower the process difficulty. On the other hand, it can also separate the bottom transistor and the top transistor, avoid the bottom transistor and the top transistor from affecting each other during the processing, and reduce the temperature control requirements during the transistor formation process.

[0101] Furthermore, because the first and second portions of the fin structure are formed from semiconductor materials with different lattice constants and are used to form the bottom transistor and top transistor, respectively, corresponding channel stress is generated in the fin structure shared by the bottom and top transistors. Based on the channel stress generated in the fin structure, the performance of the bottom and top transistors is matched, ensuring the normal operation of the top and bottom transistors.

[0102] In some embodiments, the first material layer 36 and the second material layer 37 may be formed by selectively growing corresponding material layers on the substrate 14. In one embodiment, when the substrate 14 is a semiconductor material with a third lattice constant, the first material layer 36 and the second material layer 37 may be formed by selectively growing semiconductor materials with a second lattice constant and a first lattice constant on the substrate 14.

[0103] In one embodiment, FIG6 is a schematic structural diagram of the active region of the semiconductor structure shown in FIG1 to FIG4 along the AA' cross section during the fabrication process according to an embodiment of the present disclosure. As shown in FIG6(a) to FIG6(h), the steps of forming two material layers on substrate 14 can employ multiple photolithography and selective epitaxial growth processes to randomly distribute the two material layers in the active region corresponding to bottom transistor 2 or top transistor 3.

[0104] In one embodiment, the steps of forming the first material layer 36 and the second material layer 37 include: providing a substrate 14, which may be a semiconductor material having a third lattice constant, as shown in FIG6(a); and depositing a barrier layer 32 on the substrate 14. As shown in FIG6(b), removing the barrier layer 32 at a first location on the substrate 14 shown in FIG6(a), and etching the substrate 14 to form a first trench 33. As shown in FIG6(c), growing a semiconductor material having a second lattice constant in the first trench 33 shown in FIG6(b) to form an active region 34. As shown in FIG6(d), removing the barrier layer 32 shown in FIG6(c), and mechanically planarizing the substrate 14. As shown in FIG6(e), epitaxially growing a semiconductor material having the first lattice constant on top of the substrate structure shown in FIG6(d) to form an epitaxially grown substrate 14. (As shown in FIG6(e), the semiconductor material with the first lattice constant and the semiconductor material with the third lattice constant are semiconductor materials with the same lattice constant). A barrier layer 32 is deposited on the epitaxially grown substrate 14. In one embodiment, the semiconductor material with the first lattice constant and the semiconductor material with the third lattice constant may also be semiconductor materials with different lattice constants. As shown in FIG6(f), the barrier layer 32 is removed at the second location of the substrate structure shown in FIG6(e), and the epitaxially grown substrate 14 is etched to form a second trench 35; the second location and the first location are different in the horizontal direction. As shown in FIG6(g), a semiconductor material with a second lattice constant is grown in the second trench 35 shown in FIG6(f), replacing the original semiconductor material with the third lattice constant at this location, to form an active region 34. As shown in FIG6(h), the barrier layer 32 is removed from the substrate structure shown in FIG6(g), and the epitaxially grown substrate 14 is mechanically planarized.

[0105] As can be seen from Figures 6(a) to 6(h), the second position and the first position are located at different heights in a vertical direction perpendicular to the horizontal direction, so that the active region 34 is located at different heights in the vertical direction. Therefore, in the step of etching the material layer to form the fin structure 11, the active region 34 can be the first material layer 36 formed on the substrate 14 or the second material layer 37 formed on the substrate 14.

[0106] In the embodiment of the present disclosure, the semiconductor material of the second lattice constant constituting the active area 34 and the semiconductor material of the third lattice constant constituting the substrate 14 are alternately distributed in the upper and lower parts of the substrate structure, so that the first material layer 36 and the second material layer 37 forming the fin structure 11 alternately provide stress sources, thereby achieving selectivity in the channels used by the top-layer transistor and the bottom-layer transistor, achieving polarity freedom of the upper and lower layers of the stacked transistor, and providing higher design freedom.

[0107] Figure 20 is a second structural diagram of a semiconductor structure along the AA' cross section according to an embodiment of the present disclosure. In one embodiment, as shown in Figure 20 , based on the semiconductor structure 1 shown in Figure 6 , a plurality of stacked transistor units can be fabricated on the semiconductor structure 1 .

[0108] In one embodiment, the relative positions between the active region 34 and the substrate 14 in the semiconductor structure 1 shown in FIG6 are different. After a plurality of stacked transistor units are prepared using the semiconductor structure 1 shown in FIG6 , the active structures 111 and 112 in the plurality of stacked transistor units can be made of different materials. In one example, the active structure 111 of the stacked transistor unit on the left of the plurality of stacked transistor units is silicon, and the active structure 111 of the stacked transistor unit on the right is silicon germanium. In one example, the active structure 111 of the stacked transistor unit on the left of the plurality of stacked transistor units is silicon germanium, and the active structure 111 of the stacked transistor unit on the right is silicon. In one example, the active structure 112 of the stacked transistor unit on the left of the plurality of stacked transistor units is silicon, and the active structure 112 of the stacked transistor unit on the right is silicon germanium. In one example, the active structure 112 of the stacked transistor unit on the left of the plurality of stacked transistor units is silicon germanium, and the active structure 112 of the stacked transistor unit on the right is silicon.

[0109] In one embodiment, the shallow trench isolation layer 25 is located at the connection between the active structure 111 and the active structure 112 , and is used to isolate the bottom transistor 2 from the top transistor.

[0110] In one embodiment, as shown in Figure 20, when the shallow trench isolation layer 25 isolates the bottom transistor 2 and the top transistor, in the stacked transistor unit on the left side of Figure 20, the shallow trench isolation layer 25 can be set at the connection between the active structure 111 and the active structure 112 and close to the active structure 111; in the stacked transistor unit on the right side of Figure 20, the shallow trench isolation layer 25 can be set at the connection between the active structure 111 and the active structure 112 and close to the active structure 112.

[0111] In the embodiment of the present disclosure, the semiconductor structure has multiple stacked transistor units, and the multiple top-level transistors in the multiple stacked transistor units can be transistors of different polarities, so that the polarities of multiple groups of upper and lower stacked transistors can be flexibly configured, thereby improving the design freedom of the semiconductor structure.

[0112] The disclosed embodiments also provide a method for preparing a semiconductor structure. This method can simplify the process flow of stacking transistors and reduce the difficulty of preparation. On the other hand, it can also enhance the channel stress of the transistor and ensure the normal use of the semiconductor structure.

[0113] In some embodiments, in the steps of etching the shallow trench isolation layer to a preset height to obtain the etched shallow trench isolation layer corresponding to Figures 16 and 17, due to the insufficient precision of the etching technology, it is easy to cause inaccurate etching height or completely etching the shallow trench isolation layer, thereby causing poor consistency or damage to the semiconductor structure. In order to solve this technical problem, in the step of forming the shallow trench isolation layer corresponding to Figure 8, an etch barrier layer can be formed in the middle of the shallow trench isolation layer, so that when forming the bottom transistor, the shallow trench isolation layer on the upper part of the etch barrier layer is etched away to expose the first active area 111. When forming the top transistor 3 after flipping the wafer, the shallow trench isolation layer on the upper part of the etch barrier layer is also etched away to expose the second active area 112. It can be seen that based on the position of the etch barrier layer, the height of the fin structure that can expose the upper and lower sides of the etch barrier layer can be controlled. The controllable height of the fin structure allows for relatively low fluctuations in the height of the first active structure in the bottom transistor and the height of the second active structure in the top transistor during the fabrication process, thereby improving the fabrication accuracy of the semiconductor structure and ensuring its consistency.

[0114] In one embodiment, oxide may be deposited on the basis of FIG7 to form a bottom shallow trench isolation layer; a barrier material may then be deposited on the bottom shallow trench isolation layer to form an etch barrier layer; and finally, oxide may be deposited on the etch barrier layer to form a top shallow trench isolation layer, and the top shallow trench isolation layer is flush with the top of the fin structure.

[0115] In one embodiment, the barrier material forming the etch stop layer is different from the oxide forming the shallow trench isolation layer. In one example, when the oxide forming the shallow trench isolation layer is a silicon-based oxide, the barrier material forming the etch stop layer may be silicon nitride (SiN), silicon oxycarbide (SiCO), silicon boron carbon nitride (SiBCN), titanium oxide (TiOx), aluminum oxide (AlOx), etc.

[0116] FIG21 is a schematic diagram of a method for preparing a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG21 , the method for preparing a semiconductor structure includes:

[0117] In step S2101 , a substrate 14 is provided.

[0118] In some embodiments, substrate 14 may be a semiconductor of a single element. In one embodiment, substrate 14 may be silicon, germanium, or other suitable materials. In some embodiments, substrate 14 may be a compound semiconductor. In one embodiment, substrate 14 may be silicon carbide (SiC), gallium arsenide, gallium phosphide (GaP), indium phosphide (InP), or other suitable materials.

[0119] In step S2102 , a first material layer 36 and a second material layer 37 are sequentially formed on the substrate. The first material layer 36 and the second material layer 37 are made of materials with different lattice constants.

[0120] In one embodiment, as the size of transistors in a semiconductor structure gradually decreases, the channel stress applied by source / drain epitaxy will also be significantly reduced. Therefore, in order to increase the channel stress, in the embodiment of the present disclosure, a first material layer 36 and a second material layer 37 with different lattice constants can be sequentially formed on the substrate 14. Based on the lattice mismatch between the first material layer 36 or the second material layer 37 and the substrate 14, stress is introduced into the first material layer 36 or the second material layer 37, so that the channel structure formed by the first material layer 36 and the second material layer 37 forms a channel stress.

[0121] The method of applying stress from below the substrate and the channel in the embodiment of the present disclosure is not affected by the size of the transistor and can be used in transistor size reduction solutions such as stacked transistors.

[0122] In one example, a first material layer and a second material layer are sequentially formed on a substrate.

[0123] In step S2103 , the first material layer 36 and the second material layer 37 are etched to form a fin structure 11 . The fin structure 11 includes a first portion (ie, an active structure 112 ) formed by the etched first material layer and a second portion (ie, an active structure 111 ) formed by the etched second material layer.

[0124] In one embodiment, the fin structure 11 can be formed by etching the first material layer 36 and the second material layer 37 through the same process until reaching the substrate 14 . Thus, based on the lattice mismatch of different material layers in the semiconductor junction, stress can be introduced into the fin structure 11 in the semiconductor structure 1 to increase the channel stress.

[0125] Step S2104 : forming a bottom transistor 2 based on the second portion.

[0126] In one embodiment, transistor gate formation and back-end processes may be performed on the second portion of the fin structure 11 to form a bottom transistor. The process of forming the bottom transistor 2 based on the second portion may refer to the embodiments corresponding to FIG. 8 to FIG. 16 .

[0127] In step S2105 , the wafer is flipped over and the substrate 14 is removed to expose the first portion.

[0128] In one embodiment, as shown in FIG. 15 and FIG. 16 , after the fabrication process of the bottom transistor 2 is completed, the semiconductor structure 1 may be flipped over to expose the first portion of the fin structure 11 .

[0129] Step S2106 : forming a top-layer transistor 3 based on the first portion.

[0130] In one embodiment, after exposing the first portion of the fin structure 11, transistor gate formation and back-end processes can be performed on the first portion of the fin structure 11, thereby forming a top-layer transistor 3 and obtaining a semiconductor structure 1 in which the top-layer transistor 3 and the bottom-layer transistor 2 are stacked together. The process of forming the top-layer transistor 3 based on the first portion can be referred to the embodiments corresponding to Figures 17 to 19.

[0131] In the embodiments of the present disclosure, by sequentially depositing a first material layer and a second material layer with different lattice constants, the first and second portions of the fin structure formed after etching are formed of different material layers. Subsequently, the first and second portions formed of different material layers are used to form the bottom transistor and the top transistor, respectively, so that corresponding channel stress is generated in the fin structure shared by the bottom transistor and the top transistor. Based on the channel stress generated in the fin structure, the performance of the bottom transistor and the top transistor is matched, ensuring the normal operation of the top transistor and the bottom transistor.

[0132] In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes: a semiconductor structure as described in the above embodiments. The structure of the semiconductor structure can be referred to the semiconductor structure shown in Figures 19 and 20 above.

[0133] In some embodiments, the present disclosure provides an electronic device. The electronic device includes a circuit board and a semiconductor device according to the above embodiment, disposed on the circuit board. The semiconductor device includes the above-described semiconductor structure. The structure of the semiconductor structure can be seen in the semiconductor structure shown in Figures 19 and 20 above.

[0134] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0135] The above description is merely an exemplary embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, wherein: The method comprises: providing a substrate; forming a first material layer and a second material layer in sequence on the substrate, wherein the first material layer and the second material layer are made of materials with different lattice constants; Etching the first material layer and the second material layer to form a fin structure, wherein the fin structure includes a first portion formed by the etched first material layer and a second portion formed by the etched second material layer; Based on the second part, forming a bottom layer transistor; flipping the wafer and removing the substrate to expose the first portion; Based on the first portion, a top-layer transistor is formed.

2. The preparation method according to claim 1, wherein The first material layer is made of silicon germanium, and the second material layer is made of silicon; or, the first material layer is made of silicon, and the second material layer is made of silicon germanium.

3. The preparation method according to claim 1 or 2, wherein The step of forming a bottom layer transistor based on the second part includes: Filling oxide on the substrate to form a first shallow trench isolation layer; Etching the first shallow trench isolation layer to a preset height to form a second shallow trench isolation layer, wherein the height of the second shallow trench isolation layer is higher than the height of the first portion; A bottom transistor is formed above the second shallow trench isolation layer based on the second portion.

4. The preparation method according to claim 3, wherein After etching the first shallow trench isolation layer to a preset height to form a second shallow trench isolation layer, the method further includes: Ion implantation is performed at a connection between the first portion and the second portion to form an isolation layer, wherein the isolation layer is used to electrically isolate the first portion from the second portion.

5. The preparation method according to claim 4, wherein The ions implanted include P-type ions, N-type ions or oxygen ions.

6. The preparation method according to any one of claims 3 to 5, wherein The step of forming a top-layer transistor based on the first portion includes: Etching the second shallow trench isolation layer to a preset height to form a third shallow trench isolation layer; Forming a top-layer transistor on the third shallow trench isolation layer based on the first portion; The gate structure of the first transistor is separated from the gate structure of the second transistor by the third shallow trench isolation layer.

7. A semiconductor structure, manufactured by the method according to any one of claims 1 to 6, wherein: The semiconductor structure comprises: Bottom layer transistors; A top-layer transistor, wherein the top-layer transistor and the bottom-layer transistor are stacked; The first active structure in the bottom transistor and the second active structure in the top transistor form a fin structure, and the first active structure and the second active structure are made of materials with different lattice constants.

8. The semiconductor structure according to claim 7, wherein: The first gate structure in the bottom transistor and the second gate structure in the top transistor are arranged at two opposite ends of the fin structure.

9. The semiconductor structure according to claim 7 or 8, wherein: The first active structure is made of silicon germanium, and the second active structure is made of silicon; or the first active structure is made of silicon, and the second active structure is made of silicon germanium.

10. The semiconductor structure according to claim 9, wherein: A fourth shallow trench isolation layer is disposed between the first gate structure and the second gate structure, and the active structures made of silicon in the first active structure and the second active structure are wrapped by the fourth shallow trench isolation layer.

11. The semiconductor structure according to any one of claims 7 to 10, wherein: An isolation layer is provided at a connection between the first active structure and the second active structure, and the isolation layer is formed after ion implantation of the fin structure.

12. The semiconductor structure according to claim 11, wherein: The ions implanted include P-type ions, N-type ions or oxygen ions.

13. A semiconductor device comprising the semiconductor structure according to any one of claims 7 to 12.

14. An electronic device comprising: A circuit board, and a semiconductor device according to claim 13, wherein the semiconductor device is arranged on the circuit board.

Images