Semiconductor structure, manufacturing method therefor, semiconductor device, and electronic device

Abstract

Provided in the present disclosure are a semiconductor structure, a manufacturing method therefor, a semiconductor device and an electronic device. The method comprises: providing a substrate; forming an active structure on the substrate, the active structure comprising a first active structure and a second active structure; filling the active structure with an oxide to form shallow trench isolation; removing a first part of the shallow trench isolation so as to expose the first active structure; on the basis of the first active structure, forming a first transistor, a first gate structure of the first transistor wrapping the first active structure; depositing a first insulating layer on the top of the first transistor, and bonding the first insulating layer to a carrier wafer; flipping over the first transistor; removing the substrate and a second part of the shallow trench isolation so as to expose the second active structure; and, on the basis of the second active structure, forming a second transistor, a second gate structure of the second transistor wrapping the second active structure.

Description

Semiconductor structure and preparation method thereof, semiconductor device, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202310987830.7 and application date August 7, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof, a semiconductor device, and an electronic device. Background Art

[0004] As Moore's Law continues to deepen, further advancing transistor scaling is a hot topic in the industry. Stacked transistors, by integrating two or more layers of transistors vertically, further increase transistor integration density and become a key technology for further scaling integrated circuits.

[0005] In the related art, the process of manufacturing stacked transistors (CFETs) uses either a monolithic or sequential approach, both of which are difficult and complex to manufacture. Therefore, in order to simplify the process flow and reduce the difficulty of manufacturing, the manufacturing process of stacked transistors still needs to be continuously improved.

[0006] Summary of the Invention

[0007] The present disclosure provides a semiconductor structure and a preparation method thereof, a semiconductor device, and an electronic device.

[0008] The first aspect of the present disclosure provides a method for fabricating a semiconductor structure. The method includes: providing a substrate; forming an active structure on the substrate, the active structure including a first active structure and a second active structure; filling the active structure with oxide to form a shallow trench isolation; removing a first portion of the shallow trench isolation to expose the first active structure; forming a first transistor based on the first active structure, wherein a first gate structure of the first transistor wraps around the first active structure; depositing a first insulating layer on top of the first transistor and bonding the first insulating layer to a carrier wafer; flipping the first transistor; removing the substrate and a second portion of the shallow trench isolation to expose the second active structure; forming a second transistor based on the second active structure, wherein a second gate structure of the second transistor wraps around the second active structure.

[0009] A second aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a first transistor; and a second transistor, the second transistor being disposed opposite the first transistor; wherein a first active structure of the first transistor and a second active structure of the second transistor are formed in the same process; and a first gate structure of the first transistor wraps around the first active structure, and the second gate structure of the second transistor wraps around the second active structure.

[0010] The third aspect of the present disclosure provides a semiconductor device. The semiconductor device comprises: a semiconductor structure as provided in the second aspect above

[0011] A fourth aspect of the present disclosure provides an electronic device, comprising: a circuit board and the semiconductor device provided in the third aspect, wherein the semiconductor device is disposed on the circuit board.

[0012] The method for preparing the semiconductor structure disclosed in the present invention forms a first transistor based on a first active structure, and after flipping the wafer, forms a second transistor based on a second active structure, so that the active structures of the first transistor and the second transistor are "back-to-back" designed, achieving self-alignment of the first transistor and the second transistor, and making the active area of ​​the first transistor and the active area of ​​the second transistor consistent. At the same time, because the manufacturing methods of the first gate structure of the first transistor and the second gate structure of the second transistor are independent of each other, it has higher flexibility in circuit design. In addition, because the method for preparing the semiconductor structure disclosed in the present invention greatly simplifies the process flow of stacking transistors, reduces the difficulty of preparation, avoids expensive process development, saves costs, and has high practicality and industrial value.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0015] FIG1 is a schematic diagram of a first implementation flow of a method for preparing a semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0016] FIG2 is a schematic diagram of a first structure of a semiconductor structure provided according to an embodiment of the present disclosure.

[0017] FIG3A is a schematic diagram of a first manufacturing process of a first transistor provided according to an embodiment of the present disclosure.

[0018] FIG3B is a schematic diagram of a first manufacturing process of a second transistor provided according to an embodiment of the present disclosure.

[0019] FIG4 is a schematic diagram of a second structure of a semiconductor structure provided according to an embodiment of the present disclosure.

[0020] FIG5 is a schematic diagram of a third structure of a semiconductor structure provided according to an embodiment of the present disclosure.

[0021] FIG6A is a schematic diagram of a second manufacturing process of a first transistor according to an embodiment of the present disclosure.

[0022] FIG6B is a schematic diagram of a second manufacturing process of a second transistor provided according to an embodiment of the present disclosure.

[0023] FIG7 is a schematic diagram of a fourth structure of a semiconductor structure provided according to an embodiment of the present disclosure.

[0024] FIG8 is a fifth structural schematic diagram of a semiconductor structure provided according to an embodiment of the present disclosure.

[0025] FIG9A is a schematic diagram of a third manufacturing process of a first transistor provided according to an embodiment of the present disclosure.

[0026] FIG9B is a schematic diagram of a third manufacturing process of a second transistor provided according to an embodiment of the present disclosure.

[0027] FIG10 is a sixth structural schematic diagram of a semiconductor structure provided according to an embodiment of the present disclosure.

[0028] Explanation of the reference numerals: substrate 11; columnar structure 110; BOX 111; fin structure 11A; nanosheet 11B; block planar structure 11C; shallow trench isolation 12; upper half 12A of shallow trench isolation; lower half 12B of shallow trench isolation; shallow trench isolation layer 121; first transistor 13; first active structure 130; dummy gate 131 of the first transistor; first gate dielectric layer 132; first gate structure 133; back-end process 134 of the first transistor; first insulating layer 135; carrier wafer 136; source and drain 13SD of the first transistor; second transistor 14; second active structure 140; dummy gate 141 of the second transistor; second gate dielectric layer 142; second gate structure 143; back-end process 144 of the second transistor; second insulating layer 145; source and drain 14SD of the second transistor. DETAILED DESCRIPTION

[0029] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure.

[0030] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present disclosure. The singular forms "a," "the," and "the" used in the present disclosure are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0031] As Moore's Law continues to deepen, furthering transistor scaling is a hot topic in the industry. Stacked transistors, through three-dimensional transistor stacking, enable the integration of two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. This is considered a key technology for continuing the scaling of integrated circuits.

[0032] In one embodiment, there are two schemes for fabricating stacked field effect transistors (CFETs), the first being a monolithic scheme and the second being a sequential scheme.

[0033] The first solution is to fabricate N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate. This means that transistors on the same layer must be of the same type, either NFET or PFET. Furthermore, the upper and lower layers of transistors must be strictly in the same plane, with no alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex, requiring a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied upon to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, resulting in poor design flexibility.

[0034] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by pasting a wafer on the upper part of the already manufactured lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection line. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0035] The common technical difficulties faced by the above two solutions include: (1) the thermal stability of the bottom layer devices when making the upper layer devices; (2) the performance of the top layer devices under low thermal budget; and (3) the metal interconnection of transistors between layers.

[0036] In order to solve the above technical problems, the embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, a semiconductor device, and an electronic device, so as to simplify the process flow of stacking transistors and reduce the difficulty of preparation.

[0037] In the embodiments of the present disclosure, the semiconductor structure can be applied to semiconductor devices such as memories and processors.

[0038] In one embodiment, the semiconductor structure may include at least two transistors, taking a first transistor and a second transistor as an example. The first transistor and the second transistor are arranged back to back. The first active structure in the first transistor and the second active structure in the second transistor are formed by the same process. In this case, it can be understood that the first transistor and the second transistor share an active structure. In one embodiment, the gate structure of the first transistor (i.e., the first gate structure) wraps the first active structure so that the first active structure is not exposed; the gate structure of the second transistor (i.e., the second gate structure) wraps the second active structure so that the second active structure is not exposed.

[0039] In one embodiment, the first gate structure and the second gate structure are non-self-aligned in the vertical direction of the substrate. It is understood that the first gate structure and the second gate structure are prepared using two separate processes and are different in the vertical direction of the substrate, or the first gate structure and the second gate structure are different. Exemplarily, the first gate structure and the second gate structure can be made of different metal materials, such as the first gate structure can be made of one of the following metals: titanium nitride (TiN), titanium aluminum carbide (TiCAl), titanium aluminum nitride (TiAIN), titanium aluminum carbide (TiAlC), and the second gate structure can be made of one of the following metals, and a different metal than the first gate structure: titanium nitride (TiN), titanium aluminum compound (TiCAl), titanium aluminum carbide (TiAlC); the first gate structure and the second gate structure can have different dimensions in the vertical direction of the substrate, such as the length of the first gate structure is different from the length of the second gate structure; the first gate structure and the second gate structure can be made of different materials and have different dimensions, such as the first gate structure is made of TiN and the second gate structure is made of TiAlC, and the length and width of the first gate structure are greater than or less than the length of the second gate structure.

[0040] The preparation method provided by the embodiment of the present disclosure is described below in conjunction with the above-mentioned semiconductor structure.

[0041] FIG1 is a schematic diagram of a first implementation flow of a method for preparing a semiconductor structure according to an embodiment of the present disclosure. Referring to FIG1 , the method for preparing the semiconductor structure may include:

[0042] Step S101: providing a substrate.

[0043] In the embodiment of the present disclosure, the substrate may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Of course, it may also be a substrate of other semiconductor materials, which is not specifically limited in the embodiment of the present disclosure.

[0044] In one embodiment, an SOI substrate comprises a buried oxide (BOX) layer disposed between a top silicon layer and a back silicon substrate. The SOI substrate can achieve dielectric isolation between components in the integrated circuit, eliminating the parasitic latch-up effect found in bulk silicon CMOS circuits. Integrated circuits fabricated using SOI substrates also offer advantages such as low parasitic capacitance, high integration density, high speed, simple processing, minimal short-channel effects, and are particularly suitable for low-voltage, low-power circuits. In this example, the SOI substrate effectively isolates the first transistor from the second transistor.

[0045] In one embodiment, the thickness of the BOX layer in the SOI substrate ranges from 10 nm to 200 nm.

[0046] It should be noted that the etching process mentioned in the embodiments of the present disclosure may include any one of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process; the embodiments of the present disclosure are not limited to this.

[0047] Step S102: forming an active structure on the substrate.

[0048] In one embodiment, an active structure may be formed on the substrate 11 by etching the substrate 11. Here, there may be one or more active structures.

[0049] For example, anisotropic etching can be used on the substrate 11 to form active structures in the active region, such as fin structures 11A extending in the same direction (see FIG3A(b)); parallel nanosheets 11B (see FIG6A(b)); and bulk planar structures 11C (see FIG9A(b)). The active structure is fin structure 11A, and the transistor is a fin field effect transistor (FinFET); the active structure is multiple parallel nanosheets 11B, and the transistor is a gate-all-around field effect transistor (GAAFET); and the corresponding active structure is bulk planar structure 11C, and the transistor is a planar transistor.

[0050] For ease of explanation, the following steps S103 to S108 are described using an example in which both the first transistor and the second transistor are FinFETs.

[0051] Step S103 , filling the active structure with oxide to form shallow trench isolation.

[0052] In some embodiments, after etching the substrate 11 in step S102 , trenches are formed at the etched locations, and oxide may be filled at the trench locations to form shallow trench isolation (STI) 12 (see FIG. 3A (c) ).

[0053] In some embodiments, the oxide forming the shallow trench isolation 12 may be silicon nitride (SiN, Si 3 N 4 ), silicon dioxide (SiO 2 ), or silicon oxycarbide (SiCO).

[0054] In some embodiments, in order to facilitate subsequent processing, after step S103, the shallow trench isolation 12 can also be polished or chemical-mechanical planarization (CMP) treated so that when the shallow trench isolation 12 is subsequently etched, the corrosion depths corresponding to the shallow trench isolation 12 in different areas are the same, thereby making the top heights of the exposed active structures the same.

[0055] Step S104 , removing a first portion of the shallow trench isolation to expose the first active structure.

[0056] In some embodiments, the shallow trench isolation 12 is divided into two parts, an upper part and an lower part. The upper part 12A (i.e., the first part (see (c) of FIG. 3A )) of the shallow trench isolation 12 can be etched first to expose the upper part of the active structure (i.e., the first active structure 130) (see (d) of FIG. 3A ). The solvent used for etching the shallow trench isolation 12 can be: DHF solution or BOE solution. The solvent used in the etching process of the embodiments of the present disclosure can be selected according to actual conditions and is not limited to the above-mentioned DHF solution or BOE solution.

[0057] Step S105 : forming a first transistor based on the first active structure.

[0058] In some embodiments, based on the exposed first active structure 130, front-end processes (such as forming isolation, gate structure, source and drain, contact holes, etc.) and back-end processes 134 (such as depositing dielectrics between interconnect lines, forming metal lines, forming lead pads, etc.) can be performed to form a transistor (i.e., the first transistor 13) (see (g) and (h) of Figure 3A).

[0059] Step S106: depositing a first insulating layer on top of the first transistor and bonding the first insulating layer to the carrier wafer.

[0060] In some embodiments, after the first transistor 13 is fabricated, a first insulating layer 135 is deposited on top of the first transistor 13 , and then a pre-prepared carrier wafer 136 is bonded to the first insulating layer 135 (see (h) in FIG. 3A ).

[0061] Step S107 , flipping the first transistor.

[0062] The upper portion of the semiconductor structure described in the embodiment of the present disclosure has been fabricated. Next, the fabricated first transistor 13 is flipped over, with the substrate 11 facing upward (see (i) in FIG. 3A ), for subsequent fabrication.

[0063] In step S108 , the substrate and the second portion of the shallow trench isolation are removed to expose the second active structure.

[0064] In some embodiments, after flipping the wafer, the substrate 11 is first etched to expose the lower half 12B (i.e., the second portion) of the shallow trench isolation 12 (see (a) in FIG. 3B ), and then the lower half of the shallow trench isolation 12 is etched using the same method as step S104 until the lower half of the active structure (i.e., the second active structure 140) is exposed (see (b) in FIG. 3B ).

[0065] In some embodiments, during the etching process of the lower portion 12B of the shallow trench isolation 12, after exposing the second active structure 140, etching can be stopped when the etching reaches a predetermined height. In this way, a portion of the shallow trench isolation 12 is retained. This retained portion of the shallow trench isolation can be referred to as a shallow trench isolation layer 121 (see (b) in FIG. 3B ). Here, the shallow trench isolation layer 121 can be used to isolate the first transistor 13 from the second transistor 14. The thickness of the shallow trench isolation layer 121 can be designed according to specific circumstances and is not specifically limited in the present embodiment.

[0066] It should be noted that the above-mentioned “isolation” can be understood as physical isolation or electrical isolation.

[0067] Step S109 : forming a second transistor based on the second active structure.

[0068] In some embodiments, a transistor (ie, the second transistor 14 ) may be formed based on the second active structure 140 using the same method as step S105 (see (e) in FIG. 3B ).

[0069] In the embodiment of the present disclosure, the first transistor 13 and the second transistor 14 in the semiconductor structure can be transistors of the same type, such as any of the following: a fin field-effect transistor, a gate-all-around transistor, and a planar transistor. Therefore, the semiconductor structure can also be specifically designed according to the different types of transistors.

[0070] The method for preparing the semiconductor structure in the embodiment of the present disclosure forms a first transistor based on a first active structure, and after flipping the wafer, forms a second transistor based on a second active structure, so that the active structures of the first transistor and the second transistor are "back-to-back" designed, achieving self-alignment of the first transistor and the second transistor, and making the active area of ​​the first transistor and the active area of ​​the second transistor consistent. At the same time, because the manufacturing methods of the first gate structure of the first transistor and the second gate structure of the second transistor are independent of each other, it has higher flexibility in circuit design. In addition, because the manufacturing method of the semiconductor structure described in the present disclosure greatly simplifies the process flow of stacking transistors, reduces the difficulty of manufacturing, avoids high process development, saves costs, and has high practicality and industrial value.

[0071] Below, the semiconductor structure provided by the embodiment of the present disclosure is described by taking the first transistor and the second transistor as fin field-effect transistors as an example. Figure 2 is a schematic diagram of the first structure of the semiconductor structure provided according to the embodiment of the present disclosure. (a) in Figure 2 is a design layout of the semiconductor structure. It should be noted that, for ease of understanding, the design layout only shows the fin structure, gate structure and source and drain electrodes; (b) is a cross-sectional view of the semiconductor structure taken along the cross section of the active structure (i.e., the AA' direction); (c) is a cross-sectional view of the semiconductor structure taken along the longitudinal section of the source and drain electrodes (i.e., the BB' direction); and (d) is a cross-sectional view of the semiconductor structure taken along the cross section of the gate structure (i.e., the CC' direction).

[0072] FIG3A is a schematic diagram of a first manufacturing process for a first transistor according to an embodiment of the present disclosure, and FIG3B is a schematic diagram of a first manufacturing process for a second transistor according to an embodiment of the present disclosure. Referring to FIG2 (a) to (c) and FIG3A and FIG3B , the first active structure 130 in the first transistor 13 and the second active structure 140 in the second transistor 14 are multiple fin structures 11A. The first active structure 130 and the second active structure 140 are active structures formed in the same process. The upper half of the active structure serves as the first active structure 130 in the first transistor 13, and the lower half of the active structure serves as the second active structure 140 in the second transistor 14. A shallow trench isolation layer 121 is also provided between the first transistor 13 and the second transistor 14. The shallow trench isolation layer 121 is used to isolate the first transistor 13 from the second transistor 14.

[0073] As shown in FIG2( b ), in the first transistor 13, a first gate structure 133 wraps around the first active structure 130. A first gate dielectric layer 132 is provided between the first gate structure 133 and the first active structure 130. The first gate dielectric layer 132 is used to isolate the first active structure 130 from the first gate structure 133. The structure of the second transistor 14 is substantially similar to that of the first transistor 13.

[0074] As shown in (c) and (d) of FIG. 2 , the source-drain 13SD of the first transistor 13 and the source-drain 14SD of the second transistor 14 are arranged opposite to each other.

[0075] In some embodiments, the structure of the second transistor 14 may be different from that of the first transistor 13. In one example, the second gate dielectric layer 142 of the second transistor 14 and the first gate dielectric layer 132 of the first transistor 13 may be made of different materials; in another example, the first gate structure 133 and the second gate structure 143 may be made of different materials.

[0076] In some embodiments, the second gate structure 143 in the second transistor 14 is asymmetrical with the first gate structure 133 in the first transistor 13 in a direction perpendicular to the substrate. For example, as shown in FIG2( b ), in the cross-sectional view taken along the AA′ direction, the length of the second gate structure 143 is significantly greater than the length of the first gate structure 133. This allows for more flexible design of the structures of the first transistor 13 and the second transistor 114 in the semiconductor structure according to actual needs.

[0077] It should be noted that the semiconductor structure shown in FIG2 is only one example. The first gate structure 133 and the second gate structure 143 may adopt other forms to realize an asymmetric design in the vertical direction of the substrate 11 , and the embodiments of the present disclosure do not specifically limit this.

[0078] In the embodiment of the present disclosure, the first active structure of the first transistor and the second active structure of the second transistor are formed through the same process, so that self-alignment of the first transistor and the second transistor can be achieved, and the active area of ​​the first transistor and the active area of ​​the second transistor are consistent.

[0079] The following describes the preparation process of the semiconductor structure shown in FIG. 2 in combination with the above preparation method.

[0080] In one example, taking the first transistor 13 and the second transistor 14 as fin field-effect transistors, a first manufacturing process of the semiconductor structure may include the following steps:

[0081] Step 1: providing a substrate 11 and forming a plurality of fin structures 11A on the substrate 11 by etching the substrate 11 (see (b) in FIG. 3A ).

[0082] In some embodiments, substrate 11 is anisotropically etched to form multiple fin structures 11A extending in the same direction. Fin structures 11A have a height greater than 100 nm. Substrate 11 may be a silicon substrate or an SOI substrate. Materials for the silicon substrate may include, but are not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), and silicon carbide (SiC).

[0083] Step 2: Depositing oxide in the recesses between the multiple fin structures 11A and on both sides of the multiple fin structures 11A to form shallow trench isolations 12), and planarizing the shallow trench isolations 12 (see (c) in FIG. 3A ).

[0084] In some embodiments, the oxide may include, but is not limited to, any of the following: SiN, Si 3 N 4 , SiO 2 or SiCO. The thickness of the oxide deposition should be such that the height of the shallow trench isolation 12 is consistent with the height of the fin.

[0085] Step 3: Etch the upper portion 12A of the shallow trench isolation 12 to expose the upper portion of the plurality of fin structures 11A (i.e., the first active structure 130). Ion implantation is performed at the boundary between the exposed upper portion of the plurality of fin structures 11A and the unexposed lower portion to form an electrical isolation layer (not shown).

[0086] In some embodiments, the solvent used to etch the shallow trench isolation 12 may be a DHF solution or a BOE solution. The ions implanted include P-type ions, N-type ions, or oxygen ions. The P-type ions may be one of the following: boron (B), gallium (Ga), or aluminum (Al). The N-type ions may be one of the following: phosphorus (P), arsenic (As), or antimony (Sb).

[0087] Step 4: Based on the exposed upper portions of the multiple fin structures 11A, polysilicon is deposited in the recesses between the multiple fin structures 11A and on both sides of the multiple fin structures 11A. The deposited polysilicon serves as the dummy gate 131 of the first transistor 13 (see (e) in FIG. 3A ).

[0088] In some embodiments, the deposition height of the polysilicon is greater than the height of the upper portions of the plurality of fins, that is, the polysilicon covers the plurality of fin structures 11A.

[0089] It should be noted that after forming the dummy gate 131 of the first transistor 13, spacer structures (not shown in the figure) may be formed on both sides of the dummy gate 131 of the first transistor 13. The material of the spacer structure may include, but is not limited to, silicon nitride, silicon carbide, silicon oxynitride, etc. In some embodiments, the spacer structure may be formed by a dielectric deposition and etching process.

[0090] Step 5: Etch the dummy gate 131 of the first transistor 13 until the upper portion of the multiple fin structures 11A is exposed again, and form the first transistor 13 based on the exposed multiple fin structures 11A (see (e), (f) and (g) in Figure 3A).

[0091] In some embodiments, the fifth step is as follows: after forming the dummy gate 131 of the first transistor 13, the dummy gate 131 of the first transistor 13 can be etched to expose the upper half of the multiple fin structures 11A again. Source and drain materials are grown in the recesses between the multiple fin structures 11A to form source and drain electrodes 13SD. A first gate dielectric layer 132 is deposited on the surface of the exposed upper half of the multiple fin structures 11A. The first gate dielectric layer 132 is a high dielectric constant layer. Specifically, the first gate dielectric layer 132 may include but is not limited to materials with higher dielectric constants such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2) or aluminum oxide (Al2O3). The thickness of the first gate dielectric layer 132 can be set according to the specific situation, and the embodiments of the present disclosure are not limited to this. After the first gate dielectric layer 132 is deposited, metal material is deposited in the recesses between the multiple fin structures 11A and on both sides of the multiple fin structures 11A so that the height of the deposited metal material is greater than the height of the multiple fin structures 11A. The deposited metal material becomes the first gate structure 133 of the first transistor 13, and the first gate structure 133 completely covers the upper half of the multiple fin structures 11A. The first gate structure 133 can be a stack of any one or more of the following materials: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). It should be noted that the material of the first gate structure 133 is not limited to the materials listed above. After the back-end process 134 of the first transistor 13 is completed above the first gate structure 133, the first transistor 13 is completed.

[0092] Step 6: Deposit a first insulating layer 135 on the back-end process 134 of the first transistor 13. The material of the first insulating layer 135 can be silicon oxide. Bond the carrier wafer 136 to the first transistor 13 above the first insulating layer 135, and flip the first transistor 13 (see (h) and (i) in Figure 3A).

[0093] In some embodiments, the bonded carrier wafer 136 can provide physical support for the flipped first transistor 13 after flipping, effectively preventing the first transistor 13 from being broken during the process of preparing the second transistor 14 .

[0094] Step 7: Etch the substrate 11 and the lower portion 12B of the shallow trench isolation 12 to expose the lower portion of the plurality of fin structures 11A (ie, the second active structure 140 ) (see (a) and (b) in FIG. 3B ).

[0095] In some embodiments, after the first transistor 13 is flipped over, the substrate 11 is placed upward, and a portion of the substrate 11 is etched first until the edge portion of the shallow trench isolation 12 and the multiple fin-like structures 11A are exposed, and then the lower half 12B of the shallow trench isolation 12 is etched. It should be noted that in the process of etching the lower half 12B of the shallow trench isolation 12, a certain thickness of shallow trench isolation layer 121 can be retained. This shallow trench isolation layer 121 can play the role of isolating the first transistor 13 and the second transistor 14. The thickness of the shallow trench isolation layer 121 is set according to the specific situation, and the embodiments of the present disclosure are not limited to this. After etching the lower half 12B of the shallow trench isolation 12, the lower half of the multiple fin-like structures 11A are also exposed.

[0096] Step 8: Based on the exposed lower half of the above-mentioned multiple fin structures 11A, polysilicon is deposited in the recesses between the multiple fin structures 11A and on both sides of the multiple fin structures 11A. The deposited polysilicon is the pseudo gate 141 of the second transistor 14 (see (c) in Figure 3B). The specific process can be found in Step 4.

[0097] Step 9: Etch the dummy gate 141 of the second transistor 14 until the lower half of the multiple fin structures 11A is exposed again, and form a second gate structure 143 of the second transistor 14 based on the exposed lower half of the multiple fin structures 11A. Then complete the back-end process 144 of the second transistor 13 and deposit a second insulating layer 145 (see (d) and (e) in Figure 3B). The process can be referred to in step 5.

[0098] It should be noted that the substrate used in Figures 3A and 3B is a silicon substrate. When the substrate is an SOI substrate, the preparation method is the same as the steps shown in Figures 3A and 3B. However, since the BOX in the SOI substrate is a natural isolation layer, the ion implantation process can be omitted. The first active structure 130 of the first transistor and the second active structure 140 of the second transistor can be electrically isolated by the BOX. The schematic diagram of the resulting semiconductor structure is shown in Figure 4. Figure 4 is a schematic diagram of the second structure of the semiconductor structure provided according to an embodiment of the present disclosure. Figure 4 (a) is a design layout of the semiconductor structure. It should be noted that for ease of understanding, only the fin structure, gate structure and source and drain are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure taken along the cross section of the active structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure taken along the longitudinal cross section of the source and drain (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure taken along the cross section of the gate structure (i.e., CC' direction). As shown in FIG. 4 , the BOX 111 is located between the first active structure 130 and the second active structure 140 . The BOX 111 can achieve electrical isolation between the first active structure 130 and the second active structure 140 .

[0099] Below, taking the first transistor and the second transistor as full-surround gate transistors as an example, the third structural schematic diagram of the semiconductor structure is described. Figure 5 is a third structural schematic diagram of the semiconductor structure provided according to an embodiment of the present disclosure. (a) in Figure 5 is a design layout of the semiconductor structure. It should be noted that, for ease of understanding, only the nanosheet, gate structure and source and drain are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure along the cross section of the active structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the longitudinal section of the source and drain (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross section of the gate structure (i.e., CC' direction).

[0100] As shown in FIG5 , the first active structure 130 in the first transistor 13 and the second active structure 140 in the second transistor 14 are multiple parallel nanosheets. The first active structure 130 and the second active structure 140 are formed in the same process. The upper half of the active structure serves as the first active structure 130 in the first transistor 13, and the lower half of the active structure serves as the second active structure 140 in the second transistor 14. The semiconductor structure shown in FIG5 is identical to the first active structure 130 and the second active structure 140 in FIG2 , except that the first active structure 130 and the second active structure 140 differ.

[0101] Figure 6A is a schematic diagram of the second preparation process of the first transistor provided according to an embodiment of the present disclosure, and Figure 6B is a schematic diagram of the second preparation process of the second transistor provided according to an embodiment of the present disclosure. Below, the second preparation process of the semiconductor structure provided by the embodiment of the present disclosure is described in combination with Figure 5, Figure 6A and Figure 6B.

[0102] In another example, taking the first transistor 13 and the second transistor 14 as all-around gate transistors as an example, the second preparation process of the semiconductor structure may include the following steps:

[0103] The first step is to provide a substrate 11 and form a columnar structure 110 on the substrate 11 by etching the substrate 11 (see (a) and (b) in FIG. 6A ).

[0104] In some embodiments, substrate 11 may be a silicon substrate or an SOI substrate. When substrate 11 is a silicon substrate, the silicon substrate is formed by sequentially stacking two different semiconductor materials (i.e., a first semiconductor material and a second semiconductor material). The two semiconductor materials may be a combination of any two of the following materials: silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), and silicon carbide (SiC). Substrate 11 is anisotropically etched to form a columnar structure 110 extending vertically along substrate 11.

[0105] Step 2: Deposit oxide on both sides of the columnar structure 110 to form shallow trench isolation 12, and perform planarization on the shallow trench isolation 12 (see (c) in FIG. 6A). The specific process can refer to the second step of the first method for preparing the semiconductor structure.

[0106] Step 3: Etch the upper portion 12A (i.e., the first portion) of the shallow trench isolation 12 to expose the upper portion of the columnar structure 110 (i.e., the first active structure 130) (see (d) in FIG. 6A ). Ion implantation is performed at the boundary between the exposed upper portion and the unexposed lower portion of the columnar structure 110 to form an electrical isolation layer (not shown). For detailed process details, refer to step 3 of the first method for fabricating a semiconductor structure.

[0107] Step 4: Based on the exposed upper portion of the columnar structure 110, polysilicon is deposited on both sides and above the columnar structure 110. The deposited polysilicon serves as the dummy gate 131 of the first transistor 13 (see (e) in FIG. 6A ). For the specific process, refer to step 4 of the first method for fabricating a semiconductor structure.

[0108] Step 5: Etch the dummy gate 131 of the first transistor 13 until the upper portion of the columnar structure 110 is exposed again. For the specific process, please refer to the fifth step of the first method for preparing the semiconductor structure.

[0109] Step 6: Using a selective etching process, the first semiconductor material of the columnar structure 110 is removed by etching, and the unetched second semiconductor material is distributed in a sheet-like manner, thereby forming a plurality of parallel nanosheets 11B in the first transistor 13 (see (f) in FIG. 6A ).

[0110] Step 7: Forming a first transistor 13 based on the plurality of nanosheets 11B (see (g) in FIG6A ). For the specific process, reference may be made to step 5 of the first method for preparing a semiconductor structure.

[0111] Step 8: Deposit a first insulating layer 135 on the back-end process 134 of the first transistor 13. The material of the first insulating layer 135 may be silicon oxide. A carrier wafer 136 is bonded to the first transistor 13 above the first insulating layer 135. The first transistor 13 is then flipped over (see (h) and (i) in FIG. 6A ). For the specific process, refer to step 6 of the first method for preparing a semiconductor structure.

[0112] Step 9: Fabricate the second transistor 14 (see FIG6B ). The steps of fabricating the second transistor 14 after flipping the wafer can refer to steps 7 to 9 of the first method for fabricating the semiconductor structure.

[0113] It should be noted that the substrate used in Figures 6A and 6B is a silicon substrate. When the substrate is an SOI substrate, the preparation method is the same as the steps shown in Figures 6A and 6B. However, since the BOX in the SOI substrate is a natural isolation layer, the ion implantation process can be omitted. The nanosheet of the first transistor (i.e., the first active structure 130) and the nanosheet of the second transistor (i.e., the second active structure 140) are electrically isolated by the BOX. A schematic diagram of the final semiconductor structure is shown in Figure 7. Figure 7 is a schematic diagram of the fourth structure of the semiconductor structure provided according to an embodiment of the present disclosure. Figure 7 (a) is a design layout of the semiconductor structure. It should be noted that for ease of understanding, the design layout only shows the nanosheet, gate structure, and source and drain electrodes; (b) is a cross-sectional view of the semiconductor structure taken along the cross section of the active structure (i.e., the AA' direction); (c) is a cross-sectional view of the semiconductor structure taken along the longitudinal cross section of the source and drain electrodes (i.e., the BB' direction); and (d) is a cross-sectional view of the semiconductor structure taken along the cross section of the gate structure (i.e., the CC' direction). As shown in FIG. 7 , the BOX 111 is located between the first active structure 130 and the second active structure 140 . The BOX 111 can achieve electrical isolation between the first active structure 130 and the second active structure 140 .

[0114] Below, taking the first transistor and the second transistor as planar transistors as an example, the fifth structural schematic diagram of the semiconductor structure is described. Figure 8 is a fifth structural schematic diagram of the semiconductor structure provided according to an embodiment of the present disclosure. (a) in Figure 8 is a design layout of the semiconductor structure. It should be noted that, for ease of understanding, only the block planar structure, gate structure and source and drain are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure along the cross section of the active structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the longitudinal section of the source and drain (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross section of the gate structure (i.e., CC' direction).

[0115] As shown in FIG8 , the first active structure 130 in the first transistor 13 and the second active structure 140 in the second transistor 14 are block-shaped planar structures. The first active structure 130 and the second active structure 140 are block-shaped planar structures 11C formed in the same process. The upper half of the active structure serves as the first active structure 130 in the first transistor 13, and the lower half of the active structure serves as the second active structure 140 in the second transistor 14. The semiconductor structure shown in FIG8 is identical to the first active structure 130 and the second active structure 140 in FIG2 , except that the first active structure 130 and the second active structure 140 are different.

[0116] Figure 9A is a schematic diagram of the third preparation process of the first transistor provided according to an embodiment of the present disclosure, and Figure 9B is a schematic diagram of the third preparation process of the second transistor provided according to an embodiment of the present disclosure. Below, the third preparation process of the semiconductor structure provided by the embodiment of the present disclosure is described in combination with Figures 8, 9A and 9B.

[0117] In another example, taking the first transistor 13 and the second transistor 14 as planar transistors as an example, the third preparation process of the semiconductor structure may include the following steps:

[0118] The first step is to provide a substrate 11 and to form a block-shaped planar structure 11C on the substrate 11 by etching both sides of the substrate 11 (see (a) and (b) in FIG. 9A ). The block-shaped planar structure 11C is smaller than the substrate 11 in length.

[0119] Step 2: Deposit oxide on both sides of the block planar structure 11C to form shallow trench isolation 12, and perform planarization on the shallow trench isolation 12 (see (c) in FIG. 9A). This process can be the second step of the first method for preparing a semiconductor structure.

[0120] Step 3: Etch the upper half (i.e., the first portion) of the shallow trench isolation 12 to expose the upper half of the block planar structure 11C (i.e., the first active structure 130) (see (d) in FIG. 9A ). Ion implantation is performed at the boundary between the exposed upper half of the block planar structure 11C and the unexposed lower half to form an electrical isolation layer (not shown). For the specific process, refer to step 3 of the first method for preparing a semiconductor structure.

[0121] Step 4: Based on the exposed upper portion of the block planar structure 11C, polysilicon is deposited on both sides of the block planar structure 11C. The deposited polysilicon serves as the dummy gate 131 of the first transistor 13 (see (e) in FIG. 9A ). The process can refer to step 4 of the first method for fabricating a semiconductor structure.

[0122] Step 5: Etch the dummy gate 131 of the first transistor 13 until the upper portion of the block planar structure 11C is exposed again, and form the first transistor 13 based on the exposed block planar structure 11C (see (f) and (g) in FIG. 9A ). The process can refer to step 5 of the first method for preparing a semiconductor structure.

[0123] Step 6: Deposit a first insulating layer 135 on the back-end process 134 of the first transistor 13. The material of the first insulating layer 135 may be silicon oxide. A carrier wafer 136 is bonded to the first transistor 13 above the first insulating layer 135. The first transistor 13 is then flipped over (see (h) and (i) in FIG. 9A ). The process can be referred to as step 6 of the first method for preparing a semiconductor structure.

[0124] Step 7: Fabricate the second transistor 14. The steps of fabricating the second transistor 14 after flipping the wafer can refer to steps 7 to 9 of the first method for fabricating the semiconductor structure (see FIG. 9B ).

[0125] It should be noted that the substrate used in Figures 9A and 9B above is a silicon substrate. When the substrate is an SOI substrate, the preparation method is the same as the steps shown in Figures 9A and 9B. However, since the BOX in the SOI substrate is a natural isolation layer, the ion implantation process can be omitted. The block planar structure of the first transistor (i.e., the first active structure 130) and the block planar structure of the second transistor (i.e., the second active structure 140) are electrically isolated by the BOX. A schematic diagram of the resulting semiconductor structure is shown in Figure 10. Figure 10 is a schematic diagram of the sixth structure of the semiconductor structure provided according to an embodiment of the present disclosure. Figure 10 (a) is a design layout of the semiconductor structure. It should be noted that for ease of understanding, the design layout only shows the block planar structure, gate structure, and source and drain electrodes; (b) is a cross-sectional view of the semiconductor structure taken along the cross section of the active structure (i.e., the AA' direction); (c) is a cross-sectional view of the semiconductor structure taken along the longitudinal cross section of the source and drain electrodes (i.e., the BB' direction); and (d) is a cross-sectional view of the semiconductor structure taken along the cross section of the gate structure (i.e., the CC' direction). As shown in FIG. 10 , the BOX 111 is located between the first active structure 130 and the second active structure 140 . The BOX 111 can achieve electrical isolation between the first active structure 130 and the second active structure 140 .

[0126] In the embodiment of the present disclosure, the semiconductor structure is prepared by the above three methods. Since the first gate structure 133 of the first transistor 13 and the second gate structure 143 of the second transistor 4 are completed in different process steps, the first gate structure 133 of the first transistor 13 and the second gate structure 143 of the second transistor 14 can be asymmetric in the vertical direction of the substrate. When designing the semiconductor structure, the first gate structure 133 and the second gate structure 143 can be set to different sizes according to the specific situation, so that the design flexibility of the semiconductor structure is higher; in addition, the materials of the first gate structure 133 and the second gate structure 143 can be the same or different, and the embodiment of the present disclosure does not limit this. In addition, the materials of the first gate dielectric layer 132 of the first transistor 13 and the second gate dielectric layer 142 of the second transistor 14 are different, and can be set according to actual conditions.

[0127] An embodiment of the present disclosure provides a semiconductor device, comprising: the semiconductor structure as described in the above embodiment.

[0128] An embodiment of the present disclosure provides an electronic device, including: a circuit board and the semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0129] In the description of the present disclosure, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present disclosure. In the present disclosure, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present disclosure and features of different embodiments or examples without mutual contradiction.

[0130] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0131] The above description is merely an exemplary embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, comprising: providing a substrate; forming an active structure on the substrate, the active structure comprising a first active structure and a second active structure; Filling the active structure with oxide to form shallow trench isolation; removing a first portion of the shallow trench isolation to expose the first active structure; Based on the first active structure, forming a first transistor, wherein a first gate structure of the first transistor wraps the first active structure; Depositing a first insulating layer on top of the first transistor, and bonding the first insulating layer to a carrier wafer; Flipping the first transistor; removing the substrate and a second portion of the shallow trench isolation to expose the second active structure; A second transistor is formed based on the second active structure, wherein a second gate structure of the second transistor wraps the second active structure.

2. The method according to claim 1, wherein: The first gate structure and the second gate structure are not self-aligned in a vertical direction of the substrate.

3. The method according to claim 1 or 2, wherein: The method further comprises: Depositing a first gate dielectric layer on the surface of the first active structure to isolate the first gate structure from the first active structure; Depositing a second gate dielectric layer on the surface of the second active structure to isolate the second gate structure from the second active structure; The first gate dielectric layer and the second gate dielectric layer are made of different materials.

4. The method according to claim 3, wherein: After depositing a first gate dielectric layer on the surface of the first active structure, the method further includes: forming the first gate structure on the first gate dielectric layer; A back-end process is performed on the first gate structure to form the first transistor.

5. The method according to claim 3 or 4, wherein: After depositing a second gate dielectric layer on the surface of the second active structure, the method further includes: forming the second gate structure on the second gate dielectric layer; A back-end process is performed on the second gate structure to form the second transistor.

6. The method according to any one of claims 1 to 5, wherein: The removing of the substrate and the second portion of the shallow trench isolation comprises: removing the substrate; The second portion of the shallow trench isolation is etched to a preset height to form a shallow trench isolation layer, wherein the shallow trench isolation layer is used to isolate the first transistor from the second transistor.

7. The method according to any one of claims 1 to 6, wherein: After forming an active structure on the substrate, the method further comprises: Ion implantation is performed at a connection between the first active structure and the second active structure to form an electrical isolation layer, wherein the electrical isolation layer is used to electrically isolate the first active structure from the second active structure.

8. The method according to claim 7, wherein: The ions implanted include P-type ions, N-type ions or oxygen ions.

9. The method according to any one of claims 1 to 8, wherein: The first transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor; the second transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor.

10. The method according to claim 9, wherein: The forming of an active structure on the substrate comprises one of the following: removing a portion of the substrate to form at least one fin structure; removing a portion of the substrate to form a plurality of nanosheets or nanowires arranged in parallel; A portion of the substrate is removed to form a block-like planar structure.

11. A semiconductor structure comprising: a first transistor; a second transistor, the second transistor being arranged opposite to the first transistor; The first active structure of the first transistor and the second active structure of the second transistor are formed by the same process; the first gate structure of the first transistor wraps the first active structure, and the second gate structure of the second transistor wraps the second active structure.

12. The semiconductor structure according to claim 11, wherein: A shallow trench isolation layer is provided between the first gate structure and the second gate structure, and the shallow trench isolation layer is used to isolate the first transistor from the second transistor.

13. The semiconductor structure according to claim 11 or 12, wherein: The first gate structure and the second gate structure are asymmetric in a vertical direction of the substrate.

14. The semiconductor structure according to any one of claims 11 to 13, wherein: An electrical isolation layer is provided between the first active structure and the second active structure.

15. The semiconductor structure according to any one of claims 11 to 14, wherein: The first transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor; the second transistor is one of a fin field effect transistor, a gate-all-around transistor and a planar transistor.

16. The semiconductor structure according to claim 15, wherein: The first active structure and the second active structure constitute an active structure, and the active structure is at least one of the following: Fin-like structure; Nanosheets; Nanowires; Blocky planar structure.

17. A semiconductor device comprising: A semiconductor structure as claimed in any one of claims 11 to 16.

18. An electronic device, comprising: A circuit board and a semiconductor device as claimed in claim 17, wherein the semiconductor device is arranged on the circuit board.

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