Vapor deposition mask and electronic device manufacturing method

Abstract

Provided are: a vapor deposition mask capable of forming a vapor deposition film having excellent pattern dimensions; and an electronic device manufacturing method that utilizes the vapor deposition mask. This vapor deposition mask is a vapor deposition mask for depositing a vapor deposition material from a vapor deposition source onto a surface of a vapor deposition substrate through an opening, the vapor deposition mask being disposed between the vapor deposition substrate and the vapor deposition source. The vapor deposition mask is characterized: by having a first surface facing the vapor deposition substrate side and a second surface positioned on the opposite side from the first surface and facing the vapor deposition source side; in that a plurality of openings penetrating the vapor deposition mask between the first surface and the second surface are formed; in that the width of each opening is greater than 3 μm and equal to or less than 5 μm; in that the side wall surface of the opening is inclined so that the opening width decreases from the second surface side toward the first surface side; and in that the taper angle of the opening is greater than 50°.

Description

Evaporation mask and method for manufacturing electronic device

[0001] The present invention relates to a deposition mask and a method for manufacturing an electronic device.

[0002] For example, a deposition mask is known that is used to paint three colors, RGB, in the production of organic EL displays.

[0003] Patent Document 1 discloses a configuration in which, when forming a plurality of openings in a deposition mask, the openings are formed separately into a first portion and a second portion, and the first portion is inclined, but does not disclose the taper angle.

[0004] Patent Document 2 discloses a deposition mask in which the sidewall surfaces of a grid thin film layer made of silicon nitride are formed as inclined surfaces.

[0005] JP 2022-184708 A U.S. Patent Application Publication No. 2020 / 0044010

[0006] The inclination of the sidewalls of the opening formed in the semiconductor layer causes deposition material to accumulate on the sidewalls, resulting in a problem of deterioration in the pattern dimensions of the deposited film.

[0007] An object of the present invention is to provide a deposition mask capable of forming a deposition film having excellent pattern dimensions, and a method for manufacturing an electronic device using the deposition mask.

[0008] The deposition mask of the present embodiment is a deposition mask that is disposed between a substrate to be deposited and a deposition source, and that deposits a deposition material from the deposition source onto a surface of the substrate to be not deposited through openings. The deposition mask has a first surface facing the substrate to be deposited and a second surface located opposite the first surface and facing the deposition source. The deposition mask has a plurality of openings that penetrate between the first surface and the second surface, each opening has a width greater than 3 μm and not more than 5 μm, and sidewall surfaces of the openings are inclined such that the opening width narrows from the second surface side toward the first surface side, and a taper angle of the openings is greater than 50°.

[0009] According to the present invention, by controlling the opening width and taper angle of the opening in the deposition mask, a deposition film having excellent pattern dimensions can be stably formed. Furthermore, the frequency of cleaning the deposition mask can be reduced, facilitating quality control of the deposition mask. Furthermore, the occurrence of clogging of the opening can be reduced, thereby extending the life of the deposition mask.

[0010] FIG. 1 is a cross-sectional view showing an example of a deposition mask according to the present embodiment; FIG. 2 is a cross-sectional view showing an enlarged view of a part of the deposition mask according to the present embodiment shown in FIG. 1; FIG. 3 is a partially enlarged cross-sectional view showing an enlarged view of a part of an opening of the deposition mask according to the present embodiment; FIG. 4 is a cross-sectional view showing a manufacturing method of an electronic device using the deposition mask according to the present embodiment; FIG. 5 is a process diagram showing an example of a manufacturing method of the deposition mask according to the present embodiment; FIG. 6 is a process diagram showing an example of a manufacturing method of the deposition mask according to the present embodiment; FIG. 7 is a cross-sectional view showing an example of a deposition mask according to another embodiment; FIG. 8 is a cross-sectional view showing an example of a deposition mask according to another embodiment; FIG. 9 is a cross-sectional view showing an example of a deposition mask according to another embodiment;

[0011] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those in reality. Furthermore, even when the same parts are shown between the drawings, the dimensional relationships and ratios between them may be different. In particular, the embodiments shown below are merely examples of structures for embodying the technical idea of ​​the present invention, and do not specify the technical idea of ​​the present invention. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be omitted. Furthermore, the lower and upper limits of numerical ranges include error ranges.

[0012] <Background to the Invention> Virtual reality / augmented reality (VR / AR) technology and the VR / AR-related market are growing rapidly. Along with this growth, display panels suitable for the VR / AR field are becoming smaller, with higher pixel counts (PPI: Pixels Per Inch), faster response times, and wider color gamuts. To advance this technology, silicon-based organic light-emitting diode (OLED) microdisplay panels are becoming increasingly popular.

[0013] Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and higher PPI. Furthermore, to effectively prepare for the high-value-added industries of AR and VR, it is expected to realize ultra-high resolution displays, for example, 1000 ppi or higher. This has led to a growing need for deposition masks for RGB color separation used in the manufacturing process of OLED microdisplays.

[0014] The deposition mask has a plurality of openings corresponding to the deposited film, and the accuracy of the openings in the deposition mask is important for improving the pattern dimensions of the deposited film.

[0015] The deposition mask is placed between the substrate and the deposition source, and the deposition material passes from the deposition source through the openings in the deposition mask and reaches the surface of the substrate. If the deposition material accumulates on the sidewalls of the openings, the opening width becomes narrower than the actual width, making it difficult to form a deposition film with excellent pattern dimensions.

[0016] In Patent Document 1, each opening is formed with a first portion whose opening width gradually decreases and a second portion whose opening width is approximately constant. It is claimed that this shape can prevent the deposition material from clogging the opening. However, Patent Document 1 does not mention the relationship between the taper angle and the deposition of the deposition material. Furthermore, Patent Document 1 specifies a fairly wide opening width, for example, 100 μm (0.1 mm) or more, and does not consider the deposition of the deposition material in openings with a narrow opening width of a few μm.

[0017] Patent Document 2 also does not describe or suggest the relationship between the opening width and taper angle and the pattern dimensions.

[0018] Therefore, the present inventors have conducted extensive research and have focused on the opening width and taper angle, and have developed a deposition mask that can increase the pattern dimensions of the deposited film.

[0019] <Overview of deposition mask 1 according to the present embodiment> Fig. 1 is a cross-sectional view of a deposition mask 1 according to the present embodiment. Fig. 2 is a cross-sectional view showing an enlarged view of a portion of the deposition mask shown in Fig. 1. Fig. 3 is a partially enlarged cross-sectional view showing an enlarged view of a portion of an opening of the deposition mask according to the present embodiment. Fig. 4 is a cross-sectional view showing a method for manufacturing an electronic device using the deposition mask according to the present embodiment.

[0020] The deposition mask 1 has a laminated structure of a semiconductor layer 2 , an insulating layer 3 , and a support substrate 4 , and is preferably made of an SOI (Silicon on Insulator) substrate 9 .

[0021] The semiconductor layer 2 is preferably a silicon single crystal layer, and is also called an active layer, a membrane, etc. The thickness of the semiconductor layer 2 is not limited, but is about 1 μm to 300 μm.

[0022] 1, the deposition mask 1 has a plurality of opening regions 15 and a peripheral region 16 located around the opening regions 15. The peripheral region 16 has a structure in which a semiconductor layer 2, an insulating layer 3, and a support substrate 4 are stacked. On the other hand, only the semiconductor layer 2 is disposed in the opening regions 15, that is, the insulating layer 3 and the support substrate 4 are removed, and a plurality of minute openings 5 ​​are formed in each opening region 15.

[0023] Fig. 2 is an enlarged view of the vicinity of one of the opening regions 15 shown in Fig. 1. As shown in Fig. 2, the semiconductor layer 2 has a first surface 2a and a second surface 2b that face each other in the thickness direction. An insulating layer 3 and a support substrate 4 are provided on the second surface 2b side.

[0024] As shown in FIG. 4, the first surface 2 a is the front surface facing the deposition substrate 10 , and the second surface 2 b is the rear surface facing the deposition source 11 .

[0025] 2, a plurality of openings 5 ​​are formed in the semiconductor layer 2, penetrating between the first surface 2a and the second surface 2b. As shown in Fig. 2, the opening width of each opening 5 gradually narrows from the second surface 2b to the first surface 2a. Therefore, the sidewall surface 6 of the opening 5 is inclined.

[0026] The planar pattern of the openings 5 ​​(the shape seen from directly above the semiconductor layer 2 toward the first surface 2a) is not limited, and examples thereof include a rectangle (including a square), a polygon other than a rectangle, a circle, and an ellipse. All the openings 5 ​​may have the same planar pattern, or some of them may have different patterns. The openings 5 ​​may be arranged regularly, irregularly, or a mixture of regular and irregular arrangements.

[0027] Although there are no limitations on the interval between adjacent openings 5, the interval is about 1 μm to 20 μm when viewed from the first surface 2a side.

[0028] The outer peripheral shape of the semiconductor layer 2 is preferably a rectangular or disk-shaped wafer, and the diameter (the length of one side in the case of a rectangle) is not limited, but is preferably about 100 mm to 500 mm. In this way, even if the diameter of the semiconductor layer 2 is large, the openings 5 ​​can be formed uniformly.

[0029] The insulating layer 3 can be exemplified by an oxide layer or a nitride layer, but is preferably an oxide layer, and more specifically, silicon oxide (SiO ２ The insulating layer 3 is preferably a BOX (Buried Oxide Layer) layer. The thickness of the insulating layer 3 is not limited, but is, for example, about 100 nm to 20 μm.

[0030] 1 is not provided in the opening region facing the opening 5 of the semiconductor layer 2, but has been removed, and is left only in the surrounding region of the opening region on the second surface 2b of the semiconductor layer 2. The insulating layer 3 serves as an etching stopper for the semiconductor layer 2, and the presence of the insulating layer 3 enables stable processing.

[0031] 1 is a semiconductor substrate, for example, a silicon substrate. The thickness of the support substrate 4 is not limited, but is, for example, about 100 μm to 1000 μm.

[0032] As shown in FIG. 1 , the support substrate 4 can function as columnar portions 16 a and a peripheral frame 16 b that surround the peripheral region 16 of the opening region 15 on the second surface 2 b of the semiconductor layer 2. Therefore, the semiconductor layer 2 can be maintained in a taut state by the support substrate 4, eliminating the need for a tensioning process. The deposition mask 1 of this embodiment can also be closely attached to the deposition substrate 10 using an electrostatic chuck that utilizes electrostatic force. As shown in FIG. 1 , the columnar portions 16 a are located inside the peripheral frame 16 b, and all of them have the same length (height). However, for example, the height of the columnar portions 16 a may be lower than that of the peripheral frame. However, by making the heights uniform, greater strength can be maintained.

[0033] 1 and 2, an alignment mark for positioning can be formed in the peripheral region on the first surface 2a side of the semiconductor layer 2. The alignment mark can be formed, for example, in a concave shape on the first surface 2a, and can be formed to a depth that reaches the insulating layer 3.

[0034] <Detailed Description of Opening 5 of Vapor Deposition Mask 1 in the Present Embodiment> In the present embodiment, the opening width W1 and the taper angle θ1 of the opening 5 are specified. [Method of Calculating Opening Width W1] As shown in FIG. 2, the opening 5 gradually narrows from the second surface 2b toward the first surface 2a, and the opening width varies depending on the measurement location. For this reason, as shown in FIG. 2, the opening width W1 was calculated as the dimension in the planar direction along the first surface 2a where the opening width is narrowest. The opening width W1 can be calculated from an SEM image obtained using an eCD-2 manufactured by KLA-Tencor.

[0035] [Method of Calculating Taper Angle θ1 of Opening 5] In this embodiment, the taper angle θ1 of opening 5 is calculated as follows. That is, as shown in Fig. 2, a straight line is drawn between an end of opening width W1 in the surface direction along first surface 2a and an end of opening width W2 in the surface direction along second surface 2b, and the inclination angle between this line and first surface 2a can be set as the taper angle θ1 of opening 5. The taper angle θ1 was calculated by measuring the length of an SEM image obtained using a Regulus 8220 manufactured by Hitachi High-Technologies.

[0036] 3 is a partially enlarged cross-sectional view showing one opening 5 formed in the deposition mask 1, and shows the middle part of the opening 5 in the height direction (thickness direction of the semiconductor layer 2). Note that although reference numerals are mainly attached only to the side wall surface 6 of the opening 5 on the left side in the figure, the cross-sectional shape is symmetrical, and the side wall surface 6 on the right side in the figure has the same configuration.

[0037] 3, the side wall surface 6 of the opening 5 is formed with an uneven shape. That is, on the side wall surface 6, a plurality of convex portions 7 protruding inward of the opening 5 and concave portions 8 located between the convex portions 7 are formed continuously and repeatedly along the height direction of the opening 5.

[0038] In Figure 3, only two pitches are shown and described. In Figure 3, the two convex portions 7 are denoted by reference numerals 7a and 7b to distinguish them from each other. When viewed from each of the convex portions 7a and 7b, a half pitch is formed with the concave portion 8 located on the first surface 2a side (upper side in the figure). The two concave portions 8 are also denoted by reference numerals 8a and 8b to distinguish them from each other. The convex portion 7a and the concave portion 8a form a first half pitch P1, and the convex portion 7b and the concave portion 8b form a second half pitch P2. Note that the pitch refers to the distance between convex portions or the distance between concave portions, and half that distance is defined as the half pitch.

[0039] As shown in Figure 3, an approximate line T1 was drawn connecting the lowest positions (bottoms A) of the recesses 8a, 8b within the measurement range. The bottom A is, for example, the farthest position as viewed from the center line O in the width direction of the opening 5. The approximate line T1 can be determined by the least squares method. Note that if an irregular recess 8 is formed within the measurement range (for example, if the bottom A is located at an extremely low position), the approximate line T1 can be drawn excluding that recess 8.

[0040] As shown in FIG. 3, the inclination angle θ4 of the side wall surface 6 can be determined from the inclination angle between the approximate straight line T1 shown in FIG. 3 and the first surface 2a.

[0041] The taper angle θ1 and the inclination angle θ4 are the same or approximate to each other, but the inclination of the approximate straight line T1 may change depending on, for example, the state of the uneven shape of the side wall surface 6 and the pitch, and the taper angle θ1 and the inclination angle θ4 may deviate from each other. Therefore, the inclination of the side wall surface 6 is determined by measuring the taper angle θ1 of the opening 5.

[0042] [Method of Calculating the Height Difference Between Concave and Convex] In this embodiment, in addition to the opening width W1 and the taper angle θ1 described above, the height difference between the convex and concave portions can be calculated as follows.

[0043] As shown in Fig. 3, the highest position (apex) B of the convex portion 7a was determined at the first half pitch P1. The apex B was the closest position when viewed from the center line O of the opening 5 in the width direction. Then, as shown in Fig. 3, a straight line S1 was drawn perpendicular to the approximate line T1 so as to intersect with the apex B. The length of the straight line S1 from the approximate line T1 to the apex B was determined. The length of this straight line S1 was defined as the uneven height difference D1 at the first half pitch P1.

[0044] The unevenness height difference for the second half pitch P2 and other half pitches can be calculated in the same manner as for the first half pitch P1. That is, the length of a straight line perpendicular to the approximate line T1 to the apex B of each convex portion is calculated, and this straight line length is used as the unevenness height difference for each pitch. Incidentally, the unevenness height difference D2 for the second half pitch P2 is shown in Figure 3.

[0045] In this way, multiple irregularity height differences can be determined. When five pitches are measured, five irregularity height differences Dn (n = 1 to 5) are calculated. Then, the average value Ave of these irregularity height differences Dn is calculated.

[0046] Although not limited to this, the length of five pitches of the uneven shape was measured using an SEM at a midpoint located exactly in the center of the thickness between the first surface 2a and the second surface 2b of the opening 5. Note that although it is not limited to five pitches, if the number of pitches is too small, parameter noise will increase, and if the number of pitches is too large, depending on the thickness, it may not be possible to ensure that number of pitches, and calculation of the parameters will be time-consuming and complicated, so it is preferable to set the number of pitches to within about several pitches and up to 10 pitches. In this embodiment, measurements are basically performed at five pitches, but if this is difficult, the number of pitches can be set or changed as appropriate.

[0047] Furthermore, instead of the concept of pitch described above, it is also possible to measure the height at, for example, five points at the center of the thickness in an SEM image. In this case, the points with height can be regarded as convex portions, and the areas between them can be regarded as concave portions.

[0048] Although minute irregularities may be formed on the surfaces of the recesses 8 a and 8 b (or on the bottoms of the protrusions 7 a and 7 b), these minute irregularities can be ignored. For example, minute irregularities on the order of several nanometers in wavelength or smaller can be cut off, and a waviness curve can be created to determine the tangent and the difference in irregularity height.

[0049] [Method of Calculating Concave-Convex Angles θ2 and θ3] In this embodiment, when defining the concave-convex shape of the side wall surface 6, the concave-convex angle θ2 can be calculated in addition to the concave-convex height difference described above.

[0050] As shown in Fig. 3, the unevenness angle θ2 can be determined as the angle between a straight line L1 connecting the top B of the convex portion 7a and the lowest bottom A (farthest from the center line O in the width direction of the opening 5) of the concave portion 8a located on the deposition substrate 10 side (upper side in the figure) as viewed from the convex portion 7a, and an approximate line T1. Also, as shown in Fig. 3, the unevenness angle θ3 can be determined as the angle between a straight line L2 connecting the top B of the convex portion 7a and the lowest bottom A (farthest from the center line O in the width direction of the opening 5) of the concave portion 8b located on the deposition source 11 side (lower side in the figure, see Fig. 4) as viewed from the convex portion 7a, and the approximate line T1.

[0051] Small concave-convex angles θ2 and θ3 mean that the height of the convex portion 7 is low (the depth of the concave portion 8 is shallow) and the waviness of the side wall surface 6 is small.

[0052] <Regarding Characteristic Configuration of Opening Parameters in the Present Embodiment> The deposition mask 1 in the present embodiment is characterized in that: (1) the opening width W1 is greater than 3 μm and not greater than 5 μm; and (2) the side wall surface 6 of the opening 5 is inclined so that the opening width narrows from the second surface 2 b facing the deposition source 11 side to the first surface 2 a facing the deposition substrate 10 side, and the taper angle θ1 of the opening 5 is greater than 50°.

[0053] As described above, in this embodiment, the opening width W1 is set to a range of more than 3 μm and not more than 5 μm. The opening width W1 is preferably 4 μm or more and 5 μm or less, and more preferably 4.5 μm or more and 5 μm or less. This satisfies the needs of the vapor deposition mask 1 including the semiconductor layer 2, and is particularly suitable for use as a vapor deposition mask for separate RGB coloring used in the manufacturing process of an OLED microdisplay.

[0054] In this embodiment, the sidewall surface 6 of the opening 5 is inclined so that the opening width narrows from the second surface 2b to the first surface 2a. This allows a deposited film 13 having a desired pattern width W3 to be formed stably. That is, the size of the deposited film 13 can be easily controlled. Furthermore, when the deposition material 12 deposited on the sidewall surface 6 peels off from the sidewall surface 6, it is less likely to fly toward the deposition substrate 10. Furthermore, from the viewpoint of manufacturing, by inclining the sidewall surface 6 of the opening 5, multiple openings 5 ​​can be efficiently formed in the semiconductor layer 2 by deep etching.

[0055] On the other hand, if the taper angle θ1 is set to approximately 90°, i.e., if the sidewall surface 6 is formed almost vertically, it is believed that the influence of the unevenness height difference Dn of the sidewall surface 6 during deposition will be significant. In particular, in this embodiment, since the opening width W1 is extremely narrow at several μm, it is necessary to minimize the average value Ave and maximum value of the unevenness height difference Dn. There is also a relationship with the thickness of the semiconductor layer 2. In other words, if the thickness of the semiconductor layer 2 is large, it becomes difficult to form the sidewall surface 6 as a vertical surface.

[0056] In this embodiment, in order to obtain excellent deposition results regardless of the uneven shape of the side wall surface 6, the side wall surface 6 is inclined, and the taper angle θ1 of the opening 5 is set to be greater than 50°. The upper limit of the taper angle θ1 is less than 90°, preferably 88° or less, and more preferably 85° or less. The taper angle θ1 has an error of about ±3°.

[0057] In this way, by specifying both the opening width W1 and the taper angle θ1, it becomes possible to make the pattern width of the vapor deposition film formed using the vapor deposition mask 1 80% or more of the opening width W1 of the vapor deposition mask 1.

[0058] FIG. 4 is a cross-sectional view of the deposition mask 1 of this embodiment arranged between a substrate 10 to be deposited and a deposition source 11, illustrating one step of a method for manufacturing an electronic device.

[0059] 4 , deposition material (deposition particles) 12 from a deposition source 11 passes through the openings 5 ​​in the deposition mask 1 and reaches the surface 10 a of the deposition target substrate 10, whereby a deposition film 13 is formed. When the pattern width W3 of the deposition film 13 is measured and the ratio to the opening width W1 is calculated, a combination of the opening width W1 and the taper angle θ1 that results in a pattern width ratio ((pattern width W3 / opening width W1)×100(%)) of 80% or more is defined as the present example, and a combination of the opening width W1 and the taper angle θ1 that results in a pattern width ratio of less than 80% is defined as a comparative example.

[0060] The deposition mask 1 of this embodiment can form the sidewall surface 6 with an inclined surface using the manufacturing method described below. In this case, as the taper angle θ1 decreases, deposition material 12 is more likely to deposit on the sidewall surface 6. However, by specifying the taper angle θ1 according to the opening width W1, a range in which the pattern width ratio is 80% or greater has been found. The reason for setting the required pattern ratio at 80% or greater is that a value below 80% results in a large deviation from the desired pattern width W3 of the deposition film 13, leading to reduced yields. It also leads to a reduction in the area that should emit light at the designed position, such as coordinate position accuracy, leading to reduced brightness of the light-emitting element itself, or because of the numerical value required for product quality assurance. To improve production efficiency, the pattern width ratio is set to 85% or greater, preferably 90% or greater, and more preferably 95% or greater.

[0061] In this embodiment, it is preferable that the opening width W1 is 4 μm or more and 5 μm or less, and the taper angle θ1 is 60° or more. This effectively makes it possible to achieve a pattern width ratio of 80% or more. It is also preferable that the opening width W1 is 4 μm or more and 5 μm or less, and the taper angle θ1 is 70° or more. This makes it possible to achieve an embodiment in which the pattern width ratio exceeds 90%.

[0062] Incidentally, the prior art has not mentioned a combination of the taper angle θ1 of the opening 5 and the opening width W1 that can improve the pattern width ratio when the opening width W1 is narrowed to a few μm.

[0063] Next, the uneven shape of the side wall surface 6 of the opening 5 is not particularly limited in this embodiment, but can be adjusted as follows, for example.

[0064] That is, the average value Ave of the unevenness height difference Dn is preferably 0.200 μm or less, more preferably 0.180 μm or less, and even more preferably 0.170 μm or less. Furthermore, although the lower limit of the average value Ave of the unevenness height difference Dn is not limited, it can be, for example, about 0.003 μm.

[0065] By adjusting the average value Ave of the unevenness height difference Dn within the above range, it is possible to minimize the deposition of the deposition material 12 on the side wall surface 6 of the opening 5, and more effectively reduce the number of times the deposition mask 1 is cleaned, thereby extending the life of the deposition mask 1.

[0066] The maximum value of the unevenness height difference Dn is preferably 0.300 μm or less, more preferably 0.250 μm or less, even more preferably 0.200 μm or less, and most preferably 0.100 μm or less. The maximum value of the unevenness height difference Dn is the largest unevenness height difference when the unevenness height difference Dn is calculated for the multiple pitches described in FIG.

[0067] Furthermore, the concave-convex angles θ2 and θ3 described in FIG. 3 are within a range of approximately 0.5° to 50°, preferably 45° or less, more preferably 40° or less, even more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less. By reducing the concave-convex angles θ2 and θ3, the protrusion height of the convex portions 7 can be reduced, or the spacing between adjacent convex portions 7 can be increased (the range of the concave portions 8 can be increased), thereby suppressing the deposition of the deposition material 12 on the side surfaces of the convex portions 7. The most preferable range of the concave-convex angles θ2 and θ3 is approximately 0.5° to 2°. Furthermore, the concave-convex angle θ3 shown in FIG. 3 is preferably smaller than the concave-convex angle θ2. This suppresses the deposition of the deposition material 12 on the side wall surfaces 6.

[0068] <Regarding the Manufacturing Method of the Vapor Deposition Mask 1 in the Present Embodiment> Figure 5 is a process chart showing a first manufacturing method of the vapor deposition mask 1 in the present embodiment. Here, the vapor deposition mask 1 in the manufacturing process shown in Figure 5 and Figure 6 described later shows only the vicinity of one opening region 15, as in Figure 2, but in reality, the multiple opening regions 15 shown in Figure 1 are formed simultaneously. In Figure 5(a), an SOI substrate 9 is prepared. The SOI substrate 9 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. The materials and thicknesses of each layer have been explained in Figure 1, so please refer to that.

[0069] In the case of the SOI substrate 9, the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.

[0070] 5(b), a mask layer 14 is patterned on the surface of the semiconductor layer 2. The mask layer 14 is preferably a resist, and can be patterned by exposure and development. A plurality of through holes 14a are formed in the mask layer 14. These through holes 14a are an opening pattern for forming openings 5 ​​in the semiconductor layer 2, and the width dimension W4 of the through holes 14a is formed to be approximately 2 μm to 6 μm.

[0071] 5C, the semiconductor layer 2 exposed from the through-holes 14a of the mask layer 14 is dry-etched. In this embodiment, the semiconductor layer 2 is deep-etched. ６ Etching of Si by C ４ F ８ It is preferable to use a method in which the formation of a polymer film by the Bosch process is repeated to dig deep into the silicon, and sidewall protection and bottom etching proceed alternately. By the Bosch process, the sidewall surface 6 of the opening 5 formed in the semiconductor layer 2 has an uneven shape.

[0072] 5C, the composition and flow rate of the etching gas, the internal pressure of the etching chamber, the power of the high frequency power supply, etc. are appropriately adjusted so as to form an inversely tapered surface. Furthermore, by adjusting these factors, the inclination angle of the inversely tapered surface (the taper angle θ1 of the opening 5) and the height difference Dn between the protrusions and recesses can be controlled.

[0073] For example, in a dry etching device, SF ６ Gas and C ４ F ８ The Bosch process was carried out using alternating gases. ６ Anisotropic dry etching using fluorine ions was performed using the same gas as that used for isotropic dry etching using fluorine radicals, by applying a bias to the substrate to be etched. The processing conditions were SF ６ Gas: 0 to 500 sccm, C ４ F ８The gas was set to 0 to 300 sccm, the platen LF to 0 to 1500 W, the coil RF to 300 to 1500 W, and the chamber pressure to 1 to 10 Pa, and various conditions were adjusted.

[0074] By the Bosch process described above, a plurality of openings 5 ​​can be formed by deep digging in the semiconductor layer 2, and at this time, the taper angle θ1 of the sidewall surface 6 of the openings 5 ​​and the height difference between the protrusions and recesses can be adjusted appropriately.

[0075] In this embodiment, in addition to adjusting the conditions in the etching process described above, reducing the unevenness height difference Dn can also be achieved by, for example, performing deep etching of silicon and then smoothing the unevenness height difference Dn by laser hydrogen annealing.

[0076] 5D, the mask layer 14 is removed, thereby completing the SOI substrate 9 having the plurality of openings 5 ​​formed in the semiconductor layer 2.

[0077] 5( e), a protective layer 20 is formed on the surface of the semiconductor layer 2. This makes it possible to appropriately protect the entire surface of the semiconductor layer 2. The protective layer 20 is, for example, a resist film, although it is not limited thereto.

[0078] Next, in the step shown in Figure 5(f), a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9. Although not limited to this, the mask layer 21 is a resist pattern. As shown in Figure 5(f), the mask layer 21 is not formed in the opening region 15 that faces the opening 5 formed in the semiconductor layer 2 in the thickness direction, but is provided only in the peripheral region 16 (see also Figure 1). Note that the mask layer 21 may be formed together with the mask layer 14 in the step shown in Figure 5(b).

[0079] 5( g), the support substrate 4 that is not covered with the mask layer 21 is removed by dry etching, and in the step shown in Fig. 5( h), the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching. At this time, the semiconductor layer 2 is not affected by the wet etching and maintains the shape having the plurality of openings 5.

[0080] 5(i), the protective layer 20 and the mask layer 21 are removed, thereby completing the deposition mask 1.

[0081] 6A to 6C are process diagrams showing a second manufacturing method of the deposition mask 1 according to the present embodiment. In Fig. 6A, an SOI substrate 9 is prepared. The SOI substrate 9 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. The materials and thicknesses of each layer have been explained in Fig. 1, so please refer to that explanation.

[0082] In the case of the SOI substrate 9, the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.

[0083] 6( b), a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9. The mask layer 21 is, but is not limited to, a resist pattern. As in FIG. 5( f), the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.

[0084] Next, in the step shown in FIG. 6(c), the support substrate 4 that is not covered by the mask layer 21 is removed by dry etching, and in the step shown in FIG. 6(d), the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching.

[0085] 6(e), a mask layer 22 is formed on the back surface of the semiconductor layer 2. Although not limited to this, the mask layer 22 can be formed using a resist pattern. As shown in FIG. 6(e), a plurality of openings 22a are patterned in the mask layer 22 by exposure and development.

[0086] 6(f), the semiconductor layer 2 exposed from the opening 22a is etched. This etching is dry etching, and preferably, an etching gas containing a fluorine compound and oxygen, and optionally a rare gas, is used, although this is not limited thereto.

[0087] The fluorine compound is, for example, CF ４ , SF ６ , N.F. ３ , B.F. ３ , P.F. ５ and F ２The rare gas may be selected from one or more of helium and argon.

[0088] For example, in a dry etching device, ４ Gas, O ２ Etching was performed using CF gas and Ar gas. ４ Gas: 10 to 100 sccm, O ２ The gas was set to 0-100 sccm, Ar gas to 0-200 sccm, IPC power to 200-1000 W, RIE power to 0-1000 W, and chamber pressure to 1-10 Pa, and various conditions were adjusted.

[0089] 6(f), an opening 5 whose width gradually decreases with increasing distance from the mask layer 22 (toward the first surface 2a of the semiconductor layer 2) can be formed in the semiconductor layer 2. This allows the sidewall surface 6 of the opening 5 to be formed as an inclined surface. Then, in the step of FIG. 6(g), the mask layer 22 is removed. This completes the deposition mask 1.

[0090] In both the manufacturing method shown in FIG. 5 and the manufacturing method shown in FIG. 6, a plurality of openings 5 ​​can be formed in the semiconductor layer 2, and the sidewall surfaces 6 of the openings 5 ​​can be formed as inclined surfaces such that the opening width gradually narrows from the back surface (second surface 2 b) of the semiconductor layer 2 facing the deposition source 11 toward the front surface (first surface 2 a) facing the deposition substrate 10.

[0091] In this embodiment, although not limited thereto, the opening width W1 and the taper angle θ1 can be adjusted by various gas flow rates, chamber pressure, power of the plasma generation source, and the like.

[0092] 4, the deposition mask 1 is placed between a deposition substrate 10 and a deposition source 11. At this time, the first surface 2a of the semiconductor layer 2 of the deposition mask 1 faces the deposition substrate 10, and the second surface 2b of the semiconductor layer 2 faces the deposition source 11. A plurality of openings 5 ​​are formed in the semiconductor layer 2, and the opening width is narrower on the first surface 2a side than on the second surface 2b side.

[0093] The deposition mask 1 is placed on a holder (not shown) of a deposition device, and an electrostatic chuck can be used to fix the deposition mask 1 and the deposition substrate 10. The deposition mask 1 and the deposition substrate 10 are rotated around the axis of the holder.

[0094] The deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 ​​of the deposition mask 1 and reaches the surface 10 a of the deposition substrate 10 , forming a deposition film 13 .

[0095] In this embodiment, examples of electronic devices include OLED microdisplay panels, liquid crystal panels, solar cells, etc., and the present invention is particularly suited to a method for manufacturing an OLED microdisplay panel as an organic electronic device.

[0096] By using the deposition mask 1 of this embodiment, the pattern width W3 of the deposited film 13 can be ensured to be 80% or more, preferably 90% or more, and more preferably 95% or more of the opening width W1. In this way, the deposited film 13 having excellent pattern dimensions can be formed.

[0097] <Effects of Using the Vapor Deposition Mask 1 of the Present Embodiment> In the present embodiment, the opening width W1 of the opening 5 of the vapor deposition mask 1 is set to be greater than 3 μm and not greater than 5 μm, and the taper angle θ1 of the opening 5 is set to be greater than 50°, thereby making it possible to obtain a high pattern dimension of the vapor deposition film 13.

[0098] In this embodiment, the opening width W1 is set to 4 μm or more and 5 μm or less, and the taper angle θ1 of the opening 5 is set to 60° or more, thereby making it possible to stably form a vapor-deposited film 13 having a pattern width ratio of 80% or more.

[0099] Conventionally, the unevenness formed on the sidewall surface 6 of the opening 5 has been uniformly defined based on roughness that makes it difficult for the deposition material to deposit, but the taper angle θ1 has not been adjusted. However, it has been found that for a narrow opening width W1 of several microns, the pattern width ratio fluctuates greatly depending on the taper angle θ1. Therefore, with the conventional control method, it is not possible to stably form a deposited film 13 having a high pattern dimension for a narrow opening width of several microns.

[0100] In contrast to this, in the present embodiment, by combining two factors, the opening width W1 and the taper angle θ1, it is possible to stably form a deposited film 13 having a pattern width W3 with a pattern width ratio of 80% or more, as described above.

[0101] The deposition mask 1 of the present embodiment can suppress deposition of the deposition material 12, reduce the frequency of cleaning the deposition mask, and facilitate quality control of the deposition mask. In addition, it can reduce clogging of the openings and extend the life of the deposition mask.

[0102] Although the embodiments and modifications have been described, other embodiments may be combinations of the above embodiments and modifications in whole or in part.

[0103] Furthermore, the present invention is not limited to the above-described embodiments and modifications, and may be variously changed, substituted, or modified within the scope of the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or other derived technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea.

[0104] An embodiment of a deposition mask having a layer structure different from that of the deposition mask 1 shown in Fig. 1 will be described. For example, as shown in Fig. 7, a deposition mask having a layer structure such as SiN or SiO ２ Alternatively, the membrane may have a single-layer structure in which a plurality of openings are formed in a semiconductor substrate (preferably a silicon substrate). The membrane is formed by CVD, but it is preferable to use SiN in view of ease of stress control.

[0105] 8 to 10 use an SOI substrate 9 similarly to Fig. 1 , but in Fig. 8 , a SiN layer 33 is formed on the back side (support substrate 4 side, the side facing the deposition source 11) of the SOI substrate 9, in Fig. 9 , a SiN layer 33 is formed on the front side (semiconductor layer 2 side, the side facing the deposition substrate 10) of the SOI substrate 9, and in Fig. 10 , a SiN layer 33 is formed on both the back side and the front side of the SOI substrate 9. In the configuration in which the SiN layer 33 is formed on the front side (semiconductor layer 2 side) of the SOI substrate 9, an opening 5 is formed continuous with the semiconductor layer 2, as shown in Figs. 9 and 10 .

[0106] By providing the SiN layer 33, stress control of the deposition mask is facilitated, and distortion, etc. can be suppressed. Furthermore, the SiN layer 33 formed on the front side of the SOI substrate 9 is preferably thinner than the SiN layer 33 formed on the back side of the SOI substrate 9. Although not limited thereto, the thickness of the SiN layer 33 formed on the front side of the SOI substrate 9 is approximately 0.05 μm to 0.5 μm, and the thickness of the SiN layer 33 formed on the back side of the SOI substrate 9 is approximately 0.05 μm to 3 μm. Because the semiconductor layer 2 is thinner than the support substrate 4 and also has numerous openings 5 ​​formed in the semiconductor layer 2, the SiN layer 33 formed on the front side of the SOI substrate 9 is made thinner than the SiN layer 33 formed on the back side of the SOI substrate 9 to achieve balanced stress control between the front side and the back side.

[0107] The effects of the present invention will be explained below with reference to examples and comparative examples, but the present invention is not limited to the following examples.

[0108] <SOI Substrate> The SOI substrate used had a support substrate (625 μm) / insulating layer (0.5 μm) / semiconductor layer (15 μm or 5 μm). The parentheses indicate thickness. The support substrate was a Si substrate, the semiconductor layer was a Si layer, and the insulating layer was a SiO ２ The SOI substrate had an outer diameter of 200 mm. In the experiment, two types of SOI substrates were prepared, one with a semiconductor layer thickness of 15 μm and the other with a semiconductor layer thickness of 5 μm.

[0109] <Master used> In step (b) shown in FIG. 5 and step (e) shown in FIG. 6, an opening pattern is formed in the mask layer (resist layer) by i-line exposure, and the opening width of the master used to form this opening pattern was adjusted to be within the range of 2.0 μm to 6.0 μm.

[0110] <Method for manufacturing deposition mask> A deposition mask 1 was formed using the manufacturing method shown in Figs. 5 and 6. In the experiment, the opening width W1 was changed depending on the master plate used. The opening width W1 formed in the semiconductor layer 2 and the taper angle θ1 of the sidewall surface 6 were also changed by SF ６ and C ４ F ８ The switching conditions and non-switching conditions were adjusted by adjusting the gas flow rate, chamber pressure, and power of the plasma generation source. For example, in the dry etching shown in FIG. 5C, SF ６ Anisotropic dry etching using fluorine ions was performed using the same gas as that used for isotropic dry etching using fluorine radicals, by applying a bias to the substrate to be etched. The processing conditions were SF ６ Gas: 0 to 500 sccm, C ４ F ８ The gas was set to 0 to 300 sccm, the platen LF to 0 to 1500 W, the coil RF to 300 to 1500 W, and the chamber pressure to 1 to 10 Pa, and various conditions were adjusted.

[0111] In the dry etching shown in FIG. ４ Gas: 10 to 100 sccm, O ２ The gas was set to 0-100 sccm, Ar gas to 0-200 sccm, IPC power to 200-1000 W, RIE power to 0-1000 W, and chamber pressure to 1-10 Pa, and various conditions were adjusted.

[0112] <Regarding the dimensions of the opening 5 formed in the deposition mask 1> In the experiment, the opening width W1, the taper angle θ1 of the side wall surface 6, the average value Ave of the unevenness height difference Dn, and the maximum value of the unevenness height difference Dn were determined. As shown in Fig. 2, the opening width W1 was defined as the width dimension in the surface direction along the first surface 2a of the semiconductor layer 2. The opening width W1 can be determined from an SEM image obtained using an eCD-2 manufactured by KLA-Tencor.

[0113] The unevenness height difference Dn and taper angle θ1 were determined from SEM images taken using a Hitachi High-Tech Regulus 8220 by the method described with reference to Figures 2 and 3. As described with reference to Figure 3, they were determined by observing five pitches at the center of the thickness of the unevenness formed on the side wall surface 6 at the midpoint of the opening height. For details on how to determine the unevenness height difference Dn and taper angle θ1, please refer to the explanations for Figures 2 and 3.

[0114] <Regarding Determination of Vapor Deposition Pattern Dimensions> Using the multiple vapor deposition masks formed above, a pattern of vapor-deposited film was formed on the glass surface through the vapor deposition masks by vacuum resistance heating vapor deposition of a green light-emitting material, Alq3 (tris(8-hydroxyquinoline)aluminum).

[0115] The pattern width W3 of the vapor-deposited film was then measured using a laser microscope (model number VK-X210, manufactured by Keyence Corporation) to determine the pattern width ratio ((W3 / W1) × 100(%)) of the vapor-deposited film to the opening width W1 of the vapor-deposition mask. Experimental examples with a pattern width ratio of less than 70% were marked with ×, experimental examples with a pattern width ratio of 70% to 80% with △, experimental examples with a pattern width ratio of 80% to 90% with ○, and experimental examples with a pattern width ratio of more than 90% with ◎. The experimental results are shown in Tables 1 and 2 below. Note that the "taper angle" shown in Tables 1 and 2 is expressed in 10° increments, but this is a representative value, and it was confirmed that all experimental examples fell within a range of ±3° from each representative value. Table 1 shows the experimental results when the semiconductor layer thickness was 15 μm, and Table 2 shows the experimental results when the semiconductor layer thickness was 5 μm.

[0116]

[0117]

[0118] As shown in Tables 1 and 2, experimental examples were numbered 1 to 24, and the opening width W1 was in the range of 3 μm to 5 μm. Experimental examples 1, 5, 13, and 17, in which the opening width W1 was 3 μm or 4 μm and the taper angle θ1 was 50°, had pattern width ratios of less than 70% and were evaluated as ×. Experimental examples 2 to 4 and 14 to 16, in which the opening width W1 was 3 μm and the taper angle θ1 was 60° to 80°, and experimental examples 9 and 21, in which the opening width W1 was 5 μm and the taper angle θ1 was 50°, all had pattern width ratios of 70% to 80% and were evaluated as △. Thus, experimental examples with pattern width ratios evaluated as × or △ are comparative examples. Meanwhile, experimental examples 6 to 8, 10 to 12, and 18 to 21, in which the opening width W1 was 3 μm and the taper angle θ1 was 50°, had pattern width ratios of 70% to 80% and were evaluated as △. No. 20, No. 22 to No. 24 were evaluated as ◯ or ⊚ in terms of pattern width ratio, and correspond to examples.

[0119] This experiment revealed that by setting the opening width W1 to be greater than 3 μm and less than 5 μm, and by setting the taper angle θ1 to be greater than 50°, deposition of the deposition material 12 on the sidewall surface 6 of the opening 5 can be suppressed, and a deposition film can be formed in which the pattern width W3 relative to the opening width W1 is 80% or more. In this example, the needs required for a deposition mask 1 including a semiconductor layer 2 can be met, and in particular, to be preferably used as a deposition mask for RGB color separation used in the manufacturing process of OLED microdisplays, the opening width W1 was set to be greater than 4 μm and less than 5 μm, and the taper angle θ1 was set to be greater than 60°. This allows for the stable formation of a deposition film with a pattern width ratio of 80% or more. Furthermore, by setting the opening width W1 to be greater than 4.5 μm and less than 5 μm, and the taper angle θ1 to be greater than 70°, a deposition film with a pattern width ratio of more than 90% can be stably formed.

[0120] The average value Ave of the difference in height Dn between the protrusions and recesses is preferably 0.200 μm or less, more preferably 0.180 μm or less, and even more preferably 0.170 μm or less. The lower limit of the average value Ave of the difference in height Dn between the protrusions and recesses is set to 0.100 μm or more, and 0.130 μm or more.

[0121] The maximum irregularity height difference Dn is preferably 0.500 μm or less, more preferably 0.450 μm or less, even more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.300 μm or less. The irregularity angle θ2 described in FIG. 3 was 11° to 41°.

[0122] This application is based on Japanese Patent Application No. 2023-130555, filed on August 10, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A deposition mask arranged between a substrate to be deposited and a deposition source, for depositing a deposition material from the deposition source onto a surface of the substrate to be deposited through openings, the deposition mask having a first surface facing the substrate to be deposited and a second surface located on the opposite side to the first surface facing the deposition source, with a plurality of openings formed therein penetrating between the first surface and the second surface, the width of each opening being greater than 3 μm and not greater than 5 μm, the sidewall surface of each opening being inclined so that the width of each opening narrows from the second surface side toward the first surface side, and the taper angle of each opening being greater than 50°.

2. The deposition mask according to claim 1, wherein the taper angle is 60° or more.

3. The deposition mask according to claim 1, wherein the taper angle is 70° or more.

4. The deposition mask according to claim 1, wherein the opening width is 4 μm or more and 5 μm or less.

5. The deposition mask according to claim 1, wherein the opening width is determined by the opening width on the first surface side.

6. The deposition mask according to claim 1, characterized in that the deposition mask is configured such that a membrane having the openings is supported on a supporting substrate, or is configured with a single layer structure of a semiconductor substrate, or is configured with an SOI substrate.

7. The deposition mask according to claim 6, wherein the membrane is made of SiN.

8. The deposition mask according to claim 1, characterized in that the deposition mask is composed of an SOI substrate, and a SiN layer is formed on the side facing the deposition substrate, or on the side facing the deposition source, or on both the side facing the deposition substrate and the side facing the deposition source.

9. A method for manufacturing an electronic device, comprising: disposing the deposition mask according to claim 1 between a substrate to be deposited and a deposition source; and depositing a deposition material onto the surface of the substrate through the openings.

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