Welding assembly for packaging of power semiconductor module, and method for manufacturing welding assembly

Abstract

The present invention relates to a welding assembly for packaging of a power semiconductor module. The welding assembly comprises: a first component, the outermost layer on a first side of the first component being a non-copper metal layer; a second component, a first copper layer being arranged on a first side of the second component; and a connecting copper layer, wherein two sides of the connecting copper layer are respectively connected to the non-copper metal layer and the first copper layer to form a first interface and a second interface, such that the first component and the second component are fixed together, and the average grain size of the connecting copper layer is in the range of 35-400 nm. The present invention further provides a welding assembly used for packaging of a semiconductor chip and relating to a plurality of components, and a method for producing the welding assembly for packaging of a power semiconductor module.

Description

Welding assembly for power semiconductor module packaging and manufacturing method thereof Technical Field

[0001] The present invention relates to a welding assembly for power semiconductor module packaging and a manufacturing method thereof. The welding assembly is particularly suitable for packaging power semiconductor modules, in particular power semiconductor modules used in inverter modules of new energy vehicles. Background Art

[0002] New energy vehicles, due to their clean energy and zero-emission advantages, are expected to gradually replace fuel-powered vehicles in the future and become the largest vehicle type in the market. One of the core components of new energy vehicles is the electronic control system, within which the inverter module is responsible for high-frequency conversion of high-voltage, high-current DC to AC power. It serves as the power transfer station between the vehicle battery and the drive system. Therefore, the performance of the inverter module directly affects the performance of the new energy vehicle's powertrain.

[0003] The performance and safety of inverter modules in new energy vehicles are largely influenced by packaging. The core of packaging lies in the soldering of key components, such as the copper conductive film, the semiconductor chip (with one or more metal layers on its back), the copper-clad substrate, and the heat sink, to achieve electrical and thermal conductivity. This involves three main scenarios: 1) The outermost metal layer on the back of the semiconductor chip (usually a gold or silver layer) is soldered to the copper layer of the copper-clad substrate using a third, low-melting-point metal solder; 2) The copper layer of the copper-clad substrate is connected to the aluminum layer on the aluminum heat sink using a third, low-melting-point solder or thermally conductive silicone sheet; and 3) The outermost metal layer on the front of the semiconductor chip (usually an aluminum layer) is soldered to the copper layer on the surface of the copper conductive film using a third, low-melting-point metal solder. The most widely used solder in industry is low-melting-point tin-based solder, which has a melting point between 200 and 250°C and offers excellent soldering properties (good wetting and spreading, low surface tension, etc.) and performance. The soldering method is usually: in a vacuum or inert gas protected environment, at a temperature slightly higher than the melting point of the solder, such as 250°C, heating for 1 to 10 minutes.

[0004] However, soldered assemblies obtained using tin-based solders have several drawbacks. On the one hand, tin is very active at low temperatures and reacts with metals such as gold, silver, aluminum, titanium, and nickel, resulting in the formation of intermetallic compounds at the soldering interface between the two. These intermetallic compounds grow rapidly at the interface at the operating temperature of the inverter module, forming a layer containing a large number of micron-sized intermetallic compounds (such as Ag3Sn, AuSn4, etc., depending on the metal that reacts with the tin). This reduces the conductivity of the soldering interface and makes it very susceptible to brittle cracking. This not only reduces the power of the inverter module, but also has a fatal impact on its service life, increasing the safety risks of the vehicle during use. On the other hand, for example, when soldering a chip to a copper-clad substrate using tin-based solder, the resulting soldered assembly includes large holes. These holes not only significantly reduce the electrical and thermal conductivity of the soldered assembly, reducing the power and heat dissipation efficiency of the module, making it impossible for the module to achieve the expected performance, but also become stress concentration areas when subjected to mechanical shock or thermal cycling, which can easily cause micro cracks to form, reduce shear strength, cause premature fracture, and shorten the service life of the module. At least based on these issues with current soldered components, existing inverter modules are limited in their power capabilities and cannot operate reliably at high temperatures.

[0005] Therefore, there is an urgent need for a welding assembly that can serve stably at high temperatures for a long time, which can at least alleviate or eliminate the above-mentioned technical problems caused by welding dissimilar metals, namely, the decline in performance (such as shear strength and conductivity) due to pores and brittle intermetallic compounds, thereby improving the long-term service performance of devices containing such welding assemblies.

[0006] Summary of the Invention

[0007] The present invention has been made in view of the above-mentioned existing problems.

[0008] One of the objectives of the present invention is to provide a welding assembly for power semiconductor module packaging, the welding assembly comprising:

[0009] a first component, wherein the outermost layer on the first side of the first component is a non-copper metal layer;

[0010] a second component having a first copper layer disposed on a first side of the second component;

[0011] A connecting copper layer, both sides of which are connected to the non-copper metal layer and the first copper layer to form a first interface and a second interface, thereby fixing the first component and the second component together,

[0012] Wherein, the average grain size of the connecting copper layer is 35nm-400nm.

[0013] The average grain size of the connecting copper layer is preferably 35 nm to 380 nm, more preferably 45 nm to 380 nm, more preferably 60 nm to 220 nm, and even more preferably 45 nm to 140 nm. Preferably, the average thickness of the connecting copper layer is 70 nm to 5 μm, more preferably 90 nm to 5 μm, and more preferably 500 nm to 5 μm, and the average thickness of the connecting copper layer is at least twice its average grain size.

[0014] Preferably, within a range extending 1 μm from the first and second interfaces, respectively, away from the connecting copper layer, and measuring any 10 μm along the length of the first / second interfaces, the average porosity of the soldered assembly is ≤3%, and the pore size is ≤200 nm. Further preferably, the average porosity of the soldered assembly is ≤1%.

[0015] Preferably, for the soldered assembly, 1) the first component is a semiconductor chip and the second component is a copper-clad substrate; or 2) the first component is a semiconductor chip and the second component is a copper conductive film or copper foil; or 3) the first component is a heat sink and the second component is a copper-clad substrate.

[0016] Preferably, the non-copper metal layer is a gold layer, and the average grain size of the connecting copper layer is 35 nm to 140 nm.

[0017] Preferably, the non-copper metal layer is a silver layer, and the average grain size of the connecting copper layer is 100 nm to 400 nm. This is because the diffusion coefficient of silver in copper is closer to the diffusion coefficient of copper in silver at the same temperature, so the average grain size requirement for weakening the Cockkendall effect is not as high as that of the gold layer.

[0018] Preferably, the first copper layer is formed by the initial copper layer of the copper-clad substrate or the copper conductive film, and the average grain size thereof is ≥500 nm.

[0019] In addition, preferably, the welding assembly further comprises:

[0020] a second copper layer disposed on a second side of the second component;

[0021] a third component, wherein the outermost layer on the first side of the third component is a non-copper metal layer;

[0022] Another connecting copper layer has two sides connected to the non-copper metal layer of the third component and the second copper layer respectively, thereby fixing the second component and the third component together; wherein the average grain size of the another connecting copper layer is 35nm to 400nm.

[0023] It will be understood that the soldered assembly can further similarly include more components and corresponding connecting copper layers with an average grain size of 35 nm to 400 nm for soldering the components together.

[0024] Preferably, the shear strength of the above-mentioned welding assembly is 30 to 40 MPa, more preferably 35 to 40 MPa, and the resistivity of the connecting copper layer is ≤5 μΩ·cm.

[0025] Preferably, the chip involved in the present invention includes a functional chip with silicon, silicon carbide, or gallium nitride as the main material, one or more metal layers provided on the front and back surfaces of the chip, and the outermost metal layer is a non-copper metal layer. Preferably, the outermost metal layer can be a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer. Preferably, the chip can be an insulated gate bipolar transistor (IGBT) chip, a metal oxide semiconductor field effect transistor (MOSFET) chip, a bipolar junction transistor (BJT) chip, or a fast recovery diode (FRD) chip.

[0026] Preferably, the copper-clad substrate involved in the present invention can be any substrate with a copper layer on the surface, including but not limited to a direct bond copper ceramic substrate (DBC), an active metal brazed ceramic substrate (AMB), or a copper-clad metal heat dissipation structure.

[0027] Preferably, the heat sink involved in the present invention is a heat dissipation structure with an aluminum layer on the surface.

[0028] Another object of the present invention is a welding assembly for power semiconductor module packaging, comprising:

[0029] a semiconductor chip, wherein a non-copper metal layer is provided on the outermost layers on the first side and the second side of the semiconductor chip;

[0030] a copper-clad substrate, wherein a first copper layer and a second copper layer are respectively provided on a first side and a second side of the copper-clad substrate;

[0031] a heat sink having an aluminum layer disposed on a first side of the heat sink;

[0032] a copper conductive film, wherein a third copper layer is provided on the first side of the copper-clad substrate;

[0033] a first connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the first side of the semiconductor chip and the third copper layer to fix the semiconductor chip and the copper conductive film together;

[0034] a second connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the second side of the semiconductor chip and the first copper layer to fix the semiconductor chip and the copper-clad substrate together; and

[0035] a third connecting copper layer, two sides of which are respectively connected to the second copper layer and the aluminum layer to fix the copper-clad substrate and the heat sink together;

[0036] The average grain size of the first, second and third connection copper layers is 35 nm to 400 nm.

[0037] Preferably, the average grain size of the first and second connecting copper layers is 35 nm to 380 nm, more preferably 45 nm to 380 nm, more preferably 60 nm to 220 nm, and even more preferably 45 nm to 140 nm. The average grain size of the third connecting copper layer is preferably 35 nm to 380 nm, and more preferably 62 nm to 250 nm. Preferably, the non-copper metal layer of the semiconductor chip is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer. Preferably, the average porosity of the soldered assembly is ≤3%, more preferably ≤1%, and the pore size is ≤200 nm.

[0038] Another object of the present invention is a method for producing a soldered assembly for power semiconductor module packaging, comprising the following steps:

[0039] a) providing a first component and a second component to be welded together and cleaning and drying the components, wherein the second component has an initial copper layer on a first side, and the outermost layer on the first side of the first component is a non-copper metal layer, such as a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer;

[0040] b) introducing a pre-plated copper layer on the surface of the initial copper layer of the cleaned second component or on the outermost layer of the first side of the cleaned first component and cleaning to remove an oxide layer on the surface of the pre-plated copper layer, wherein the average grain size of the pre-plated copper layer is 20 nm to 360 nm;

[0041] c) laminating the second component or the pre-plated copper layer of the first component to the non-copper metal layer of the first component or the initial copper layer of the second component in surface contact with each other to form a stacked structure;

[0042] d) welding the first component and the second component together by diffusion welding, thereby obtaining the welded assembly of the present invention.

[0043] Preferably, the average grain size of the pre-plated copper layer is 25 nm to 360 nm, more preferably 30 nm to 300 nm, and the average thickness of the pre-plated copper layer is greater than or equal to 2 times the average grain size. Further preferably, the average thickness of the pre-plated copper layer is 100 nm to 5 μm, more preferably 500 nm to 5 μm and is at least 3 times the average grain size.

[0044] Preferably, the first component is a semiconductor chip, and its non-copper metal layer is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer. Preferably, the first component is a heat sink, its surface is an aluminum layer, and the average grain size of the pre-plated copper layer is 30nm to 200nm, and the average thickness of the pre-plated copper layer is 100nm to 3μm and is at least three times the average grain size.

[0045] Preferably, in step d, diffusion welding is performed as follows: in a helium atmosphere at a temperature of 250-350° C., pressurizing the stacked structure from both the top and bottom, with a pressure of 15-40 MPa, for a holding time of 10-30 minutes. More preferably, the holding temperature is 250-300° C., or the pressure is 20-30 MPa, or the holding time is 10-20 minutes.

[0046] Preferably, the pre-plated copper layer is formed by electroplating, evaporation, sputtering, ion plating or the like to provide a pre-plated copper layer having relatively uniform thickness and grain size.

[0047] Preferably, in step b, the pre-plated copper layer is deposited by electrochemical deposition, and the electrolyte solution used comprises 200-250 g / L of anhydrous copper sulfate, 10-50 ml / L of sulfuric acid and 0.01-0.05 g / L of thiourea, and the solution temperature is 30°C. Further preferably, the current density of the electrochemical deposition is 0.05-0.15 A / cm 2 , the deposition time is 60 to 300 seconds. In addition, preferably, the electrolyte solution contains 200 to 250 g / L of anhydrous copper sulfate, 10 to 50 ml / L of sulfuric acid and 0.005 to 0.01 g / L of thiourea, the solution temperature is 30°C, and further preferably, the current density of the electrochemical deposition is 0.01 to 0.04 A / cm 2 , the deposition time is 250 to 350 seconds.

[0048] The method of the present invention achieves improved performance in a welded assembly with simple operation. Specifically, by providing a dense pre-plated copper layer for welding two components and controlling its grain size, the present invention achieves a connecting copper layer with a desired grain size, resulting in a welded assembly with low porosity and resistivity. Furthermore, due to copper's low activity and small lattice parameter, it reacts very slowly with dissimilar metals, resulting in minimal intermetallic compounds in the welded assembly. Consequently, the welded assembly obtained by the method of the present invention exhibits low porosity and resistivity, is essentially free of intermetallic compounds, and exhibits excellent electrical and thermal conductivity and high shear strength.

[0049] Furthermore, during service, the high grain boundary volume fraction of the connecting copper layer in the welded assembly provides a fast diffusion channel for dissimilar metals, so that the diffusion rate of dissimilar metal atoms is between 1 / 6 and 6 times the diffusion rate of copper atoms, more preferably between 0.5 and 2 times, thereby making the atomic inflow and outflow fluxes in the connecting copper layer basically consistent, fundamentally slowing down or avoiding the formation of Cockendale holes. At the same time, there are very few intermetallic compounds in the welded assembly. The combination of the two means that even if it operates for a long time in a high-temperature environment, a large number of Cockendale holes will not be generated and grow, and intermetallic compounds will not grow in the welded assembly, thereby not significantly affecting the mechanical properties and improving the long-term service stability of the welded assembly.

[0050] Compared with the prior art, the welding assembly for connecting dissimilar metals in the power semiconductor module package of the present invention has excellent performance and stable service performance, and solves the problems of low mechanical strength, high resistivity and poor heat dissipation caused by the generation of Kirkendall holes and intermetallic compounds when the welding assembly of dissimilar metals is in service.

[0051] In addition, those skilled in the art will understand that any range or any value within the above intervals is applicable to the present invention. For example, the average grain size of the connecting copper layer is 35 nm to 400 nm, which means that it can be taken from any range or any specific value within the range, for example: the average grain size is any range of 35 nm to 320 nm, 40 nm to 300 nm, 50 nm to 300 nm, 50 nm to 280 nm, 50 nm to 250 nm, 50 nm to 200 nm, 42 nm to 200 nm, 45 nm to 150 nm, 40 nm to 150 nm, 35 nm to 100 nm, 50 nm to 150 nm, or 50 nm to 100 nm, or any value such as the average grain size is 55 nm, 55 nm, 68 nm, 75 nm, 85 nm, 90 nm, 110 nm, 140 nm, 170 nm, 220 nm, 260 nm, 275 nm, 300 nm, 320 nm, 340 nm, 368 nm, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG1 shows an example scenario including a welded assembly according to the present invention;

[0053] FIG2 shows a light illumination microscopy (SIM) image of a cross-section of a copper-clad ceramic substrate after depositing a pre-copper layer according to the first embodiment of the present invention;

[0054] 3 shows an atomic force microscope (AFM) image of the surface morphology of a pre-plated copper layer on a copper-clad ceramic substrate after depositing the pre-plated copper layer according to the first embodiment of the present invention;

[0055] FIG4 shows a scanning electron microscope (SEM) image of a cross-section of a welded assembly according to the first embodiment of the present invention;

[0056] FIG5 shows a partially enlarged SEM image of FIG4 ;

[0057] FIG6 shows a transmission electron microscope (TEM) image of a cross-section of a welded assembly according to the first embodiment of the present invention;

[0058] FIG7 shows an SEM image of a shear cross section of a welded assembly according to the first embodiment of the present invention;

[0059] FIG8 shows an SEM image of a cross-section of a welded assembly according to the first embodiment of the present invention after being heated at 250° C. for 165 hours;

[0060] FIG9 shows a partially enlarged TEM image of a cross-section of the welded assembly according to the first embodiment of the present invention after being heated at 250° C. for 165 hours;

[0061] FIG10 shows an SEM image of a shear cross section of a welded assembly according to the first embodiment of the present invention after being held at 250° C. for 165 hours;

[0062] FIG11 shows an SEM image of a cross-section of a welded assembly according to a second embodiment of the present invention;

[0063] FIG12 shows a TEM image of a cross-section of a welded assembly according to a second embodiment of the present invention;

[0064] FIG13 shows an SEM image of a cross-section of a welded assembly according to a second embodiment of the present invention after being heated at 250° C. for 165 hours;

[0065] FIG14 shows a partially enlarged TEM image of a cross-section of a welded assembly according to the second embodiment of the present invention after being heated at 250° C. for 165 hours;

[0066] FIG15 shows an SEM image of a cross-section of a welded assembly according to a third embodiment of the present invention;

[0067] FIG16 shows a TEM image of a cross-section of a welded assembly according to a third embodiment of the present invention;

[0068] FIG17 shows an SEM image of a cross-section of a welded assembly according to a third embodiment of the present invention after being heated at 250° C. for 165 hours;

[0069] FIG18 shows a partially enlarged TEM image of a cross-section of a welded assembly according to a third embodiment of the present invention after being heated at 250° C. for 165 hours;

[0070] FIG19 shows a first comparative example of a welding assembly of a silicon-based IGBT chip and a copper-clad ceramic substrate welded with tin-based solder paste SAC305;

[0071] FIG20 shows an SEM image of a cross-section of the welded assembly of the first comparative example after being held at 200° C. for 72 hours;

[0072] FIG21 shows an SEM image of a shear cross-section of the welded assembly of the first comparative example after being held at 200° C. for 72 hours;

[0073] FIG22 shows a SIM image of a cross-section of the copper-clad ceramic substrate of the second comparative example after annealing of the pre-copper layer;

[0074] FIG23 shows an AFM image of the surface morphology of the pre-plated copper layer on the copper-clad ceramic substrate of the second comparative example after annealing;

[0075] FIG24 shows an SEM image of a cross-section of a welded assembly of a second comparative example; and

[0076] FIG25 shows an SEM image of a cross-section of the welded assembly of the second comparative example after being heated at 250° C. for 165 hours. DETAILED DESCRIPTION

[0077] The present invention will be described below in conjunction with specific embodiments. Specific embodiments and the accompanying drawings show several embodiments, which are intended to illustrate the disclosure. It should be understood that although one or more exemplary embodiments are shown below, the present disclosure is by no means limited to the exemplary embodiments, drawings and technology shown below, but can be modified within the scope of the appended claims and the full scope of their equivalents. It should be understood that any numbering (e.g., first, second, etc.) of the disclosed features and the directional terms (e.g., front, back, upper, lower, etc.) used with the disclosed features are relative terms representing the exemplary relationship between the relevant features or for distinguishing the relevant features. The word "example" is intended to be used as an example, instance or illustration when used in this article. Unless expressly stated, all ranges include end values. It will be understood by those skilled in the art that the data and various parameters described in the examples are exemplary only and do not constitute a limitation of the present invention.

[0078] The inventors have discovered that tin-based soldered components have the defect of low strength, mainly due to the following reasons: On the one hand, tin metal is very active and will react with various components of the surface to be soldered during the packaging process to form brittle intermetallic compounds, such as reacting with Au to form AuSn4, reacting with Ag to form Ag3Sn, reacting with Cu to form Cu3Sn and Cu6Sn5, and reacting with Ni to form Ni3Sn, etc. Since the energy required for the generation and growth of these intermetallic compounds is generally low, they can be rapidly generated and grown in a low-temperature environment, forming a weak interface with low strength and easy to break under stress, making the device prone to early failure during service. On the other hand, tin atoms and dissimilar metal atoms diffuse into each other at the soldering interface. When the diffusion rates of the two atoms are significantly different, a large number of Cockkendall holes will be formed on the side near the soldering interface where the atoms diffuse faster due to the rapid diffusion of atoms but the inability to fill the vacancies left by the diffused atoms in time. These holes grow with the extension of service time, forming stress concentration areas. Under stress, the soldered assembly is prone to cracking along these holes, creating an additional mechanically weak layer, causing the strength of the soldered assembly to gradually decrease during service. Furthermore, a large number of holes reduces the electrical and thermal conductivity of the soldered assembly, hindering the improvement of the device's power efficiency.

[0079] Similarly, the Cockendale effect also exists for the interdiffusion between a coarse-grained copper layer and a non-copper metal layer. In the present invention, copper with a grain size greater than 400 nm is defined as coarse-grained copper, while grains less than 400 nm are defined as fine-grained copper. For example, at 250°C, the diffusion rate of copper atoms in a gold layer is D Cu / Au 2.2×10 -18 m 2 / s, the diffusion rate of gold atoms in the coarse-grained copper layer D Au / Cu 2.4×10 -21 m 2 / s, the former is about 1000 times that of the latter. Therefore, for a welded assembly formed by a coarse-grained copper layer and a non-copper metal layer, during the welding process of its formation and its subsequent use at high temperatures, due to the slow diffusion of dissimilar metal atoms (such as gold atoms), they are unable to fill the gaps in the coarse-grained copper layer left by the rapidly diffused copper atoms. As a result, a large number of Cockkendall holes are generated in the coarse-grained copper layer near the welding interface between the non-copper metal layer and the coarse-grained copper layer. These holes not only become weak points of the device containing the welded assembly, but also reduce the electrical conductivity and thermal conductivity of the welded assembly, adversely affecting the performance of the device.

[0080] In order to avoid or at least reduce the impact of Kirkendall voids on the performance of welded assemblies, the inventors of the present invention proposed to increase the diffusion rate of dissimilar metal atoms in the adjacent copper layer to make it similar to the diffusion rate of copper atoms, so that the diffusion rates of different atoms entering and leaving the copper layer are basically balanced to avoid or reduce the formation of voids. The inventors of the present invention realized that the diffusion rate of dissimilar metals can be adjusted by controlling the volume fraction of grain boundaries. This is because the atoms at the grain boundaries are loosely arranged. Therefore, compared with the energy barrier required for atoms to migrate within the neatly arranged grains, the energy barrier required for atoms to break through the arrangement at the grain boundaries is lower, resulting in a high diffusion rate, so that the grain boundaries can provide a high-speed channel for atomic diffusion. Therefore, the present invention proposes to use this characteristic of rapid atomic diffusion at grain boundaries to solve the aforementioned problems.

[0081] Specifically, for copper layers with smaller grain sizes, the diffusion length of dissimilar metals is greater than the grain size, thus satisfying the Harrison A-type diffusion model, that is, grain boundary diffusion and lattice diffusion occur simultaneously. In this case, considering the effective diffusion rate D of the two diffusion modes, eff It can be calculated by the following formula (1): D eff =f gb D gb +D l (1),

[0082] in,

[0083] f gb is the grain boundary volume fraction;

[0084] D gb is the grain boundary diffusion coefficient;

[0085] D l is the lattice diffusion coefficient;

[0086] Because D gb 、D l The equal factors can be considered as fixed values ​​for the same system (such as Cu-Au system) at the same temperature, so the grain boundary volume fraction f can be adjusted gb The diffusion rate of the dissimilar metal in the system (specifically, the surface metal layer of the first component to be welded) in the copper layer to which it is connected (such as the connecting copper layer in the aforementioned welded assembly) is controlled so that it at least approximately matches the diffusion rate of copper atoms. In this application, "approximately matching the diffusion rate" means that the diffusion rate of the dissimilar metal atoms is between 1 / 6 and 6 times the diffusion rate of copper atoms, and more preferably between 0.5 and 2 times.

[0087] f gb It is affected by the grain size and can be calculated by the following formula (2):

[0088] Where Δ is the grain boundary thickness, which is 0.5 nm, and d is the grain size.

[0089] According to the formula, the control of the grain boundary volume fraction can be achieved by controlling the grain size. Because the operating temperature of the third-generation SiC semiconductor chip high-power devices in future applications is between 200 and 300°C, and the higher the operating temperature, the more susceptible it is to the Cockendall effect, so the temperature adjustment range targeted by the present invention is within the range of 200 to 300°C. Within this temperature range, by controlling the grain size of the connecting copper layer connected to the dissimilar metal to no more than 400nm (that is, the connecting copper layer is a fine-grained copper layer), a grain boundary volume fraction of at least 0.375% is obtained, and the grain boundary volume fraction increases as the grain size decreases. For example, when the grain size is 35nm, the grain boundary volume fraction is as high as about 4.3%, so that the diffusion coefficient of the dissimilar metal in the above-mentioned copper layer and the diffusion coefficient of copper in the dissimilar metal meet 1 / 6D Cu / X ≤D X / Cu-eff ≤6D Cu / X , where D Cu / X is the diffusion coefficient of Cu atoms in metal X; D X / Cu-eff is the effective diffusion coefficient of metal X atoms in the connecting copper layer. By reducing the difference between the diffusion coefficients of dissimilar metal atoms and copper atoms, the generation and growth of Kirkendall voids during service is reduced or even suppressed.

[0090] If the average grain size of the above-mentioned copper layer is greater than 400nm, the grain boundary volume fraction of the copper layer is less than 0.375%, so that there are not enough grain boundaries as fast channels to promote the rapid diffusion of dissimilar metals, that is, the difference in diffusion coefficients between dissimilar metal atoms and copper atoms is still large, thereby failing to significantly alleviate the problems caused by Cockendale holes. In addition, although smaller grains (i.e., larger grain boundary volume fractions) can further increase the diffusion rate of dissimilar metal atoms in the copper layer, when the grains are too small, the diffusion rate of dissimilar metal atoms may be excessively higher than the diffusion coefficient of copper atoms, so that the Cockendale effect may still be caused. For this reason, the present invention requires that the average grain size of the connecting copper layer be not less than 35nm, that is, the average grain size of the connecting copper layer connected between the two welded components is 35nm to 400nm.

[0091] Taking the Cu-X system where the dissimilar metals X are Au, Ag, Al, Ti, and Ni as an example, the D under the preferred grain size is calculated according to the above equations (1-2). X / Cu-eff , where D gb 、D l The values ​​are D X / Cu-gb and D X / Cu-lTable 1 lists the preferred grain sizes of the connecting copper layers of these Cu-X systems and the corresponding diffusion coefficients of the dissimilar metal X atoms in the connecting copper layers calculated based on the grain sizes, which satisfy the 0.5D Cu / X ≤D X / Cu-eff ≤2D Cu / X . D Cu / X is the diffusion coefficient of Cu atoms in metal X; D X / Cu is the diffusion coefficient of metal X atoms in the connecting copper layer; D X / Cu-gb is the grain boundary diffusion coefficient of metal X atoms in the connecting copper layer; D X / Cu-l is the lattice diffusion coefficient of metal X atoms in the connecting copper layer; D X / Cu-eff is the effective diffusion coefficient of metal X atoms in the connecting copper layer, 1 *D X / Cu-eff is the effective diffusion coefficient of metal X atoms in the connecting copper layer with an average grain size of 35 nm, 2 *D X / Cu-eff is the effective diffusion coefficient of metal X atoms in the connecting copper layer with an average grain size of 400 nm, 1 *D X / Cu-eff and 2 *D X / Cu-eff Meet 1 / 6D Cu / X ≤D X / Cu-eff ≤6D Cu / X .

[0092] Table 1 Preferred grain size and diffusion coefficient at 250°C for the connecting copper layer of Cu-X system

[0093] Taking Cu / Au as an example, the diffusion rate of Cu in Au at 250°C is known to be Cu / Au 2.2×10 -18 m 2 s -1 , and the diffusion rate of Au in Cu is D Au / Cu 2.4×10 -21 m 2 s -1 , which is much lower than the former. If the average grain size of the connecting copper layer is controlled at 35nm, the grain boundary volume fraction is f gb =3×0.5×10 -9 / (35×10 -9 )=0.0429, and substituting into formula (1) we can get the effective diffusion rate D of Au in Cu at this time: Au / Cu-eff =(0.0429×1.0×10 -16 )+5.0×10 -24 =4.3×10 -18 m 2 s-1 , about D Cu / Au 2 times; accordingly, when the average grain size of the connecting copper layer is 140nm, according to formula (1), D Au / Cu-eff 1.1×10 -18 m 2 s -1 , is D Cu / Au 0.5 times; further, when the average grain size of the connecting copper layer is 400nm, according to formula (1), D Au / Cu-eff 3.8×10 -19 m 2 s -1 , about D Cu / Au Therefore, when the average grain size of the copper layer at 250℃ is 35nm~400nm, the effective diffusion rate of Au in Cu is D Au / Cu-eff Meet 1 / 6D Cu / Au ≤D Au / Cu-eff ≤6D Cu / Au , so that the diffusion rates of Cu and Au are roughly matched, which can effectively weaken the Kirkendall effect. Furthermore, when the average grain size of the connecting copper layer is 35nm~140nm, the effective diffusion rate of Au in Cu is D Au / Cu-eff Meet 0.5D Cu / Au ≤D Au / Cu-eff ≤2D Cu / Au Further reducing the difference in diffusion rates between Cu and Au further weakens the Kirkendall effect, resulting in a soldered assembly with improved performance. Similarly, for other dissimilar metals X, setting the average grain size of the connecting copper layer to 35nm to 400nm can also effectively reduce the difference in diffusion rates between the dissimilar metal X and Cu. Furthermore, at the optimal grain size corresponding to each metal, the difference in diffusion rates between the dissimilar metal X and Cu can be further reduced. Furthermore, while only illustrative data at 250°C is provided, the preferred average grain size of the connecting copper layer will be applicable to the expected temperature range of 200-300°C.

[0094] Furthermore, in order to obtain the desired grain boundary volume fraction, that is, the desired grain size, of the connecting copper layer (i.e., the fine-grained copper layer) in the welded assembly, the manufacturing method of the present invention proposes to control the grain size of the pre-plated copper layer used for welding so that the grain size of the connecting copper layer is 35nm to 400nm. In this case, whether during the formation of the welded assembly or during the service period of the obtained welded assembly, the small grain size of the pre-plated copper layer and the connecting copper layer increases the diffusion rate of the dissimilar metals to be welded in the pre-plated copper layer and the connecting copper layer, respectively, making it roughly close to the diffusion rate of copper in the dissimilar metals, thereby avoiding or at least reducing the generation and growth of Cockendale holes during the welding process and during service, thereby avoiding or at least weakening the performance degradation of the welded assembly caused by the Cockendale effect as a whole, and improving the performance of the welded assembly. At the same time, the stable nature of copper itself also avoids the generation of brittle intermetallic compounds during the welding process, thereby avoiding the influence of intermetallic compounds on the performance of the obtained welded assembly.

[0095] In the present invention, porosity is defined as the ratio of the total area of ​​pores to the sampling area. The method for measuring the porosity of the welded assembly is as follows: on the cross-sectional surface of the welded assembly obtained, the width is measured by extending 1 μm outward from the aforementioned first interface and the aforementioned second interface respectively away from the aforementioned connecting copper layer (that is, the connecting copper layer is included) and the length is any 10 μm along the length direction of the first / second interface. The total area of ​​all visible pores within the sampling range at each position is measured by image processing software ImageJ. Then, the porosity at each sampling position is calculated and averaged according to the measurement results. As schematically shown in Figure 4, the field of view width is 1 μm extending outward from the interface between the gold layer and the connecting copper layer and the interface between the connecting copper layer and the coarse-grained copper layer respectively away from the connecting copper layer, and the length is any 10 μm along the length direction of the interface.

[0096] In the present invention, the resistivity of the connecting copper layer is tested as follows: To simulate a soldering scenario, a pre-plated copper layer of the same thickness as in actual soldering is deposited on the surface of the first copper layer of a silicon wafer having a 1μm first copper layer. A non-copper metal layer of the same thickness as the non-copper metal layer on the outermost surface of the component to be soldered is then directly sputtered onto the pre-plated copper layer. Heat and pressure are then applied to simulate the resulting soldered assembly. A four-point probe thin-film resistivity measurement is then performed on the surface of this soldered assembly, covering the non-copper metal layer, the connecting copper layer, and a small amount of the first copper layer. This resistivity reflects the impact of Cockkendall voids on the soldered assembly.

[0097] In this invention, the shear fracture test method is as follows: the bottom of the second component of the welded assembly is fixed to the test platform with resin. A movable mechanical component is pressed against the side of the first component of the welded assembly and a shear force is applied parallel to the sample at a speed of 20 μm / min. Five samples of each product are tested and the average value is calculated.

[0098] The excellent performance of the welding assembly of the present invention will be described below with reference to specific examples. It will be understood that the following embodiments are merely specific examples of the welding assembly of the present invention and are not intended to limit the present invention in any way.

[0099] FIG1 schematically illustrates a combined solder assembly according to the present invention, which schematically illustrates various application scenarios in which the solder assembly of the present invention may be applied, such as a solder assembly composed of a chip and a copper conductive film. It will be understood that the various illustrated scenarios may exist individually or in combination and will be schematically described in various embodiments.

[0100] First embodiment

[0101] The method for producing a welded assembly according to the first embodiment of the present invention is as follows:

[0102] Step 1.1: Provide a copper-clad ceramic substrate and a silicon-based IGBT chip to be soldered together. The copper-clad ceramic substrate has an initial copper layer with a thickness of approximately 2.4 μm, formed from coarse grains with an average grain size of no less than 500 nm (see Figure 2). Grain size is measured based on the maximum size of each grain as shown in the figure. The back metal layer of the silicon-based IGBT chip, from the inside out, consists of a titanium layer, a nickel layer, and a gold layer.

[0103] Step 1.2: The surface of the initial copper layer of the copper-clad ceramic substrate is cleaned in sequence with acetone, anhydrous ethanol, and dilute hydrochloric acid (HCl:H2O=1:1, by volume) using an ultrasonic cleaning method, and then rinsed with deionized water and dried to remove surface impurities and an oxide layer.

[0104] Step 1.3: Clean the gold layer of the silicon-based IGBT chip using acetone, anhydrous ethanol, and isopropyl alcohol (IPA) in sequence using an ultrasonic cleaning method, then rinse with deionized water and dry.

[0105] Step 1.4: Deposit a pre-plated copper layer on the surface of the initial copper layer in an area of ​​10 mm x 10 mm by electrochemical deposition, wherein the electrochemical deposition parameters are as follows: direct current plating, current density 0.05-0.15 A / cm 2The electrolyte solution contains 200-250 g / L of anhydrous copper sulfate, 10-50 ml / L of sulfuric acid, and 0.01-0.05 g / L of thiourea. The deposition time is 60 seconds, and the solution temperature is 30°C. Figure 2 shows a SIM image of a cross-section of a copper-clad ceramic substrate after deposition of the pre-plated copper layer. The average thickness of the deposited pre-plated copper layer is approximately 100 nm. In actual production applications, the thickness of the connecting copper layer can be adjusted appropriately as needed. To protect the deposited pre-plated copper layer during cross-sectioning, a Pt protective layer is additionally deposited on the pre-plated copper layer before cutting. Figure 3 shows an AFM image of the surface morphology of the pre-plated copper layer on the copper-clad ceramic substrate after deposition. The average grain size of the pre-plated copper layer is approximately 30 nm, which is much smaller than the grain size of the initial copper layer below it. Preferably, similarly, the pre-plated copper layer can also be deposited on the gold layer of a silicon-based IGBT chip. Preferably, in order to avoid the influence of specific grain orientation in a single layer of grains on the atomic diffusion rate, the thickness of the pre-plated copper layer is at least 2 times, more preferably 3 times, the average grain size.

[0106] Step 1.5: Cleaning the surface of the pre-plated copper layer of the copper-clad ceramic substrate with dilute hydrochloric acid (HCl:H2O=1:1, calculated by volume fraction) to remove the surface oxide layer;

[0107] Step 1.6: Laminating the gold layer of the silicon-based IGBT chip and the pre-plated copper layer of the copper-clad ceramic substrate together in surface contact to form a stacked structure;

[0108] Step 1.7: applying pressure to the stacked structure from above and below at 280°C in a helium atmosphere for 10 minutes at a pressure of 20 MPa; and

[0109] In step 1.8, the connected silicon-based IGBT chip and copper-clad ceramic substrate are air-cooled to room temperature to obtain a soldered assembly.

[0110] In order to better illustrate the details of the component, the obtained welded component was sectioned. Figure 4 shows an SEM image of the cross-section of the welded component obtained by the above method according to the first embodiment of the present invention, and Figure 5 is a partial enlarged view of Figure 4. As shown in Figures 4 and 5, the obtained welded component includes a silicon-based IGBT chip, a copper-clad ceramic substrate, and a connecting copper layer between the two and fixing the two together. It is a fine-grained copper layer. The two sides of the fine-grained copper layer are respectively combined with the outermost gold layer of the chip and the coarse-grained copper layer (i.e., the first copper layer) of the copper-clad substrate to form a first interface and a second interface respectively. The circles in Figure 4 are pore locations, and all pores are no larger than 200nm (based on the maximum size that can be measured for each pore shown in the figure). Figure 5 also confirms this, where the white dotted line is the interface between the gold layer and the fine-grained copper layer identified by the software, and the black dotted line is the interface between the coarse-grained copper layer and the fine-grained copper layer identified by the software. As shown in FIG5 , there are several holes on the fine-grained copper layer side near the interface between the gold layer and the fine-grained copper layer. The holes will be measured later to calculate the porosity.

[0111] FIG6 shows a TEM image of a cross-section of a soldered assembly according to the first embodiment of the present invention, in which the average grain diameter of the fine-grained copper layer is approximately 70 nm and the thickness is approximately 100 nm. Compared to the pre-plated copper layer before forming the soldered assembly, the grain size of the connecting copper layer increases, but the thickness remains essentially unchanged. This is because during the soldering process, the grains of the pre-plated copper layer grow by merging with each other. This merging occurs through the gradual movement of grain boundaries, where the grain boundaries of certain grains push toward surrounding grains, thereby absorbing these grains. Therefore, the connecting copper layer of the resulting soldered assembly can inherit the thickness of the pre-plated copper layer even as the grains grow. Nanocrystals are highly active and therefore easily grow through this merging at soldering temperatures. However, after the grain size exceeds 100 nm, the activity of the nanocrystals decreases exponentially, and their growth slows (see subsequent Examples 2 and 3).

[0112] According to formula (1), where D gb 、D l The values ​​are respectively D at the current temperature Au / Cu-gb and D Au / Cu-l , at 200℃, D Au / Cu-gb =7.3×10 -19 m 2 s - 1,D Au / Cu-l =1.0×10 -24 m 2 s - The grain size of 1.70 nm results in an effective diffusion rate D of gold atoms in the fine-grained copper layer at 200 °C. Au / Cu-eff Reaching 1.6×10 -20 m2 s -1 , which is compared with the effective diffusion rate D of coarse-grained copper Au / Cu-eff =3.2×10 -23 m 2 s -1 (grain size greater than 500 nm) and the diffusion rate of copper atoms in the gold layer (7.3×10 -21 m 2 s -1 ) is closer; at 300℃, D Au / Cu-gb =4.8×10 -15 m 2 s - 1,D Au / Cu-l =9.0×10 -24 m 2 s - 1. Calculated D Au / Cu-eff Reaching 1.0×10 -16 m 2 s -1 , compared with the D of coarse-grained copper Au / Cu-eff '=9.4×10 -20 m 2 s -1 , and the diffusion rate of copper atoms in the gold layer (6.0×10 -17 m 2 s -1 ) is closer. Therefore, the soldered assembly with the above-described connecting copper layer can avoid or at least mitigate the impact of the Cockkendall effect on its performance during subsequent use at 200-300°C. This was confirmed by subsequent high-temperature durability testing results.

[0113] In order to calculate the porosity, samples were taken at five locations on the cross-section of the obtained soldered assembly (one location is schematically shown in FIG4 ) within the following field of view: the width was 1 μm extending outward from the first interface between the gold layer and the connecting copper layer and the second interface between the connecting copper layer and the coarse-grained copper layer away from the connecting copper layer (i.e., the connecting copper layer was included), and the length was any 10 μm along the length direction of the first / second interface. In this example, the sampling range was approximately 22 μm. 2 , to measure the total pore area at each location. The specific measurement results are listed in Table 2. According to Table 2, the average porosity of this embodiment is approximately 0.79±0.09%. In addition, the maximum size of the pores at each sampling location does not exceed 200 nm.

[0114] In addition, the resistivity of the connecting copper layer was tested. Specifically, by simulating a welding scenario, a pre-plated copper layer with a thickness of 100nm and a grain size of 30nm was deposited on the surface of a silicon wafer with a 1μm first copper layer. A 100nm gold layer was directly sputtered on the pre-plated copper layer, and the welded assembly obtained after heating and pressing was simulated according to the aforementioned welding. The average resistivity of the connecting copper layer was measured by four-point probe thin film resistivity and was 3.0±1.4μΩ·cm. This low resistivity corresponds to the low porosity, which is conducive to achieving high-power operation of the welded assembly.

[0115] Table 2 Porosity of the first embodiment according to the present invention (sampling area is about 22 μm 2 )

[0116] Shear fracture testing was performed on the welded assembly of this example. The shear strengths of the five samples were 35.8 MPa, 36.6 MPa, 38.2 MPa, 34.7 MPa, and 36.2 MPa, respectively, with an average shear strength of 36.3 ± 1.2 MPa. Figure 7 shows an SEM image of a shear cross-section of the welded assembly of this example, demonstrating ductile fracture.

[0117] Furthermore, to verify the service stability of the welded assembly of the present invention, the welded assembly of this embodiment was subjected to a high-temperature durability test. The test parameters were as follows: the sample was held at 250°C in a vacuum environment for 165 hours; after the holding period, the sample was air-cooled. The samples that had undergone the high-temperature durability test were then subjected to porosity measurement, resistivity, and shear fracture testing, as described above.

[0118] Figures 8 and 9 both show images of cross-sections of the welded assembly according to the first embodiment of the present invention after high-temperature durability testing. No significant Cockendale pores or intermetallic compound formation were observed. The average porosity of the welded assembly remained virtually unchanged after the high-temperature durability test, at 0.82±0.15%, while the average resistivity increased slightly to 3.5±1.2 μΩ·cm. In the shear fracture test, the shear strengths of the five samples after the high-temperature durability test were 32.7 MPa, 35.2 MPa, 33.8 MPa, 34.5 MPa, and 31.3 MPa, respectively, with an average shear strength of 33.5±1.3 MPa. This represents a decrease of only approximately 7.7% compared to the shear strength before the high-temperature durability test, demonstrating excellent shear resistance. Furthermore, as shown in Figure 10, the shear cross-section of the welded assembly after the high-temperature durability test still exhibited ductile fracture, with no oxide concentration.

[0119] As can be seen from the above, the welded assembly obtained according to the first embodiment of the present invention has a porosity of no more than 1%, a resistivity of the connecting copper layer of approximately 3.0±1.4 μΩ·cm, and a shear strength of 36.3±1.2 MPa. Furthermore, even after high-temperature durability testing, the welded assembly maintains low porosity and resistivity, as well as high shear strength, ensuring long-term, reliable service under high-power conditions. This is attributed to the minimal number of Cockendale voids in the welded assembly, or the small size of any existing voids. This embodiment avoids or at least mitigates the impact of Cockendale voids on the performance of the welded assembly.

[0120] Second embodiment

[0121] The method for producing a welded assembly according to the second embodiment of the present invention is similar to the method of the first embodiment, except for the following differences:

[0122] 1) The components to be welded are a copper-clad ceramic substrate and an aluminum radiator, and the surface layer of the aluminum radiator is an aluminum layer;

[0123] 2) Current density in electrochemical deposition: 0.01-0.04 A / cm 2 The electrolyte solution contains 200-250 g / L of anhydrous copper sulfate, 10-50 ml / L of sulfuric acid and 0.005-0.01 g / L of thiourea, the deposition time is 250 seconds, and the solution temperature is 30°C. The average thickness of the deposited pre-plated copper layer is about 700 nm, and the average grain size is about 200 nm (the measurement method is the same as that of the first embodiment, so it will not be described in detail). This average thickness can avoid the appearance of single-layer grains during the welding process and the use of the obtained welded assembly to reduce the influence of specific grain orientation on the atomic diffusion rate. Similarly, the pre-plated copper layer can also be deposited on the aluminum layer of an aluminum heat sink.

[0124] 3) Welding step: in a helium protective environment at a temperature of 280° C., pressurize the stacked structure from the top and bottom respectively, with a pressure of 20 MPa and a holding time of 15 minutes.

[0125] Figure 11 shows an SEM image of a cross-section of a welded assembly of the second embodiment obtained using the above method, wherein the welded assembly includes an aluminum heat sink, a copper-clad ceramic substrate, and a connecting copper layer between the two to fix the two together, which is a fine-grained copper layer. The two sides of the fine-grained copper layer are respectively combined with the surface aluminum layer of the aluminum heat sink and the coarse-grained copper layer of the copper-clad substrate to form a first interface and a second interface, as shown by the white dotted line and the black dotted line in Figure 11, respectively.

[0126] Similar to the first embodiment, the soldered assembly of the second embodiment was measured and tested accordingly. Figure 12 shows a TEM image of a cross-section of the soldered assembly according to the second embodiment of the present invention, where the black dashed line indicates several grains in the connecting copper layer. Due to the heat from soldering, the average grain diameter of the connecting copper layer increases to approximately 220 nm, while the thickness remains approximately 700 nm. The average porosity of the soldered assembly of the second embodiment is 0.76±0.05%, the average resistivity of the connecting copper layer is 3.8±0.8 μΩ·cm, and the shear strength is 35.8±1.1 MPa. Figures 13 and 14 respectively show SEM and TEM images of a cross-section of the soldered assembly according to the second embodiment of the present invention after high-temperature durability testing. No obvious Kirkendall voids or intermetallic compound formation are observed. After the high-temperature durability test, the average porosity is 0.83±0.10%, the average resistivity of the connecting copper layer is 4.3±1.0 μΩ·cm, and the shear strength is 34.0±2.2 MPa. The shear cross-section of the welded assembly of the second embodiment exhibits ductile fracture characteristics both before and after the high-temperature durability test.

[0127] Likewise, the welded assembly of the second embodiment also has low porosity and resistivity and high shear strength, thereby enabling the welded assembly to provide long-term and reliable service under high power usage.

[0128] Third embodiment

[0129] The method for producing a welded assembly according to the third embodiment of the present invention is similar to the method of the first embodiment, except for the following differences:

[0130] 1) The components to be welded are a copper conductive film and a silicon carbide MOSFET chip, wherein the copper conductive film is a coarse-grained copper film with a thickness of 20 μm and is formed of coarse crystals with an average grain size of not less than 500 nm; the front metal layer of the silicon carbide-based MOSFET chip is, from the inside to the outside, a titanium layer, a nickel layer, and a silver layer;

[0131] 2) The pre-plated copper layer is deposited on the copper conductive film, wherein the current density in the electrochemical deposition is 0.005 to 0.015 A / cm 2 The deposition time is 350 seconds, and the electrolyte solution includes 200-250 g / L of anhydrous copper sulfate, 10-50 ml / L of sulfuric acid, and 0.005-0.01 g / L of thiourea, so that the average thickness of the deposited pre-plated copper layer is about 1 μm and the average grain size is about 360 nm; similarly, the pre-plated copper layer can also be deposited on the gold layer of the silicon-based IGBT chip.

[0132] 3) Welding step: in a helium protective environment at a temperature of 280° C., pressurize the stacked structure from the top and bottom respectively, with a pressure of 15 MPa and a holding time of 20 minutes.

[0133] Figure 15 shows an SEM image of a cross-section of a welded assembly of the third embodiment obtained using the above method, wherein the welded assembly includes a silicon carbide MOSFET chip, a copper conductive film, and a connecting copper layer therebetween to fix the two together, which is a fine-grained copper layer. Both sides of the fine-grained copper layer are respectively combined with the surface silver layer of the silicon carbide MOSFET chip and the coarse-grained copper layer of the copper conductive film to form a first interface and a second interface, as shown by the white dotted line and the black dotted line in Figure 15, respectively.

[0134] Similar to the first embodiment, the welded assembly of the third embodiment was measured and tested accordingly. Figure 16 shows a TEM image of a cross-section of the welded assembly according to the third embodiment of the present invention, wherein the average grain diameter of the connecting copper layer is approximately 380 nm. The average porosity of the welded assembly of the third embodiment of the present invention is 0.82±0.11%, the average resistivity of the connecting copper layer is 3.1±1.0 μΩ·cm, and the shear strength is 33.4±1.3 MPa. Figures 17 and 18 both show SEM images of a cross-section of the welded assembly according to the third embodiment of the present invention after high-temperature durability testing. No obvious Kirkendall pores or intermetallic compound formation were observed. After the high-temperature durability testing, the average porosity of the welded assembly was 1.39±0.09%, the average resistivity of the connecting copper layer was 6.2±1.1 μΩ·cm, and the shear strength was 32.8±1.2 MPa. The shear cross-section of the welded assembly of the third embodiment exhibited ductile fracture characteristics both before and after the high-temperature durability testing.

[0135] Likewise, the welding assembly of the third embodiment also has low porosity and resistivity and high shear strength, thereby enabling the welding assembly to provide long-term and reliable service under high power usage.

[0136] These examples demonstrate that the soldered assembly of the present invention possesses excellent performance (high electrical and thermal conductivity and high shear strength), and maintains excellent performance even after prolonged use in high-temperature environments, ensuring the stability and reliability of devices containing such soldered assemblies during long-term service. This is because, first, the soldered assembly of the present invention contains very few defects such as Cockendale pores, so these defects have little impact on subsequent service performance; second, the fine grains of the connecting copper layer in the soldered assembly increase the diffusion rate of dissimilar metal atoms therein, thereby weakening the Cockendale effect caused by the difference in diffusion rates, thereby inhibiting or at least slowing the formation and growth of Cockendale pores, thereby improving the stability of the soldered assembly during service; and third, the stable nature of copper itself prevents the formation of brittle intermetallic compounds during the soldering process and subsequent service, thereby preventing the intermetallic compounds from affecting the performance of the resulting soldered assembly.

[0137] The first comparison

[0138] The silicon-based IGBT chip and the copper-clad ceramic substrate were soldered using the commonly used tin-based solder paste SAC305 in the industry. The specific steps are as follows: the silicon-based IGBT chip and the copper-clad ceramic substrate were cleaned to remove surface impurities and dried separately. The back metal layer of the silicon-based IGBT chip consists of a titanium layer, a nickel layer, and a gold layer from the inside to the outside, and the copper-clad ceramic substrate has an initial copper layer. The tin-based solder paste was printed on the surface of the initial copper layer of the copper-clad ceramic substrate using tape to print 10mm×10mm, with a thickness of approximately 30μm. Then, the gold layer of the chip and the tin-based solder paste on the copper-clad ceramic substrate were superimposed in surface contact to form a chip-tin-based solder paste-copper-clad ceramic substrate stacked structure. The stacked structure was then maintained at 250°C in a vacuum environment for 2 minutes and finally air-cooled to room temperature.

[0139] The soldered assembly obtained by the above method is shown in Figure 19. This soldered assembly includes a silicon-based IGBT chip, a copper-clad ceramic substrate, and the junction between the two. From top to bottom, the junction consists of: intermetallic compound layer 1 - tin solder layer - intermetallic compound layer 2. The intermetallic compound layer 1 and intermetallic compound layer 2 of this junction respectively combine with the outermost gold layer of the chip and the coarse-grained copper layer of the copper-clad substrate to form a first interface and a second interface, as shown by the white dashed lines in Figure 19. These white dashed lines represent the interfaces between the layers identified by software recognition. This edge recognition is used to calculate the area of ​​the formed intermetallic compound in the cross-sectional view, and the average thickness of the intermetallic compound is determined by the ratio of this area to the straight-line length of the interface. Sampling at five locations along the cross-section of the same sample revealed an average thickness of 7.2 μm for the intermetallic compound 1 layer at the junction, and 5.3 μm for the intermetallic compound 2 layer. The porosity sampling range was 10 μm long and 1 μm wide, extending from 1 μm above the first interface between the gold layer and the intermetallic compound 1 layer on the chip surface to 1 μm below the second interface between the intermetallic compound 2 layer and the coarse-grained copper layer. This sampling range encompassed at least the intermetallic compound 1 layer, the tin solder layer, and the intermetallic compound 2 layer, all of which were areas of Kirkendall pore aggregation. The average porosity of the soldered assembly in this comparative example was 4.4 ± 1.5%, and the resistivity was 140 ± 2 μΩ·cm.

[0140] Table 3 Porosity of the first comparative example according to the present invention (sampling area is about 300 μm 2 )

[0141] Similarly, a shear fracture test was performed on the welding assembly of the comparative example. The shear strengths of the five samples were 22.1 MPa, 24.5 MPa, 23.8 MPa, 22.9 MPa and 26.2 MPa, respectively, with an average shear strength of 23.9±0.6 MPa, which was significantly lower than the shear strength of the various embodiments of the present application (approximately 33 to 36 MPa).

[0142] In addition, the comparative welded components were also subjected to a high-temperature durability test, and the test parameters were as follows: the sample was kept at 200°C in a vacuum environment for 72 hours; after the insulation was completed, the sample was air-cooled.

[0143] After the high-temperature durability test, cross-sections at five different locations of the same sample were sampled. As shown in Figure 20, a large number of Cockendale pores were generated at the interface (porosity was 10.8±2.1%), which will adversely affect the shear performance of the welded assembly. After measurement, the average thickness of the intermetallic compound layer 1 was 7.8μm; while the average thickness of the intermetallic compound layer 2 was 9.5μm, an increase of approximately 79.2% compared to before the high-temperature durability test. This is because the energy required for the generation of Cu / Sn metal compounds is less than that of Au / Sn, so the thickness of the intermetallic compound layer 2 near the coarse-grained copper layer grows faster. The increase in the thickness of the intermetallic compound means that when the welded assembly obtained by tin-based solder paste is used at high temperatures, the welded assembly will undergo significant changes. Combined with the generation and growth of Cockendale pores, this will adversely affect the stability and durability of the welded assembly.

[0144] The shear fracture test results confirmed this adverse effect. The shear strengths of the five samples after the high-temperature durability test were 18.0 MPa, 15.6 MPa, 23.8 MPa, 22.3 MPa, and 20.6 MPa, respectively, with an average shear strength of 20.3 ± 1.3 MPa. This represents a decrease of approximately 15% compared to the shear strength before the high-temperature durability test, significantly exceeding the decrease in shear strength observed after the high-temperature durability test for the welded assemblies of the various embodiments of the present invention. Furthermore, as shown in Figure 21, the shear cross-section of the welded assembly of the comparative example exhibited a candy-like fracture surface after the high-temperature durability test, a clear sign of brittle fracture.

[0145] The welded assembly of this comparative example not only contains an intermetallic compound layer but also contains over 5% porosity, which disadvantageously reduces the shear strength of the resulting welded assembly. Furthermore, since these intermetallic compounds and pores continue to form and grow during the service life of the welded assembly, they adversely affect the electrical and thermal conductivity, service stability, and durability of the welded assembly.

[0146] The second comparison

[0147] The method for producing the welded assembly of the second comparative example is similar to that of the first embodiment, except for the following differences:

[0148] 1) The copper-clad ceramic substrate has an initial copper layer with a thickness of about 1 μm and an average grain size of not less than 500 nm;

[0149] 2) After electrochemical deposition of the pre-plated copper layer, annealing is performed to allow grain growth, wherein the electrochemical deposition parameters are as follows: direct current plating, current density 0.005-0.015A / cm 2The electrolyte solution consisted of 200-250 g / L anhydrous copper sulfate and 10-50 ml / L sulfuric acid, the deposition time was 400 seconds, and the solution temperature was 30°C. Figure 22 shows a SIM image of a cross-section of a copper-clad ceramic substrate after annealing the pre-copper layer. The average thickness of the pre-copper layer was approximately 1 μm. The annealed surface of the copper-clad ceramic substrate is shown in Figure 23. The average grain size of the pre-copper layer was approximately 500 nm.

[0150] 3) Welding step: In a helium protective environment at a temperature of 400° C., pressurize the stacked structure from the top and bottom respectively, with a pressure of 20 MPa and a holding time of 30 minutes.

[0151] FIG24 shows an SEM image of a cross-section of a second comparative example solder assembly obtained using the above method, wherein the solder assembly obtained includes: a silicon-based IGBT chip, a copper-clad ceramic substrate, and a coarse-grained copper layer between the two to secure them together: the two sides of the coarse-grained copper layer are bonded to the outermost gold layer of the chip and the initial copper layer of the copper-clad substrate, respectively. Because the grain size of the coarse-grained copper layer and the initial copper layer of the copper-clad substrate are similar, migration occurs through the grain boundaries at high temperatures, resulting in the coarse-grained copper layer and the initial copper layer of the copper-clad ceramic substrate being unable to be directly distinguished by the software. As previously mentioned, the thickness of the pre-plated layer remains substantially unchanged during the soldering process. Therefore, in FIG24 and FIG25 , the boundary of the coarse-grained copper layer theoretically formed by the pre-plated copper layer is shown by a black dashed line 1 μm below the interface between the gold layer and the coarse-grained copper layer, as indicated by the white dashed line. No connecting copper layer with fine grains exists in this solder assembly.

[0152] Similar to the first embodiment, the soldered assembly of the second comparative example was measured and tested accordingly. For porosity measurement, the sampling range is as follows: the length is any 10 μm along the length direction of the interface, the width is from 1 μm above the interface between the gold layer and the coarse-grained copper layer (i.e., the white dotted line) to 1 μm below the interface between the coarse-grained copper layer formed by the pre-plated copper layer and the initial copper layer of the copper-clad ceramic substrate (i.e., the black dotted line), and the measurement area is approximately 30 μm 2 The soldered assembly of the second comparative example had a porosity of 0.95±0.20%, an average resistivity of the coarse-grained copper layer of 4.0±0.9 μΩ·cm, and a shear strength of 33.8±1.0 MPa.

[0153] Figure 25 shows an SEM image of the cross-section of the welded assembly of the second comparative example after being kept at 250°C for 165 hours, wherein a large number of Kokendall pores are present in the coarse-grained copper layer near the interface between the gold layer and the copper layer. Measurements show that after the high-temperature durability test, the maximum size of a single pore is up to about 460nm. The porosity and resistivity increased significantly, to about 8.53±0.12% and 58±2μΩ·cm, respectively, and the shear strength dropped sharply to 22.3±1.8Mpa. In addition, after the high-temperature durability test, the shear section of the welded assembly of the second comparative example changed from a ductile fracture to a brittle fracture.

[0154] The relevant measurement data of each embodiment and comparative example are listed in Table 4.

[0155] Table 4 Porosity, resistivity and shear strength of various embodiments and comparative examples (all average values)

[0156] Note: 1 Data measured before high temperature durability test; 2 Data measured after high-temperature durability testing.

[0157] Compared to the tin-based solder paste of the first comparative example, the soldered assemblies of the three embodiments using the pre-plated copper layer exhibited low porosity and resistivity and high shear strength, both when unused and after high-temperature durability testing, which is superior to soldered assemblies obtained with tin-based solder. This is because, on the one hand, the pre-plated copper layer itself is denser than the tin-based solder paste, effectively eliminating the gaps between the particles in the solder paste; at the same time, the small grain size of the connecting copper layer makes the diffusion rate between dissimilar metals (such as aluminum, gold, silver, nickel, etc.) and copper roughly the same, greatly reducing the generation and growth of Cockkendall voids, thereby weakening their adverse effects on the long-term stability and reliability of the soldered assembly; on the other hand, the stable nature of copper itself ensures that the soldered assembly does not contain brittle intermetallic compounds and can also inhibit the generation of the latter during use, thereby eliminating the adverse effects caused by intermetallic compounds.

[0158] For the second comparative example, although its soldered assembly exhibited comparable performance to the embodiments of the present invention when unused, its durability test results were poor, failing to achieve good operational stability and reliability. This demonstrates that the use of a dense pre-copper layer does not necessarily guarantee a soldered assembly with good service performance.

[0159] By comparing the second comparative example with the various embodiments of the present invention, it can be found that in order to achieve good service performance, there are requirements for the grain size of the connecting copper layer of the formed welding assembly. As shown in the second comparative example, when the grain size of the joint of the welding assembly is greater than 400nm, the service stability and conductivity of the welding assembly are insufficient. In contrast, as verified in the various embodiments, when the average grain size of the connecting copper layer is 35nm to 400nm, the small grain size provides a fast diffusion channel for the dissimilar metals, achieving a diffusion rate of both the dissimilar metal atoms and the copper atoms that meets 1 / 6D Cu / X ≤D X / Cu-eff ≤6D Cu / X , effectively weakening the Cockendale effect during the service life of the welded assembly. This significantly reduces the formation and growth of Cockendale voids, ensuring the stability and conductivity of the welded assembly during subsequent service. Therefore, in addition to requiring the use of a pre-plated copper layer for welding the first and second components, the present invention also requires that the average grain size of the connecting copper layer obtained from the pre-plated copper layer be between 35nm and 400nm to ensure the stability and durability of the welded assembly in high-temperature service environments.

[0160] In addition, the results of each embodiment also show that within this range, the smaller the grain size, the better the effect of suppressing the Kokendall pores. For example, compared to a larger grain size, such as 380nm in the third embodiment, when the grain size is 70nm to 220nm, the porosity after high temperature insulation can still be maintained below 1%, the resistivity is below 5μΩ·cm and the shear performance is above 33MPa, thereby achieving further performance improvement. In addition, Table 1 shows that for different metals, due to differences in diffusion coefficients, their preferred average grain sizes will be different. Therefore, a more preferred average grain size can be selected based on actual use conditions to further reduce the difference in diffusion rates between dissimilar metals and achieve better performance.

[0161] The present invention also includes a welding assembly for semiconductor chip packaging involving multiple components. For example, the welding assembly of the present invention includes a welding assembly formed by at least two of the first, second, and third embodiments. For example, as shown in FIG1 , a welding assembly according to another embodiment of the present invention includes:

[0162] a semiconductor chip, wherein a non-copper metal layer is provided on the outermost layers on the first side and the second side of the semiconductor chip;

[0163] a copper-clad substrate, wherein a first copper layer and a second copper layer are respectively provided on a first side and a second side of the copper-clad substrate;

[0164] an aluminum heat sink having an aluminum layer disposed on a first side of the heat sink;

[0165] a copper conductive film, wherein a third copper layer is disposed on a first side of the copper conductive film;

[0166] a first connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the first side of the semiconductor chip and the third copper layer to fix the semiconductor chip and the copper conductive film together;

[0167] a second connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the second side of the semiconductor chip and the first copper layer to fix the semiconductor chip and the copper-clad substrate together; and

[0168] a third connecting copper layer, two sides of which are respectively connected to the second copper layer and the aluminum layer to fix the copper-clad substrate and the aluminum heat sink together;

[0169] The average grain size of the first, second and third connection copper layers is 35 nm to 400 nm.

[0170] Preferably, the first, second and third connection copper layers may have a preferred grain size selected according to the metals actually connected and their thickness is at least one time of the grain size.

[0171] The above examples and experimental data are intended to illustrate the present invention by way of example. It should be clear to those skilled in the art that the present invention is not limited to these examples and that various modifications may be made without departing from the scope of the present invention. In addition, the steps in any of the above methods may not necessarily occur in the order depicted in the accompanying drawings, and in some cases, one or more of the depicted steps may occur substantially simultaneously, or may involve additional steps.

Claims

1. A welding assembly for power semiconductor module packaging, the welding assembly comprising: a first component, the outermost layer on the first side of the first component being a non-copper metal layer; a second component having a first copper layer disposed on a first side of the second component; A connecting copper layer, two sides of which are respectively connected to the non-copper metal layer and the first copper layer to form a first interface and a second interface, thereby fixing the first component and the second component together, Wherein, the average grain size of the connecting copper layer is 35nm-400nm.

2. The welding assembly according to claim 1, wherein: The average grain size of the connecting copper layer is 35 nm to 380 nm, and the average thickness thereof is 70 nm to 5 μm and is at least one time of the average grain size.

3. The welding assembly according to claim 1, wherein: Within a range of a width of 1 μm extending outward from the first interface and the second interface respectively away from the connection copper layer and a length of any 10 μm along the length direction of the first interface, the average porosity of the soldered assembly is ≤3%, and the pore size is ≤200 nm.

4. The welding assembly according to claim 1, wherein: Within a range of a width of 1 μm extending outward from the first interface and the second interface respectively away from the connection copper layer and a length of any 10 μm along the length direction of the first interface, the average porosity of the soldered assembly is ≤1%, and the pore size is ≤200 nm.

5. The welding assembly according to any one of claims 1 to 4, wherein: The first component is a semiconductor chip, and the second component is a copper-clad substrate; or the first component is a semiconductor chip, and the second component is a copper conductive film or a copper foil, wherein the average grain size of the first copper layer is ≥500nm, wherein the semiconductor chip comprises a functional chip with silicon, silicon carbide, or gallium nitride as the main material, one or more metal layers are arranged on the first side and the second side of the chip, and the outermost metal layer is a non-copper metal layer, wherein the non-copper metal layer is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer.

6. The welding assembly according to claim 5, wherein: The non-copper metal layer is a gold layer, and the average grain size of the connecting copper layer is 35nm-140nm.

7. The welding assembly according to claim 5, wherein: The non-copper metal layer is a silver layer, and the average grain size of the connecting copper layer is 100nm to 380nm.

8. The welding assembly according to claim 1, wherein: The average grain size of the connecting copper layer is 70nm-220nm.

9. The welding assembly according to any one of claims 1 to 4, wherein: The first component is a heat sink and its non-copper metal layer is an aluminum layer, and the second component is a copper-clad substrate, wherein the average grain size of the first copper layer is ≥500 nm.

10. The welding assembly according to any one of claims 1 to 4, wherein: The shear strength of the welding assembly is 30-40 MPa, and / or the resistivity of the connecting copper layer is ≤5 μΩ·cm.

11. The welding assembly according to any one of claims 1 to 4, wherein: The welding assembly further comprises: a second copper layer disposed on a second side of the second component; a third component, the outermost layer on the first side of the third component being a non-copper metal layer; Another connecting copper layer, two sides of which are respectively connected to the non-copper metal layer of the third component and the second copper layer, so as to fix the second component and the third component together; Wherein, the average grain size of the additional connecting copper layer is 35nm-400nm.

12. The welding assembly according to any one of claims 1 to 4, after being kept at 250°C for 165 hours, the shear strength of the welding assembly is 30-35 MPa, the resistivity of the connecting copper layer is ≤7 μΩ·cm, and / or the average porosity of the welding assembly is ≤3%, and the pore size is ≤200 nm.

13. A welding assembly for power semiconductor module packaging, comprising: A semiconductor chip, wherein a non-copper metal layer is disposed on the outermost layer on the first side and the second side of the semiconductor chip; A copper-clad substrate, wherein a first copper layer and a second copper layer are respectively arranged on a first side and a second side of the copper-clad substrate; a heat sink having an aluminum layer disposed on a first side of the heat sink; a copper conductive film, wherein a third copper layer is disposed on a first side of the copper conductive film; a first connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the first side of the semiconductor chip and the third copper layer to fix the semiconductor chip and the copper conductive film together; A second connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the second side of the semiconductor chip and the first copper layer to fix the semiconductor chip and the copper-clad substrate together; as well as The third connecting copper layer has two sides connected to the second copper layer and the aluminum layer respectively to connect The copper-clad substrate and the heat sink are fixed together; The average grain sizes of the first, second and third connection copper layers are between 35nm and 400nm.

14. The welding assembly according to claim 13, wherein: The average grain size of the first, second and third connection copper layers is 70nm-380nm, and the average thickness thereof is 70nm-5μm and is at least one time of the average grain size.

15. The welding assembly according to claim 13 or 14, wherein: The non-copper metal layer of the semiconductor chip is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer, and / or the average porosity of the welding assembly is ≤3%, more preferably ≤1%, and the pore size is ≤200nm.

16. A method for producing a welded assembly, comprising the steps of: a) providing a first component and a second component to be welded together and cleaning and drying them, wherein: The second component has an initial copper layer on the first side, and the outermost layer of the first side of the first component is a non-copper metal layer; b) introducing a pre-plated copper layer on the surface of the initial copper layer of the cleaned second component or on the outermost layer of the first side of the cleaned first component and cleaning to remove an oxide layer on the surface of the pre-plated copper layer, wherein the average grain size of the pre-plated copper layer is 20 nm to 360 nm; c) laminating the second component or the pre-plated copper layer of the first component to the non-copper metal layer of the first component or the initial copper layer of the second component in surface contact to form a stacked structure; d) welding the first component and the second component together using diffusion welding.

17. The method according to claim 16, wherein: The average grain size of the pre-plated copper layer is 25nm to 360nm.

18. The method according to claim 16 or 17, wherein: The first component is a semiconductor chip, and its non-copper metal layer is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer; or the average grain size of the pre-plated copper layer is 30nm to 200nm.

19. The method according to claim 16 or 17, wherein: In step d), diffusion welding is performed as follows: in a helium protective environment at a temperature of 250-350° C., pressurizing is performed from the top and bottom of the stacked structure, the pressure is 15-40 MPa, and the insulation time is 10-30 minutes.

20. The method according to claim 16 or 17, wherein: The pre-plated copper layer is formed by electroplating, evaporation, sputtering, or ion plating.

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